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Microchip AT91 device tree updates for v6.17

Browse Source 
This update includes:
 - controllers enabled for SAMA7D65 SoC (crypto controllers, PWM, CAN)
 - controllers enabled for SAM9X7 SoC (LCD, LVDS)
 - cache configuration updates for SAMA5D2, SAMA5D3, SAMA5D4, SAMA7G5,
   SAMA7D65
 - cleanups
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Merge tag 'at91-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt

Microchip AT91 device tree updates for v6.17

This update includes:
- controllers enabled for SAMA7D65 SoC (crypto controllers, PWM, CAN)
- controllers enabled for SAM9X7 SoC (LCD, LVDS)
- cache configuration updates for SAMA5D2, SAMA5D3, SAMA5D4, SAMA7G5,
  SAMA7D65
- cleanups

* tag 'at91-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: (22 commits)
  ARM: dts: microchip: sama7g5: Add cache configuration for cpu node
  ARM: dts: microchip: sama7d65: Add cache configuration for cpu node
  ARM: dts: microchip: sama5d4: Update the cache configuration for CPU
  ARM: dts: microchip: sama5d3: Update the cache configuration for CPU
  ARM: dts: microchip: sama5d2: Update the cache configuration for CPU
  ARM: dts: microchip: sam9x7: Add LVDS controller
  ARM: dts: microchip: sama5d2_icp: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
  ARM: dts: microchip: sama5d27_wlsom1: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
  ARM: dts: microchip: sama5d27_som1: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
  ARM: dts: microchip: sam9x60ek: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
  ARM: dts: at91-sama5d27_wlsom1: Improve the Wifi compatible
  ARM: dts: microchip: gardena-smart-gateway: Fix power LED
  ARM: dts: microchip: sam9x7: Add clock name property
  ARM: dts: microchip: sama7d65: Add clock name property
  ARM: dts: microchip: sama7g5: Adjust clock xtal phandle
  ARM: dts: microchip: sam9x7: Add HLCD controller
  ARM: dts: microchip: sama7d65: Enable CAN bus
  ARM: dts: microchip: sama7d65: Clean up extra space
  ARM: dts: microchip: sama7d65: Add CAN bus support
  ARM: dts: microchip: sama7d65: Add PWM support
  ...

Link: https://lore.kernel.org/r/20250721100904.568575-2-claudiu.beznea@tuxon.dev
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-07-22 23:02:23 +02:00
commit dc56e105c5
21 changed files with 272 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/microchip/at91-sam9x60ek.dts
View File

@ -609,7 +609,7 @@ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
spi-cs-setup-ns = <7>;
spi-cs-setup-delay-ns = <7>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;

2
arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi
View File

@ -44,7 +44,7 @@ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
spi-cs-setup-ns = <7>;
spi-cs-setup-delay-ns = <7>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;

4
arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi
View File

@ -234,7 +234,7 @@ qspi1_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
spi-cs-setup-ns = <7>;
spi-cs-setup-delay-ns = <7>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
m25p,fast-read;
@ -385,7 +385,7 @@ &sdmmc1 {
wilc: wifi@0 {
reg = <0>;
compatible = "microchip,wilc1000";
compatible = "microchip,wilc3000", "microchip,wilc1000";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wilc_default>;
clocks = <&pmc PMC_TYPE_SYSTEM 9>;

2
arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts
View File

@ -714,7 +714,7 @@ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
spi-cs-setup-ns = <7>;
spi-cs-setup-delay-ns = <7>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;

35
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts
View File

@ -38,7 +38,24 @@ reg_5v: regulator-5v {
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2_default>;
status = "okay";
};
&can3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can3_default>;
status = "okay";
};
&dma0 {
@ -278,6 +295,24 @@ &main_xtal {
};
&pioa {
pinctrl_can1_default: can1-default {
pinmux = <PIN_PD10__CANTX1>,
<PIN_PD11__CANRX1>;
bias-disable;
};
pinctrl_can2_default: can2-default {
pinmux = <PIN_PD12__CANTX2>,
<PIN_PD13__CANRX2>;
bias-disable;
};
pinctrl_can3_default: can3-default {
pinmux = <PIN_PD14__CANTX3>,
<PIN_PD15__CANRX3>;
bias-disable;
};
pinctrl_gmac0_default: gmac0-default {
pinmux = <PIN_PA26__G0_TX0>,
<PIN_PA27__G0_TX1>,

18
arch/arm/boot/dts/microchip/at91-sama7g5ek.dts
View File

@ -35,16 +35,6 @@ aliases {
i2c2 = &i2c9;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <24000000>;
};
};
gpio-keys {
compatible = "gpio-keys";
@ -556,6 +546,10 @@ &i2s0 {
pinctrl-0 = <&pinctrl_i2s0_default>;
};
&main_xtal {
clock-frequency = <24000000>;
};
&pdmc0 {
#sound-dai-cells = <0>;
microchip,mic-pos = <MCHP_PDMC_DS0 MCHP_PDMC_CLK_NEGATIVE>, /* MIC 1 */
@ -885,6 +879,10 @@ input@0 {
};
};
&slow_xtal {
clock-frequency = <32768>;
};
&spdifrx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdifrx_default>;

5
arch/arm/boot/dts/microchip/at91rm9200.dtsi
View File

@ -714,9 +714,8 @@ usb0: usb@300000 {
i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
&pioA 26 GPIO_ACTIVE_HIGH /* scl */
>;
sda-gpios = <&pioA 25 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA 26 GPIO_ACTIVE_HIGH>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <2>; /* ~100 kHz */

5
arch/arm/boot/dts/microchip/at91sam9260.dtsi
View File

@ -781,9 +781,8 @@ nand_controller: nand-controller {
i2c_gpio0: i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
&pioA 24 GPIO_ACTIVE_HIGH /* scl */
>;
sda-gpios = <&pioA 23 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA 24 GPIO_ACTIVE_HIGH>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <2>; /* ~100 kHz */

4
arch/arm/boot/dts/microchip/at91sam9261.dtsi
View File

@ -655,8 +655,8 @@ i2c-gpio-0 {
compatible = "i2c-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c_bitbang>;
gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */
<&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */
sda-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA 8 GPIO_ACTIVE_HIGH>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <2>; /* ~100 kHz */

5
arch/arm/boot/dts/microchip/at91sam9263.dtsi
View File

@ -826,9 +826,8 @@ nand_controller1: nand-controller {
i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
&pioB 5 GPIO_ACTIVE_HIGH /* scl */
>;
sda-gpios = <&pioB 4 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioB 5 GPIO_ACTIVE_HIGH>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <2>; /* ~100 kHz */

2
arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts
View File

@ -46,7 +46,7 @@ led-power-blue {
led-power-green {
label = "smartgw:power:green";
gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "timer";
};
led-power-red {

5
arch/arm/boot/dts/microchip/at91sam9g45.dtsi
View File

@ -1010,9 +1010,8 @@ nand_controller: nand-controller {
i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
&pioA 21 GPIO_ACTIVE_HIGH /* scl */
>;
sda-gpios = <&pioA 20 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA 21 GPIO_ACTIVE_HIGH>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <5>; /* ~100 kHz */

5
arch/arm/boot/dts/microchip/at91sam9n12.dtsi
View File

@ -786,9 +786,8 @@ nand_controller: nand-controller {
i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
&pioA 31 GPIO_ACTIVE_HIGH /* scl */
>;
sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <2>; /* ~100 kHz */

8
arch/arm/boot/dts/microchip/at91sam9rl.dtsi
View File

@ -833,8 +833,8 @@ rtc@fffffe00 {
i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */
<&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */
sda-gpios = <&pioA 23 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA 24 GPIO_ACTIVE_HIGH>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <2>; /* ~100 kHz */
@ -847,8 +847,8 @@ i2c-gpio-0 {
i2c-gpio-1 {
compatible = "i2c-gpio";
gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */
<&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */
sda-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <2>; /* ~100 kHz */

15
arch/arm/boot/dts/microchip/at91sam9x5.dtsi
View File

@ -933,9 +933,8 @@ nand_controller: nand-controller {
i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
&pioA 31 GPIO_ACTIVE_HIGH /* scl */
>;
sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <2>; /* ~100 kHz */
@ -948,9 +947,8 @@ &pioA 31 GPIO_ACTIVE_HIGH /* scl */
i2c-gpio-1 {
compatible = "i2c-gpio";
gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
&pioC 1 GPIO_ACTIVE_HIGH /* scl */
>;
sda-gpios = <&pioC 0 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioC 1 GPIO_ACTIVE_HIGH>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <2>; /* ~100 kHz */
@ -963,9 +961,8 @@ &pioC 1 GPIO_ACTIVE_HIGH /* scl */
i2c-gpio-2 {
compatible = "i2c-gpio";
gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
&pioB 5 GPIO_ACTIVE_HIGH /* scl */
>;
sda-gpios = <&pioB 4 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioB 5 GPIO_ACTIVE_HIGH>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <2>; /* ~100 kHz */

37
arch/arm/boot/dts/microchip/sam9x7.dtsi
View File

@ -45,11 +45,13 @@ cpu@0 {
clocks {
slow_xtal: clock-slowxtal {
compatible = "fixed-clock";
clock-output-names = "slow_xtal";
#clock-cells = <0>;
};
main_xtal: clock-mainxtal {
compatible = "fixed-clock";
clock-output-names = "main_xtal";
#clock-cells = <0>;
};
};
@ -983,6 +985,32 @@ pwm0: pwm@f8034000 {
status = "disabled";
};
hlcdc: hlcdc@f8038000 {
compatible = "microchip,sam9x75-xlcdc";
reg = <0xf8038000 0x4000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
clock-names = "periph_clk", "sys_clk", "slow_clk";
status = "disabled";
display-controller {
compatible = "atmel,hlcdc-display-controller";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
};
pwm {
compatible = "atmel,hlcdc-pwm";
#pwm-cells = <3>;
};
};
flx9: flexcom@f8040000 {
compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
reg = <0xf8040000 0x200>;
@ -1087,6 +1115,15 @@ AT91_XDMAC_DT_PER_IF(1) |
};
};
lvds_controller: lvds-controller@f8060000 {
compatible = "microchip,sam9x75-lvds";
reg = <0xf8060000 0x100>;
interrupts = <56 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 56>;
clock-names = "pclk";
status = "disabled";
};
matrix: matrix@ffffde00 {
compatible = "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon";
reg = <0xffffde00 0x200>;

3
arch/arm/boot/dts/microchip/sama5d2.dtsi
View File

@ -32,6 +32,8 @@ cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a5";
reg = <0>;
d-cache-size = <0x8000>; // L1, 32 KB
i-cache-size = <0x8000>; // L1, 32 KB
next-level-cache = <&L2>;
};
};
@ -160,6 +162,7 @@ L2: cache-controller@a00000 {
interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
cache-unified;
cache-level = <2>;
cache-size = <0x20000>; // L2, 128 KB
};
ebi: ebi@10000000 {

2
arch/arm/boot/dts/microchip/sama5d3.dtsi
View File

@ -48,6 +48,8 @@ cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a5";
reg = <0x0>;
d-cache-size = <0x8000>; // L1, 32 KB
i-cache-size = <0x8000>; // L1, 32 KB
};
};

3
arch/arm/boot/dts/microchip/sama5d4.dtsi
View File

@ -50,6 +50,8 @@ cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a5";
reg = <0>;
d-cache-size = <0x8000>; // L1, 32 KB
i-cache-size = <0x8000>; // L1, 32 KB
next-level-cache = <&L2>;
};
};
@ -143,6 +145,7 @@ L2: cache-controller@a00000 {
interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
cache-unified;
cache-level = <2>;
cache-size = <0x20000>; // L2, 128 KB
};
ebi: ebi@10000000 {

140
arch/arm/boot/dts/microchip/sama7d65.dtsi
View File

@ -32,17 +32,29 @@ cpu0: cpu@0 {
device_type = "cpu";
clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
clock-names = "cpu";
d-cache-size = <0x8000>; // L1, 32 KB
i-cache-size = <0x8000>; // L1, 32 KB
next-level-cache = <&L2>;
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>; // L2, 256 KB
cache-unified;
};
};
};
clocks {
main_xtal: clock-mainxtal {
compatible = "fixed-clock";
clock-output-names = "main_xtal";
#clock-cells = <0>;
};
slow_xtal: clock-slowxtal {
compatible = "fixed-clock";
clock-output-names = "slow_xtal";
#clock-cells = <0>;
};
};
@ -163,6 +175,86 @@ chipid@e0020000 {
reg = <0xe0020000 0x8>;
};
can0: can@e0828000 {
compatible = "bosch,m_can";
reg = <0xe0828000 0x200>, <0x100000 0x7800>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 58>;
assigned-clock-rates = <40000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
status = "disabled";
};
can1: can@e082c000 {
compatible = "bosch,m_can";
reg = <0xe082c000 0x200>, <0x100000 0xbc00>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 59>;
assigned-clock-rates = <40000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
status = "disabled";
};
can2: can@e0830000 {
compatible = "bosch,m_can";
reg = <0xe0830000 0x200>, <0x100000 0x10000>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 60>, <&pmc PMC_TYPE_GCK 60>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 60>;
assigned-clock-rates = <40000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
status = "disabled";
};
can3: can@e0834000 {
compatible = "bosch,m_can";
reg = <0xe0834000 0x200>, <0x110000 0x4400>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
assigned-clock-rates = <40000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
status = "disabled";
};
can4: can@e0838000 {
compatible = "bosch,m_can";
reg = <0xe0838000 0x200>, <0x110000 0x8800>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
assigned-clock-rates = <40000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
status = "disabled";
};
dma2: dma-controller@e1200000 {
compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
reg = <0xe1200000 0x1000>;
@ -186,6 +278,45 @@ sdmmc1: mmc@e1208000 {
status = "disabled";
};
aes: crypto@e1600000 {
compatible = "microchip,sama7d65-aes", "atmel,at91sam9g46-aes";
reg = <0xe1600000 0x100>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
clock-names = "aes_clk";
dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
<&dma0 AT91_XDMAC_DT_PERID(2)>;
dma-names = "tx", "rx";
};
sha: crypto@e1604000 {
compatible = "microchip,sama7d65-sha", "atmel,at91sam9g46-sha";
reg = <0xe1604000 0x100>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 78>;
clock-names = "sha_clk";
dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
dma-names = "tx";
};
tdes: crypto@e1608000 {
compatible = "microchip,sama7d65-tdes", "atmel,at91sam9g46-tdes";
reg = <0xe1608000 0x100>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 91>;
clock-names = "tdes_clk";
dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
<&dma0 AT91_XDMAC_DT_PERID(53)>;
dma-names = "tx", "rx";
};
trng: rng@e160c000 {
compatible = "microchip,sama7d65-trng", "microchip,sam9x60-trng";
reg = <0xe160c000 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 92>;
};
dma0: dma-controller@e1610000 {
compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
reg = <0xe1610000 0x1000>;
@ -254,6 +385,15 @@ pit64b1: timer@e1804000 {
clock-names = "pclk", "gclk";
};
pwm: pwm@e1818000 {
compatible = "microchip,sama7d65-pwm", "atmel,sama5d2-pwm";
reg = <0xe1818000 0x500>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 72>;
#pwm-cells = <3>;
status = "disabled";
};
flx0: flexcom@e1820000 {
compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe1820000 0x200>;

19
arch/arm/boot/dts/microchip/sama7g5.dtsi
View File

@ -38,6 +38,16 @@ cpu0: cpu@0 {
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
d-cache-size = <0x8000>; // L1, 32 KB
i-cache-size = <0x8000>; // L1, 32 KB
next-level-cache = <&L2>;
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>; // L2, 256 KB
cache-unified;
};
};
};
@ -117,19 +127,22 @@ map1 {
};
clocks {
slow_xtal: slow_xtal {
slow_xtal: clock-slowxtal {
compatible = "fixed-clock";
clock-output-names = "slow_xtal";
#clock-cells = <0>;
};
main_xtal: main_xtal {
main_xtal: clock-mainxtal {
compatible = "fixed-clock";
clock-output-names = "main_xtal";
#clock-cells = <0>;
};
usb_clk: usb_clk {
usb_clk: clock-usbclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "usb_clk";
clock-frequency = <48000000>;
};
};