From 9c2026fe46dfed1d5c48390c841ff26dc9c6b0b6 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 19 May 2025 13:21:05 +0200 Subject: [PATCH 01/22] ARM: dts: microchip: use recent scl/sda gpio bindings We have dedictaded bindings for scl/sda nowadays. Switch away from the deprecated plain 'gpios' property. Signed-off-by: Wolfram Sang Reviewed-by: Claudiu Beznea Link: https://lore.kernel.org/r/20250519112107.2980-4-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/at91rm9200.dtsi | 5 ++--- arch/arm/boot/dts/microchip/at91sam9260.dtsi | 5 ++--- arch/arm/boot/dts/microchip/at91sam9261.dtsi | 4 ++-- arch/arm/boot/dts/microchip/at91sam9263.dtsi | 5 ++--- arch/arm/boot/dts/microchip/at91sam9g45.dtsi | 5 ++--- arch/arm/boot/dts/microchip/at91sam9n12.dtsi | 5 ++--- arch/arm/boot/dts/microchip/at91sam9rl.dtsi | 8 ++++---- arch/arm/boot/dts/microchip/at91sam9x5.dtsi | 15 ++++++--------- 8 files changed, 22 insertions(+), 30 deletions(-) diff --git a/arch/arm/boot/dts/microchip/at91rm9200.dtsi b/arch/arm/boot/dts/microchip/at91rm9200.dtsi index 2a4c83d88733..e105ad855ce8 100644 --- a/arch/arm/boot/dts/microchip/at91rm9200.dtsi +++ b/arch/arm/boot/dts/microchip/at91rm9200.dtsi @@ -714,9 +714,8 @@ usb0: usb@300000 { i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */ - &pioA 26 GPIO_ACTIVE_HIGH /* scl */ - >; + sda-gpios = <&pioA 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 26 GPIO_ACTIVE_HIGH>; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; i2c-gpio,delay-us = <2>; /* ~100 kHz */ diff --git a/arch/arm/boot/dts/microchip/at91sam9260.dtsi b/arch/arm/boot/dts/microchip/at91sam9260.dtsi index ec973f07a961..fc0b6a73204f 100644 --- a/arch/arm/boot/dts/microchip/at91sam9260.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9260.dtsi @@ -781,9 +781,8 @@ nand_controller: nand-controller { i2c_gpio0: i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ - &pioA 24 GPIO_ACTIVE_HIGH /* scl */ - >; + sda-gpios = <&pioA 23 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 24 GPIO_ACTIVE_HIGH>; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; i2c-gpio,delay-us = <2>; /* ~100 kHz */ diff --git a/arch/arm/boot/dts/microchip/at91sam9261.dtsi b/arch/arm/boot/dts/microchip/at91sam9261.dtsi index 0b556c234557..d1d678b77e84 100644 --- a/arch/arm/boot/dts/microchip/at91sam9261.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9261.dtsi @@ -655,8 +655,8 @@ i2c-gpio-0 { compatible = "i2c-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c_bitbang>; - gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */ - <&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */ + sda-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 8 GPIO_ACTIVE_HIGH>; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; i2c-gpio,delay-us = <2>; /* ~100 kHz */ diff --git a/arch/arm/boot/dts/microchip/at91sam9263.dtsi b/arch/arm/boot/dts/microchip/at91sam9263.dtsi index 3e9e5ce7c6c8..a4b5d1f228f9 100644 --- a/arch/arm/boot/dts/microchip/at91sam9263.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9263.dtsi @@ -826,9 +826,8 @@ nand_controller1: nand-controller { i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ - &pioB 5 GPIO_ACTIVE_HIGH /* scl */ - >; + sda-gpios = <&pioB 4 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioB 5 GPIO_ACTIVE_HIGH>; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; i2c-gpio,delay-us = <2>; /* ~100 kHz */ diff --git a/arch/arm/boot/dts/microchip/at91sam9g45.dtsi b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi index 535e26e05e99..4e00ed2d3ecd 100644 --- a/arch/arm/boot/dts/microchip/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi @@ -1010,9 +1010,8 @@ nand_controller: nand-controller { i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ - &pioA 21 GPIO_ACTIVE_HIGH /* scl */ - >; + sda-gpios = <&pioA 20 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 21 GPIO_ACTIVE_HIGH>; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; i2c-gpio,delay-us = <5>; /* ~100 kHz */ diff --git a/arch/arm/boot/dts/microchip/at91sam9n12.dtsi b/arch/arm/boot/dts/microchip/at91sam9n12.dtsi index 2f930c39ce4d..af41c3dbb4bf 100644 --- a/arch/arm/boot/dts/microchip/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9n12.dtsi @@ -786,9 +786,8 @@ nand_controller: nand-controller { i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ - &pioA 31 GPIO_ACTIVE_HIGH /* scl */ - >; + sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; i2c-gpio,delay-us = <2>; /* ~100 kHz */ diff --git a/arch/arm/boot/dts/microchip/at91sam9rl.dtsi b/arch/arm/boot/dts/microchip/at91sam9rl.dtsi index 1fec9fcc7cd1..de74cf2980a0 100644 --- a/arch/arm/boot/dts/microchip/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9rl.dtsi @@ -833,8 +833,8 @@ rtc@fffffe00 { i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */ - <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */ + sda-gpios = <&pioA 23 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 24 GPIO_ACTIVE_HIGH>; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; i2c-gpio,delay-us = <2>; /* ~100 kHz */ @@ -847,8 +847,8 @@ i2c-gpio-0 { i2c-gpio-1 { compatible = "i2c-gpio"; - gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */ - <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */ + sda-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; i2c-gpio,delay-us = <2>; /* ~100 kHz */ diff --git a/arch/arm/boot/dts/microchip/at91sam9x5.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi index 17bdf1e4db01..9070fd06995a 100644 --- a/arch/arm/boot/dts/microchip/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi @@ -933,9 +933,8 @@ nand_controller: nand-controller { i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ - &pioA 31 GPIO_ACTIVE_HIGH /* scl */ - >; + sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; i2c-gpio,delay-us = <2>; /* ~100 kHz */ @@ -948,9 +947,8 @@ &pioA 31 GPIO_ACTIVE_HIGH /* scl */ i2c-gpio-1 { compatible = "i2c-gpio"; - gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ - &pioC 1 GPIO_ACTIVE_HIGH /* scl */ - >; + sda-gpios = <&pioC 0 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioC 1 GPIO_ACTIVE_HIGH>; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; i2c-gpio,delay-us = <2>; /* ~100 kHz */ @@ -963,9 +961,8 @@ &pioC 1 GPIO_ACTIVE_HIGH /* scl */ i2c-gpio-2 { compatible = "i2c-gpio"; - gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ - &pioB 5 GPIO_ACTIVE_HIGH /* scl */ - >; + sda-gpios = <&pioB 4 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioB 5 GPIO_ACTIVE_HIGH>; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; i2c-gpio,delay-us = <2>; /* ~100 kHz */ From 71b39aeaaff152a4899f7fbee5a7f5fa8b335b85 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Wed, 11 Jun 2025 12:47:30 -0700 Subject: [PATCH 02/22] ARM: dts: microchip: sama7d65: Add crypto support Add and enable SHA, AES, TDES, and TRNG for SAMA7D65 SoC. Signed-off-by: Ryan Wanner Reviewed-by: Claudiu Beznea Link: https://lore.kernel.org/r/fc791949c97f368f32a710e64d8db4018e45e70f.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 39 +++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index d08d773b1cc5..90cbea576d91 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -186,6 +186,45 @@ sdmmc1: mmc@e1208000 { status = "disabled"; }; + aes: crypto@e1600000 { + compatible = "microchip,sama7d65-aes", "atmel,at91sam9g46-aes"; + reg = <0xe1600000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; + clock-names = "aes_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + }; + + sha: crypto@e1604000 { + compatible = "microchip,sama7d65-sha", "atmel,at91sam9g46-sha"; + reg = <0xe1604000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 78>; + clock-names = "sha_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; + dma-names = "tx"; + }; + + tdes: crypto@e1608000 { + compatible = "microchip,sama7d65-tdes", "atmel,at91sam9g46-tdes"; + reg = <0xe1608000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 91>; + clock-names = "tdes_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, + <&dma0 AT91_XDMAC_DT_PERID(53)>; + dma-names = "tx", "rx"; + }; + + trng: rng@e160c000 { + compatible = "microchip,sama7d65-trng", "microchip,sam9x60-trng"; + reg = <0xe160c000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 92>; + }; + dma0: dma-controller@e1610000 { compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; reg = <0xe1610000 0x1000>; From a9ea0d5f70ab63370159b3b07d2ebbf9de12532b Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Wed, 11 Jun 2025 12:47:31 -0700 Subject: [PATCH 03/22] ARM: dts: microchip: sama7d65: Add PWM support Add support for PWMs to the SAMA7D65 SoC. Signed-off-by: Ryan Wanner Reviewed-by: Claudiu Beznea Link: https://lore.kernel.org/r/195c69a19be1ff14736db402e0f1ee64438b4b20.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 90cbea576d91..796909fa2368 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -293,6 +293,15 @@ pit64b1: timer@e1804000 { clock-names = "pclk", "gclk"; }; + pwm: pwm@e1818000 { + compatible = "microchip,sama7d65-pwm", "atmel,sama5d2-pwm"; + reg = <0xe1818000 0x500>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 72>; + #pwm-cells = <3>; + status = "disabled"; + }; + flx0: flexcom@e1820000 { compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe1820000 0x200>; From ec9a309d0c7e26efd7705600e15ff0909434e67a Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Wed, 11 Jun 2025 12:47:32 -0700 Subject: [PATCH 04/22] ARM: dts: microchip: sama7d65: Add CAN bus support Add support for CAN bus to the SAMA7D65 SoC. Signed-off-by: Ryan Wanner Reviewed-by: Claudiu Beznea Link: https://lore.kernel.org/r/f80a4206c05ed5d80a9527476963a18070ca42b6.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 80 +++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 796909fa2368..a62d2ef9fcab 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -163,6 +163,86 @@ chipid@e0020000 { reg = <0xe0020000 0x8>; }; + can0: can@e0828000 { + compatible = "bosch,m_can"; + reg = <0xe0828000 0x200>, <0x100000 0x7800>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 58>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can1: can@e082c000 { + compatible = "bosch,m_can"; + reg = <0xe082c000 0x200>, <0x100000 0xbc00>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 59>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can2: can@e0830000 { + compatible = "bosch,m_can"; + reg = <0xe0830000 0x200>, <0x100000 0x10000>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 60>, <&pmc PMC_TYPE_GCK 60>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 60>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can3: can@e0834000 { + compatible = "bosch,m_can"; + reg = <0xe0834000 0x200>, <0x110000 0x4400>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 61>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can4: can@e0838000 { + compatible = "bosch,m_can"; + reg = <0xe0838000 0x200>, <0x110000 0x8800>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 62>; + assigned-clock-rates = <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + dma2: dma-controller@e1200000 { compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; reg = <0xe1200000 0x1000>; From 5a4aad596e0d930c8fa189764ad4b06835843a13 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Wed, 11 Jun 2025 12:47:33 -0700 Subject: [PATCH 05/22] ARM: dts: microchip: sama7d65: Clean up extra space Remove the extra space that causes formatting issues. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/ac1decc35e2b4f706cf6ab9378f2c88e5295dde4.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 53a657cf4efb..759b963d987c 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -38,7 +38,6 @@ reg_5v: regulator-5v { regulator-max-microvolt = <5000000>; regulator-always-on; }; - }; &dma0 { From 198b54b0a6870d83576115deaecb5523ab6e56b9 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Wed, 11 Jun 2025 12:47:34 -0700 Subject: [PATCH 06/22] ARM: dts: microchip: sama7d65: Enable CAN bus Enable CAN bus for SAMA7D65 curiosity board. Signed-off-by: Ryan Wanner Reviewed-by: Claudiu Beznea Link: https://lore.kernel.org/r/ab719861de53432bdf19593fa4eee40adf57aed9.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea --- .../dts/microchip/at91-sama7d65_curiosity.dts | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 759b963d987c..7eaf6ca233ec 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -40,6 +40,24 @@ reg_5v: regulator-5v { }; }; +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2_default>; + status = "okay"; +}; + +&can3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can3_default>; + status = "okay"; +}; + &dma0 { status = "okay"; }; @@ -277,6 +295,24 @@ &main_xtal { }; &pioa { + pinctrl_can1_default: can1-default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_can2_default: can2-default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_can3_default: can3-default { + pinmux = , + ; + bias-disable; + }; + pinctrl_gmac0_default: gmac0-default { pinmux = , , From 11b83df6bb920123409dfbb8d2e824fddb279186 Mon Sep 17 00:00:00 2001 From: Dharma Balasubiramani Date: Wed, 11 Jun 2025 14:47:59 +0530 Subject: [PATCH 07/22] ARM: dts: microchip: sam9x7: Add HLCD controller Add support for HLCD controller. Signed-off-by: Dharma Balasubiramani Link: https://lore.kernel.org/r/20250611-sam9x7-dts-v1-1-7f52fcb488ad@microchip.com [claudiu.beznea: keep reg the 1st property on port@0 to comply with dts coding style] Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sam9x7.dtsi | 26 +++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi index b217a908f525..2c8ab223fdf6 100644 --- a/arch/arm/boot/dts/microchip/sam9x7.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi @@ -983,6 +983,32 @@ pwm0: pwm@f8034000 { status = "disabled"; }; + hlcdc: hlcdc@f8038000 { + compatible = "microchip,sam9x75-xlcdc"; + reg = <0xf8038000 0x4000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>; + clock-names = "periph_clk", "sys_clk", "slow_clk"; + status = "disabled"; + + display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + pwm { + compatible = "atmel,hlcdc-pwm"; + #pwm-cells = <3>; + }; + }; + flx9: flexcom@f8040000 { compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; reg = <0xf8040000 0x200>; From 47b77557d3beb748c505ffd4cc378725f7c495c5 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Tue, 17 Jun 2025 09:08:40 -0700 Subject: [PATCH 08/22] ARM: dts: microchip: sama7g5: Adjust clock xtal phandle Adjust clock xtal phandles to match the new xtal phandle formatting. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/8a9ece664958d07b1be73b4b6676a2a2ee397a94.1750175453.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 18 ++++++++---------- arch/arm/boot/dts/microchip/sama7g5.dtsi | 9 ++++++--- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts index 2543599013b1..3924f62ff0fb 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts @@ -35,16 +35,6 @@ aliases { i2c2 = &i2c9; }; - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <24000000>; - }; - }; - gpio-keys { compatible = "gpio-keys"; @@ -556,6 +546,10 @@ &i2s0 { pinctrl-0 = <&pinctrl_i2s0_default>; }; +&main_xtal { + clock-frequency = <24000000>; +}; + &pdmc0 { #sound-dai-cells = <0>; microchip,mic-pos = , /* MIC 1 */ @@ -885,6 +879,10 @@ input@0 { }; }; +&slow_xtal { + clock-frequency = <32768>; +}; + &spdifrx { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spdifrx_default>; diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi index 17bcdcf0cf4a..e128074137e0 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -117,19 +117,22 @@ map1 { }; clocks { - slow_xtal: slow_xtal { + slow_xtal: clock-slowxtal { compatible = "fixed-clock"; + clock-output-names = "slow_xtal"; #clock-cells = <0>; }; - main_xtal: main_xtal { + main_xtal: clock-mainxtal { compatible = "fixed-clock"; + clock-output-names = "main_xtal"; #clock-cells = <0>; }; - usb_clk: usb_clk { + usb_clk: clock-usbclk { compatible = "fixed-clock"; #clock-cells = <0>; + clock-output-names = "usb_clk"; clock-frequency = <48000000>; }; }; From 0029468132ba2e00a3010865038783d9b2e6cc07 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Tue, 17 Jun 2025 09:08:41 -0700 Subject: [PATCH 09/22] ARM: dts: microchip: sama7d65: Add clock name property Add clock-output-names to the xtal nodes, so the driver can correctly register the main and slow xtal. This fixes the issue of the SoC clock driver not being able to find the main xtal and slow xtal correctly causing a bad clock tree. Fixes: 261dcfad1b59 ("ARM: dts: microchip: add sama7d65 SoC DT") Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/3878ae6d0016d46f0c91bd379146d575d5d336aa.1750175453.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index a62d2ef9fcab..7f3d67099b7d 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -38,11 +38,13 @@ cpu0: cpu@0 { clocks { main_xtal: clock-mainxtal { compatible = "fixed-clock"; + clock-output-names = "main_xtal"; #clock-cells = <0>; }; slow_xtal: clock-slowxtal { compatible = "fixed-clock"; + clock-output-names = "slow_xtal"; #clock-cells = <0>; }; }; From 2e24723492b28ffdccb0e3e68725673e299e3823 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Tue, 17 Jun 2025 09:08:42 -0700 Subject: [PATCH 10/22] ARM: dts: microchip: sam9x7: Add clock name property Add clock-output-names to the xtal nodes, so the driver can correctly register the main and slow xtal. This fixes the issue of the SoC clock driver not being able to find the main xtal and slow xtal correctly causing a bad clock tree. Fixes: 41af45af8bc3 ("ARM: dts: at91: sam9x7: add device tree for SoC") Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/036518968ac657b93e315bb550b822b59ae6f17c.1750175453.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sam9x7.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi index 2c8ab223fdf6..2063507d0c50 100644 --- a/arch/arm/boot/dts/microchip/sam9x7.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi @@ -45,11 +45,13 @@ cpu@0 { clocks { slow_xtal: clock-slowxtal { compatible = "fixed-clock"; + clock-output-names = "slow_xtal"; #clock-cells = <0>; }; main_xtal: clock-mainxtal { compatible = "fixed-clock"; + clock-output-names = "main_xtal"; #clock-cells = <0>; }; }; From 7c0650f1f95fa0b72d47214458f68d26732128aa Mon Sep 17 00:00:00 2001 From: Ezra Buehler Date: Thu, 12 Jun 2025 09:47:37 +0200 Subject: [PATCH 11/22] ARM: dts: microchip: gardena-smart-gateway: Fix power LED When starting up, the GARDENA smart Gateway's power LED should be flashing green. It is unclear why this has not been done earlier. The LED frequency cannot be configured in the devicetree. Luckily, the default is 1 Hz, which is what we want. Signed-off-by: Ezra Buehler Link: https://lore.kernel.org/r/20250612074737.311346-1-ezra@easyb.ch Signed-off-by: Claudiu Beznea --- .../boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts b/arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts index e0c1e8df81b1..947c011c1b00 100644 --- a/arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts +++ b/arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts @@ -46,7 +46,7 @@ led-power-blue { led-power-green { label = "smartgw:power:green"; gpios = <&pioC 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; + linux,default-trigger = "timer"; }; led-power-red { From 51860eebc98fc7fbd110c781ca33898f7a305627 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 17 Jun 2025 11:05:01 -0300 Subject: [PATCH 12/22] ARM: dts: at91-sama5d27_wlsom1: Improve the Wifi compatible The at91-sama5d27_wlsom1 SoM has a WIL3000 Wifi SDIO device populated. Improve the description of the Wifi compatible string by passing the more specific "microchip,wilc3000" string. Signed-off-by: Fabio Estevam Reviewed-by: Claudiu Beznea Link: https://lore.kernel.org/r/20250617140502.1042812-1-festevam@gmail.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi index ef11606a82b3..e35dd79beb16 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi @@ -385,7 +385,7 @@ &sdmmc1 { wilc: wifi@0 { reg = <0>; - compatible = "microchip,wilc1000"; + compatible = "microchip,wilc3000", "microchip,wilc1000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wilc_default>; clocks = <&pmc PMC_TYPE_SYSTEM 9>; From 55fae6f3e5723557ade88d8d19f9244cf65bcabf Mon Sep 17 00:00:00 2001 From: Manikandan Muralidharan Date: Wed, 21 May 2025 11:13:06 +0530 Subject: [PATCH 13/22] ARM: dts: microchip: sam9x60ek: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 2c0a1faa4da5 ("ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan Reviewed-by: Alexander Dahl Link: https://lore.kernel.org/r/20250521054309.361894-1-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/at91-sam9x60ek.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/microchip/at91-sam9x60ek.dts b/arch/arm/boot/dts/microchip/at91-sam9x60ek.dts index cdc56b53299d..c1ff3248bd8f 100644 --- a/arch/arm/boot/dts/microchip/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sam9x60ek.dts @@ -609,7 +609,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <104000000>; - spi-cs-setup-ns = <7>; + spi-cs-setup-delay-ns = <7>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read; From 71c6dc93e96af8a6a755dc6c0f393fbbf07e7a54 Mon Sep 17 00:00:00 2001 From: Manikandan Muralidharan Date: Wed, 21 May 2025 11:13:07 +0530 Subject: [PATCH 14/22] ARM: dts: microchip: sama5d27_som1: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 09ce8651229b ("ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan Reviewed-by: Alexander Dahl Reviewed-by: Claudiu Beznea Link: https://lore.kernel.org/r/20250521054309.361894-2-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi index 8ac85dac5a96..13c28e92b17e 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi @@ -44,7 +44,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <104000000>; - spi-cs-setup-ns = <7>; + spi-cs-setup-delay-ns = <7>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read; From fa664ff76e79cf72d33c62343f6597c796273ba6 Mon Sep 17 00:00:00 2001 From: Manikandan Muralidharan Date: Wed, 21 May 2025 11:13:08 +0530 Subject: [PATCH 15/22] ARM: dts: microchip: sama5d27_wlsom1: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 417e58ea41ab ("ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan Reviewed-by: Claudiu Beznea Link: https://lore.kernel.org/r/20250521054309.361894-3-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi index e35dd79beb16..0417f53b3e96 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi @@ -234,7 +234,7 @@ qspi1_flash: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <104000000>; - spi-cs-setup-ns = <7>; + spi-cs-setup-delay-ns = <7>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; m25p,fast-read; From 5b4522098bdb22aaa60710e9eba44967d028fe15 Mon Sep 17 00:00:00 2001 From: Manikandan Muralidharan Date: Wed, 21 May 2025 11:13:09 +0530 Subject: [PATCH 16/22] ARM: dts: microchip: sama5d2_icp: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 46a8a137d8f6 ("ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan Reviewed-by: Claudiu Beznea Link: https://lore.kernel.org/r/20250521054309.361894-4-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts index 9fa6f1395aa6..fbae6a9af6c3 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts @@ -714,7 +714,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <104000000>; - spi-cs-setup-ns = <7>; + spi-cs-setup-delay-ns = <7>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read; From 7360dab3beadeeea48c2c314d48a290cb7a22398 Mon Sep 17 00:00:00 2001 From: Dharma Balasubiramani Date: Wed, 25 Jun 2025 14:38:45 +0530 Subject: [PATCH 17/22] ARM: dts: microchip: sam9x7: Add LVDS controller Add support for LVDS controller. Signed-off-by: Dharma Balasubiramani Link: https://lore.kernel.org/r/20250625-b4-sam9x7-dts-v1-1-92aaee14ed16@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sam9x7.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi index 2063507d0c50..66c07e642c3e 100644 --- a/arch/arm/boot/dts/microchip/sam9x7.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi @@ -1115,6 +1115,15 @@ AT91_XDMAC_DT_PER_IF(1) | }; }; + lvds_controller: lvds-controller@f8060000 { + compatible = "microchip,sam9x75-lvds"; + reg = <0xf8060000 0x100>; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names = "pclk"; + status = "disabled"; + }; + matrix: matrix@ffffde00 { compatible = "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon"; reg = <0xffffde00 0x200>; From ab435d1265e9667c49b91210ef1162a9fb928580 Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Wed, 25 Jun 2025 09:49:32 +0300 Subject: [PATCH 18/22] ARM: dts: microchip: sama5d2: Update the cache configuration for CPU Add the memory size properties for L1 and L2 according with block diagram from datasheet: - L1 cache configuration with 32 KB for both data and instruction cache. - L2 cache configuration with 128 KB unified cache. [root@sama5d2 ~]$ lscpu Architecture: armv7l Byte Order: Little Endian CPU(s): 1 On-line CPU(s) list: 0 Vendor ID: ARM Model name: Cortex-A5 Caches (sum of all): L1d: 32 KiB (1 instance) L1i: 32 KiB (1 instance) L2: 128 KiB (1 instance) Signed-off-by: Mihai Sain Link: https://lore.kernel.org/r/20250625064934.4828-2-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama5d2.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama5d2.dtsi b/arch/arm/boot/dts/microchip/sama5d2.dtsi index dc22fb679333..17430d7f2055 100644 --- a/arch/arm/boot/dts/microchip/sama5d2.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d2.dtsi @@ -32,6 +32,8 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a5"; reg = <0>; + d-cache-size = <0x8000>; // L1, 32 KB + i-cache-size = <0x8000>; // L1, 32 KB next-level-cache = <&L2>; }; }; @@ -160,6 +162,7 @@ L2: cache-controller@a00000 { interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; cache-unified; cache-level = <2>; + cache-size = <0x20000>; // L2, 128 KB }; ebi: ebi@10000000 { From 31a820245903f75e6f5d908561fe5d3eab94f057 Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Wed, 25 Jun 2025 09:49:33 +0300 Subject: [PATCH 19/22] ARM: dts: microchip: sama5d3: Update the cache configuration for CPU Add the memory size properties for L1 according with block diagram from datasheet: - L1 cache configuration with 32 KB for both data and instruction cache. [root@sama5d3 ~]$ lscpu Architecture: armv7l Byte Order: Little Endian CPU(s): 1 On-line CPU(s) list: 0 Vendor ID: ARM Model name: Cortex-A5 Caches (sum of all): L1d: 32 KiB (1 instance) L1i: 32 KiB (1 instance) Signed-off-by: Mihai Sain Link: https://lore.kernel.org/r/20250625064934.4828-3-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama5d3.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama5d3.dtsi b/arch/arm/boot/dts/microchip/sama5d3.dtsi index e95799c17fdb..00ba59ac1968 100644 --- a/arch/arm/boot/dts/microchip/sama5d3.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d3.dtsi @@ -48,6 +48,8 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a5"; reg = <0x0>; + d-cache-size = <0x8000>; // L1, 32 KB + i-cache-size = <0x8000>; // L1, 32 KB }; }; From 1e2e0ed390cc3c074817b2026a59da008b6cd2a6 Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Wed, 25 Jun 2025 09:49:34 +0300 Subject: [PATCH 20/22] ARM: dts: microchip: sama5d4: Update the cache configuration for CPU Add the memory size properties for L1 and L2 according with block diagram from datasheet: - L1 cache configuration with 32 KB for both data and instruction cache. - L2 cache configuration with 128 KB unified cache. [root@sama5d4 ~]$ lscpu Architecture: armv7l Byte Order: Little Endian CPU(s): 1 On-line CPU(s) list: 0 Vendor ID: ARM Model name: Cortex-A5 Caches (sum of all): L1d: 32 KiB (1 instance) L1i: 32 KiB (1 instance) L2: 128 KiB (1 instance) Signed-off-by: Mihai Sain Link: https://lore.kernel.org/r/20250625064934.4828-4-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama5d4.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama5d4.dtsi b/arch/arm/boot/dts/microchip/sama5d4.dtsi index 59a7d557c7cb..ec1d68c640de 100644 --- a/arch/arm/boot/dts/microchip/sama5d4.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d4.dtsi @@ -50,6 +50,8 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a5"; reg = <0>; + d-cache-size = <0x8000>; // L1, 32 KB + i-cache-size = <0x8000>; // L1, 32 KB next-level-cache = <&L2>; }; }; @@ -143,6 +145,7 @@ L2: cache-controller@a00000 { interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; cache-unified; cache-level = <2>; + cache-size = <0x20000>; // L2, 128 KB }; ebi: ebi@10000000 { From 4101c8274b093519019761e174c81980f7b30f56 Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Thu, 19 Jun 2025 10:06:35 +0300 Subject: [PATCH 21/22] ARM: dts: microchip: sama7d65: Add cache configuration for cpu node Describe the cache memories according with datasheet chapter 15.2: - L1 cache configuration with 32KB for both data and instruction cache. - L2 cache configuration with 256KB unified cache. Before this patch the kernel reported the warning: [ 0.161955] cacheinfo: Unable to detect cache hierarchy for CPU 0 Signed-off-by: Mihai Sain Link: https://lore.kernel.org/r/20250619070636.8844-2-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 7f3d67099b7d..c191acc2c89f 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -32,6 +32,16 @@ cpu0: cpu@0 { device_type = "cpu"; clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; clock-names = "cpu"; + d-cache-size = <0x8000>; // L1, 32 KB + i-cache-size = <0x8000>; // L1, 32 KB + next-level-cache = <&L2>; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; // L2, 256 KB + cache-unified; + }; }; }; From 314862edb13d52c481ecc330c9d3fec0507cd9bb Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Thu, 19 Jun 2025 10:06:36 +0300 Subject: [PATCH 22/22] ARM: dts: microchip: sama7g5: Add cache configuration for cpu node Describe the cache memories according with datasheet chapter 15.2: - L1 cache configuration with 32KB for both data and instruction cache. - L2 cache configuration with 256KB unified cache. Before this patch the kernel reported the warning: [ 0.171425] cacheinfo: Unable to detect cache hierarchy for CPU 0 Signed-off-by: Mihai Sain Link: https://lore.kernel.org/r/20250619070636.8844-3-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7g5.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi index e128074137e0..381cbcfcb34a 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -38,6 +38,16 @@ cpu0: cpu@0 { clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ + d-cache-size = <0x8000>; // L1, 32 KB + i-cache-size = <0x8000>; // L1, 32 KB + next-level-cache = <&L2>; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; // L2, 256 KB + cache-unified; + }; }; };