drm/amdgpu: Add per-ASIC PTE init flag

On GFX12.1, default PTE setup needs an additional bit to be
set. Add PTE initialization flags to handle setup default PTE
on a per-ASIC basis.
While at it, fixup the coding style too.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mukul Joshi 2025-04-24 21:51:23 -04:00 committed by Alex Deucher
parent 5056b75fed
commit db29ddf650
3 changed files with 4 additions and 2 deletions

View File

@ -356,6 +356,7 @@ struct amdgpu_gmc {
u64 MC_VM_MX_L1_TLB_CNTL;
u64 noretry_flags;
u64 init_pte_flags;
bool flush_tlb_needs_extra_type_0;
bool flush_tlb_needs_extra_type_2;

View File

@ -367,6 +367,7 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,
struct amdgpu_bo *ancestor = &vmbo->bo;
unsigned int entries;
struct amdgpu_bo *bo = &vmbo->bo;
uint64_t value = 0, flags = 0;
uint64_t addr;
int r, idx;
@ -404,7 +405,6 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,
addr = 0;
uint64_t value = 0, flags = 0;
if (adev->asic_type >= CHIP_VEGA10) {
if (level != AMDGPU_VM_PTB) {
/* Handle leaf PDEs as PTEs */
@ -413,7 +413,7 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,
&value, &flags);
} else {
/* Workaround for fault priority problem on GMC9 */
flags = AMDGPU_PTE_EXECUTABLE;
flags = AMDGPU_PTE_EXECUTABLE | adev->gmc.init_pte_flags;
}
}

View File

@ -656,6 +656,7 @@ static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block)
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
case IP_VERSION(12, 1, 0):
gmc_v12_1_set_gmc_funcs(adev);
adev->gmc.init_pte_flags = AMDGPU_PTE_IS_PTE;
break;
default:
gmc_v12_0_set_gmc_funcs(adev);