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drm/amdgpu: Add gmc v12_1 gmc callbacks
Implement gmc v12_1 gmc callbacks v2: revert temporary PDE MTYPE to UC setting Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang
Alex Deucher
parent
036c0e38bb
commit
5056b75fed
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@ -105,7 +105,7 @@ amdgpu-y += \
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mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o \
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mmhub_v3_0_1.o gfxhub_v3_0_3.o gfxhub_v1_2.o mmhub_v1_8.o mmhub_v3_3.o \
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gfxhub_v11_5_0.o mmhub_v4_1_0.o gfxhub_v12_0.o gmc_v12_0.o \
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mmhub_v4_2_0.o gfxhub_v12_1.o
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mmhub_v4_2_0.o gfxhub_v12_1.o gmc_v12_1.o
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# add UMC block
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amdgpu-y += \
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@ -28,6 +28,7 @@
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#include "amdgpu.h"
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#include "amdgpu_atomfirmware.h"
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#include "gmc_v12_0.h"
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#include "gmc_v12_1.h"
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#include "athub/athub_4_1_0_sh_mask.h"
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#include "athub/athub_4_1_0_offset.h"
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#include "oss/osssys_7_0_0_offset.h"
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@ -652,9 +653,16 @@ static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
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case IP_VERSION(12, 1, 0):
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gmc_v12_1_set_gmc_funcs(adev);
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break;
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default:
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gmc_v12_0_set_gmc_funcs(adev);
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break;
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}
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gmc_v12_0_set_gfxhub_funcs(adev);
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gmc_v12_0_set_mmhub_funcs(adev);
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gmc_v12_0_set_gmc_funcs(adev);
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gmc_v12_0_set_irq_funcs(adev);
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gmc_v12_0_set_umc_funcs(adev);
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323
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
Normal file
323
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
Normal file
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@ -0,0 +1,323 @@
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "gmc_v12_1.h"
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#include "soc15_common.h"
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#include "soc_v1_0_enum.h"
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#include "oss/osssys_7_1_0_offset.h"
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#include "oss/osssys_7_1_0_sh_mask.h"
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static bool gmc_v12_1_get_vmid_pasid_mapping_info(struct amdgpu_device *adev,
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uint8_t vmid, uint16_t *p_pasid)
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{
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*p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;
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return !!(*p_pasid);
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}
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/*
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* GART
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* VMID 0 is the physical GPU addresses as used by the kernel.
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* VMIDs 1-15 are used for userspace clients and are handled
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* by the amdgpu vm/hsa code.
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*/
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static void gmc_v12_1_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
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unsigned int vmhub, uint32_t flush_type)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
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u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
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u32 tmp;
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/* Use register 17 for GART */
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const unsigned eng = 17;
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unsigned int i;
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unsigned char hub_ip = 0;
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hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ?
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GC_HWIP : MMHUB_HWIP;
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spin_lock(&adev->gmc.invalidate_lock);
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WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip);
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/* Wait for ACK with a delay.*/
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
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hub->eng_distance * eng, hub_ip);
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tmp &= 1 << vmid;
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if (tmp)
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break;
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udelay(1);
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}
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/* Issue additional private vm invalidation to MMHUB */
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if ((vmhub != AMDGPU_GFXHUB(0)) &&
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(hub->vm_l2_bank_select_reserved_cid2) &&
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!amdgpu_sriov_vf(adev)) {
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inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
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/* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */
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inv_req |= (1 << 25);
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/* Issue private invalidation */
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WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req);
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/* Read back to ensure invalidation is done*/
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RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
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}
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spin_unlock(&adev->gmc.invalidate_lock);
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if (i < adev->usec_timeout)
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return;
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dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n");
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}
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/**
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* gmc_v12_1_flush_gpu_tlb - gart tlb flush callback
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*
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* @adev: amdgpu_device pointer
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* @vmid: vm instance to flush
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* @vmhub: which hub to flush
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* @flush_type: the flush type
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*
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* Flush the TLB for the requested page table.
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*/
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static void gmc_v12_1_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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uint32_t vmhub, uint32_t flush_type)
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{
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if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron)
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return;
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/* This is necessary for SRIOV as well as for GFXOFF to function
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* properly under bare metal
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*/
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if (((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring[0].sched.ready) &&
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(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)))) {
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struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
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const unsigned eng = 17;
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u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
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u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
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u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
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amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,
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1 << vmid, GET_INST(GC, 0));
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return;
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}
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mutex_lock(&adev->mman.gtt_window_lock);
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gmc_v12_1_flush_vm_hub(adev, vmid, vmhub, 0);
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mutex_unlock(&adev->mman.gtt_window_lock);
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return;
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}
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/**
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* gmc_v12_1_flush_gpu_tlb_pasid - tlb flush via pasid
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*
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* @adev: amdgpu_device pointer
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* @pasid: pasid to be flush
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* @flush_type: the flush type
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* @all_hub: flush all hubs
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* @inst: is used to select which instance of KIQ to use for the invalidation
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*
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* Flush the TLB for the requested pasid.
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*/
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static void gmc_v12_1_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
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uint16_t pasid, uint32_t flush_type,
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bool all_hub, uint32_t inst)
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{
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uint16_t queried;
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int vmid, i;
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for (vmid = 1; vmid < 16; vmid++) {
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bool valid;
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valid = gmc_v12_1_get_vmid_pasid_mapping_info(adev, vmid,
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&queried);
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if (!valid || queried != pasid)
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continue;
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if (all_hub) {
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for_each_set_bit(i, adev->vmhubs_mask,
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AMDGPU_MAX_VMHUBS)
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gmc_v12_1_flush_gpu_tlb(adev, vmid, i,
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flush_type);
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} else {
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gmc_v12_1_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0),
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flush_type);
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}
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}
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}
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static uint64_t gmc_v12_1_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
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unsigned vmid, uint64_t pd_addr)
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{
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
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uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
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unsigned eng = ring->vm_inv_eng;
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amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
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(hub->ctx_addr_distance * vmid),
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lower_32_bits(pd_addr));
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amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
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(hub->ctx_addr_distance * vmid),
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upper_32_bits(pd_addr));
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amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
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hub->eng_distance * eng,
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hub->vm_inv_eng0_ack +
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hub->eng_distance * eng,
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req, 1 << vmid);
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return pd_addr;
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}
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static void gmc_v12_1_emit_pasid_mapping(struct amdgpu_ring *ring,
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unsigned vmid, unsigned pasid)
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{
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struct amdgpu_device *adev = ring->adev;
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uint32_t reg;
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if (ring->vm_hub == AMDGPU_GFXHUB(0))
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reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid;
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else
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reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid;
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amdgpu_ring_emit_wreg(ring, reg, pasid);
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}
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/*
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* PTE format:
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* 63 P
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* 62:59 reserved
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* 58 D
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* 57 G
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* 56 T
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* 55:54 M
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* 53:52 SW
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* 51:48 reserved for future
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* 47:12 4k physical page base address
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* 11:7 fragment
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* 6 write
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* 5 read
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* 4 exe
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* 3 Z
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* 2 snooped
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* 1 system
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* 0 valid
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*
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* PDE format:
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* 63 P
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* 62:58 block fragment size
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* 57 reserved
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* 56 A
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* 55:54 M
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* 53:52 reserved
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* 51:48 reserved for future
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* 47:6 physical base address of PD or PTE
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* 5:3 reserved
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* 2 C
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* 1 system
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* 0 valid
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*/
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static void gmc_v12_1_get_vm_pde(struct amdgpu_device *adev, int level,
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uint64_t *addr, uint64_t *flags)
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{
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if (!(*flags & AMDGPU_PDE_PTE_GFX12) && !(*flags & AMDGPU_PTE_SYSTEM))
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*addr = adev->vm_manager.vram_base_offset + *addr -
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adev->gmc.vram_start;
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BUG_ON(*addr & 0xFFFF00000000003FULL);
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if (!adev->gmc.translate_further)
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return;
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if (level == AMDGPU_VM_PDB1) {
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/* Set the block fragment size */
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if (!(*flags & AMDGPU_PDE_PTE_GFX12))
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*flags |= AMDGPU_PDE_BFS_GFX12(0x9);
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} else if (level == AMDGPU_VM_PDB0) {
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if (*flags & AMDGPU_PDE_PTE_GFX12)
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*flags &= ~AMDGPU_PDE_PTE_GFX12;
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}
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}
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static void gmc_v12_1_get_vm_pte(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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struct amdgpu_bo *bo,
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uint32_t vm_flags,
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uint64_t *flags)
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{
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if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE)
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*flags |= AMDGPU_PTE_EXECUTABLE;
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else
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*flags &= ~AMDGPU_PTE_EXECUTABLE;
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switch (vm_flags & AMDGPU_VM_MTYPE_MASK) {
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case AMDGPU_VM_MTYPE_DEFAULT:
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*flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC);
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break;
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case AMDGPU_VM_MTYPE_NC:
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default:
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*flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC);
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break;
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case AMDGPU_VM_MTYPE_UC:
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*flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC);
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break;
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}
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if (vm_flags & AMDGPU_VM_PAGE_NOALLOC)
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*flags |= AMDGPU_PTE_NOALLOC;
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else
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*flags &= ~AMDGPU_PTE_NOALLOC;
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if (vm_flags & AMDGPU_VM_PAGE_PRT) {
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*flags |= AMDGPU_PTE_SNOOPED;
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*flags |= AMDGPU_PTE_SYSTEM;
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*flags |= AMDGPU_PTE_IS_PTE;
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*flags &= ~AMDGPU_PTE_VALID;
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}
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if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
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AMDGPU_GEM_CREATE_EXT_COHERENT |
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AMDGPU_GEM_CREATE_UNCACHED))
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*flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC);
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if (bo && bo->flags & AMDGPU_GEM_CREATE_UNCACHED)
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*flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC);
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}
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static const struct amdgpu_gmc_funcs gmc_v12_1_gmc_funcs = {
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.flush_gpu_tlb = gmc_v12_1_flush_gpu_tlb,
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.flush_gpu_tlb_pasid = gmc_v12_1_flush_gpu_tlb_pasid,
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.emit_flush_gpu_tlb = gmc_v12_1_emit_flush_gpu_tlb,
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.emit_pasid_mapping = gmc_v12_1_emit_pasid_mapping,
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.get_vm_pde = gmc_v12_1_get_vm_pde,
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.get_vm_pte = gmc_v12_1_get_vm_pte,
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};
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void gmc_v12_1_set_gmc_funcs(struct amdgpu_device *adev)
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{
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adev->gmc.gmc_funcs = &gmc_v12_1_gmc_funcs;
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}
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29
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.h
Normal file
29
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.h
Normal file
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@ -0,0 +1,29 @@
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
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*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __GMC_V12_1_H__
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#define __GMC_V12_1_H__
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void gmc_v12_1_set_gmc_funcs(struct amdgpu_device *adev);
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#endif
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