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video: rockchip: remove unused fb driver

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Change-Id: I13be9d40d44c2c3ed0bb9abf186410bf39636ec6
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This commit is contained in:
Tao Huang 2019-09-09 17:54:12 +08:00
parent bbabed05f0
commit d96d147740
57 changed files with 0 additions and 50060 deletions
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389
drivers/video/rockchip/bmp_helper.c
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@ -1,389 +0,0 @@
/*
* linux/drivers/video/rockchip/bmp_helper.c
*
* Copyright (C) 2012 Rockchip Corporation
* Author: Mark Yao <mark.yao@rock-chips.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/sysfs.h>
#include <linux/uaccess.h>
#include <linux/kernel.h>
#include <linux/rk_fb.h>
#include "bmp_helper.h"
static void draw_unencoded_bitmap(uint16_t **dst, uint8_t *bmap, uint16_t *cmap,
uint32_t cnt)
{
while (cnt > 0) {
*(*dst)++ = cmap[*bmap++];
cnt--;
}
}
static void draw_encoded_bitmap(uint16_t **dst, uint16_t c, uint32_t cnt)
{
uint16_t *fb = *dst;
int cnt_8copy = cnt >> 3;
cnt -= cnt_8copy << 3;
while (cnt_8copy > 0) {
*fb++ = c;
*fb++ = c;
*fb++ = c;
*fb++ = c;
*fb++ = c;
*fb++ = c;
*fb++ = c;
*fb++ = c;
cnt_8copy--;
}
while (cnt > 0) {
*fb++ = c;
cnt--;
}
*dst = fb;
}
static void yuv_to_rgb(int y, int u, int v, int *r, int *g, int *b)
{
int rdif, invgdif, bdif;
u -= 128;
v -= 128;
rdif = v + ((v * 103) >> 8);
invgdif = ((u * 88) >> 8) + ((v * 183) >> 8);
bdif = u + ((u*198) >> 8);
*r = range(y + rdif, 0, 0xff);
*g = range(y - invgdif, 0, 0xff);
*b = range(y + bdif, 0, 0xff);
}
int bmpencoder(void *__iomem *vaddr, int width, int height, u8 data_format,
void *data, void (*fn)(void *, void *, int))
{
uint32_t *d = NULL, *d1 = NULL, *d2 = NULL;
uint8_t *dst = NULL, *yrgb = NULL, *uv = NULL, *y1 = NULL, *y2 = NULL;
int y = 0, u = 0, v = 0, r = 0, g = 0, b = 0;
int yu = width * 4 % 4;
int byteperline;
unsigned int size;
BITMAPHEADER header;
BITMAPINFOHEADER infoheader;
void *buf;
int i, j;
yu = yu != 0 ? 4 - yu : yu;
byteperline = width * 4 + yu;
size = byteperline * height + 54;
memset(&header, 0, sizeof(header));
memset(&infoheader, 0, sizeof(infoheader));
header.type = 'M'<<8|'B';
header.size = size;
header.offset = 54;
infoheader.size = 40;
infoheader.width = width;
infoheader.height = 0 - height;
infoheader.bitcount = 4 * 8;
infoheader.compression = 0;
infoheader.imagesize = byteperline * height;
infoheader.xpelspermeter = 0;
infoheader.ypelspermeter = 0;
infoheader.colors = 0;
infoheader.colorsimportant = 0;
fn(data, (void *)&header, sizeof(header));
fn(data, (void *)&infoheader, sizeof(infoheader));
/*
* if data_format is ARGB888 or XRGB888, not need convert.
*/
if (data_format == ARGB888 || data_format == XRGB888) {
fn(data, (char *)vaddr, width * height * 4);
return 0;
}
/*
* alloc 2 line buffer.
*/
buf = kmalloc(width * 2 * 4, GFP_KERNEL);
if (!buf)
return -ENOMEM;
yrgb = (uint8_t *)vaddr;
uv = yrgb + width * height;
for (j = 0; j < height; j++) {
if (j % 2 == 0) {
dst = buf;
y1 = yrgb + j * width;
y2 = y1 + width;
d1 = buf;
d2 = d1 + width;
}
for (i = 0; i < width; i++) {
switch (data_format) {
case XBGR888:
case ABGR888:
dst[0] = yrgb[2];
dst[1] = yrgb[1];
dst[2] = yrgb[0];
dst[3] = yrgb[3];
dst += 4;
yrgb += 4;
break;
case RGB888:
dst[0] = yrgb[0];
dst[1] = yrgb[1];
dst[2] = yrgb[2];
dst[3] = 0xff;
dst += 4;
yrgb += 3;
break;
case RGB565:
dst[0] = (yrgb[0] & 0x1f) << 3;
dst[1] = (yrgb[0] & 0xe0) >> 3 |
(yrgb[1] & 0x7) << 5;
dst[2] = yrgb[1] & 0xf8;
dst[3] = 0xff;
dst += 4;
yrgb += 2;
break;
case YUV420:
case YUV422:
case YUV444:
if (data_format == YUV420) {
if (i % 2 == 0) {
d = d1++;
y = *y1++;
} else {
d = d2++;
y = *y2++;
}
if (i % 4 == 0) {
u = *uv++;
v = *uv++;
}
} else if (data_format == YUV422) {
if (i % 2 == 0) {
u = *uv++;
v = *uv++;
}
d = d1++;
} else {
u = *uv++;
v = *uv++;
d = d1++;
}
yuv_to_rgb(y, u, v, &r, &g, &b);
*d = 0xff<<24 | r << 16 | g << 8 | b;
break;
case YUV422_A:
case YUV444_A:
default:
pr_err("unsupport now\n");
return -EINVAL;
}
}
if (j % 2 == 1)
fn(data, (char *)buf, 2 * width * 4);
}
return 0;
}
static void decode_rle8_bitmap(uint8_t *psrc, uint8_t *pdst, uint16_t *cmap,
unsigned int width, unsigned int height,
int bits, int x_off, int y_off, bool flip)
{
uint32_t cnt, runlen;
int x = 0, y = 0;
int decode = 1;
uint8_t *bmap = psrc;
uint8_t *dst = pdst;
int linesize = width * 2;
if (flip) {
y = height - 1;
dst = pdst + y * linesize;
}
while (decode) {
if (bmap[0] == BMP_RLE8_ESCAPE) {
switch (bmap[1]) {
case BMP_RLE8_EOL:
/* end of line */
bmap += 2;
x = 0;
if (flip) {
y--;
dst -= linesize * 2;
} else {
y++;
}
break;
case BMP_RLE8_EOBMP:
/* end of bitmap */
decode = 0;
break;
case BMP_RLE8_DELTA:
/* delta run */
x += bmap[2];
if (flip) {
y -= bmap[3];
dst -= bmap[3] * linesize;
dst += bmap[2] * 2;
} else {
y += bmap[3];
dst += bmap[3] * linesize;
dst += bmap[2] * 2;
}
bmap += 4;
break;
default:
/* unencoded run */
runlen = bmap[1];
bmap += 2;
if (y >= height || x >= width) {
decode = 0;
break;
}
if (x + runlen > width)
cnt = width - x;
else
cnt = runlen;
draw_unencoded_bitmap((uint16_t **)&dst, bmap,
cmap, cnt);
x += runlen;
bmap += runlen;
if (runlen & 1)
bmap++;
}
} else {
/* encoded run */
if (y < height) {
runlen = bmap[0];
if (x < width) {
/* aggregate the same code */
while (bmap[0] == 0xff &&
bmap[2] != BMP_RLE8_ESCAPE &&
bmap[1] == bmap[3]) {
runlen += bmap[2];
bmap += 2;
}
if (x + runlen > width)
cnt = width - x;
else
cnt = runlen;
draw_encoded_bitmap((uint16_t **)&dst,
cmap[bmap[1]], cnt);
}
x += runlen;
}
bmap += 2;
}
}
}
int bmpdecoder(void *bmp_addr, void *pdst, int *width, int *height, int *bits)
{
BITMAPHEADER header;
BITMAPINFOHEADER infoheader;
uint16_t *bmp_logo_palette;
uint32_t size;
uint16_t linesize;
int stride;
char *cmap_base;
char *src = bmp_addr;
char *dst = pdst;
int i;
bool flip = false;
memcpy(&header, src, sizeof(header));
src += sizeof(header);
if (header.type != 0x4d42) {
pr_err("not bmp file type[%x], can't support\n", header.type);
return -1;
}
memcpy(&infoheader, src, sizeof(infoheader));
*width = infoheader.width;
*height = infoheader.height;
if (*height < 0)
*height = 0 - *height;
else
flip = true;
size = header.size - header.offset;
linesize = *width * infoheader.bitcount >> 3;
cmap_base = src + sizeof(infoheader);
src = bmp_addr + header.offset;
switch (infoheader.bitcount) {
case 8:
bmp_logo_palette = kmalloc(sizeof(bmp_logo_palette) * 256, GFP_KERNEL);
/* Set color map */
for (i = 0; i < 256; i++) {
ushort colreg = ((cmap_base[2] << 8) & 0xf800) |
((cmap_base[1] << 3) & 0x07e0) |
((cmap_base[0] >> 3) & 0x001f) ;
cmap_base += 4;
bmp_logo_palette[i] = colreg;
}
/*
* only support convert 8bit bmap file to RGB565.
*/
decode_rle8_bitmap(src, dst, bmp_logo_palette,
infoheader.width, infoheader.height,
infoheader.bitcount, 0, 0, flip);
kfree(bmp_logo_palette);
*bits = 16;
break;
case 16:
/*
* Todo
*/
pr_info("unsupport bit=%d now\n", infoheader.bitcount);
break;
case 24:
stride = ALIGN(*width * 3, 4);
if (flip)
src += stride * (*height - 1);
for (i = 0; i < *height; i++) {
memcpy(dst, src, 3 * (*width));
dst += stride;
src += stride;
if (flip)
src -= stride * 2;
}
*bits = 24;
break;
case 32:
/*
* Todo
*/
pr_info("unsupport bit=%d now\n", infoheader.bitcount);
break;
default:
pr_info("unsupport bit=%d now\n", infoheader.bitcount);
break;
}
return 0;
}

54
drivers/video/rockchip/bmp_helper.h
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@ -1,54 +0,0 @@
/*
* drivers/video/rockchip/bmp_helper.h
*
* Copyright (C) 2012 Rockchip Corporation
* Author: Mark Yao <mark.yao@rock-chips.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _BMP_HELPER_H_
#define _BMP_HELPER_H_
typedef struct bmpheader {
unsigned short type;
unsigned int size;
unsigned int reserved;
unsigned int offset;
}__attribute__((packed)) BITMAPHEADER;
typedef struct bmpinfoheader {
unsigned int size;
unsigned int width;
unsigned int height;
unsigned short planes;
unsigned short bitcount;
unsigned int compression;
unsigned int imagesize;
unsigned int xpelspermeter;
unsigned int ypelspermeter;
unsigned int colors;
unsigned int colorsimportant;
}__attribute__((packed)) BITMAPINFOHEADER;
#define BMP_RLE8_ESCAPE 0
#define BMP_RLE8_EOL 0
#define BMP_RLE8_EOBMP 1
#define BMP_RLE8_DELTA 2
#define range(x, min, max) ((x) < (min)) ? (min) : (((x) > (max)) ? (max) : (x))
int bmpencoder(void *__iomem *vaddr,int width, int height, u8 data_format,
void *data, void (*fn)(void *, void *, int));
int bmpdecoder(void *bmp_addr, void *dst, int *width, int *height, int *bits);
#endif /* _BMP_HELPER_H_ */

793
drivers/video/rockchip/display-sys.c
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@ -1,793 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/module.h>
#include <linux/ctype.h>
#include <linux/idr.h>
#include <linux/err.h>
#include <linux/kdev_t.h>
#include <linux/display-sys.h>
static struct list_head main_display_device_list;
static struct list_head aux_display_device_list;
static ssize_t name_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
return snprintf(buf, PAGE_SIZE, "%s\n", dsp->name);
}
static DEVICE_ATTR_RO(name);
static ssize_t type_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
return snprintf(buf, PAGE_SIZE, "%s\n", dsp->type);
}
static DEVICE_ATTR_RO(type);
static ssize_t property_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
return snprintf(buf, PAGE_SIZE, "%d\n", dsp->property);
}
static DEVICE_ATTR_RO(property);
static ssize_t enable_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
int enable;
if (dsp->ops && dsp->ops->getenable)
enable = dsp->ops->getenable(dsp);
else
return 0;
return snprintf(buf, PAGE_SIZE, "%d\n", enable);
}
static ssize_t enable_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
int enable;
if (kstrtoint(buf, 0, &enable))
return size;
if (dsp->ops && dsp->ops->setenable)
dsp->ops->setenable(dsp, enable);
return size;
}
static DEVICE_ATTR_RW(enable);
static ssize_t connect_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
int connect;
if (dsp->ops && dsp->ops->getstatus)
connect = dsp->ops->getstatus(dsp);
else
return 0;
return snprintf(buf, PAGE_SIZE, "%d\n", connect);
}
static DEVICE_ATTR_RO(connect);
static int mode_string(char *buf, unsigned int offset,
const struct fb_videomode *mode)
{
char v = 'p';
if (!buf || !mode) {
pr_err("%s parameter error\n", __func__);
return 0;
}
if (mode->xres == 0 && mode->yres == 0)
return snprintf(&buf[offset], PAGE_SIZE - offset, "auto\n");
if (mode->vmode & FB_VMODE_INTERLACED)
v = 'i';
if (mode->vmode & FB_VMODE_DOUBLE)
v = 'd';
if (mode->flag)
return snprintf(&buf[offset], PAGE_SIZE - offset,
"%dx%d%c-%d(YCbCr420)\n",
mode->xres, mode->yres, v, mode->refresh);
else
return snprintf(&buf[offset], PAGE_SIZE - offset,
"%dx%d%c-%d\n",
mode->xres, mode->yres, v, mode->refresh);
}
static ssize_t modes_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
struct list_head *modelist, *pos;
struct display_modelist *display_modelist;
const struct fb_videomode *mode;
int i;
mutex_lock(&dsp->lock);
if (dsp->ops && dsp->ops->getmodelist) {
if (dsp->ops->getmodelist(dsp, &modelist)) {
mutex_unlock(&dsp->lock);
return -EINVAL;
}
} else {
mutex_unlock(&dsp->lock);
return 0;
}
i = 0;
if (dsp->priority == DISPLAY_PRIORITY_HDMI)
i += snprintf(buf, PAGE_SIZE, "auto\n");
list_for_each(pos, modelist) {
display_modelist = list_entry(pos,
struct display_modelist,
list);
mode = &display_modelist->mode;
i += mode_string(buf, i, mode);
}
mutex_unlock(&dsp->lock);
return i;
}
static DEVICE_ATTR_RO(modes);
static ssize_t mode_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
struct fb_videomode mode;
if (dsp->ops && dsp->ops->getmode)
if (dsp->ops->getmode(dsp, &mode) == 0)
return mode_string(buf, 0, &mode);
return 0;
}
static ssize_t mode_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
char mstr[100];
struct list_head *modelist, *pos;
struct display_modelist *display_modelist;
struct fb_videomode *mode;
size_t i;
mutex_lock(&dsp->lock);
if (!memcmp(buf, "auto", 4)) {
if (dsp->ops && dsp->ops->setmode)
dsp->ops->setmode(dsp, NULL);
mutex_unlock(&dsp->lock);
return count;
}
if (dsp->ops && dsp->ops->getmodelist) {
if (dsp->ops && dsp->ops->getmodelist) {
if (dsp->ops->getmodelist(dsp, &modelist)) {
mutex_unlock(&dsp->lock);
return -EINVAL;
}
}
list_for_each(pos, modelist) {
display_modelist = list_entry(pos,
struct display_modelist,
list);
mode = &display_modelist->mode;
i = mode_string(mstr, 0, mode);
if (strncmp(mstr, buf, max(count, i)) == 0) {
if (dsp->ops && dsp->ops->setmode)
dsp->ops->setmode(dsp, mode);
mutex_unlock(&dsp->lock);
return count;
}
}
}
mutex_unlock(&dsp->lock);
return -EINVAL;
}
static DEVICE_ATTR_RW(mode);
static ssize_t scale_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
int xscale, yscale;
if (dsp->ops && dsp->ops->getscale) {
xscale = dsp->ops->getscale(dsp, DISPLAY_SCALE_X);
yscale = dsp->ops->getscale(dsp, DISPLAY_SCALE_Y);
if (xscale && yscale)
return snprintf(buf, PAGE_SIZE,
"xscale=%d yscale=%d\n",
xscale, yscale);
}
return -EINVAL;
}
static ssize_t scale_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
int scale = 100;
if (dsp->ops && dsp->ops->setscale) {
if (!strncmp(buf, "xscale", 6)) {
if (!kstrtoint(buf, 0, &scale))
dsp->ops->setscale(dsp,
DISPLAY_SCALE_X,
scale);
} else if (!strncmp(buf, "yscale", 6)) {
if (!kstrtoint(buf, 0, &scale))
dsp->ops->setscale(dsp,
DISPLAY_SCALE_Y,
scale);
} else {
if (!kstrtoint(buf, 0, &scale)) {
dsp->ops->setscale(dsp,
DISPLAY_SCALE_X,
scale);
dsp->ops->setscale(dsp,
DISPLAY_SCALE_Y,
scale);
}
}
return count;
}
return -EINVAL;
}
static DEVICE_ATTR_RW(scale);
static ssize_t mode3d_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
struct list_head *modelist, *pos;
struct display_modelist *display_modelist;
struct fb_videomode mode;
int i = 0, cur_3d_mode = -1;
char mode_str[128];
int mode_strlen, format_3d;
mutex_lock(&dsp->lock);
if (dsp->ops && dsp->ops->getmodelist) {
if (dsp->ops->getmodelist(dsp, &modelist)) {
mutex_unlock(&dsp->lock);
return -EINVAL;
}
} else {
mutex_unlock(&dsp->lock);
return 0;
}
if (dsp->ops && dsp->ops->getmode) {
if (dsp->ops->getmode(dsp, &mode)) {
mutex_unlock(&dsp->lock);
return -EINVAL;
}
} else {
mutex_unlock(&dsp->lock);
return 0;
}
list_for_each(pos, modelist) {
display_modelist = list_entry(pos,
struct display_modelist,
list);
if (!fb_mode_is_equal(&mode, &display_modelist->mode))
display_modelist = NULL;
else
break;
}
if (display_modelist)
i = snprintf(buf, PAGE_SIZE, "3dmodes=%d\n",
display_modelist->format_3d);
else
i = snprintf(buf, PAGE_SIZE, "3dmodes=0\n");
if (dsp->ops && dsp->ops->get3dmode)
cur_3d_mode = dsp->ops->get3dmode(dsp);
i += snprintf(buf + i, PAGE_SIZE - i, "cur3dmode=%d\n", cur_3d_mode);
list_for_each(pos, modelist) {
display_modelist = list_entry(pos,
struct display_modelist,
list);
mode_strlen = mode_string(mode_str, 0,
&display_modelist->mode);
mode_str[mode_strlen - 1] = 0;
format_3d = display_modelist->format_3d;
i += snprintf(buf + i, PAGE_SIZE, "%s,%d\n",
mode_str, format_3d);
}
mutex_unlock(&dsp->lock);
return i;
}
static ssize_t mode3d_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
int mode;
mutex_lock(&dsp->lock);
if (dsp->ops && dsp->ops->set3dmode) {
if (!kstrtoint(buf, 0, &mode))
dsp->ops->set3dmode(dsp, mode);
mutex_unlock(&dsp->lock);
return count;
}
mutex_unlock(&dsp->lock);
return -EINVAL;
}
static DEVICE_ATTR_RW(mode3d);
static ssize_t color_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
int ret = 0;
mutex_lock(&dsp->lock);
if (dsp->ops && dsp->ops->getcolor)
ret = dsp->ops->getcolor(dsp, buf);
mutex_unlock(&dsp->lock);
return ret;
}
static ssize_t color_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
mutex_lock(&dsp->lock);
if (dsp->ops && dsp->ops->setcolor) {
if (!dsp->ops->setcolor(dsp, buf, count)) {
mutex_unlock(&dsp->lock);
return count;
}
}
mutex_unlock(&dsp->lock);
return -EINVAL;
}
static DEVICE_ATTR_RW(color);
static ssize_t audioinfo_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
char audioinfo[200];
int ret = 0;
mutex_lock(&dsp->lock);
if (dsp->ops && dsp->ops->getedidaudioinfo) {
ret = dsp->ops->getedidaudioinfo(dsp, audioinfo, 200);
if (!ret) {
mutex_unlock(&dsp->lock);
return snprintf(buf, PAGE_SIZE, "%s\n", audioinfo);
}
}
mutex_unlock(&dsp->lock);
return -EINVAL;
}
static DEVICE_ATTR_RO(audioinfo);
static ssize_t monspecs_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
struct fb_monspecs monspecs;
int ret = 0;
mutex_lock(&dsp->lock);
if (dsp->ops && dsp->ops->getmonspecs) {
ret = dsp->ops->getmonspecs(dsp, &monspecs);
if (!ret) {
mutex_unlock(&dsp->lock);
memcpy(buf, &monspecs, sizeof(struct fb_monspecs));
return sizeof(struct fb_monspecs);
}
}
mutex_unlock(&dsp->lock);
return -EINVAL;
}
static DEVICE_ATTR_RO(monspecs);
static ssize_t debug_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
int ret = -EINVAL;
mutex_lock(&dsp->lock);
if (dsp->ops && dsp->ops->getdebug)
ret = dsp->ops->getdebug(dsp, buf);
mutex_unlock(&dsp->lock);
return ret;
}
static ssize_t debug_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
int cmd, ret = -EINVAL;
struct rk_display_device *dsp = dev_get_drvdata(dev);
mutex_lock(&dsp->lock);
if (dsp->ops && dsp->ops->setdebug) {
if (kstrtoint(buf, 0, &cmd) == 0)
dsp->ops->setdebug(dsp, cmd);
ret = count;
}
mutex_unlock(&dsp->lock);
return ret;
}
static DEVICE_ATTR_RW(debug);
static ssize_t prop_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
int ret = -EINVAL;
mutex_lock(&dsp->lock);
if (dsp->ops && dsp->ops->getvrinfo)
ret = dsp->ops->getvrinfo(dsp, buf);
mutex_unlock(&dsp->lock);
return ret;
}
static DEVICE_ATTR_RO(prop);
static struct attribute *display_device_attrs[] = {
&dev_attr_name.attr,
&dev_attr_type.attr,
&dev_attr_property.attr,
&dev_attr_enable.attr,
&dev_attr_connect.attr,
&dev_attr_modes.attr,
&dev_attr_mode.attr,
&dev_attr_scale.attr,
&dev_attr_mode3d.attr,
&dev_attr_color.attr,
&dev_attr_audioinfo.attr,
&dev_attr_monspecs.attr,
&dev_attr_debug.attr,
&dev_attr_prop.attr,
NULL,
};
ATTRIBUTE_GROUPS(display_device);
static int display_suspend(struct device *dev, pm_message_t state)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
mutex_lock(&dsp->lock);
if (likely(dsp->driver->suspend))
dsp->driver->suspend(dsp, state);
mutex_unlock(&dsp->lock);
return 0;
};
static int display_resume(struct device *dev)
{
struct rk_display_device *dsp = dev_get_drvdata(dev);
mutex_lock(&dsp->lock);
if (likely(dsp->driver->resume))
dsp->driver->resume(dsp);
mutex_unlock(&dsp->lock);
return 0;
};
int display_add_videomode(const struct fb_videomode *mode,
struct list_head *head)
{
struct list_head *pos;
struct display_modelist *modelist;
struct fb_videomode *m;
int found = 0;
list_for_each(pos, head) {
modelist = list_entry(pos, struct display_modelist, list);
m = &modelist->mode;
if (fb_mode_is_equal(m, mode)) {
found = 1;
break;
}
}
if (!found) {
modelist = kmalloc(sizeof(*modelist),
GFP_KERNEL);
if (!modelist)
return -ENOMEM;
modelist->mode = *mode;
list_add(&modelist->list, head);
}
return 0;
}
void rk_display_device_enable(struct rk_display_device *ddev)
{
struct list_head *pos, *head;
struct rk_display_device *dev = NULL, *dev_enabled = NULL;
struct rk_display_device *dev_enable = NULL;
int enable = 0, connect;
if (ddev->property == DISPLAY_MAIN)
head = &main_display_device_list;
else
head = &aux_display_device_list;
list_for_each(pos, head) {
dev = list_entry(pos, struct rk_display_device, list);
enable = dev->ops->getenable(dev);
connect = dev->ops->getstatus(dev);
if (connect)
dev_enable = dev;
if (enable == 1)
dev_enabled = dev;
}
/* If no device is connected, enable highest priority device. */
if (!dev_enable) {
dev->ops->setenable(dev, 1);
return;
}
if (dev_enable == dev_enabled) {
if (dev_enable != ddev)
ddev->ops->setenable(ddev, 0);
} else {
if (dev_enabled &&
dev_enabled->priority != DISPLAY_PRIORITY_HDMI)
dev_enabled->ops->setenable(dev_enabled, 0);
dev_enable->ops->setenable(dev_enable, 1);
}
}
EXPORT_SYMBOL(rk_display_device_enable);
void rk_display_device_enable_other(struct rk_display_device *ddev)
{
#ifndef CONFIG_DISPLAY_AUTO_SWITCH
return;
#else
struct list_head *pos, *head;
struct rk_display_device *dev;
int connect = 0;
if (ddev->property == DISPLAY_MAIN)
head = &main_display_device_list;
else
head = &aux_display_device_list;
list_for_each_prev(pos, head) {
dev = list_entry(pos, struct rk_display_device, list);
if (dev != ddev) {
connect = dev->ops->getstatus(dev);
if (connect) {
dev->ops->setenable(dev, 1);
return;
}
}
}
#endif
}
EXPORT_SYMBOL(rk_display_device_enable_other);
void rk_display_device_disable_other(struct rk_display_device *ddev)
{
#ifndef CONFIG_DISPLAY_AUTO_SWITCH
return;
#else
struct list_head *pos, *head;
struct rk_display_device *dev;
int enable = 0;
if (ddev->property == DISPLAY_MAIN)
head = &main_display_device_list;
else
head = &aux_display_device_list;
list_for_each(pos, head) {
dev = list_entry(pos, struct rk_display_device, list);
if (dev != ddev) {
enable = dev->ops->getenable(dev);
if (enable)
dev->ops->setenable(dev, 0);
}
}
ddev->ops->setenable(ddev, 1);
#endif
}
EXPORT_SYMBOL(rk_display_device_disable_other);
void rk_display_device_select(int property, int priority)
{
struct list_head *pos, *head;
struct rk_display_device *dev;
int enable, found = 0;
if (property == DISPLAY_MAIN)
head = &main_display_device_list;
else
head = &aux_display_device_list;
list_for_each(pos, head) {
dev = list_entry(pos, struct rk_display_device, list);
if (dev->priority == priority)
found = 1;
}
if (!found) {
pr_err("[%s] select display interface %d not exist\n",
__func__, priority);
return;
}
list_for_each(pos, head) {
dev = list_entry(pos, struct rk_display_device, list);
enable = dev->ops->getenable(dev);
if (dev->priority == priority) {
if (!enable)
dev->ops->setenable(dev, 1);
} else if (enable) {
dev->ops->setenable(dev, 0);
}
}
}
EXPORT_SYMBOL(rk_display_device_select);
static struct mutex allocated_dsp_lock;
static DEFINE_IDR(allocated_dsp);
static struct class *display_class;
struct rk_display_device
*rk_display_device_register(struct rk_display_driver *driver,
struct device *parent, void *devdata)
{
struct rk_display_device *new_dev = NULL;
int ret = -EINVAL;
if (unlikely(!driver))
return ERR_PTR(ret);
new_dev = kzalloc(sizeof(*new_dev), GFP_KERNEL);
if (likely(new_dev) && unlikely(driver->probe(new_dev, devdata))) {
/* Reserve the index for this display */
mutex_lock(&allocated_dsp_lock);
new_dev->idx = idr_alloc(&allocated_dsp, new_dev,
0, 0, GFP_KERNEL);
mutex_unlock(&allocated_dsp_lock);
if (new_dev->idx >= 0) {
struct list_head *pos, *head;
struct rk_display_device *dev;
int i = 0;
head = &main_display_device_list;
list_for_each_entry(dev, head, list) {
if (strcmp(dev->type, new_dev->type) == 0)
i++;
}
head = &aux_display_device_list;
list_for_each_entry(dev, head, list) {
if (strcmp(dev->type, new_dev->type) == 0)
i++;
}
if (i == 0)
new_dev->dev =
device_create(display_class, parent,
MKDEV(0, 0), new_dev,
"%s", new_dev->type);
else
new_dev->dev =
device_create(display_class, parent,
MKDEV(0, 0), new_dev,
"%s%d", new_dev->type, i);
if (!IS_ERR(new_dev->dev)) {
new_dev->parent = parent;
new_dev->driver = driver;
if (parent)
new_dev->dev->driver = parent->driver;
mutex_init(&new_dev->lock);
/* Add new device to display device list. */
if (new_dev->property == DISPLAY_MAIN)
head = &main_display_device_list;
else
head = &aux_display_device_list;
list_for_each(pos, head) {
dev =
list_entry(pos,
struct rk_display_device,
list);
if (dev->priority > new_dev->priority)
break;
}
list_add_tail(&new_dev->list, pos);
return new_dev;
}
mutex_lock(&allocated_dsp_lock);
idr_remove(&allocated_dsp, new_dev->idx);
mutex_unlock(&allocated_dsp_lock);
ret = -EINVAL;
}
}
kfree(new_dev);
return ERR_PTR(ret);
}
EXPORT_SYMBOL(rk_display_device_register);
void rk_display_device_unregister(struct rk_display_device *ddev)
{
if (!ddev)
return;
/* Free device */
mutex_lock(&ddev->lock);
device_unregister(ddev->dev);
mutex_unlock(&ddev->lock);
/* Mark device index as available */
mutex_lock(&allocated_dsp_lock);
idr_remove(&allocated_dsp, ddev->idx);
mutex_unlock(&allocated_dsp_lock);
list_del(&ddev->list);
kfree(ddev);
}
EXPORT_SYMBOL(rk_display_device_unregister);
static int __init rk_display_class_init(void)
{
display_class = class_create(THIS_MODULE, "display");
if (IS_ERR(display_class)) {
pr_err("Failed to create display class\n");
display_class = NULL;
return -EINVAL;
}
display_class->dev_groups = display_device_groups;
display_class->suspend = display_suspend;
display_class->resume = display_resume;
mutex_init(&allocated_dsp_lock);
INIT_LIST_HEAD(&main_display_device_list);
INIT_LIST_HEAD(&aux_display_device_list);
return 0;
}
static void __exit rk_display_class_exit(void)
{
class_destroy(display_class);
}
subsys_initcall(rk_display_class_init);
module_exit(rk_display_class_exit);
MODULE_AUTHOR("zhengyang@rock-chips.com");
MODULE_DESCRIPTION("Driver for rk display device");
MODULE_LICENSE("GPL");

66
drivers/video/rockchip/lcdc/Kconfig
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@ -1,66 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
config LCDC_RK2928
tristate "rk2928 lcdc support"
depends on (DRM_ROCKCHIP || FB_ROCKCHIP) && ARCH_RK2928
help
Driver for rk2928 lcdc .
config LCDC_RK30
tristate "rk30 lcdc support"
depends on (DRM_ROCKCHIP || FB_ROCKCHIP) && ARCH_RK30XX
help
Driver for rk30 lcdc .There are two lcd controllers on rk30
config LCDC_RK3066B
tristate "rk3066b lcdc support"
depends on (DRM_ROCKCHIP || FB_ROCKCHIP) && ARCH_RK3066B
help
Driver for rk3066b lcdc.
config LCDC_RK3188
bool "rk3188 lcdc support"
depends on DRM_ROCKCHIP || FB_ROCKCHIP
depends on ARM
help
Driver for rk3188/rk302x/rk319x lcdc.There are two lcd controllers on rk3188
config LCDC_RK3288
bool "rk3288 lcdc support"
depends on DRM_ROCKCHIP || FB_ROCKCHIP
depends on ARM
help
Driver for rk3288 lcdc.There are two lcd controllers on rk3288
config LCDC_RK3036
bool "rk3036 lcdc support"
depends on DRM_ROCKCHIP || FB_ROCKCHIP
depends on ARM
help
Driver for rk3036 lcdc.
config LCDC_RK312X
bool "rk312x lcdc support"
depends on DRM_ROCKCHIP || FB_ROCKCHIP
depends on ARM
help
Driver for rk312x lcdc.
config LCDC_RK3368
bool "rk3368 lcdc support"
depends on DRM_ROCKCHIP || FB_ROCKCHIP
depends on ARM64
help
Driver for rk3368 lcdc.There are one lcd controllers on rk3368
config LCDC_RK322X
bool "rk322x lcdc support"
depends on FB_ROCKCHIP
help
Driver for rk322x lcdc.There are one lcd controllers on rk322x
config LCDC_LITE_RK3X
bool "rk lcdc lite support"
depends on FB_ROCKCHIP
help
Driver for rk lcdc lite.There are one lcd controllers on rk3366 or
on other chips in future

11
drivers/video/rockchip/lcdc/Makefile
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@ -1,11 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_LCDC_RK30) += rk30_lcdc.o
obj-$(CONFIG_LCDC_RK2928) += rk2928_lcdc.o
obj-$(CONFIG_LCDC_RK3066B) += rk3066b_lcdc.o
obj-$(CONFIG_LCDC_RK3188) += rk3188_lcdc.o
obj-$(CONFIG_LCDC_RK3288) += rk3288_lcdc.o
obj-$(CONFIG_LCDC_RK3036) += rk3036_lcdc.o
obj-$(CONFIG_LCDC_RK312X) += rk312x_lcdc.o
obj-$(CONFIG_LCDC_RK3368) += rk3368_lcdc.o
obj-$(CONFIG_LCDC_RK322X) += rk322x_lcdc.o
obj-$(CONFIG_LCDC_LITE_RK3X) += rk_vop_lite.o

1422
drivers/video/rockchip/lcdc/rk2928_lcdc.c
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File diff suppressed because it is too large Load Diff

527
drivers/video/rockchip/lcdc/rk2928_lcdc.h
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@ -1,527 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef RK2928_LCDC_H_
#define RK2928_LCDC_H_
#include<linux/rk_fb.h>
#define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk))
#define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val)
#define LcdRdReg(inf, addr) (inf->preg->addr)
#define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk))
#define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk))
#define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk))
#define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val))
#define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb()
/********************************************************************
** 结构定义 *
********************************************************************/
/* LCDC的寄存器结构 */
typedef volatile struct tagLCDC_REG
{
/* offset 0x00~0xc0 */
unsigned int SYS_CFG; //0x00 system config register
unsigned int DSP_CTRL; //0x0c display control register
unsigned int BG_COLOR; //back ground color register
unsigned int ALPHA_CTRL; //alpha control register
unsigned int INT_STATUS; //0x10 Interrupt status register
unsigned int WIN0_COLOR_KEY_CTRL; //0x1c Win0 blending control register
unsigned int WIN1_COLOR_KEY_CTRL; //0x20 Win1 blending control register
unsigned int WIN0_YRGB_MST; //0x28 Win0 active YRGB memory start address0
unsigned int WIN0_CBR_MST; //0x2c Win0 active Cbr memory start address0
unsigned int WIN_VIR; //0x38 WIN0 virtual display width/height
unsigned int WIN0_ACT_INFO; //0x3C Win0 active window width/height
unsigned int WIN0_DSP_INFO; //0x40 Win0 display width/height on panel
unsigned int WIN0_DSP_ST; //0x44 Win0 display start point on panel
unsigned int WIN0_SCL_FACTOR_YRGB; //0x48Win0 YRGB scaling factor setting
unsigned int WIN0_SCL_FACTOR_CBR; //0x4c Win0 YRGB scaling factor setting
unsigned int WIN0_SCL_OFFSET; //0x50 Win0 Cbr scaling start point offset
unsigned int WIN1_RGB_MST; //0x54 Win1 active YRGB memory start address
unsigned int WIN1_DSP_INFO; //0x64 Win1 display width/height on panel
unsigned int WIN1_DSP_ST; //0x68 Win1 display start point on panel
unsigned int HWC_MST; //0x88 HWC memory start address
unsigned int HWC_DSP_ST; //0x8C HWC display start point on panel
unsigned int HWC_COLOR_LUT0; //0x90 Hardware cursor color 2’b01 look up table 0
unsigned int HWC_COLOR_LUT1; //0x94 Hardware cursor color 2’b10 look up table 1
unsigned int HWC_COLOR_LUT2; //0x98 Hardware cursor color 2’b11 look up table 2
unsigned int DSP_HTOTAL_HS_END; //0x9c Panel scanning horizontal width and hsync pulse end point
unsigned int DSP_HACT_ST_END; //0xa0 Panel active horizontal scanning start/end point
unsigned int DSP_VTOTAL_VS_END; //0xa4 Panel scanning vertical height and vsync pulse end point
unsigned int DSP_VACT_ST_END; //0xa8 Panel active vertical scanning start/end point
unsigned int SCL_REG0; //scaler register
unsigned int SCL_REG1;
unsigned int SCL_REG2;
unsigned int SCL_REG3;
unsigned int SCL_REG4;
unsigned int SCL_REG5;
unsigned int SCL_REG6;
unsigned int SCL_REG7;
unsigned int SCL_REG8;
unsigned int reserve[3];
unsigned int REG_CFG_DONE; //0xc0 REGISTER CONFIG FINISH
} LCDC_REG, *pLCDC_REG;
/* SYS_CONFIG */
#define m_W0_EN (1<<0)
#define m_W1_EN (1<<1)
#define m_HWC_EN (1<<2)
#define m_W0_FORMAT (7<<3)
#define m_W1_FORMAT (7<<6)
#define m_W0_RGB_RB_SWAP (1<<10)
#define m_W1_RGB_RB_SWAP (1<<14)
#define m_W0_AXI_OUTSTANDING_DISABLE (1<<16)
#define m_W1_AXI_OUTSTANDING_DISABLE (1<<17)
#define m_DMA_BURST_LENGTH (3<<18)
#define m_LCDC_STANDBY (1<<22)
#define m_LCDC_AXICLK_AUTO_ENABLE (1<<24) //eanble for low power
#define m_DSP_OUT_ZERO (1<<25)
#define v_W0_EN(x) (((x)&1)<<0)
#define v_W1_EN(x) (((x)&1)<<1)
#define v_HWC_EN(x) (((x)&1)<<2)
#define v_W0_FORMAT(x) (((x)&7)<<3)
#define v_W1_FORMAT(x) (((x)&7)<<6)
#define v_W0_RGB_RB_SWAP(x) (((x)&1)<<10)
#define v_W1_RGB_RB_SWAP(x) (((x)&1)<<14)
#define v_LCDC_STANDBY(x) (((x)&1)<<22)
#define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<24)
#define v_DSP_OUT_ZERO(x) (((x)&1)<<25)
#define v_LCDC_DMA_STOP(x) (((x)&1)<<0)
#define v_HWC_RELOAD_EN(x) (((x)&1)<<2)
#define v_W0_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<3)
#define v_W1_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<4)
#define v_W2_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<5)
#define v_DMA_BURST_LENGTH(x) (((x)&3)<<6)
#define v_WIN0_YRGB_CHANNEL0_ID(x) (((x)&7)<<8)
#define v_WIN0_CBR_CHANNEL0_ID(x) (((x)&7)<<11)
#define v_WIN0_YRGB_CHANNEL1_ID(x) (((x)&7)<<14)
#define v_WIN0_CBR_CHANNEL1_ID(x) (((x)&7)<<17)
#define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&7)<<20)
#define v_WIN1_CBR_CHANNEL_ID(x) (((x)&7)<<23)
#define v_WIN2_CHANNEL_ID(x) (((x)&7)<<26)
#define v_HWC_CHANNEL_ID(x) (((x)&7)<<29)
//LCDC_DSP_CTRL_REG
#define m_DISPLAY_FORMAT (3<<0)
#define m_BLANK_MODE (1<<2)
#define m_BLACK_MODE (1<<3)
#define m_HSYNC_POLARITY (1<<4)
#define m_VSYNC_POLARITY (1<<5)
#define m_DEN_POLARITY (1<<6)
#define m_DCLK_POLARITY (1<<7)
#define m_W0W1_POSITION_SWAP (1<<8)
#define m_OUTPUT_BG_SWAP (1<<9)
#define m_OUTPUT_RB_SWAP (1<<10)
#define m_OUTPUT_RG_SWAP (1<<11)
#define m_DITHER_UP_EN (1<<12)
#define m_DITHER_DOWN_MODE (1<<13)
#define m_DITHER_DOWN_EN (1<<14)
#define m_W1_INTERLACE_READ_MODE (1<<15)
#define m_W2_INTERLACE_READ_MODE (1<<16)
#define m_W0_YRGB_DEFLICK_MODE (1<<17)
#define m_W0_CBR_DEFLICK_MODE (1<<18)
#define m_W1_YRGB_DEFLICK_MODE (1<<19)
#define m_W1_CBR_DEFLICK_MODE (1<<20)
#define m_W0_ALPHA_MODE (1<<21)
#define m_W1_ALPHA_MODE (1<<22)
#define m_W2_ALPHA_MODE (1<<23)
#define m_W0_COLOR_SPACE_CONVERSION (3<<24)
#define m_W1_COLOR_SPACE_CONVERSION (3<<26)
#define m_W2_COLOR_SPACE_CONVERSION (1<<28)
#define m_YCRCB_CLIP_EN (1<<29)
#define m_CBR_FILTER_656 (1<<30)
#define v_DISPLAY_FORMAT(x) (((x)&0x3)<<0)
#define v_BLANK_MODE(x) (((x)&1)<<2)
#define v_BLACK_MODE(x) (((x)&1)<<3)
#define v_HSYNC_POLARITY(x) (((x)&1)<<4)
#define v_VSYNC_POLARITY(x) (((x)&1)<<5)
#define v_DEN_POLARITY(x) (((x)&1)<<6)
#define v_DCLK_POLARITY(x) (((x)&1)<<7)
#define v_W0W1_POSITION_SWAP(x) (((x)&1)<<8)
#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<9)
#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<10)
#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<11)
#define v_DITHER_UP_EN(x) (((x)&1)<<12)
#define v_DITHER_DOWN_MODE(x) (((x)&1)<<13)
#define v_DITHER_DOWN_EN(x) (((x)&1)<<14)
#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12)
#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13)
#define v_W0_INTERLACE_READ_MODE(x) (((x)&1)<<14)
#define v_W1_INTERLACE_READ_MODE(x) (((x)&1)<<15)
#define v_W2_INTERLACE_READ_MODE(x) (((x)&1)<<16)
#define v_W0_YRGB_DEFLICK_MODE(x) (((x)&1)<<17)
#define v_W0_CBR_DEFLICK_MODE(x) (((x)&1)<<18)
#define v_W1_YRGB_DEFLICK_MODE(x) (((x)&1)<<19)
#define v_W1_CBR_DEFLICK_MODE(x) (((x)&1)<<20)
#define v_W0_ALPHA_MODE(x) (((x)&1)<<21)
#define v_W1_ALPHA_MODE(x) (((x)&1)<<22)
#define v_W2_ALPHA_MODE(x) (((x)&1)<<23)
#define v_W0_COLOR_SPACE_CONVERSION(x) (((x)&3)<<24)
#define v_W1_COLOR_SPACE_CONVERSION(x) (((x)&3)<<26)
#define v_W2_COLOR_SPACE_CONVERSION(x) (((x)&1)<<28)
#define v_YCRCB_CLIP_EN(x) (((x)&1)<<29)
#define v_CBR_FILTER_656(x) (((x)&1)<<30)
//LCDC_BG_COLOR
#define m_BG_COLOR (0xffffff<<0)
#define m_BG_B (0xff<<0)
#define m_BG_G (0xff<<8)
#define m_BG_R (0xff<<16)
#define v_BG_COLOR(x) (((x)&0xffffff)<<0)
#define v_BG_B(x) (((x)&0xff)<<0)
#define v_BG_G(x) (((x)&0xff)<<8)
#define v_BG_R(x) (((x)&0xff)<<16)
//LCDC_ BLEND_CTRL
#define m_HWC_BLEND_EN (1<<0)
#define m_W2_BLEND_EN (1<<1)
#define m_W1_BLEND_EN (1<<2)
#define m_W0_BLEND_EN (1<<3)
#define m_HWC_BLEND_FACTOR (15<<4)
#define m_W2_BLEND_FACTOR (0xff<<8)
#define m_W1_BLEND_FACTOR (0xff<<16)
#define m_W0_BLEND_FACTOR (0xff<<24)
#define v_HWC_BLEND_EN(x) (((x)&1)<<0)
#define v_W2_BLEND_EN(x) (((x)&1)<<1)
#define v_W1_BLEND_EN(x) (((x)&1)<<2)
#define v_W0_BLEND_EN(x) (((x)&1)<<3)
#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4)
#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8)
#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16)
#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24)
//LCDC_INT_STATUS
#define v_HOR_START_INT_STA (1<<0) //status
#define v_FRM_START_INT_STA (1<<1)
#define v_LINE_FLAG_INT_STA (1<<2)
#define v_BUS_ERR_INT_STA (1<<3)
#define m_HOR_START_INT_EN (1<<4) //enable
#define m_FRM_START_INT_EN (1<<5)
#define m_LINE_FLAG_INT_EN (1<<6)
#define m_BUS_ERR_INT_EN (1<<7)
#define m_HOR_START_INT_CLEAR (1<<8) //auto clear
#define m_FRM_START_INT_CLEAR (1<<9)
#define m_LINE_FLAG_INT_CLEAR (1<<10)
#define m_BUS_ERR_INT_CLEAR (1<<11)
#define m_LINE_FLAG_NUM (0xfff<<12)
#define v_HOR_START_INT_EN(x) (((x)&1)<<4)
#define v_FRM_START_INT_EN(x) (((x)&1)<<5)
#define v_LINE_FLAG_INT_EN(x) (((x)&1)<<6)
#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7)
#define v_HOR_START_INT_CLEAR(x) (((x)&1)<<8)
#define v_FRM_START_INT_CLEAR(x) (((x)&1)<<9)
#define v_LINE_FLAG_INT_CLEAR(x) (((x)&1)<<10)
#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11)
#define v_LINE_FLAG_NUM(x) (((x)&0xfff)<<12)
//LCDC_WIN_VIR
#define m_WIN0_VIR (0xfff << 0)
#define m_WIN1_VIR (0xfff << 16)
//LCDC_WINx_VIR ,x is number of words of win0 virtual width
#define v_WIN0_ARGB888_VIRWIDTH(x) (x)
#define v_WIN0_RGB888_VIRWIDTH(x) (((x*3)>>2)+((x)%3))
#define v_WIN0_RGB565_VIRWIDTH(x) (((x)>>1) + ((x%2)?1:0))
#define v_WIN0_YUV_VIRWIDTH(x) (((x)>>2) +((x%4)?1:0))
#define v_WIN1_ARGB888_VIRWIDTH(x) (x << 16)
#define v_WIN1_RGB888_VIRWIDTH(x) ((((x*3)>>2)+((x)%3)) << 16)
#define v_WIN1_RGB565_VIRWIDTH(x) ((((x)>>1) + ((x%2)?1:0)) << 16)
#define v_WIN1_YUV_VIRWIDTH(x) ((((x)>>2) +((x%4)?1:0)) << 16 )
//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL
#define m_KEYCOLOR (0xffffff<<0)
#define m_KEYCOLOR_B (0xff<<0)
#define m_KEYCOLOR_G (0xff<<8)
#define m_KEYCOLOR_R (0xff<<16)
#define m_COLORKEY_EN (1<<24)
#define v_KEYCOLOR(x) (((x)&0xffffff)<<0)
#define v_KEYCOLOR_B(x) (((x)&0xff)<<0)
#define v_KEYCOLOR_G(x) (((x)&0xff)<<8)
#define v_KEYCOLOR_R(x) (((x)&0xff)<<16)
#define v_COLORKEY_EN(x) (((x)&1)<<24)
//LCDC_DEFLICKER_SCL_OFFSET
#define m_W0_YRGB_VSD_OFFSET (0xff<<0)
#define m_W0_YRGB_VSP_OFFSET (0xff<<8)
#define m_W1_VSD_OFFSET (0xff<<16)
#define m_W1_VSP_OFFSET (0xff<<24)
#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0)
#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8)
#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16)
#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24)
//AXI MS ID
#define m_W0_YRGB_CH_ID (0xF<<0)
#define m_W0_CBR_CH_ID (0xF<<4)
#define m_W1_YRGB_CH_ID (0xF<<8)
#define m_W2_CH_ID (0xF<<12)
#define m_HWC_CH_ID (0xF<<16)
#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0)
#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4)
#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8)
#define v_W2_CH_ID(x) (((x)&0xF)<<12)
#define v_HWC_CH_ID(x) (((x)&0xF)<<16)
/* Low Bits Mask */
#define m_WORDLO (0xffff<<0)
#define m_WORDHI (0xffff<<16)
#define v_WORDLO(x) (((x)&0xffff)<<0)
#define v_WORDHI(x) (((x)&0xffff)<<16)
//LCDC_WINx_SCL_FACTOR_Y/CBCR
#define v_X_SCL_FACTOR(x) ((x)<<0)
#define v_Y_SCL_FACTOR(x) ((x)<<16)
//LCDC_DSP_HTOTAL_HS_END
#define v_HSYNC(x) ((x)<<0) //hsync pulse width
#define v_HORPRD(x) ((x)<<16) //horizontal period
//LCDC_DSP_HACT_ST_END
#define v_HAEP(x) ((x)<<0) //horizontal active end point
#define v_HASP(x) ((x)<<16) //horizontal active start point
//LCDC_DSP_VTOTAL_VS_END
#define v_VSYNC(x) ((x)<<0)
#define v_VERPRD(x) ((x)<<16)
//LCDC_DSP_VACT_ST_END
#define v_VAEP(x) ((x)<<0)
#define v_VASP(x) ((x)<<16)
#define m_ACTWIDTH (0xffff<<0)
#define m_ACTHEIGHT (0xffff<<16)
#define v_ACTWIDTH(x) (((x)&0xffff)<<0)
#define v_ACTHEIGHT(x) (((x)&0xffff)<<16)
#define m_VIRST_X (0xffff<<0)
#define m_VIRST_Y (0xffff<<16)
#define v_VIRST_X(x) (((x)&0xffff)<<0)
#define v_VIRST_Y(x) (((x)&0xffff)<<16)
#define m_PANELST_X (0x3ff<<0)
#define m_PANELST_Y (0x3ff<<16)
#define v_PANELST_X(x) (((x)&0x3ff)<<0)
#define v_PANELST_Y(x) (((x)&0x3ff)<<16)
#define m_PANELWIDTH (0x3ff<<0)
#define m_PANELHEIGHT (0x3ff<<16)
#define v_PANELWIDTH(x) (((x)&0x3ff)<<0)
#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16)
#define m_HWC_B (0xff<<0)
#define m_HWC_G (0xff<<8)
#define m_HWC_R (0xff<<16)
#define m_W0_YRGB_HSP_OFFSET (0xff<<24)
#define m_W0_YRGB_HSD_OFFSET (0xff<<24)
#define v_HWC_B(x) (((x)&0xff)<<0)
#define v_HWC_G(x) (((x)&0xff)<<8)
#define v_HWC_R(x) (((x)&0xff)<<16)
#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24)
#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24)
//LCDC_WIN0_ACT_INFO
#define v_ACT_WIDTH(x) ((x-1)<<0)
#define v_ACT_HEIGHT(x) ((x-1)<<16)
//LCDC_WIN0_DSP_INFO
#define v_DSP_WIDTH(x) ((x-1)<<0)
#define v_DSP_HEIGHT(x) ((x-1)<<16)
//LCDC_WIN0_DSP_ST //x,y start point of the panel scanning
#define v_DSP_STX(x) (x<<0)
#define v_DSP_STY(x) (x<<16)
//Panel display scanning
#define m_PANEL_HSYNC_WIDTH (0x3ff<<0)
#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16)
#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0)
#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16)
#define m_PANEL_END (0x3ff<<0)
#define m_PANEL_START (0x3ff<<16)
#define v_PANEL_END(x) (((x)&0x3ff)<<0)
#define v_PANEL_START(x) (((x)&0x3ff)<<16)
#define m_PANEL_VSYNC_WIDTH (0x3ff<<0)
#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16)
#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0)
#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16)
//-----------
#define m_HSCALE_FACTOR (0xffff<<0)
#define m_VSCALE_FACTOR (0xffff<<16)
#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0)
#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16)
#define m_W0_CBR_HSD_OFFSET (0xff<<0)
#define m_W0_CBR_HSP_OFFSET (0xff<<8)
#define m_W0_CBR_VSD_OFFSET (0xff<<16)
#define m_W0_CBR_VSP_OFFSET (0xff<<24)
#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0)
#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8)
#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16)
#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24)
//LCDC_SCL_REG0
#define m_SCL_DSP_ZERO (1<<4)
#define m_SCL_DEN_INVERT (1<<3)
#define m_SCL_SYNC_INVERT (1<<2)
#define m_SCL_DCLK_INVERT (1<<1)
#define m_SCL_EN (1<<0)
#define v_SCL_DSP_ZERO(x) (((x)&1)<<4)
#define v_SCL_DEN_INVERT(x) (((x)&1)<<3)
#define v_SCL_SYNC_INVERT(x) (((x)&1)<<2)
#define v_SCL_DCLK_INVERT(x) (((x)&1)<<1)
#define v_SCL_EN(x) (((x)&1)<<0)
//LCDC_SCL_REG1
#define m_SCL_V_FACTOR (0x3fff<<16)
#define m_SCL_H_FACTOR (0x3fff<<0)
#define v_SCL_V_FACTOR(x) (((x)&0x3fff)<<16)
#define v_SCL_H_FACTOR(x) (((x)&0x3fff)<<0)
//LCDC_SCL_REG2
#define m_SCL_DSP_FRAME_VST (0xfff<<16)
#define m_SCL_DSP_FRAME_HST (0xfff<<0)
#define v_SCL_DSP_FRAME_VST(x) (((x)&0xfff)<<16)
#define v_SCL_DSP_FRAME_HST(x) (((x)&0xfff)<<0)
//LCDC_SCL_REG3
#define m_SCL_DSP_HS_END (0xff<<16)
#define m_SCL_DSP_HTOTAL (0xfff<<0)
#define v_SCL_DSP_HS_END(x) (((x)&0xff)<<16)
#define v_SCL_DSP_HTOTAL(x) (((x)&0xfff)<<0)
//LCDC_SCL_REG4
#define m_SCL_DSP_HACT_ST (0x3ff<<16)
#define m_SCL_DSP_HACT_END (0xfff<<0)
#define v_SCL_DSP_HACT_ST(x) (((x)&0x3ff)<<16)
#define v_SCL_DSP_HACT_END(x) (((x)&0xfff)<<0)
//LCDC_SCL_REG5
#define m_SCL_DSP_VS_END (0xff<<16)
#define m_SCL_DSP_VTOTAL (0xfff<<0)
#define v_SCL_DSP_VS_END(x) (((x)&0xff)<<16)
#define v_SCL_DSP_VTOTAL(x) (((x)&0xfff)<<0)
//LCDC_SCL_REG6
#define m_SCL_DSP_VACT_ST (0xff<<16)
#define m_SCL_DSP_VACT_END (0xfff<<0)
#define v_SCL_DSP_VACT_ST(x) (((x)&0xff)<<16)
#define v_SCL_DSP_VACT_END(x) (((x)&0xfff)<<0)
//LCDC_SCL_REG7
#define m_SCL_DSP_HBOR_ST (0x3ff<<16)
#define m_SCL_DSP_HBOR_END (0xfff<<0)
#define v_SCL_DSP_HBOR_ST(x) (((x)&0x3ff)<<16)
#define v_SCL_DSP_HBOR_END(x) (((x)&0xfff)<<0)
//LCDC_SCL_REG8
#define m_SCL_DSP_VBOR_ST (0xff<<16)
#define m_SCL_DSP_VBOR_END (0xfff<<0)
#define v_SCL_DSP_VBOR_ST(x) (((x)&0xff)<<16)
#define v_SCL_DSP_VBOR_END(x) (((x)&0xfff)<<0)
#define CalScale(x, y) (((u32)(x)*0x1000)/(y))
struct rk2928_lcdc_device{
int id;
struct rk_lcdc_device_driver driver;
rk_screen *screen;
LCDC_REG *preg; // LCDC reg base address and backup reg
LCDC_REG regbak;
void __iomem *reg_vir_base; // virtual basic address of lcdc register
u32 reg_phy_base; // physical basic address of lcdc register
u32 len; // physical map length of lcdc register
spinlock_t reg_lock; //one time only one process allowed to config the register
bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed
u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc
unsigned int irq;
struct clk *pd; //lcdc power domain
struct clk *hclk; //lcdc AHP clk
struct clk *dclk; //lcdc dclk
struct clk *aclk; //lcdc share memory frequency
struct clk *sclk; //scale clk
struct clk *aclk_parent; //lcdc aclk divider frequency source
struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable.
struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable.
struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable.
struct clk *pd_display; // display power domain
u32 pixclock;
};
struct lcdc_info{
/*LCD CLK*/
struct rk2928_lcdc_device lcdc0;
};
struct win_set {
volatile u32 y_offset;
volatile u32 c_offset;
};
struct win0_par {
u32 refcount;
u32 pseudo_pal[16];
u32 y_offset;
u32 c_offset;
u32 xpos; //size in panel
u32 ypos;
u32 xsize; //start point in panel
u32 ysize;
enum data_format format;
wait_queue_head_t wait;
struct win_set mirror;
struct win_set displ;
struct win_set done;
u8 par_seted;
u8 addr_seted;
};
#endif

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drivers/video/rockchip/lcdc/rk3036_lcdc.c
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drivers/video/rockchip/lcdc/rk3036_lcdc.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _RK3036_LCDC_H_
#define _RK3036_LCDC_H_
#include<linux/rk_fb.h>
#include<linux/io.h>
#include<linux/clk.h>
/*******************register definition**********************/
#define SYS_CTRL (0x00)
#define m_WIN0_EN (1<<0)
#define m_WIN1_EN (1<<1)
#define m_HWC_EN (1<<2)
#define m_WIN0_FORMAT (7<<3)
#define m_WIN1_FORMAT (7<<6)
#define m_HWC_LUT_EN (1<<9)
#define m_HWC_SIZE (1<<10)
#define m_WIN0_RB_SWAP (1<<15)
#define m_WIN0_ALPHA_SWAP (1<<16)
#define m_WIN0_Y8_SWAP (1<<17)
#define m_WIN0_UV_SWAP (1<<18)
#define m_WIN1_RB_SWAP (1<<19)
#define m_WIN1_ALPHA_SWAP (1<<20)
#define m_WIN0_OTSD_DISABLE (1<<22)
#define m_WIN1_OTSD_DISABLE (1<<23)
#define m_DMA_BURST_LENGTH (3<<24)
#define m_HWC_LODAD_EN (1<<26)
#define m_DMA_STOP (1<<29)
#define m_LCDC_STANDBY (1<<30)
#define m_AUTO_GATING_EN (1<<31)
#define v_WIN0_EN(x) (((x)&1)<<0)
#define v_WIN1_EN(x) (((x)&1)<<1)
#define v_HWC_EN(x) (((x)&1)<<2)
#define v_WIN0_FORMAT(x) (((x)&7)<<3)
#define v_WIN1_FORMAT(x) (((x)&7)<<6)
#define v_HWC_LUT_EN(x) (((x)&1)<<9)
#define v_HWC_SIZE(x) (((x)&1)<<10)
#define v_WIN0_RB_SWAP(x) (((x)&1)<<15)
#define v_WIN0_ALPHA_SWAP(x) (((x)&1)<<16)
#define v_WIN0_Y8_SWAP(x) (((x)&1)<<17)
#define v_WIN0_UV_SWAP(x) (((x)&1)<<18)
#define v_WIN1_RB_SWAP(x) (((x)&1)<<19)
#define v_WIN1_ALPHA_SWAP(x) (((x)&1)<<20)
#define v_WIN0_OTSD_DISABLE(x) (((x)&1)<<22)
#define v_WIN1_OTSD_DISABLE(x) (((x)&1)<<23)
#define v_DMA_BURST_LENGTH(x) (((x)&3)<<24)
#define v_HWC_LODAD_EN(x) (((x)&1)<<26)
#define v_WIN1_LUT_EN(x) (((x)&1)<<27)
#define v_DMA_STOP(x) (((x)&1)<<29)
#define v_LCDC_STANDBY(x) (((x)&1)<<30)
#define v_AUTO_GATING_EN(x) (((x)&1)<<31)
#define DSP_CTRL0 (0x04)
#define m_DSP_OUT_FORMAT (0x0f<<0)
#define m_HSYNC_POL (1<<4)
#define m_VSYNC_POL (1<<5)
#define m_DEN_POL (1<<6)
#define m_DCLK_POL (1<<7)
#define m_WIN0_TOP (1<<8)
#define m_DITHER_UP_EN (1<<9)
#define m_INTERLACE_DSP_EN (1<<12)
#define m_INTERLACE_DSP_POL (1<<13)
#define m_WIN0_INTERLACE_EN (1<<14)
#define m_WIN1_INTERLACE_EN (1<<15)
#define m_WIN0_YRGB_DEFLICK_EN (1<<16)
#define m_WIN0_CBR_DEFLICK_EN (1<<17)
#define m_WIN0_ALPHA_MODE (1<<18)
#define m_WIN1_ALPHA_MODE (1<<19)
#define m_WIN0_CSC_MODE (3<<20)
#define m_WIN0_YUV_CLIP (1<<23)
#define m_TVE_MODE (1<<25)
#define m_HWC_ALPHA_MODE (1<<28)
#define m_PREMUL_ALPHA_ENABLE (1<<29)
#define m_ALPHA_MODE_SEL1 (1<<30)
#define m_WIN1_DIFF_DCLK_EN (1<<31)
#define v_DSP_OUT_FORMAT(x) (((x)&0x0f)<<0)
#define v_HSYNC_POL(x) (((x)&1)<<4)
#define v_VSYNC_POL(x) (((x)&1)<<5)
#define v_DEN_POL(x) (((x)&1)<<6)
#define v_DCLK_POL(x) (((x)&1)<<7)
#define v_WIN0_TOP(x) (((x)&1)<<8)
#define v_DITHER_UP_EN(x) (((x)&1)<<9)
#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12)
#define v_INTERLACE_DSP_POL(x) (((x)&1)<<13)
#define v_WIN0_INTERLACE_EN(x) (((x)&1)<<14)
#define v_WIN1_INTERLACE_EN(x) (((x)&1)<<15)
#define v_WIN0_YRGB_DEFLICK_EN(x) (((x)&1)<<16)
#define v_WIN0_CBR_DEFLICK_EN(x) (((x)&1)<<17)
#define v_WIN0_ALPHA_MODE(x) (((x)&1)<<18)
#define v_WIN1_ALPHA_MODE(x) (((x)&1)<<19)
#define v_WIN0_CSC_MODE(x) (((x)&3)<<20)
#define v_WIN0_YUV_CLIP(x) (((x)&1)<<23)
#define v_TVE_MODE(x) (((x)&1)<<25)
#define v_HWC_ALPHA_MODE(x) (((x)&1)<<28)
#define v_PREMUL_ALPHA_ENABLE(x) (((x)&1)<<29)
#define v_ALPHA_MODE_SEL1(x) (((x)&1)<<30)
#define v_WIN1_DIFF_DCLK_EN(x) (((x)&1)<<31)
#define DSP_CTRL1 (0x08)
#define m_BG_COLOR (0xffffff<<0)
#define m_BG_B (0xff<<0)
#define m_BG_G (0xff<<8)
#define m_BG_R (0xff<<16)
#define m_BLANK_EN (1<<24)
#define m_BLACK_EN (1<<25)
#define m_DSP_BG_SWAP (1<<26)
#define m_DSP_RB_SWAP (1<<27)
#define m_DSP_RG_SWAP (1<<28)
#define m_DSP_DELTA_SWAP (1<<29)
#define m_DSP_DUMMY_SWAP (1<<30)
#define m_DSP_OUT_ZERO (1<<31)
#define v_BG_COLOR(x) (((x)&0xffffff)<<0)
#define v_BG_B(x) (((x)&0xff)<<0)
#define v_BG_G(x) (((x)&0xff)<<8)
#define v_BG_R(x) (((x)&0xff)<<16)
#define v_BLANK_EN(x) (((x)&1)<<24)
#define v_BLACK_EN(x) (((x)&1)<<25)
#define v_DSP_BG_SWAP(x) (((x)&1)<<26)
#define v_DSP_RB_SWAP(x) (((x)&1)<<27)
#define v_DSP_RG_SWAP(x) (((x)&1)<<28)
#define v_DSP_DELTA_SWAP(x) (((x)&1)<<29)
#define v_DSP_DUMMY_SWAP(x) (((x)&1)<<30)
#define v_DSP_OUT_ZERO(x) (((x)&1)<<31)
#define INT_STATUS (0x10)
#define m_HS_INT_STA (1<<0) /* status */
#define m_FS_INT_STA (1<<1)
#define m_LF_INT_STA (1<<2)
#define m_BUS_ERR_INT_STA (1<<3)
#define m_HS_INT_EN (1<<4) /* enable */
#define m_FS_INT_EN (1<<5)
#define m_LF_INT_EN (1<<6)
#define m_BUS_ERR_INT_EN (1<<7)
#define m_HS_INT_CLEAR (1<<8) /* auto clear*/
#define m_FS_INT_CLEAR (1<<9)
#define m_LF_INT_CLEAR (1<<10)
#define m_BUS_ERR_INT_CLEAR (1<<11)
#define m_LF_INT_NUM (0xfff<<12)
#define m_WIN0_EMPTY_INT_EN (1<<24)
#define m_WIN1_EMPTY_INT_EN (1<<25)
#define m_WIN0_EMPTY_INT_CLEAR (1<<26)
#define m_WIN1_EMPTY_INT_CLEAR (1<<27)
#define m_WIN0_EMPTY_INT_STA (1<<28)
#define m_WIN1_EMPTY_INT_STA (1<<29)
#define m_FS_RAW_STA (1<<30)
#define m_LF_RAW_STA (1<<31)
#define v_HS_INT_EN(x) (((x)&1)<<4)
#define v_FS_INT_EN(x) (((x)&1)<<5)
#define v_LF_INT_EN(x) (((x)&1)<<6)
#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7)
#define v_HS_INT_CLEAR(x) (((x)&1)<<8)
#define v_FS_INT_CLEAR(x) (((x)&1)<<9)
#define v_LF_INT_CLEAR(x) (((x)&1)<<10)
#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11)
#define v_LF_INT_NUM(x) (((x)&0xfff)<<12)
#define v_WIN0_EMPTY_INT_EN(x) (((x)&1)<<24)
#define v_WIN1_EMPTY_INT_EN(x) (((x)&1)<<25)
#define v_WIN0_EMPTY_INT_CLEAR(x) (((x)&1)<<26)
#define v_WIN1_EMPTY_INT_CLEAR(x) (((x)&1)<<27)
#define ALPHA_CTRL (0x14)
#define m_WIN0_ALPHA_EN (1<<0)
#define m_WIN1_ALPHA_EN (1<<1)
#define m_HWC_ALPAH_EN (1<<2)
#define m_WIN1_PREMUL_SCALE (1<<3)
#define m_WIN0_ALPHA_VAL (0xff<<4)
#define m_WIN1_ALPHA_VAL (0xff<<12)
#define m_HWC_ALPAH_VAL (0xff<<20)
#define v_WIN0_ALPHA_EN(x) (((x)&1)<<0)
#define v_WIN1_ALPHA_EN(x) (((x)&1)<<1)
#define v_HWC_ALPAH_EN(x) (((x)&1)<<2)
#define v_WIN1_PREMUL_SCALE(x) (((x)&1)<<3)
#define v_WIN0_ALPHA_VAL(x) (((x)&0xff)<<4)
#define v_WIN1_ALPHA_VAL(x) (((x)&0xff)<<12)
#define v_HWC_ALPAH_VAL(x) (((x)&0xff)<<20)
#define WIN0_COLOR_KEY (0x18)
#define WIN1_COLOR_KEY (0x1C)
#define m_COLOR_KEY_VAL (0xffffff<<0)
#define m_COLOR_KEY_EN (1<<24)
#define v_COLOR_KEY_VAL(x) (((x)&0xffffff)<<0)
#define v_COLOR_KEY_EN(x) (((x)&1)<<24)
/* Layer Registers */
#define WIN0_YRGB_MST (0x20)
#define WIN0_CBR_MST (0x24)
#define WIN1_MST (0xa0)
#define HWC_MST (0x58)
#define WIN1_VIR (0x28)
#define WIN0_VIR (0x30)
#define m_YRGB_VIR (0x1fff << 0)
#define m_CBBR_VIR (0x1fff << 16)
#define v_YRGB_VIR(x) ((x & 0x1fff) << 0)
#define v_CBBR_VIR(x) ((x & 0x1fff) << 16)
#define v_ARGB888_VIRWIDTH(x) (((x) & 0x1fff) << 0)
#define v_RGB888_VIRWIDTH(x) (((((x * 3) >> 2)+(x % 3))&0x1fff)<<0)
#define v_RGB565_VIRWIDTH(x) ((DIV_ROUND_UP(x, 2)&0x1fff)<<0)
#define v_YUV_VIRWIDTH(x) ((DIV_ROUND_UP(x, 4)&0x1fff)<<0)
#define v_CBCR_VIR(x) ((x & 0x1fff) << 16)
#define WIN0_ACT_INFO (0x34)
#define WIN1_ACT_INFO (0xB4)
#define m_ACT_WIDTH (0x1fff << 0)
#define m_ACT_HEIGHT (0x1fff << 16)
#define v_ACT_WIDTH(x) (((x-1) & 0x1fff)<<0)
#define v_ACT_HEIGHT(x) (((x-1) & 0x1fff)<<16)
#define WIN0_DSP_INFO (0x38)
#define WIN1_DSP_INFO (0xB8)
#define v_DSP_WIDTH(x) (((x-1)&0x7ff)<<0)
#define v_DSP_HEIGHT(x) (((x-1)&0x7ff)<<16)
#define WIN0_DSP_ST (0x3C)
#define WIN1_DSP_ST (0xBC)
#define HWC_DSP_ST (0x5C)
#define v_DSP_STX(x) (((x)&0xfff)<<0)
#define v_DSP_STY(x) (((x)&0xfff)<<16)
#define WIN0_SCL_FACTOR_YRGB (0x40)
#define WIN0_SCL_FACTOR_CBR (0x44)
#define WIN1_SCL_FACTOR_YRGB (0xC0)
#define v_X_SCL_FACTOR(x) (((x)&0xffff)<<0)
#define v_Y_SCL_FACTOR(x) (((x)&0xffff)<<16)
#define WIN0_SCL_OFFSET (0x48)
#define WIN1_SCL_OFFSET (0xC8)
/* LUT Registers */
#define WIN1_LUT_ADDR (0x0400)
#define HWC_LUT_ADDR (0x0800)
/* Display Infomation Registers */
#define DSP_HTOTAL_HS_END (0x6C)
/*hsync pulse width*/
#define v_HSYNC(x) (((x)&0xfff)<<0)
/*horizontal period*/
#define v_HORPRD(x) (((x)&0xfff)<<16)
#define DSP_HACT_ST_END (0x70)
/*horizontal active end point*/
#define v_HAEP(x) (((x)&0xfff)<<0)
/*horizontal active start point*/
#define v_HASP(x) (((x)&0xfff)<<16)
#define DSP_VTOTAL_VS_END (0x74)
#define v_VSYNC(x) (((x)&0xfff)<<0)
#define v_VERPRD(x) (((x)&0xfff)<<16)
#define DSP_VACT_ST_END (0x78)
#define v_VAEP(x) (((x)&0xfff)<<0)
#define v_VASP(x) (((x)&0xfff)<<16)
#define DSP_VS_ST_END_F1 (0x7C)
#define v_VSYNC_END_F1(x) (((x)&0xfff)<<0)
#define v_VSYNC_ST_F1(x) (((x)&0xfff)<<16)
#define DSP_VACT_ST_END_F1 (0x80)
/*BCSH Registers*/
#define BCSH_CTRL (0xD0)
#define m_BCSH_EN (1 << 0)
#define m_BCSH_OUT_MODE (3 << 2)
#define m_BCSH_CSC_MODE (3 << 4)
#define v_BCSH_EN(x) ((1 & x) << 0)
#define v_BCSH_OUT_MODE(x) ((3 & x) << 2)
#define v_BCSH_CSC_MODE(x) ((3 & x) << 4)
#define BCSH_COLOR_BAR (0xD4)
#define v_BCSH_COLOR_BAR_Y(x) (((x)&0xf) << 0)
#define v_BCSH_COLOR_BAR_U(x) (((x)&0xf) << 8)
#define v_BCSH_COLOR_BAR_V(x) (((x)&0xf) << 16)
#define m_BCSH_COLOR_BAR_Y (0xf << 0)
#define m_BCSH_COLOR_BAR_U (0xf << 8)
#define m_BCSH_COLOR_BAR_V (0xf << 16)
#define BCSH_BCS (0xD8)
#define v_BCSH_BRIGHTNESS(x) (((x)&0x3f) << 0)
#define v_BCSH_CONTRAST(x) (((x)&0xff) << 8)
#define v_BCSH_SAT_CON(x) (((x)&0x1ff) << 16)
#define m_BCSH_BRIGHTNESS (0x3f << 0)
#define m_BCSH_CONTRAST (0xff << 8)
#define m_BCSH_SAT_CON (0x1ff << 16)
#define BCSH_H (0xDC)
#define v_BCSH_SIN_HUE(x) (((x)&0xff) << 0)
#define v_BCSH_COS_HUE(x) (((x)&0xff) << 8)
#define m_BCSH_SIN_HUE (0xff << 0)
#define m_BCSH_COS_HUE (0xff << 8)
/* Bus Register */
#define AXI_BUS_CTRL (0x2C)
#define m_IO_PAD_CLK (1 << 31)
#define m_CORE_CLK_DIV_EN (1 << 30)
#define m_HDMI_DCLK_INVERT (1 << 23)
#define m_HDMI_DCLK_EN (1 << 22)
#define m_TVE_DAC_DCLK_INVERT (1 << 21)
#define m_TVE_DAC_DCLK_EN (1 << 20)
#define m_HDMI_DCLK_DIV_EN (1 << 19)
#define m_AXI_OUTSTANDING_MAX_NUM (0x1f << 12)
#define m_AXI_MAX_OUTSTANDING_EN (1 << 11)
#define m_MMU_EN (1 << 10)
#define m_NOC_HURRY_THRESHOLD (0xf << 6)
#define m_NOC_HURRY_VALUE (3 << 4)
#define m_NOC_HURRY_EN (1 << 3)
#define m_NOC_QOS_VALUE (3 << 1)
#define m_NOC_QOS_EN (1 << 0)
#define v_IO_PAD_CLK(x) ((x&1) << 31)
#define v_CORE_CLK_DIV_EN(x) ((x&1) << 30)
#define v_HDMI_DCLK_INVERT(x) ((x&1) << 23)
#define v_HDMI_DCLK_EN(x) ((x&1) << 22)
#define v_TVE_DAC_DCLK_INVERT(x) ((x&1) << 21)
#define v_TVE_DAC_DCLK_EN(x) ((x&1) << 20)
#define v_HDMI_DCLK_DIV_EN(x) ((x&1) << 19)
#define v_AXI_OUTSTANDING_MAX_NUM(x) ((x&0x1f) << 12)
#define v_AXI_MAX_OUTSTANDING_EN(x) ((x&1) << 11)
#define v_MMU_EN(x) ((x&1) << 10)
#define v_NOC_HURRY_THRESHOLD(x) ((x&0xf) << 6)
#define v_NOC_HURRY_VALUE(x) ((x&3) << 4)
#define v_NOC_HURRY_EN(x) ((x&1) << 3)
#define v_NOC_QOS_VALUE(x) ((x&3) << 1)
#define v_NOC_QOS_EN(x) ((x&1) << 0)
#define GATHER_TRANSFER (0x84)
#define m_WIN1_AXI_GATHER_NUM (0xf << 12)
#define m_WIN0_CBCR_AXI_GATHER_NUM (0x7 << 8)
#define m_WIN0_YRGB_AXI_GATHER_NUM (0xf << 4)
#define m_WIN1_AXI_GAHTER_EN (1 << 2)
#define m_WIN0_CBCR_AXI_GATHER_EN (1 << 1)
#define m_WIN0_YRGB_AXI_GATHER_EN (1 << 0)
#define v_WIN1_AXI_GATHER_NUM(x) ((x & 0xf) << 12)
#define v_WIN0_CBCR_AXI_GATHER_NUM(x) ((x & 0x7) << 8)
#define v_WIN0_YRGB_AXI_GATHER_NUM(x) ((x & 0xf) << 4)
#define v_WIN1_AXI_GAHTER_EN(x) ((x & 1) << 2)
#define v_WIN0_CBCR_AXI_GATHER_EN(x) ((x & 1) << 1)
#define v_WIN0_YRGB_AXI_GATHER_EN(x) ((x & 1) << 0)
#define VERSION_INFO (0x94)
#define m_MAJOR (0xff << 24)
#define m_MINOR (0xff << 16)
#define m_BUILD (0xffff)
#define REG_CFG_DONE (0x90)
/* TV Control Registers */
#define TV_CTRL (0x200)
#define TV_SYNC_TIMING (0x204)
#define TV_ACT_TIMING (0x208)
#define TV_ADJ_TIMING (0x20c)
#define TV_FREQ_SC (0x210)
#define TV_FILTER0 (0x214)
#define TV_FILTER1 (0x218)
#define TV_FILTER2 (0x21C)
#define TV_ACT_ST (0x234)
#define TV_ROUTING (0x238)
#define TV_SYNC_ADJUST (0x250)
#define TV_STATUS (0x254)
#define TV_RESET (0x268)
#define TV_SATURATION (0x278)
#define TV_BW_CTRL (0x28C)
#define TV_BRIGHTNESS_CONTRAST (0x290)
/* MMU registers */
#define MMU_DTE_ADDR (0x0300)
#define v_MMU_DTE_ADDR(x) (((x)&0xffffffff)<<0)
#define m_MMU_DTE_ADDR (0xffffffff<<0)
#define MMU_STATUS (0x0304)
#define v_PAGING_ENABLED(x) (((x)&1)<<0)
#define v_PAGE_FAULT_ACTIVE(x) (((x)&1)<<1)
#define v_STAIL_ACTIVE(x) (((x)&1)<<2)
#define v_MMU_IDLE(x) (((x)&1)<<3)
#define v_REPLAY_BUFFER_EMPTY(x) (((x)&1)<<4)
#define v_PAGE_FAULT_IS_WRITE(x) (((x)&1)<<5)
#define v_PAGE_FAULT_BUS_ID(x) (((x)&0x1f)<<6)
#define m_PAGING_ENABLED (1<<0)
#define m_PAGE_FAULT_ACTIVE (1<<1)
#define m_STAIL_ACTIVE (1<<2)
#define m_MMU_IDLE (1<<3)
#define m_REPLAY_BUFFER_EMPTY (1<<4)
#define m_PAGE_FAULT_IS_WRITE (1<<5)
#define m_PAGE_FAULT_BUS_ID (0x1f<<6)
#define MMU_COMMAND (0x0308)
#define v_MMU_CMD(x) (((x)&0x3)<<0)
#define m_MMU_CMD (0x3<<0)
#define MMU_PAGE_FAULT_ADDR (0x030c)
#define v_PAGE_FAULT_ADDR(x) (((x)&0xffffffff)<<0)
#define m_PAGE_FAULT_ADDR (0xffffffff<<0)
#define MMU_ZAP_ONE_LINE (0x0310)
#define v_MMU_ZAP_ONE_LINE(x) (((x)&0xffffffff)<<0)
#define m_MMU_ZAP_ONE_LINE (0xffffffff<<0)
#define MMU_INT_RAWSTAT (0x0314)
#define v_PAGE_FAULT_RAWSTAT(x) (((x)&1)<<0)
#define v_READ_BUS_ERROR_RAWSTAT(x) (((x)&1)<<1)
#define m_PAGE_FAULT_RAWSTAT (1<<0)
#define m_READ_BUS_ERROR_RAWSTAT (1<<1)
#define MMU_INT_CLEAR (0x0318)
#define v_PAGE_FAULT_CLEAR(x) (((x)&1)<<0)
#define v_READ_BUS_ERROR_CLEAR(x) (((x)&1)<<1)
#define m_PAGE_FAULT_CLEAR (1<<0)
#define m_READ_BUS_ERROR_CLEAR (1<<1)
#define MMU_INT_MASK (0x031c)
#define v_PAGE_FAULT_MASK(x) (((x)&1)<<0)
#define v_READ_BUS_ERROR_MASK(x) (((x)&1)<<1)
#define m_PAGE_FAULT_MASK (1<<0)
#define m_READ_BUS_ERROR_MASK (1<<1)
#define MMU_INT_STATUS (0x0320)
#define v_PAGE_FAULT_STATUS(x) (((x)&1)<<0)
#define v_READ_BUS_ERROR_STATUS(x) (((x)&1)<<1)
#define m_PAGE_FAULT_STATUS (1<<0)
#define m_READ_BUS_ERROR_STATUS (1<<1)
#define MMU_AUTO_GATING (0x0324)
#define v_MMU_AUTO_GATING(x) (((x)&1)<<0)
#define m_MMU_AUTO_GATING (1<<0)
enum _vop_dma_burst {
DMA_BURST_16 = 0,
DMA_BURST_8,
DMA_BURST_4
};
enum _vop_format_e {
VOP_FORMAT_ARGB888 = 0,
VOP_FORMAT_RGB888,
VOP_FORMAT_RGB565,
VOP_FORMAT_YCBCR420 = 4,
VOP_FORMAT_YCBCR422,
VOP_FORMAT_YCBCR444
};
enum _vop_tv_mode {
TV_NTSC,
TV_PAL,
};
enum _vop_csc_mode {
VOP_CSC_BT601 = 0,
VOP_CSC_JPEG,
VOP_CSC_BT709
};
enum _vop_hwc_size {
VOP_HWC_SIZE_32,
VOP_HWC_SIZE_64
};
#define calscale(x, y) ((((u32)(x-1))*0x1000)/(y-1))
struct lcdc_device {
int id;
struct rk_lcdc_driver driver;
struct device *dev;
struct rk_screen *screen;
void __iomem *regs;
void *regsbak; /* back up reg */
u32 reg_phy_base; /* physical basic address of lcdc register*/
u32 len; /* physical map length of lcdc register*/
spinlock_t reg_lock; /* one time only one process allowed to
config the register*/
int __iomem *hwc_lut_addr_base;
int __iomem *dsp_lut_addr_base;
int prop; /*used for primary or */
/*extended display device*/
bool pre_init;
bool pwr18; /*if lcdc use 1.8v power supply*/
bool clk_on; /*if aclk or hclk is closed,
acess to register is not allowed*/
u8 atv_layer_cnt; /*active layer counter, when
atv_layer_cnt = 0,disable lcdc*/
unsigned int irq;
struct clk *pd; /*lcdc power domain*/
struct clk *hclk; /*lcdc AHP clk*/
struct clk *dclk; /*lcdc dclk*/
struct clk *aclk; /*lcdc share memory frequency*/
u32 pixclock;
u32 standby; /*1:standby,0:work*/
u32 iommu_status;
};
static inline
void lcdc_writel(struct lcdc_device *lcdc_dev, u32 offset, u32 v)
{
u32 *_pv = (u32 *)lcdc_dev->regsbak;
_pv += (offset >> 2);
*_pv = v;
writel_relaxed(v, lcdc_dev->regs + offset);
}
static inline
u32 lcdc_readl(struct lcdc_device *lcdc_dev, u32 offset)
{
u32 v;
u32 *_pv = (u32 *)lcdc_dev->regsbak;
_pv += (offset >> 2);
v = readl_relaxed(lcdc_dev->regs + offset);
*_pv = v;
return v;
}
static inline
u32 lcdc_read_bit(struct lcdc_device *lcdc_dev, u32 offset, u32 msk)
{
u32 _v = readl_relaxed(lcdc_dev->regs + offset);
_v &= msk;
return _v ? 1 : 0;
}
static inline
void lcdc_set_bit(struct lcdc_device *lcdc_dev, u32 offset, u32 msk)
{
u32 *_pv = (u32 *)lcdc_dev->regsbak;
_pv += (offset >> 2);
(*_pv) |= msk;
writel_relaxed(*_pv, lcdc_dev->regs + offset);
}
static inline
void lcdc_clr_bit(struct lcdc_device *lcdc_dev, u32 offset, u32 msk)
{
u32 *_pv = (u32 *)lcdc_dev->regsbak;
_pv += (offset >> 2);
(*_pv) &= (~msk);
writel_relaxed(*_pv, lcdc_dev->regs + offset);
}
static inline
void lcdc_msk_reg(struct lcdc_device *lcdc_dev, u32 offset, u32 msk, u32 v)
{
u32 *_pv = (u32 *)lcdc_dev->regsbak;
_pv += (offset >> 2);
(*_pv) &= (~msk);
(*_pv) |= v;
writel_relaxed(*_pv, lcdc_dev->regs + offset);
}
static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev)
{
writel_relaxed(0x01, lcdc_dev->regs + REG_CFG_DONE);
dsb();
}
#endif /* _RK3036_LCDC_H_ */

1519
drivers/video/rockchip/lcdc/rk3066b_lcdc.c
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558
drivers/video/rockchip/lcdc/rk3066b_lcdc.h
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@ -1,558 +0,0 @@
/* drivers/video/rockchip/chips/rk29_fb.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __RK3066B_LCDC_H
#define __RK3066B_LCDC_H
#include<linux/rk_fb.h>
#define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk))
#define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val)
#define LcdRdReg(inf, addr) (inf->preg->addr)
#define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk))
#define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk))
#define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk))
#define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val))
#define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb()
/********************************************************************
** 宏定义 *
********************************************************************/
/* SYS_CONFIG */
#define m_W2_FORMAT (3<<0)
#define m_W1_FORMAT (1<<2)
#define m_W0_FORMAT (7<<3)
#define m_W0_CBR_DEFLICK_EN (1<<6)
#define m_W0_YRGB_DEFLICK_EN (1<<7)
#define m_INTERIACE_EN (1<<8)
#define m_W2_EN (1<<9)
#define m_W1_EN (1<<10)
#define m_W0_EN (1<<11)
#define m_HWC_EN (1<<12)
#define m_HWC_RELOAD_EN (1<<13)
#define m_W2_INTERLACE_READ (1<<14)
#define m_W1_INTERLACE_READ (1<<15)
#define m_W0_INTERLACE_READ (1<<16)
#define m_LCDC_STANDBY (1<<17)
#define m_HWC_BURST (3<<18)
#define m_W2_BURST (3<<20)
#define m_W1_BURST (3<<22)
#define m_W0_BURST (3<<24)
#define m_W2_LUT_CTL (1<<26)
#define m_DSIP_LUT_CTL (1<<27)
#define m_HWC_REVERSED_COLOR (1<<28)
#define m_W1_AXI_OUTSTANDING2 (1<<29)
#define m_W0_AXI_OUTSTANDING2 (1<<30)
#define m_LCDC_AXICLK_AUTO_ENABLE (1<<31)
#define v_W2_FORMAT(x) (((x)&3)<<0)
#define v_W1_FORMAT(x) (((x)&1)<<2)
#define v_W0_FORMAT(x) (((x)&7)<<3)
#define v_W0_CBR_DEFLICK_EN(x) (((x)&1)<<6)
#define v_W0_YRGB_DEFLICK_EN(x) (((x)&1)<<7)
#define v_INTERIACE_EN(x) (((x)&1)<<8)
#define v_W2_EN(x) (((x)&)1<<9)
#define v_W1_EN(x) (((x)&1)<<10)
#define v_W0_EN(x) (((x)&1)<<11)
#define v_HWC_EN(x) (((x)&1)<<12)
#define v_HWC_RELOAD_EN(x) (((x)&1)<<13)
#define v_W2_INTERLACE_READ(x) (((x)&1)<<14)
#define v_W1_INTERLACE_READ(x) (((x)&1)<<15)
#define v_W0_INTERLACE_READ(x) (((x)&1)<<16)
#define v_LCDC_STANDBY(x) (((x)&1)<<17)
#define v_HWC_BURST(x) (((x)&3)<<18)
#define v_W2_BURST(x) (((x)&3)<<20)
#define v_W1_BURST(x) (((x)&3)<<22)
#define v_W0_BURST(x) (((x)&3)<<24)
#define v_W2_LUT_CTL(x) (((x)&1)<<26)
#define v_DSIP_LUT_CTL(x) (((x)&1)<<27)
#define v_HWC_REVERSED_COLOR(x) (((x)&1)<<28)
#define v_W1_AXI_OUTSTANDING2(x) (((x)&1)<<29)
#define v_W0_AXI_OUTSTANDING2(x) (((x)&1)<<30)
#define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<31)
//LCDC_SWAP_CTRL
#define m_W1_565_RB_SWAP (1<<0)
#define m_W0_565_RB_SWAP (1<<1)
#define m_W0_YRGB_M8_SWAP (1<<2)
#define m_W0_YRGB_R_SHIFT_SWAP (1<<3)
#define m_W0_CBR_R_SHIFT_SWAP (1<<4)
#define m_W0_YRGB_16_SWAP (1<<5)
#define m_W0_YRGB_8_SWAP (1<<6)
#define m_W0_CBR_16_SWAP (1<<7)
#define m_W0_CBR_8_SWAP (1<<8)
#define m_W1_16_SWAP (1<<9)
#define m_W1_8_SWAP (1<<10)
#define m_W1_R_SHIFT_SWAP (1<<11)
#define m_OUTPUT_BG_SWAP (1<<12)
#define m_OUTPUT_RB_SWAP (1<<13)
#define m_OUTPUT_RG_SWAP (1<<14)
#define m_DELTA_SWAP (1<<15)
#define m_DUMMY_SWAP (1<<16)
#define m_W2_BYTE_SWAP (1<<17)
#define v_W1_565_RB_SWAP(x) (((x)&1)<<0)
#define v_W0_565_RB_SWAP(x) (((x)&1)<<1)
#define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<2)
#define v_W0_YRGB_R_SHIFT_SWAP(x) (((x)&1)<<3)
#define v_W0_CBR_R_SHIFT_SWAP(x) (((x)&1)<<4)
#define v_W0_YRGB_16_SWAP(x) (((x)&1)<<5)
#define v_W0_YRGB_8_SWAP(x) (((x)&1)<<6)
#define v_W0_CBR_16_SWAP(x) (((x)&1)<<7)
#define v_W0_CBR_8_SWAP(x) (((x)&1)<<8)
#define v_W1_16_SWAP(x) (((x)&1)<<9)
#define v_W1_8_SWAP(x) (((x)&1)<<10)
#define v_W1_R_SHIFT_SWAP(x) (((x)&1)<<11)
#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<12)
#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<13)
#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<14)
#define v_DELTA_SWAP(x) (((x)&1)<<15)
#define v_DUMMY_SWAP(x) (((x)&1)<<16)
#define v_W2_BYTE_SWAP(x) (((x)&1)<<17)
//LCDC_MCU_TIMING_CTRL
#define m_MCU_WRITE_PERIOD (31<<0)
#define m_MCU_CS_ST (31<<5)
#define m_MCU_CS_END (31<<10)
#define m_MCU_RW_ST (31<<15)
#define m_MCU_RW_END (31<<20)
#define m_MCU_HOLDMODE_SELECT (1<<27)
#define m_MCU_HOLDMODE_FRAME_ST (1<<28)
#define m_MCU_RS_SELECT (1<<29)
#define m_MCU_BYPASSMODE_SELECT (1<<30)
#define m_MCU_OUTPUT_SELECT (1<<31)
#define v_MCU_WRITE_PERIOD(x) (((x)&31)<<0)
#define v_MCU_CS_ST(x) (((x)&31)<<5)
#define v_MCU_CS_END(x) (((x)&31)<<10)
#define v_MCU_RW_ST(x) (((x)&31)<<15)
#define v_MCU_RW_END(x) (((x)&31)<<20)
#define v_MCU_HOLD_STATUS(x) (((x)&1)<<26)
#define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27)
#define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28)
#define v_MCU_RS_SELECT(x) (((x)&1)<<29)
#define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30)
#define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31)
//LCDC_ BLEND_CTRL
#define m_HWC_BLEND_EN (1<<0)
#define m_W2_BLEND_EN (1<<1)
#define m_W1_BLEND_EN (1<<2)
#define m_W0_BLEND_EN (1<<3)
#define m_HWC_BLEND_FACTOR (15<<4)
#define m_W2_BLEND_FACTOR (0xff<<8)
#define m_W1_BLEND_FACTOR (0xff<<16)
#define m_W0_BLEND_FACTOR (0xff<<24)
#define v_HWC_BLEND_EN(x) (((x)&1)<<0)
#define v_W2_BLEND_EN(x) (((x)&1)<<1)
#define v_W1_BLEND_EN(x) (((x)&1)<<2)
#define v_W0_BLEND_EN(x) (((x)&1)<<3)
#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4)
#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8)
#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16)
#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24)
//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL
#define m_KEYCOLOR (0xffffff<<0)
#define m_KEYCOLOR_B (0xff<<0)
#define m_KEYCOLOR_G (0xff<<8)
#define m_KEYCOLOR_R (0xff<<16)
#define m_COLORKEY_EN (1<<24)
#define v_KEYCOLOR(x) (((x)&0xffffff)<<0)
#define v_KEYCOLOR_B(x) (((x)&0xff)<<0)
#define v_KEYCOLOR_G(x) (((x)&0xff)<<8)
#define v_KEYCOLOR_R(x) (((x)&0xff)<<16)
#define v_COLORKEY_EN(x) (((x)&1)<<24)
//LCDC_DEFLICKER_SCL_OFFSET
#define m_W0_YRGB_VSD_OFFSET (0xff<<0)
#define m_W0_YRGB_VSP_OFFSET (0xff<<8)
#define m_W1_VSD_OFFSET (0xff<<16)
#define m_W1_VSP_OFFSET (0xff<<24)
#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0)
#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8)
#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16)
#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24)
//LCDC_DSP_CTRL_REG0
#define m_DISPLAY_FORMAT (0xf<<0)
#define m_HSYNC_POLARITY (1<<4)
#define m_VSYNC_POLARITY (1<<5)
#define m_DEN_POLARITY (1<<6)
#define m_DCLK_POLARITY (1<<7)
#define m_COLOR_SPACE_CONVERSION (3<<8)
#define m_DITHER_UP_EN (1<<10)
#define m_DITHER_DOWN_MODE (1<<11)
#define m_DITHER_DOWN_EN (1<<12)
#define m_INTERLACE_FIELD_POLARITY (1<<13)
#define m_YUV_CLIP (1<<14)
#define m_W1_TRANSP_FROM (1<<15)
#define m_W0_TRANSP_FROM (1<<16)
#define m_W0W1_POSITION_SWAP (1<<17)
#define m_W1_CLIP_EN (1<<18)
#define m_W0_CLIP_EN (1<<19)
#define m_W0_YCBR_PRIORITY_MODE (1<<20)
#define m_CBR_FILTER_656 (1<<21)
#define m_W2_CHIP_EN (1<<22)
#define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0)
#define v_HSYNC_POLARITY(x) (((x)&1)<<4)
#define v_VSYNC_POLARITY(x) (((x)&1)<<5)
#define v_DEN_POLARITY(x) (((x)&1)<<6)
#define v_DCLK_POLARITY(x) (((x)&1)<<7)
#define v_COLOR_SPACE_CONVERSION(x) (((x)&3)<<8)
#define v_DITHER_UP_EN(x) (((x)&1)<<10)
#define v_DITHER_DOWN_MODE(x) (((x)&1)<<11)
#define v_DITHER_DOWN_EN(x) (((x)&1)<<12)
#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13)
#define v_YUV_CLIP(x) (((x)&1)<<14)
#define v_W1_TRANSP_FROM(x) (((x)&1)<<15)
#define v_W0_TRANSP_FROM(x) (((x)&1)<<16)
#define v_W0W1_POSITION_SWAP(x) (((x)&1)<<17)
#define v_W1_CLIP_EN(x) (((x)&1)<<18)
#define v_W0_CLIP_EN(x) (((x)&1)<<19)
#define v_W0_YCBR_PRIORITY_MODE(x) (((x)&1)<<20)
#define v_CBR_FILTER_656(x) (((x)&1)<<21)
#define v_W2_CHIP_EN(x) (((x)&1)<<22)
//LCDC_DSP_CTRL_REG1
#define m_BG_COLOR (0xffffff<<0)
#define m_BG_B (0xff<<0)
#define m_BG_G (0xff<<8)
#define m_BG_R (0xff<<16)
#define m_BLANK_MODE (1<<24)
#define m_BLACK_MODE (1<<25)
#define m_DISP_FILTER_FACTOR (3<<26)
#define m_DISP_FILTER_MODE (1<<28)
#define m_DISP_FILTER_EN (1<<29)
#define v_BG_COLOR(x) (((x)&0xffffff)<<0)
#define v_BG_B(x) (((x)&0xff)<<0)
#define v_BG_G(x) (((x)&0xff)<<8)
#define v_BG_R(x) (((x)&0xff)<<16)
#define v_BLANK_MODE(x) (((x)&1)<<24)
#define v_BLACK_MODE(x) (((x)&1)<<25)
#define v_DISP_FILTER_FACTOR(x) (((x)&3)<<26)
#define v_DISP_FILTER_MODE(x) (((x)&1)<<28)
#define v_DISP_FILTER_EN(x) (((x)&1)<<29)
//LCDC_INT_STATUS
#define m_HOR_START (1<<0)
#define m_FRM_START (1<<1)
#define m_SCANNING_FLAG (1<<2)
#define m_HOR_STARTMASK (1<<3)
#define m_FRM_STARTMASK (1<<4)
#define m_SCANNING_MASK (1<<5)
#define m_HOR_STARTCLEAR (1<<6)
#define m_FRM_STARTCLEAR (1<<7)
#define m_SCANNING_CLEAR (1<<8)
#define m_SCAN_LINE_NUM (0x7ff<<9)
#define v_HOR_START(x) (((x)&1)<<0)
#define v_FRM_START(x) (((x)&1)<<1)
#define v_SCANNING_FLAG(x) (((x)&1)<<2)
#define v_HOR_STARTMASK(x) (((x)&1)<<3)
#define v_FRM_STARTMASK(x) (((x)&1)<<4)
#define v_SCANNING_MASK(x) (((x)&1)<<5)
#define v_HOR_STARTCLEAR(x) (((x)&1)<<6)
#define v_FRM_STARTCLEAR(x) (((x)&1)<<7)
#define v_SCANNING_CLEAR(x) (((x)&1)<<8)
#define v_SCAN_LINE_NUM(x) (((x)&0x7ff)<<9)
//AXI MS ID
#define m_W0_YRGB_CH_ID (0xF<<0)
#define m_W0_CBR_CH_ID (0xF<<4)
#define m_W1_YRGB_CH_ID (0xF<<8)
#define m_W2_CH_ID (0xF<<12)
#define m_HWC_CH_ID (0xF<<16)
#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0)
#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4)
#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8)
#define v_W2_CH_ID(x) (((x)&0xF)<<12)
#define v_HWC_CH_ID(x) (((x)&0xF)<<16)
/* Low Bits Mask */
#define m_WORDLO (0xffff<<0)
#define m_WORDHI (0xffff<<16)
#define v_WORDLO(x) (((x)&0xffff)<<0)
#define v_WORDHI(x) (((x)&0xffff)<<16)
#define m_BIT11LO (0x7ff<<0)
#define m_BIT11HI (0x7ff<<16)
#define v_BIT11LO(x) (((x)&0x7ff)<<0)
#define v_BIT11HI(x) (((x)&0x7ff)<<16)
#define m_BIT12LO (0xfff<<0)
#define m_BIT12HI (0xfff<<16)
#define v_BIT12LO(x) (((x)&0xfff)<<0)
#define v_BIT12HI(x) (((x)&0xfff)<<16)
#define m_VIRWIDTH (0xffff<<0)
#define m_VIRHEIGHT (0xffff<<16)
#define v_VIRWIDTH(x) (((x)&0xffff)<<0)
#define v_VIRHEIGHT(x) (((x)&0xffff)<<16)
#define m_ACTWIDTH (0xffff<<0)
#define m_ACTHEIGHT (0xffff<<16)
#define v_ACTWIDTH(x) (((x)&0xffff)<<0)
#define v_ACTHEIGHT(x) (((x)&0xffff)<<16)
#define m_VIRST_X (0xffff<<0)
#define m_VIRST_Y (0xffff<<16)
#define v_VIRST_X(x) (((x)&0xffff)<<0)
#define v_VIRST_Y(x) (((x)&0xffff)<<16)
#define m_PANELST_X (0x3ff<<0)
#define m_PANELST_Y (0x3ff<<16)
#define v_PANELST_X(x) (((x)&0x3ff)<<0)
#define v_PANELST_Y(x) (((x)&0x3ff)<<16)
#define m_PANELWIDTH (0x3ff<<0)
#define m_PANELHEIGHT (0x3ff<<16)
#define v_PANELWIDTH(x) (((x)&0x3ff)<<0)
#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16)
#define m_HWC_B (0xff<<0)
#define m_HWC_G (0xff<<8)
#define m_HWC_R (0xff<<16)
#define m_W0_YRGB_HSP_OFFSET (0xff<<24)
#define m_W0_YRGB_HSD_OFFSET (0xff<<24)
#define v_HWC_B(x) (((x)&0xff)<<0)
#define v_HWC_G(x) (((x)&0xff)<<8)
#define v_HWC_R(x) (((x)&0xff)<<16)
#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24)
#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24)
//Panel display scanning
#define m_PANEL_HSYNC_WIDTH (0x3ff<<0)
#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16)
#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0)
#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16)
#define m_PANEL_END (0x3ff<<0)
#define m_PANEL_START (0x3ff<<16)
#define v_PANEL_END(x) (((x)&0x3ff)<<0)
#define v_PANEL_START(x) (((x)&0x3ff)<<16)
#define m_PANEL_VSYNC_WIDTH (0x3ff<<0)
#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16)
#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0)
#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16)
//-----------
#define m_HSCALE_FACTOR (0xffff<<0)
#define m_VSCALE_FACTOR (0xffff<<16)
#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0)
#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16)
#define m_W0_CBR_HSD_OFFSET (0xff<<0)
#define m_W0_CBR_HSP_OFFSET (0xff<<8)
#define m_W0_CBR_VSD_OFFSET (0xff<<16)
#define m_W0_CBR_VSP_OFFSET (0xff<<24)
#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0)
#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8)
#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16)
#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24)
#define m_WIN1_FIFO_FULL_LEVEL (0x7f << 0)
#define m_WIN2_FIFO_FULL_LEVEL (0x1f << 7)
#define v_WIN1_FIFO_FULL_LEVEL(x) (((x)&0x7f) << 0)
#define v_WIN2_FIFO_FULL_LEVEL(x) (((x)&0x1f) << 7)
#define m_WIN0_YRGB_CHANNEL_ID ((0x0f)<<0)
#define m_WIN0_CBR_CHANNEL_ID ((0x0f)<<4)
#define m_WIN1_YRGB_CHANNEL_ID ((0x0f)<<8)
#define m_WIN2_CHANNEL_ID ((0x0f)<<12)
#define m_HWC_CHANNEL_ID ((0x0f)<<16)
#define v_WIN0_YRGB_CHANNEL_ID(x) (((x)&0x0f)<<0)
#define v_WIN0_CBR_CHANNEL_ID(x) (((x)&0x0f)<<4)
#define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&0x0f)<<8)
#define v_WIN2_CHANNEL_ID(x) (((x)&0x0f)<<12)
#define v_HWC_CHANNEL_ID(x) (((x)&0x0f)<<16)
//LCDC_WINx_SCL_FACTOR_Y/CBCR
#define v_X_SCL_FACTOR(x) ((x)<<0)
#define v_Y_SCL_FACTOR(x) ((x)<<16)
//LCDC_DSP_HTOTAL_HS_END
#define v_HSYNC(x) ((x)<<0) //hsync pulse width
#define v_HORPRD(x) ((x)<<16) //horizontal period
//LCDC_DSP_HACT_ST_END
#define v_HAEP(x) ((x)<<0) //horizontal active end point
#define v_HASP(x) ((x)<<16) //horizontal active start point
//LCDC_DSP_VTOTAL_VS_END
#define v_VSYNC(x) ((x)<<0)
#define v_VERPRD(x) ((x)<<16)
//LCDC_DSP_VACT_ST_END
#define v_VAEP(x) ((x)<<0)
#define v_VASP(x) ((x)<<16)
//LCDC_WIN0_ACT_INFO
#define v_ACT_WIDTH(x) ((x)<<0)
#define v_ACT_HEIGHT(x) ((x)<<16)
//LCDC_WIN0_DSP_INFO
#define v_DSP_WIDTH(x) ((x)<<0)
#define v_DSP_HEIGHT(x) ((x)<<16)
//LCDC_WIN0_DSP_ST //x,y start point of the panel scanning
#define v_DSP_STX(x) (x<<0)
#define v_DSP_STY(x) (x<<16)
/********************************************************************
** 结构定义 *
********************************************************************/
/* LCDC的寄存器结构 */
typedef volatile struct tagLCDC_REG
{
/* offset 0x00~0xc0 */
unsigned int SYS_CFG; //0x00 SYSTEM configure register
unsigned int SWAP_CTRL; //0x04 Data SWAP control
unsigned int MCU_CTRL; //0x08 MCU TIMING control register
unsigned int BLEND_CTRL; //0x0c Blending control register
unsigned int WIN0_COLOR_KEY_CTRL; //0x10 Win0 blending control register
unsigned int WIN1_COLOR_KEY_CTRL; //0x14 Win1 blending control register
unsigned int WIN2_VIR; //0x18 WIN2 virtual display width
unsigned int DSP_CTRL0; //0x1c Display control register0
unsigned int DSP_CTRL1; //0x20 Display control register1
unsigned int INT_STATUS; //0x24 Interrupt status register
unsigned int WIN0_VIR; //0x28 WIN0 virtual display width/height
unsigned int WIN0_YRGB_MST; //0x2c Win0 active YRGB memory start address
unsigned int WIN0_CBR_MST; //0x30 Win0 active Cbr memory start address
unsigned int WIN0_ACT_INFO; //0x34 Win0 active window width/height
unsigned int WIN0_DSP_ST; //0x38 Win0 display start point on panel
unsigned int WIN0_DSP_INFO; //0x3c Win0 display width/height on panel
unsigned int WIN1_VIR; //0x40 Win1 virtual display width/height
unsigned int WIN1_YRGB_MST; //0x44 Win1 active memory start address
unsigned int WIN1_DSP_INFO; //0x48 Win1 display width/height on panel
unsigned int WIN1_DSP_ST; //0x4c Win1 display start point on panel
unsigned int WIN2_MST; //0X50 Win2 memory start address
unsigned int WIN2_DSP_INFO; //0x54 Win1 display width/height on panel
unsigned int WIN2_DSP_ST; //0x58 Win1 display start point on panel
unsigned int HWC_MST; //0x5C HWC memory start address
unsigned int HWC_DSP_ST; //0x60 HWC display start point on panel
unsigned int HWC_COLOR_LUT0; //0x64 Hardware cursor color 2’b01 look up table 0
unsigned int HWC_COLOR_LUT1; //0x68 Hardware cursor color 2’b10 look up table 1
unsigned int HWC_COLOR_LUT2; //0x6c Hardware cursor color 2’b11 look up table 2
unsigned int DSP_HTOTAL_HS_END; //0x70 Panel scanning horizontal width and hsync pulse end point
unsigned int DSP_HACT_ST_END; //0x74 Panel active horizontal scanning start/end point
unsigned int DSP_VTOTAL_VS_END; //0x78 Panel scanning vertical height and vsync pulse end point
unsigned int DSP_VACT_ST_END; //0x7c Panel active vertical scanning start/end point
unsigned int DSP_VS_ST_END_F1; //0x80 Vertical scanning start point and vsync pulse end point of even filed in interlace mode
unsigned int DSP_VACT_ST_END_F1; //0x84 Vertical scanning active start/end point of even filed in interlace mode
unsigned int WIN0_SCL_FACTOR_YRGB; //0x88 Win0 YRGB scaling down factor setting
unsigned int WIN0_SCL_FACTOR_CBR; //0x8c Win0 YRGB scaling up factor setting
unsigned int WIN0_SCL_OFFSET; //0x90 Win0 Cbr scaling start point offset
unsigned int FIFO_WATER_MARK; //0x94 Fifo water mark
unsigned int AXI_MS_ID; //0x98 Axi master ID
unsigned int reserved0; //0x9c
unsigned int REG_CFG_DONE; //0xa0 REGISTER CONFIG FINISH
unsigned int reserved1[(0x100-0xa4)/4];
unsigned int MCU_BYPASS_WPORT; //0x100 MCU BYPASS MODE, DATA Write Only Port
unsigned int reserved2[(0x200-0x104)/4];
unsigned int MCU_BYPASS_RPORT; //0x200 MCU BYPASS MODE, DATA Read Only Port
} LCDC_REG, *pLCDC_REG;
#define Win2_LUT_ADDR 0x400
#define DSP_LUT_ADDR 0x800
//roate
#define ROTATE_0 0
#define ROTATE_90 90
#define ROTATE_180 180
#define ROTATE_270 270
#define X_MIRROR (1<<10)
#define Y_MIRROR (1<<11)
#define CalScale(x, y) (((u32)x*0x1000)/y)
struct rk3066b_lcdc_device{
int id;
struct rk_lcdc_device_driver driver;
rk_screen *screen;
LCDC_REG *preg; // LCDC reg base address and backup reg
LCDC_REG regbak;
void __iomem *reg_vir_base; // virtual basic address of lcdc register
u32 reg_phy_base; // physical basic address of lcdc register
u32 len; // physical map length of lcdc register
spinlock_t reg_lock; //one time only one process allowed to config the register
int __iomem *dsp_lut_addr_base;
bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed
u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc
unsigned int irq;
struct clk *pd; //lcdc power domain
struct clk *hclk; //lcdc AHP clk
struct clk *dclk; //lcdc dclk
struct clk *aclk; //lcdc share memory frequency
struct clk *aclk_parent; //lcdc aclk divider frequency source
struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable.
struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable.
struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable.
struct clk *pd_display; // display power domain
u32 pixclock;
};
struct lcdc_info{
/*LCD CLK*/
struct rk3066b_lcdc_device lcdc0;
struct rk3066b_lcdc_device lcdc1;
};
struct win_set {
volatile u32 y_offset;
volatile u32 c_offset;
};
struct win0_par {
u32 refcount;
u32 pseudo_pal[16];
u32 y_offset;
u32 c_offset;
u32 xpos; //size in panel
u32 ypos;
u32 xsize; //start point in panel
u32 ysize;
enum data_format format;
wait_queue_head_t wait;
struct win_set mirror;
struct win_set displ;
struct win_set done;
u8 par_seted;
u8 addr_seted;
};
#endif

1748
drivers/video/rockchip/lcdc/rk30_lcdc.c
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700
drivers/video/rockchip/lcdc/rk30_lcdc.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef RK30_LCDC_H_
#define RK30_LCDC_H_
#include<linux/rk_fb.h>
#if 0
#define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk))
#define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val)
#define LcdRdReg(inf, addr) (inf->preg->addr)
#define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk))
#define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk))
#define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk))
#define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val))
#define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb()
/********************************************************************
** 结构定义 *
********************************************************************/
/* LCDC的寄存器结构 */
typedef volatile struct tagLCDC_REG
{
/* offset 0x00~0xc0 */
unsigned int SYS_CTRL0; //0x00 system control register 0
unsigned int SYS_CTRL1; //0x04 system control register 1
unsigned int DSP_CTRL0; //0x08 display control register 0
unsigned int DSP_CTRL1; //0x0c display control register 1
unsigned int INT_STATUS; //0x10 Interrupt status register
unsigned int MCU_CTRL ; //0x14 MCU mode contol register
unsigned int BLEND_CTRL; //0x18 Blending control register
unsigned int WIN0_COLOR_KEY_CTRL; //0x1c Win0 blending control register
unsigned int WIN1_COLOR_KEY_CTRL; //0x20 Win1 blending control register
unsigned int WIN2_COLOR_KEY_CTRL; //0x24 Win2 blending control register
unsigned int WIN0_YRGB_MST0; //0x28 Win0 active YRGB memory start address0
unsigned int WIN0_CBR_MST0; //0x2c Win0 active Cbr memory start address0
unsigned int WIN0_YRGB_MST1; //0x30 Win0 active YRGB memory start address1
unsigned int WIN0_CBR_MST1; //0x34 Win0 active Cbr memory start address1
unsigned int WIN0_VIR; //0x38 WIN0 virtual display width/height
unsigned int WIN0_ACT_INFO; //0x3C Win0 active window width/height
unsigned int WIN0_DSP_INFO; //0x40 Win0 display width/height on panel
unsigned int WIN0_DSP_ST; //0x44 Win0 display start point on panel
unsigned int WIN0_SCL_FACTOR_YRGB; //0x48Win0 YRGB scaling factor setting
unsigned int WIN0_SCL_FACTOR_CBR; //0x4c Win0 YRGB scaling factor setting
unsigned int WIN0_SCL_OFFSET; //0x50 Win0 Cbr scaling start point offset
unsigned int WIN1_YRGB_MST; //0x54 Win1 active YRGB memory start address
unsigned int WIN1_CBR_MST; //0x58 Win1 active Cbr memory start address
unsigned int WIN1_VIR; //0x5c WIN1 virtual display width/height
unsigned int WIN1_ACT_INFO; //0x60 Win1 active window width/height
unsigned int WIN1_DSP_INFO; //0x64 Win1 display width/height on panel
unsigned int WIN1_DSP_ST; //0x68 Win1 display start point on panel
unsigned int WIN1_SCL_FACTOR_YRGB; //0x6c Win1 YRGB scaling factor setting
unsigned int WIN1_SCL_FACTOR_CBR; //0x70 Win1 YRGB scaling factor setting
unsigned int WIN1_SCL_OFFSET; //0x74 Win1 Cbr scaling start point offset
unsigned int WIN2_MST; //0x78 win2 memort start address
unsigned int WIN2_VIR; //0x7c win2 virtual stride
unsigned int WIN2_DSP_INFO; //0x80 Win2 display width/height on panel
unsigned int WIN2_DSP_ST; //0x84 Win2 display start point on panel
unsigned int HWC_MST; //0x88 HWC memory start address
unsigned int HWC_DSP_ST; //0x8C HWC display start point on panel
unsigned int HWC_COLOR_LUT0; //0x90 Hardware cursor color 2’b01 look up table 0
unsigned int HWC_COLOR_LUT1; //0x94 Hardware cursor color 2’b10 look up table 1
unsigned int HWC_COLOR_LUT2; //0x98 Hardware cursor color 2’b11 look up table 2
unsigned int DSP_HTOTAL_HS_END; //0x9c Panel scanning horizontal width and hsync pulse end point
unsigned int DSP_HACT_ST_END; //0xa0 Panel active horizontal scanning start/end point
unsigned int DSP_VTOTAL_VS_END; //0xa4 Panel scanning vertical height and vsync pulse end point
unsigned int DSP_VACT_ST_END; //0xa8 Panel active vertical scanning start/end point
unsigned int DSP_VS_ST_END_F1; //0xac Vertical scanning start point and vsync pulse end point of even filed in interlace mode
unsigned int DSP_VACT_ST_END_F1; //0xb0 Vertical scanning active start/end point of even filed in interlace mode
unsigned int reserved0[(0xc0-0xb4)/4];
unsigned int REG_CFG_DONE; //0xc0 REGISTER CONFIG FINISH
unsigned int reserved1[(0x100-0xc4)/4];
unsigned int MCU_BYPASS_WPORT; //0x100 MCU BYPASS MODE, DATA Write Only Port
unsigned int reserved2[(0x200-0x104)/4];
unsigned int MCU_BYPASS_RPORT; //0x200 MCU BYPASS MODE, DATA Read Only Port
unsigned int reserved3[(0x400-0x204)/4];
unsigned int WIN2_LUT_ADDR;
unsigned int reserved4[(0x800-0x404)/4];
unsigned int DSP_LUT_ADDR;
} LCDC_REG, *pLCDC_REG;
#else
#define SYS_CTRL0 0x00 //0x00 system control register 0
#define SYS_CTRL1 0x04 //0x04 system control register 1
#define DSP_CTRL0 0x08 //0x08 display control register 0
#define DSP_CTRL1 0x0c //0x0c display control register 1
#define INT_STATUS 0x10 //0x10 Interrupt status register
#define MCU_CTRL 0x14 //0x14 MCU mode contol register
#define BLEND_CTRL 0x18 //0x18 Blending control register
#define WIN0_COLOR_KEY_CTRL 0x1c //0x1c Win0 blending control register
#define WIN1_COLOR_KEY_CTRL 0x20 //0x20 Win1 blending control register
#define WIN2_COLOR_KEY_CTRL 0x24 //0x24 Win2 blending control register
#define WIN0_YRGB_MST0 0x28 //0x28 Win0 active YRGB memory start address0
#define WIN0_CBR_MST0 0x2c //0x2c Win0 active Cbr memory start address0
#define WIN0_YRGB_MST1 0x30 //0x30 Win0 active YRGB memory start address1
#define WIN0_CBR_MST1 0x34 //0x34 Win0 active Cbr memory start address1
#define WIN0_VIR 0x38 //0x38 WIN0 virtual display width/height
#define WIN0_ACT_INFO 0x3c //0x3C Win0 active window width/height
#define WIN0_DSP_INFO 0x40 //0x40 Win0 display width/height on panel
#define WIN0_DSP_ST 0x44 //0x44 Win0 display start point on panel
#define WIN0_SCL_FACTOR_YRGB 0x48 //0x48Win0 YRGB scaling factor setting
#define WIN0_SCL_FACTOR_CBR 0x4c //0x4c Win0 YRGB scaling factor setting
#define WIN0_SCL_OFFSET 0x50 //0x50 Win0 Cbr scaling start point offset
#define WIN1_YRGB_MST 0x54 //0x54 Win1 active YRGB memory start address
#define WIN1_CBR_MST 0x58 //0x58 Win1 active Cbr memory start address
#define WIN1_VIR 0x5c //0x5c WIN1 virtual display width/height
#define WIN1_ACT_INFO 0x60 //0x60 Win1 active window width/height
#define WIN1_DSP_INFO 0x64 //0x64 Win1 display width/height on panel
#define WIN1_DSP_ST 0x68 //0x68 Win1 display start point on panel
#define WIN1_SCL_FACTOR_YRGB 0x6c //0x6c Win1 YRGB scaling factor setting
#define WIN1_SCL_FACTOR_CBR 0x70 //0x70 Win1 YRGB scaling factor setting
#define WIN1_SCL_OFFSET 0x74 //0x74 Win1 Cbr scaling start point offset
#define WIN2_MST 0x78 //0x78 win2 memort start address
#define WIN2_VIR 0x7c //0x7c win2 virtual stride
#define WIN2_DSP_INFO 0x80 //0x80 Win2 display width/height on panel
#define WIN2_DSP_ST 0x84 //0x84 Win2 display start point on panel
#define HWC_MST 0x88 //0x88 HWC memory start address
#define HWC_DSP_ST 0x8c //0x8C HWC display start point on panel
#define HWC_COLOR_LUT0 0x90 //0x90 Hardware cursor color 2’b01 look up table 0
#define HWC_COLOR_LUT1 0x94 //0x94 Hardware cursor color 2’b10 look up table 1
#define HWC_COLOR_LUT2 0x98 //0x98 Hardware cursor color 2’b11 look up table 2
#define DSP_HTOTAL_HS_END 0x9c //0x9c Panel scanning horizontal width and hsync pulse end point
#define DSP_HACT_ST_END 0xa0 //0xa0 Panel active horizontal scanning start/end point
#define DSP_VTOTAL_VS_END 0xa4 //0xa4 Panel scanning vertical height and vsync pulse end point
#define DSP_VACT_ST_END 0xa8 //0xa8 Panel active vertical scanning start/end point
#define DSP_VS_ST_END_F1 0xac //0xac Vertical scanning start point and vsync pulse end point of even filed in interlace mode
#define DSP_VACT_ST_END_F1 0xb0 //0xb0 Vertical scanning active start/end point of even filed in interlace mode
#define REG_CFG_DONE 0xc0 //0xc0 REGISTER CONFIG FINISH
#define MCU_BYPASS_WPORT 0x100 //0x100 MCU BYPASS MODE, DATA Write Only Port
#define MCU_BYPASS_RPORT 0x200 //0x200 MCU BYPASS MODE, DATA Read Only Port
#define WIN2_LUT_ADDR 0x400
#define DSP_LUT_ADDR 0x800
#if 0
#define lcdc_writel(lcdc_dev,offset,v) do { \
u32 *_pv = (u32*)lcdc_dev->regsbak; \
_pv += (offset >> 2); \
writel_relaxed(v,lcdc_dev->regs+offset);\
*_pv = v; \
} while(0)
#define lcdc_readl(lcdc_dev,offset) \
readl_relaxed(lcdc_dev->regs+offset)
#define lcdc_read_bit(lcdc_dev,offset,msk) ( { \
u32 _v = readl_relaxed(lcdc_dev->regs+offset); \
_v &= msk;_v; } )
#define lcdc_set_bit(lcdc_dev,offset,msk) do { \
u32* _pv = (u32*)lcdc_dev->regsbak; \
_pv += (offset >> 2); \
(*_pv) |= msk; \
writel_relaxed(*_pv,lcdc_dev->regs + offset); \
} while(0)
#define lcdc_clr_bit(lcdc_dev,offset,msk) do{ \
u32* _pv = (u32*)lcdc_dev->regsbak; \
_pv += (offset >> 2); \
(*_pv) &= ~msk; \
writel_relaxed(*_pv,lcdc_dev->regs + offset); \
} while (0)
#define lcdc_msk_reg(lcdc_dev,offset,msk,v) do { \
u32 *_pv = (u32*)lcdc_dev->regsbak; \
_pv += (offset >> 2); \
(*_pv) &= (~msk); \
(*_pv) |= v; \
writel_relaxed(*_pv,lcdc_dev->regs+offset); \
} while(0)
#define lcdc_cfg_done(lcdc_dev) do{ \
writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE); \
dsb(); \
} while(0)
#endif
#endif
/* SYS_CONFIG */
#define m_LCDC_DMA_STOP (1<<0)
#define m_LCDC_STANDBY (1<<1)
#define m_HWC_RELOAD_EN (1<<2)
#define m_W0_AXI_OUTSTANDING_DISABLE (1<<3)
#define m_W1_AXI_OUTSTANDING_DISABLE (1<<4)
#define m_W2_AXI_OUTSTANDING_DISABLE (1<<5)
#define m_DMA_BURST_LENGTH (3<<6)
#define m_WIN0_YRGB_CHANNEL0_ID ((0x07)<<8)
#define m_WIN0_CBR_CHANNEL0_ID ((0x07)<<11)
#define m_WIN0_YRGB_CHANNEL1_ID ((0x07)<<14)
#define m_WIN0_CBR_CHANNEL1_ID ((0x07)<<17)
#define m_WIN1_YRGB_CHANNEL_ID ((0x07)<<20)
#define m_WIN1_CBR_CHANNEL_ID ((0x07)<<23)
#define m_WIN2_CHANNEL_ID ((0x07)<<26)
#define m_HWC_CHANNEL_ID ((0x07)<<29)
#define v_LCDC_DMA_STOP(x) (((x)&1)<<0)
#define v_LCDC_STANDBY(x) (((x)&1)<<1)
#define v_HWC_RELOAD_EN(x) (((x)&1)<<2)
#define v_W0_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<3)
#define v_W1_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<4)
#define v_W2_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<5)
#define v_DMA_BURST_LENGTH(x) (((x)&3)<<6)
#define v_WIN0_YRGB_CHANNEL0_ID(x) (((x)&7)<<8)
#define v_WIN0_CBR_CHANNEL0_ID(x) (((x)&7)<<11)
#define v_WIN0_YRGB_CHANNEL1_ID(x) (((x)&7)<<14)
#define v_WIN0_CBR_CHANNEL1_ID(x) (((x)&7)<<17)
#define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&7)<<20)
#define v_WIN1_CBR_CHANNEL_ID(x) (((x)&7)<<23)
#define v_WIN2_CHANNEL_ID(x) (((x)&7)<<26)
#define v_HWC_CHANNEL_ID(x) (((x)&7)<<29)
//LCDC_SYS_CTRL1
#define m_W0_EN (1<<0)
#define m_W1_EN (1<<1)
#define m_W2_EN (1<<2)
#define m_HWC_EN (1<<3)
#define m_W0_FORMAT (7<<4)
#define m_W1_FORMAT (7<<7)
#define m_W2_FORMAT (7<<10)
#define m_HWC_COLOR_MODE (1<<13)
#define m_HWC_SIZE_SELET (1<<14)
#define m_W0_3D_MODE_EN (1<<15)
#define m_W0_3D_MODE_SELET (7<<16)
#define m_W0_RGB_RB_SWAP (1<<19)
#define m_W0_RGB_ALPHA_SWAP (1<<20)
#define m_W0_YRGB_M8_SWAP (1<<21)
#define m_W0_CBCR_SWAP (1<<22)
#define m_W1_RGB_RB_SWAP (1<<23)
#define m_W1_RGB_ALPHA_SWAP (1<<24)
#define m_W1_YRGB_M8_SWAP (1<<25)
#define m_W1_CBCR_SWAP (1<<26)
#define m_W2_RGB_RB_SWAP (1<<27)
#define m_W2_RGB_ALPHA_SWAP (1<<28)
#define m_W2_8pp_PALETTE_ENDIAN_SELECT (1<<29)
#define m_W2_LUT_RAM_EN (1<<30)
#define m_DSP_LUT_RAM_EN (1<<31)
#define v_W0_EN(x) (((x)&1)<<0)
#define v_W1_EN(x) (((x)&1)<<1)
#define v_W2_EN(x) (((x)&1)<<2)
#define v_HWC_EN(x) (((x)&1)<<3)
#define v_W0_FORMAT(x) (((x)&7)<<4)
#define v_W1_FORMAT(x) (((x)&7)<<7)
#define v_W2_FORMAT(x) (((x)&7)<<10)
#define v_HWC_COLOR_MODE(x) (((x)&1)<<13)
#define v_HWC_SIZE_SELET(x) (((x)&1)<<14)
#define v_W0_3D_MODE_EN(x) (((x)&1)<<15)
#define v_W0_3D_MODE_SELET(x) (((x)&3)<<16)
#define v_W0_RGB_RB_SWAP(x) (((x)&1)<<19)
#define v_W0_RGB_ALPHA_SWAP(x) (((x)&1)<<20)
#define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<21)
#define v_W0_CBCR_SWAP(x) (((x)&1)<<22)
#define v_W1_RGB_RB_SWAP(x) (((x)&1)<<23)
#define v_W1_RGB_ALPHA_SWAP(x) (((x)&1)<<24)
#define v_W1_YRGB_M8_SWAP(x) (((x)&1)<<25)
#define v_W1_CBCR_SWAP(x) (((x)&1)<<26)
#define v_W2_RGB_RB_SWAP(x) (((x)&1)<<27)
#define v_W2_RGB_ALPHA_SWAP(x) (((x)&1)<<28)
#define v_W2_8pp_PALETTE_ENDIAN_SELECT (((x)&1)<<29)
#define v_W2_LUT_RAM_EN(x) (((x)&1)<<30)
#define v_DSP_LUT_RAM_EN(x) (((x)&1)<<31)
//LCDC_DSP_CTRL_REG0
#define m_DISPLAY_FORMAT (0x0f<<0)
#define m_HSYNC_POLARITY (1<<4)
#define m_VSYNC_POLARITY (1<<5)
#define m_DEN_POLARITY (1<<6)
#define m_DCLK_POLARITY (1<<7)
#define m_W0W1_POSITION_SWAP (1<<8)
#define m_DITHER_UP_EN (1<<9)
#define m_DITHER_DOWN_MODE (1<<10)
#define m_DITHER_DOWN_EN (1<<11)
#define m_INTERLACE_DSP_EN (1<<12)
#define m_INTERLACE_FIELD_POLARITY (1<<13)
#define m_W0_INTERLACE_READ_MODE (1<<14)
#define m_W1_INTERLACE_READ_MODE (1<<15)
#define m_W2_INTERLACE_READ_MODE (1<<16)
#define m_W0_YRGB_DEFLICK_MODE (1<<17)
#define m_W0_CBR_DEFLICK_MODE (1<<18)
#define m_W1_YRGB_DEFLICK_MODE (1<<19)
#define m_W1_CBR_DEFLICK_MODE (1<<20)
#define m_W0_ALPHA_MODE (1<<21)
#define m_W1_ALPHA_MODE (1<<22)
#define m_W2_ALPHA_MODE (1<<23)
#define m_W0_COLOR_SPACE_CONVERSION (3<<24)
#define m_W1_COLOR_SPACE_CONVERSION (3<<26)
#define m_W2_COLOR_SPACE_CONVERSION (1<<28)
#define m_YCRCB_CLIP_EN (1<<29)
#define m_CBR_FILTER_656 (1<<30)
#define m_LCDC_AXICLK_AUTO_ENABLE (1<<31) //eanble for low power
#define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0)
#define v_HSYNC_POLARITY(x) (((x)&1)<<4)
#define v_VSYNC_POLARITY(x) (((x)&1)<<5)
#define v_DEN_POLARITY(x) (((x)&1)<<6)
#define v_DCLK_POLARITY(x) (((x)&1)<<7)
#define v_W0W1_POSITION_SWAP(x) (((x)&1)<<8)
#define v_DITHER_UP_EN(x) (((x)&1)<<9)
#define v_DITHER_DOWN_MODE(x) (((x)&1)<<10)
#define v_DITHER_DOWN_EN(x) (((x)&1)<<11)
#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12)
#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13)
#define v_W0_INTERLACE_READ_MODE(x) (((x)&1)<<14)
#define v_W1_INTERLACE_READ_MODE(x) (((x)&1)<<15)
#define v_W2_INTERLACE_READ_MODE(x) (((x)&1)<<16)
#define v_W0_YRGB_DEFLICK_MODE(x) (((x)&1)<<17)
#define v_W0_CBR_DEFLICK_MODE(x) (((x)&1)<<18)
#define v_W1_YRGB_DEFLICK_MODE(x) (((x)&1)<<19)
#define v_W1_CBR_DEFLICK_MODE(x) (((x)&1)<<20)
#define v_W0_ALPHA_MODE(x) (((x)&1)<<21)
#define v_W1_ALPHA_MODE(x) (((x)&1)<<22)
#define v_W2_ALPHA_MODE(x) (((x)&1)<<23)
#define v_W0_COLOR_SPACE_CONVERSION(x) (((x)&3)<<24)
#define v_W1_COLOR_SPACE_CONVERSION(x) (((x)&3)<<26)
#define v_W2_COLOR_SPACE_CONVERSION(x) (((x)&1)<<28)
#define v_YCRCB_CLIP_EN(x) (((x)&1)<<29)
#define v_CBR_FILTER_656(x) (((x)&1)<<30)
#define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<31) //eanble for low power
//LCDC_DSP_CTRL_REG1
#define m_BG_COLOR (0xffffff<<0)
#define m_BG_B (0xff<<0)
#define m_BG_G (0xff<<8)
#define m_BG_R (0xff<<16)
#define m_BLANK_MODE (1<<24)
#define m_BLACK_MODE (1<<25)
#define m_OUTPUT_BG_SWAP (1<<26)
#define m_OUTPUT_RB_SWAP (1<<27)
#define m_OUTPUT_RG_SWAP (1<<28)
#define m_DELTA_SWAP (1<<29)
#define m_DUMMY_SWAP (1<<30)
#define v_BG_COLOR(x) (((x)&0xffffff)<<0)
#define v_BG_B(x) (((x)&0xff)<<0)
#define v_BG_G(x) (((x)&0xff)<<8)
#define v_BG_R(x) (((x)&0xff)<<16)
#define v_BLANK_MODE(x) (((x)&1)<<24)
#define v_BLACK_MODE(x) (((x)&1)<<25)
#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<26)
#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<27)
#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<28)
#define v_DELTA_SWAP(x) (((x)&1)<<29)
#define v_DUMMY_SWAP(x) (((x)&1)<<30)
//LCDC_INT_STATUS
#define v_HOR_START_INT_STA (1<<0) //status
#define v_FRM_START_INT_STA (1<<1)
#define v_LINE_FLAG_INT_STA (1<<2)
#define v_BUS_ERR_INT_STA (1<<3)
#define m_HOR_START_INT_EN (1<<4) //enable
#define m_FRM_START_INT_EN (1<<5)
#define m_LINE_FLAG_INT_EN (1<<6)
#define m_BUS_ERR_INT_EN (1<<7)
#define m_HOR_START_INT_CLEAR (1<<8) //auto clear
#define m_FRM_START_INT_CLEAR (1<<9)
#define m_LINE_FLAG_INT_CLEAR (1<<10)
#define m_BUS_ERR_INT_CLEAR (1<<11)
#define m_LINE_FLAG_NUM (0xfff<<12)
#define v_HOR_START_INT_EN(x) (((x)&1)<<4)
#define v_FRM_START_INT_EN(x) (((x)&1)<<5)
#define v_LINE_FLAG_INT_EN(x) (((x)&1)<<6)
#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7)
#define v_HOR_START_INT_CLEAR(x) (((x)&1)<<8)
#define v_FRM_START_INT_CLEAR(x) (((x)&1)<<9)
#define v_LINE_FLAG_INT_CLEAR(x) (((x)&1)<<10)
#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11)
#define v_LINE_FLAG_NUM(x) (((x)&0xfff)<<12)
//LCDC_MCU_TIMING_CTRL
#define m_MCU_WRITE_PERIOD (0x3f<<0)
#define m_MCU_CS_ST (0xf<<6)
#define m_MCU_CS_END (0x3f<<10)
#define m_MCU_RW_ST (0xf<<16)
#define m_MCU_RW_END (0x3f<<20)
#define m_MCU_BPS_CLK_SEL (1<<26)
#define m_MCU_HOLDMODE_SELECT (1<<27)
#define m_MCU_HOLDMODE_FRAME_ST (1<<28)
#define m_MCU_RS_SELECT (1<<29)
#define m_MCU_BYPASSMODE_SELECT (1<<30)
#define m_MCU_OUTPUT_SELECT (1<<31)
#define v_MCU_WRITE_PERIOD(x) (((x)&0x3f)<<0)
#define v_MCU_CS_ST(x) (((x)&0xf)<<6)
#define v_MCU_CS_END(x) (((x)&0x3f)<<10)
#define v_MCU_RW_ST(x) (((x)&0xf)<<16)
#define v_MCU_RW_END(x) (((x)&0x3f)<<20)
#define v_MCU_BPS_CLK_SEL (((x)&1)<<26)
#define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27)
#define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28)
#define v_MCU_RS_SELECT(x) (((x)&1)<<29)
#define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30)
#define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31)
//LCDC_ BLEND_CTRL
#define m_W0_BLEND_EN (1<<0)
#define m_W1_BLEND_EN (1<<1)
#define m_W2_BLEND_EN (1<<2)
#define m_HWC_BLEND_EN (1<<3)
#define m_W0_BLEND_FACTOR (15<<4)
#define m_W1_BLEND_FACTOR (0xff<<8)
#define m_W2_BLEND_FACTOR (0xff<<16)
#define m_HWC_BLEND_FACTOR (0xff<<24)
#define v_W0_BLEND_EN(x) (((x)&1)<<0)
#define v_W1_BLEND_EN(x) (((x)&1)<<1)
#define v_W2_BLEND_EN(x) (((x)&1)<<2)
#define v_HWC_BLEND_EN(x) (((x)&1)<<3)
#define v_W0_BLEND_FACTOR(x) (((x)&15)<<4)
#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<8)
#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<16)
#define v_HWC_BLEND_FACTOR(x) (((x)&0xff)<<24)
//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL
#define m_KEYCOLOR (0xffffff<<0)
#define m_KEYCOLOR_B (0xff<<0)
#define m_KEYCOLOR_G (0xff<<8)
#define m_KEYCOLOR_R (0xff<<16)
#define m_COLORKEY_EN (1<<24)
#define v_KEYCOLOR(x) (((x)&0xffffff)<<0)
#define v_KEYCOLOR_B(x) (((x)&0xff)<<0)
#define v_KEYCOLOR_G(x) (((x)&0xff)<<8)
#define v_KEYCOLOR_R(x) (((x)&0xff)<<16)
#define v_COLORKEY_EN(x) (((x)&1)<<24)
//LCDC_DEFLICKER_SCL_OFFSET
#define m_W0_YRGB_VSD_OFFSET (0xff<<0)
#define m_W0_YRGB_VSP_OFFSET (0xff<<8)
#define m_W1_VSD_OFFSET (0xff<<16)
#define m_W1_VSP_OFFSET (0xff<<24)
#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0)
#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8)
#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16)
#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24)
//AXI MS ID
#define m_W0_YRGB_CH_ID (0xF<<0)
#define m_W0_CBR_CH_ID (0xF<<4)
#define m_W1_YRGB_CH_ID (0xF<<8)
#define m_W2_CH_ID (0xF<<12)
#define m_HWC_CH_ID (0xF<<16)
#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0)
#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4)
#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8)
#define v_W2_CH_ID(x) (((x)&0xF)<<12)
#define v_HWC_CH_ID(x) (((x)&0xF)<<16)
/* Low Bits Mask */
#define m_WORDLO (0xffff<<0)
#define m_WORDHI (0xffff<<16)
#define v_WORDLO(x) (((x)&0xffff)<<0)
#define v_WORDHI(x) (((x)&0xffff)<<16)
//LCDC_WINx_SCL_FACTOR_Y/CBCR
#define v_X_SCL_FACTOR(x) ((x)<<0)
#define v_Y_SCL_FACTOR(x) ((x)<<16)
//LCDC_DSP_HTOTAL_HS_END
#define v_HSYNC(x) ((x)<<0) //hsync pulse width
#define v_HORPRD(x) ((x)<<16) //horizontal period
//LCDC_DSP_HACT_ST_END
#define v_HAEP(x) ((x)<<0) //horizontal active end point
#define v_HASP(x) ((x)<<16) //horizontal active start point
//LCDC_DSP_VTOTAL_VS_END
#define v_VSYNC(x) ((x)<<0)
#define v_VERPRD(x) ((x)<<16)
//LCDC_DSP_VACT_ST_END
#define v_VAEP(x) ((x)<<0)
#define v_VASP(x) ((x)<<16)
//LCDC_WINx_VIR ,x is number of words of win0 virtual width
#define v_ARGB888_VIRWIDTH(x) (x)
#define v_RGB888_VIRWIDTH(x) (((x*3)>>2)+((x)%3))
#define v_RGB565_VIRWIDTH(x) (((x)>>1) + ((x%2)?1:0))
#define v_YUV_VIRWIDTH(x) (((x)>>2) +((x%4)?1:0))
#define m_ACTWIDTH (0xffff<<0)
#define m_ACTHEIGHT (0xffff<<16)
#define v_ACTWIDTH(x) (((x)&0xffff)<<0)
#define v_ACTHEIGHT(x) (((x)&0xffff)<<16)
#define m_VIRST_X (0xffff<<0)
#define m_VIRST_Y (0xffff<<16)
#define v_VIRST_X(x) (((x)&0xffff)<<0)
#define v_VIRST_Y(x) (((x)&0xffff)<<16)
#define m_PANELST_X (0x3ff<<0)
#define m_PANELST_Y (0x3ff<<16)
#define v_PANELST_X(x) (((x)&0x3ff)<<0)
#define v_PANELST_Y(x) (((x)&0x3ff)<<16)
#define m_PANELWIDTH (0x3ff<<0)
#define m_PANELHEIGHT (0x3ff<<16)
#define v_PANELWIDTH(x) (((x)&0x3ff)<<0)
#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16)
#define m_HWC_B (0xff<<0)
#define m_HWC_G (0xff<<8)
#define m_HWC_R (0xff<<16)
#define m_W0_YRGB_HSP_OFFSET (0xff<<24)
#define m_W0_YRGB_HSD_OFFSET (0xff<<24)
#define v_HWC_B(x) (((x)&0xff)<<0)
#define v_HWC_G(x) (((x)&0xff)<<8)
#define v_HWC_R(x) (((x)&0xff)<<16)
#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24)
#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24)
//LCDC_WIN0_ACT_INFO
#define v_ACT_WIDTH(x) ((x-1)<<0)
#define v_ACT_HEIGHT(x) ((x-1)<<16)
//LCDC_WIN0_DSP_INFO
#define v_DSP_WIDTH(x) ((x-1)<<0)
#define v_DSP_HEIGHT(x) ((x-1)<<16)
//LCDC_WIN0_DSP_ST //x,y start point of the panel scanning
#define v_DSP_STX(x) (x<<0)
#define v_DSP_STY(x) (x<<16)
//Panel display scanning
#define m_PANEL_HSYNC_WIDTH (0x3ff<<0)
#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16)
#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0)
#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16)
#define m_PANEL_END (0x3ff<<0)
#define m_PANEL_START (0x3ff<<16)
#define v_PANEL_END(x) (((x)&0x3ff)<<0)
#define v_PANEL_START(x) (((x)&0x3ff)<<16)
#define m_PANEL_VSYNC_WIDTH (0x3ff<<0)
#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16)
#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0)
#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16)
//-----------
#define m_HSCALE_FACTOR (0xffff<<0)
#define m_VSCALE_FACTOR (0xffff<<16)
#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0)
#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16)
#define m_W0_CBR_HSD_OFFSET (0xff<<0)
#define m_W0_CBR_HSP_OFFSET (0xff<<8)
#define m_W0_CBR_VSD_OFFSET (0xff<<16)
#define m_W0_CBR_VSP_OFFSET (0xff<<24)
#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0)
#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8)
#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16)
#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24)
#define CalScale(x, y) (((u32)x*0x1000)/y)
struct rk30_lcdc_device{
int id;
struct rk_lcdc_device_driver driver;
rk_screen *screen;
//LCDC_REG *preg; // LCDC reg base address and backup reg
//LCDC_REG regbak;
void __iomem *regs;
void *regsbak; //back up reg
int __iomem *dsp_lut_addr_base;
void __iomem *reg_vir_base; // virtual basic address of lcdc register
u32 reg_phy_base; // physical basic address of lcdc register
u32 len; // physical map length of lcdc register
spinlock_t reg_lock; //one time only one process allowed to config the register
bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed
u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc
unsigned int irq;
struct clk *pd; //lcdc power domain
struct clk *hclk; //lcdc AHP clk
struct clk *dclk; //lcdc dclk
struct clk *aclk; //lcdc share memory frequency
struct clk *aclk_parent; //lcdc aclk divider frequency source
struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable.
struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable.
struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable.
struct clk *pd_display; // display power domain
u32 pixclock;
};
struct lcdc_info{
/*LCD CLK*/
struct rk30_lcdc_device lcdc0;
struct rk30_lcdc_device lcdc1;
};
struct win_set {
volatile u32 y_offset;
volatile u32 c_offset;
};
struct win0_par {
u32 refcount;
u32 pseudo_pal[16];
u32 y_offset;
u32 c_offset;
u32 xpos; //size in panel
u32 ypos;
u32 xsize; //start point in panel
u32 ysize;
enum data_format format;
wait_queue_head_t wait;
struct win_set mirror;
struct win_set displ;
struct win_set done;
u8 par_seted;
u8 addr_seted;
};
static inline void lcdc_writel(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 v)
{
u32 *_pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
*_pv = v;
writel_relaxed(v,lcdc_dev->regs+offset);
}
static inline u32 lcdc_readl(struct rk30_lcdc_device *lcdc_dev,u32 offset)
{
u32 v;
u32 *_pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
v = readl_relaxed(lcdc_dev->regs+offset);
*_pv = v;
return v;
}
static inline u32 lcdc_read_bit(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 msk)
{
u32 _v = readl_relaxed(lcdc_dev->regs+offset);
_v &= msk;
return (_v >> msk);
}
static inline void lcdc_set_bit(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 msk)
{
u32* _pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
(*_pv) |= msk;
writel_relaxed(*_pv,lcdc_dev->regs + offset);
}
static inline void lcdc_clr_bit(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 msk)
{
u32* _pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
(*_pv) &= (~msk);
writel_relaxed(*_pv,lcdc_dev->regs + offset);
}
static inline void lcdc_msk_reg(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 msk,u32 v)
{
u32 *_pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
(*_pv) &= (~msk);
(*_pv) |= v;
writel_relaxed(*_pv,lcdc_dev->regs+offset);
}
static inline void lcdc_cfg_done(struct rk30_lcdc_device *lcdc_dev)
{
writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE);
dsb();
}
#endif

2781
drivers/video/rockchip/lcdc/rk312x_lcdc.c
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768
drivers/video/rockchip/lcdc/rk312x_lcdc.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _RK312X_LCDC_H_
#define _RK312X_LCDC_H_
#include<linux/rk_fb.h>
#include<linux/io.h>
#include<linux/clk.h>
enum _VOP_SOC_TYPE {
VOP_RK3036 = 0,
VOP_RK312X,
};
#define BITS(x, bit) ((x) << (bit))
#define BITS_MASK(x, mask, bit) BITS((x) & (mask), bit)
/*******************register definition**********************/
#define SYS_CTRL (0x00)
#define m_WIN0_EN BITS(1, 0)
#define m_WIN1_EN BITS(1, 1)
#define m_HWC_EN BITS(1, 2)
#define m_WIN0_FORMAT BITS(7, 3)
#define m_WIN1_FORMAT BITS(7, 6)
#define m_HWC_LUT_EN BITS(1, 9)
#define m_HWC_SIZE BITS(1, 10)
#define m_DIRECT_PATH_EN BITS(1, 11) /* rk312x */
#define m_DIRECT_PATH_LAYER BITS(1, 12) /* rk312x */
#define m_TVE_MODE_SEL BITS(1, 13) /* rk312x */
#define m_TVE_DAC_EN BITS(1, 14) /* rk312x */
#define m_WIN0_RB_SWAP BITS(1, 15)
#define m_WIN0_ALPHA_SWAP BITS(1, 16)
#define m_WIN0_Y8_SWAP BITS(1, 17)
#define m_WIN0_UV_SWAP BITS(1, 18)
#define m_WIN1_RB_SWAP BITS(1, 19)
#define m_WIN1_ALPHA_SWAP BITS(1, 20)
#define m_WIN1_ENDIAN_SWAP BITS(1, 21) /* rk312x */
#define m_WIN0_OTSD_DISABLE BITS(1, 22)
#define m_WIN1_OTSD_DISABLE BITS(1, 23)
#define m_DMA_BURST_LENGTH BITS(3, 24)
#define m_HWC_LODAD_EN BITS(1, 26)
#define m_WIN1_LUT_EN BITS(1, 27) /* rk312x */
#define m_DSP_LUT_EN BITS(1, 28) /* rk312x */
#define m_DMA_STOP BITS(1, 29)
#define m_LCDC_STANDBY BITS(1, 30)
#define m_AUTO_GATING_EN BITS(1, 31)
#define v_WIN0_EN(x) BITS_MASK(x, 1, 0)
#define v_WIN1_EN(x) BITS_MASK(x, 1, 1)
#define v_HWC_EN(x) BITS_MASK(x, 1, 2)
#define v_WIN0_FORMAT(x) BITS_MASK(x, 7, 3)
#define v_WIN1_FORMAT(x) BITS_MASK(x, 7, 6)
#define v_HWC_LUT_EN(x) BITS_MASK(x, 1, 9)
#define v_HWC_SIZE(x) BITS_MASK(x, 1, 10)
#define v_DIRECT_PATH_EN(x) BITS_MASK(x, 1, 11)
#define v_DIRECT_PATH_LAYER(x) BITS_MASK(x, 1, 12)
#define v_TVE_MODE_SEL(x) BITS_MASK(x, 1, 13)
#define v_TVE_DAC_EN(x) BITS_MASK(x, 1, 14)
#define v_WIN0_RB_SWAP(x) BITS_MASK(x, 1, 15)
#define v_WIN0_ALPHA_SWAP(x) BITS_MASK(x, 1, 16)
#define v_WIN0_Y8_SWAP(x) BITS_MASK(x, 1, 17)
#define v_WIN0_UV_SWAP(x) BITS_MASK(x, 1, 18)
#define v_WIN1_RB_SWAP(x) BITS_MASK(x, 1, 19)
#define v_WIN1_ALPHA_SWAP(x) BITS_MASK(x, 1, 20)
#define v_WIN1_ENDIAN_SWAP(x) BITS_MASK(x, 1, 21)
#define v_WIN0_OTSD_DISABLE(x) BITS_MASK(x, 1, 22)
#define v_WIN1_OTSD_DISABLE(x) BITS_MASK(x, 1, 23)
#define v_DMA_BURST_LENGTH(x) BITS_MASK(x, 3, 24)
#define v_HWC_LODAD_EN(x) BITS_MASK(x, 1, 26)
#define v_WIN1_LUT_EN(x) BITS_MASK(x, 1, 27)
#define v_DSP_LUT_EN(x) BITS_MASK(x, 1, 28)
#define v_DMA_STOP(x) BITS_MASK(x, 1, 29)
#define v_LCDC_STANDBY(x) BITS_MASK(x, 1, 30)
#define v_AUTO_GATING_EN(x) BITS_MASK(x, 1, 31)
#define DSP_CTRL0 (0x04)
#define m_DSP_OUT_FORMAT BITS(0x0f, 0)
#define m_HSYNC_POL BITS(1, 4)
#define m_VSYNC_POL BITS(1, 5)
#define m_DEN_POL BITS(1, 6)
#define m_DCLK_POL BITS(1, 7)
#define m_WIN0_TOP BITS(1, 8)
#define m_DITHER_UP_EN BITS(1, 9)
#define m_DITHER_DOWN_MODE BITS(1, 10) /* use for rk312x */
#define m_DITHER_DOWN_EN BITS(1, 11) /* use for rk312x */
#define m_INTERLACE_DSP_EN BITS(1, 12)
#define m_INTERLACE_FIELD_POL BITS(1, 13) /* use for rk312x */
#define m_WIN0_INTERLACE_EN BITS(1, 14) /* use for rk312x */
#define m_WIN1_INTERLACE_EN BITS(1, 15)
#define m_WIN0_YRGB_DEFLICK_EN BITS(1, 16)
#define m_WIN0_CBR_DEFLICK_EN BITS(1, 17)
#define m_WIN0_ALPHA_MODE BITS(1, 18)
#define m_WIN1_ALPHA_MODE BITS(1, 19)
#define m_WIN0_CSC_MODE BITS(3, 20)
#define m_WIN1_CSC_MODE BITS(1, 22)
#define m_WIN0_YUV_CLIP BITS(1, 23)
#define m_TVE_MODE BITS(1, 25)
#define m_SW_UV_OFFSET_EN BITS(1, 26) /* use for rk312x */
#define m_DITHER_DOWN_SEL BITS(1, 27) /* use for rk312x */
#define m_HWC_ALPHA_MODE BITS(1, 28)
#define m_ALPHA_MODE_SEL0 BITS(1, 29)
#define m_ALPHA_MODE_SEL1 BITS(1, 30)
#define m_WIN1_DIFF_DCLK_EN BITS(1, 31) /* use for rk3036 */
#define m_SW_OVERLAY_MODE BITS(1, 31) /* use for rk312x */
#define v_DSP_OUT_FORMAT(x) BITS_MASK(x, 0x0f, 0)
#define v_HSYNC_POL(x) BITS_MASK(x, 1, 4)
#define v_VSYNC_POL(x) BITS_MASK(x, 1, 5)
#define v_DEN_POL(x) BITS_MASK(x, 1, 6)
#define v_DCLK_POL(x) BITS_MASK(x, 1, 7)
#define v_WIN0_TOP(x) BITS_MASK(x, 1, 8)
#define v_DITHER_UP_EN(x) BITS_MASK(x, 1, 9)
#define v_DITHER_DOWN_MODE(x) BITS_MASK(x, 1, 10) /* rk312x */
#define v_DITHER_DOWN_EN(x) BITS_MASK(x, 1, 11) /* rk312x */
#define v_INTERLACE_DSP_EN(x) BITS_MASK(x, 1, 12)
#define v_INTERLACE_FIELD_POL(x) BITS_MASK(x, 1, 13) /* rk312x */
#define v_WIN0_INTERLACE_EN(x) BITS_MASK(x, 1, 14) /* rk312x */
#define v_WIN1_INTERLACE_EN(x) BITS_MASK(x, 1, 15)
#define v_WIN0_YRGB_DEFLICK_EN(x) BITS_MASK(x, 1, 16)
#define v_WIN0_CBR_DEFLICK_EN(x) BITS_MASK(x, 1, 17)
#define v_WIN0_ALPHA_MODE(x) BITS_MASK(x, 1, 18)
#define v_WIN1_ALPHA_MODE(x) BITS_MASK(x, 1, 19)
#define v_WIN0_CSC_MODE(x) BITS_MASK(x, 3, 20)
#define v_WIN1_CSC_MODE(x) BITS_MASK(x, 1, 22)
#define v_WIN0_YUV_CLIP(x) BITS_MASK(x, 1, 23)
#define v_TVE_MODE(x) BITS_MASK(x, 1, 25)
#define v_SW_UV_OFFSET_EN(x) BITS_MASK(x, 1, 26) /* rk312x */
#define v_DITHER_DOWN_SEL(x) BITS_MASK(x, 1, 27) /* rk312x */
#define v_HWC_ALPHA_MODE(x) BITS_MASK(x, 1, 28)
#define v_ALPHA_MODE_SEL0(x) BITS_MASK(x, 1, 29)
#define v_ALPHA_MODE_SEL1(x) BITS_MASK(x, 1, 30)
#define v_WIN1_DIFF_DCLK_EN(x) BITS_MASK(x, 1, 31) /* rk3036 */
#define v_SW_OVERLAY_MODE(x) BITS_MASK(x, 1, 31) /* rk312x */
#define DSP_CTRL1 (0x08)
#define m_BG_COLOR BITS(0xffffff, 0)
#define m_BG_B BITS(0xff, 0)
#define m_BG_G BITS(0xff, 8)
#define m_BG_R BITS(0xff, 16)
#define m_BLANK_EN BITS(1, 24)
#define m_BLACK_EN BITS(1, 25)
#define m_DSP_BG_SWAP BITS(1, 26)
#define m_DSP_RB_SWAP BITS(1, 27)
#define m_DSP_RG_SWAP BITS(1, 28)
#define m_DSP_DELTA_SWAP BITS(1, 29) /* rk3036 */
#define m_DSP_DUMMY_SWAP BITS(1, 30) /* rk3036 */
#define m_DSP_OUT_ZERO BITS(1, 31)
#define v_BG_COLOR(x) BITS_MASK(x, 0xffffff, 0)
#define v_BG_B(x) BITS_MASK(x, 0xff, 0)
#define v_BG_G(x) BITS_MASK(x, 0xff, 8)
#define v_BG_R(x) BITS_MASK(x, 0xff, 16)
#define v_BLANK_EN(x) BITS_MASK(x, 1, 24)
#define v_BLACK_EN(x) BITS_MASK(x, 1, 25)
#define v_DSP_BG_SWAP(x) BITS_MASK(x, 1, 26)
#define v_DSP_RB_SWAP(x) BITS_MASK(x, 1, 27)
#define v_DSP_RG_SWAP(x) BITS_MASK(x, 1, 28)
#define v_DSP_DELTA_SWAP(x) BITS_MASK(x, 1, 29) /* rk3036 */
#define v_DSP_DUMMY_SWAP(x) BITS_MASK(x, 1, 30) /* rk3036 */
#define v_DSP_OUT_ZERO(x) BITS_MASK(x, 1, 31)
#define INT_SCALER (0x0c) /* only use for rk312x */
#define m_SCALER_EMPTY_INTR_EN BITS(1, 0)
#define m_SCLAER_EMPTY_INTR_CLR BITS(1, 1)
#define m_SCLAER_EMPTY_INTR_STA BITS(1, 2)
#define m_FS_MASK_EN BITS(1, 3)
#define m_HDMI_HSYNC_POL BITS(1, 4)
#define m_HDMI_VSYNC_POL BITS(1, 5)
#define m_HDMI_DEN_POL BITS(1, 6)
#define v_SCALER_EMPTY_INTR_EN(x) BITS_MASK(x, 1, 0)
#define v_SCLAER_EMPTY_INTR_CLR(x) BITS_MASK(x, 1, 1)
#define v_SCLAER_EMPTY_INTR_STA(x) BITS_MASK(x, 1, 2)
#define v_FS_MASK_EN(x) BITS_MASK(x, 1, 3)
#define v_HDMI_HSYNC_POL(x) BITS_MASK(x, 1, 4)
#define v_HDMI_VSYNC_POL(x) BITS_MASK(x, 1, 5)
#define v_HDMI_DEN_POL(x) BITS_MASK(x, 1, 6)
#define INT_STATUS (0x10)
#define m_HS_INT_STA BITS(1, 0)
#define m_FS_INT_STA BITS(1, 1)
#define m_LF_INT_STA BITS(1, 2)
#define m_BUS_ERR_INT_STA BITS(1, 3)
#define m_HS_INT_EN BITS(1, 4)
#define m_FS_INT_EN BITS(1, 5)
#define m_LF_INT_EN BITS(1, 6)
#define m_BUS_ERR_INT_EN BITS(1, 7)
#define m_HS_INT_CLEAR BITS(1, 8)
#define m_FS_INT_CLEAR BITS(1, 9)
#define m_LF_INT_CLEAR BITS(1, 10)
#define m_BUS_ERR_INT_CLEAR BITS(1, 11)
#define m_LF_INT_NUM BITS(0xfff, 12)
#define m_WIN0_EMPTY_INT_EN BITS(1, 24)
#define m_WIN1_EMPTY_INT_EN BITS(1, 25)
#define m_WIN0_EMPTY_INT_CLEAR BITS(1, 26)
#define m_WIN1_EMPTY_INT_CLEAR BITS(1, 27)
#define m_WIN0_EMPTY_INT_STA BITS(1, 28)
#define m_WIN1_EMPTY_INT_STA BITS(1, 29)
#define m_FS_RAW_STA BITS(1, 30)
#define m_LF_RAW_STA BITS(1, 31)
#define v_HS_INT_EN(x) BITS_MASK(x, 1, 4)
#define v_FS_INT_EN(x) BITS_MASK(x, 1, 5)
#define v_LF_INT_EN(x) BITS_MASK(x, 1, 6)
#define v_BUS_ERR_INT_EN(x) BITS_MASK(x, 1, 7)
#define v_HS_INT_CLEAR(x) BITS_MASK(x, 1, 8)
#define v_FS_INT_CLEAR(x) BITS_MASK(x, 1, 9)
#define v_LF_INT_CLEAR(x) BITS_MASK(x, 1, 10)
#define v_BUS_ERR_INT_CLEAR(x) BITS_MASK(x, 1, 11)
#define v_LF_INT_NUM(x) BITS_MASK(x, 0xfff, 12)
#define v_WIN0_EMPTY_INT_EN(x) BITS_MASK(x, 1, 24)
#define v_WIN1_EMPTY_INT_EN(x) BITS_MASK(x, 1, 25)
#define v_WIN0_EMPTY_INT_CLEAR(x) BITS_MASK(x, 1, 26)
#define v_WIN1_EMPTY_INT_CLEAR(x) BITS_MASK(x, 1, 27)
#define ALPHA_CTRL (0x14)
#define m_WIN0_ALPHA_EN BITS(1, 0)
#define m_WIN1_ALPHA_EN BITS(1, 1)
#define m_HWC_ALPAH_EN BITS(1, 2)
#define m_WIN1_PREMUL_SCALE BITS(1, 3) /* rk3036 */
#define m_WIN0_ALPHA_VAL BITS(0xff, 4)
#define m_WIN1_ALPHA_VAL BITS(0xff, 12)
#define m_HWC_ALPAH_VAL BITS(0xff, 20)
#define v_WIN0_ALPHA_EN(x) BITS_MASK(x, 1, 0)
#define v_WIN1_ALPHA_EN(x) BITS_MASK(x, 1, 1)
#define v_HWC_ALPAH_EN(x) BITS_MASK(x, 1, 2)
#define v_WIN1_PREMUL_SCALE(x) BITS_MASK(x, 1, 3) /* rk3036 */
#define v_WIN0_ALPHA_VAL(x) BITS_MASK(x, 0xff, 4)
#define v_WIN1_ALPHA_VAL(x) BITS_MASK(x, 0xff, 12)
#define v_HWC_ALPAH_VAL(x) BITS_MASK(x, 0xff, 20)
#define WIN0_COLOR_KEY (0x18)
#define WIN1_COLOR_KEY (0x1c)
#define m_COLOR_KEY_VAL BITS(0xffffff, 0)
#define m_COLOR_KEY_EN BITS(1, 24)
#define v_COLOR_KEY_VAL(x) BITS_MASK(x, 0xffffff, 0)
#define v_COLOR_KEY_EN(x) BITS_MASK(x, 1, 24)
/* Layer Registers */
#define WIN0_YRGB_MST (0x20)
#define WIN0_CBR_MST (0x24)
#define WIN1_MST (0xa0) /* rk3036 */
#define WIN1_MST_RK312X (0x4c) /* rk312x */
#define HWC_MST (0x58)
#define WIN1_VIR (0x28)
#define WIN0_VIR (0x30)
#define m_YRGB_VIR BITS(0x1fff, 0)
#define m_CBBR_VIR BITS(0x1fff, 16)
#define v_YRGB_VIR(x) BITS_MASK(x, 0x1fff, 0)
#define v_CBBR_VIR(x) BITS_MASK(x, 0x1fff, 16)
#define v_ARGB888_VIRWIDTH(x) BITS_MASK(x, 0x1fff, 0)
#define v_RGB888_VIRWIDTH(x) BITS_MASK(((x*3)>>2)+((x)%3), 0x1fff, 0)
#define v_RGB565_VIRWIDTH(x) BITS_MASK(DIV_ROUND_UP(x, 2), 0x1fff, 0)
#define v_YUV_VIRWIDTH(x) BITS_MASK(DIV_ROUND_UP(x, 4), 0x1fff, 0)
#define v_CBCR_VIR(x) BITS_MASK(x, 0x1fff, 16)
#define WIN0_ACT_INFO (0x34)
#define WIN1_ACT_INFO (0xb4) /* rk3036 */
#define m_ACT_WIDTH BITS(0x1fff, 0)
#define m_ACT_HEIGHT BITS(0x1fff, 16)
#define v_ACT_WIDTH(x) BITS_MASK(x - 1, 0x1fff, 0)
#define v_ACT_HEIGHT(x) BITS_MASK(x - 1, 0x1fff, 16)
#define WIN0_DSP_INFO (0x38)
#define WIN1_DSP_INFO (0xb8) /* rk3036 */
#define WIN1_DSP_INFO_RK312X (0x50) /* rk312x */
#define m_DSP_WIDTH BITS(0x7ff, 0)
#define m_DSP_HEIGHT BITS(0x7ff, 16)
#define v_DSP_WIDTH(x) BITS_MASK(x - 1, 0x7ff, 0)
#define v_DSP_HEIGHT(x) BITS_MASK(x - 1, 0x7ff, 16)
#define WIN0_DSP_ST (0x3c)
#define WIN1_DSP_ST (0xbc) /* rk3036 */
#define WIN1_DSP_ST_RK312X (0x54) /* rk312x */
#define HWC_DSP_ST (0x5c)
#define m_DSP_STX BITS(0xfff, 0)
#define m_DSP_STY BITS(0xfff, 16)
#define v_DSP_STX(x) BITS_MASK(x, 0xfff, 0)
#define v_DSP_STY(x) BITS_MASK(x, 0xfff, 16)
#define WIN0_SCL_FACTOR_YRGB (0x40)
#define WIN0_SCL_FACTOR_CBR (0x44)
#define WIN1_SCL_FACTOR_YRGB (0xc0) /* rk3036 */
#define m_X_SCL_FACTOR BITS(0xffff, 0)
#define m_Y_SCL_FACTOR BITS(0xffff, 16)
#define v_X_SCL_FACTOR(x) BITS_MASK(x, 0xffff, 0)
#define v_Y_SCL_FACTOR(x) BITS_MASK(x, 0xffff, 16)
#define WIN0_SCL_OFFSET (0x48)
#define WIN1_SCL_OFFSET (0xc8) /* rk3036 */
/* LUT Registers */
#define WIN1_LUT_ADDR (0x0400) /* rk3036 */
#define HWC_LUT_ADDR (0x0800)
#define DSP_LUT_ADDR (0x0c00) /* rk312x */
/* Display Infomation Registers */
#define DSP_HTOTAL_HS_END (0x6c)
#define v_HSYNC(x) BITS_MASK(x, 0xfff, 0) /* hsync pulse width */
#define v_HORPRD(x) BITS_MASK(x, 0xfff, 16) /* horizontal period */
#define DSP_HACT_ST_END (0x70)
#define v_HAEP(x) BITS_MASK(x, 0xfff, 0) /* horizontal active end point */
#define v_HASP(x) BITS_MASK(x, 0xfff, 16) /* horizontal active start point */
#define DSP_VTOTAL_VS_END (0x74)
#define v_VSYNC(x) BITS_MASK(x, 0xfff, 0)
#define v_VERPRD(x) BITS_MASK(x, 0xfff, 16)
#define DSP_VACT_ST_END (0x78)
#define v_VAEP(x) BITS_MASK(x, 0xfff, 0)
#define v_VASP(x) BITS_MASK(x, 0xfff, 16)
#define DSP_VS_ST_END_F1 (0x7c)
#define v_VSYNC_END_F1(x) BITS_MASK(x, 0xfff, 0)
#define v_VSYNC_ST_F1(x) BITS_MASK(x, 0xfff, 16)
#define DSP_VACT_ST_END_F1 (0x80)
#define v_VAEP_F1(x) BITS_MASK(x, 0xfff, 0)
#define v_VASP_F1(x) BITS_MASK(x, 0xfff, 16)
/* Scaler Registers
* Only used for rk312x
*/
#define SCALER_CTRL (0xa0)
#define m_SCALER_EN BITS(1, 0)
#define m_SCALER_SYNC_INVERT BITS(1, 2)
#define m_SCALER_DEN_INVERT BITS(1, 3)
#define m_SCALER_OUT_ZERO BITS(1, 4)
#define m_SCALER_OUT_EN BITS(1, 5)
#define m_SCALER_VSYNC_MODE BITS(3, 6)
#define m_SCALER_VSYNC_VST BITS(0xff, 8)
#define v_SCALER_EN(x) BITS_MASK(x, 1, 0)
#define v_SCALER_SYNC_INVERT(x) BITS_MASK(x, 1, 2)
#define v_SCALER_DEN_INVERT(x) BITS_MASK(x, 1, 3)
#define v_SCALER_OUT_ZERO(x) BITS_MASK(x, 1, 4)
#define v_SCALER_OUT_EN(x) BITS_MASK(x, 1, 5)
#define v_SCALER_VSYNC_MODE(x) BITS_MASK(x, 3, 6)
#define v_SCALER_VSYNC_VST(x) BITS_MASK(x, 0xff, 8)
#define SCALER_FACTOR (0xa4)
#define m_SCALER_H_FACTOR BITS(0x3fff, 0)
#define m_SCALER_V_FACTOR BITS(0x3fff, 16)
#define v_SCALER_H_FACTOR(x) BITS_MASK(x, 0x3fff, 0)
#define v_SCALER_V_FACTOR(x) BITS_MASK(x, 0x3fff, 16)
#define SCALER_FRAME_ST (0xa8)
#define m_SCALER_FRAME_HST BITS(0xfff, 0)
#define m_SCALER_FRAME_VST BITS(0xfff, 16)
#define v_SCALER_FRAME_HST(x) BITS_MASK(x, 0xfff, 0)
#define v_SCALER_FRAME_VST(x) BITS_MASK(x, 0xfff, 16)
#define SCALER_DSP_HOR_TIMING (0xac)
#define m_SCALER_HTOTAL BITS(0xfff, 0)
#define m_SCALER_HS_END BITS(0xff, 16)
#define v_SCALER_HTOTAL(x) BITS_MASK(x, 0xfff, 0)
#define v_SCALER_HS_END(x) BITS_MASK(x, 0xff, 16)
#define SCALER_DSP_HACT_ST_END (0xb0)
#define m_SCALER_HAEP BITS(0xfff, 0)
#define m_SCALER_HASP BITS(0x3ff, 16)
#define v_SCALER_HAEP(x) BITS_MASK(x, 0xfff, 0)
#define v_SCALER_HASP(x) BITS_MASK(x, 0x3ff, 16)
#define SCALER_DSP_VER_TIMING (0xb4)
#define m_SCALER_VTOTAL BITS(0xfff, 0)
#define m_SCALER_VS_END BITS(0xff, 16)
#define v_SCALER_VTOTAL(x) BITS_MASK(x, 0xfff, 0)
#define v_SCALER_VS_END(x) BITS_MASK(x, 0xff, 16)
#define SCALER_DSP_VACT_ST_END (0xb8)
#define m_SCALER_VAEP BITS(0xfff, 0)
#define m_SCALER_VASP BITS(0xff, 16)
#define v_SCALER_VAEP(x) BITS_MASK(x, 0xfff, 0)
#define v_SCALER_VASP(x) BITS_MASK(x, 0xff, 16)
#define SCALER_DSP_HBOR_TIMING (0xbc)
#define m_SCALER_HBOR_END BITS(0xfff, 0)
#define m_SCALER_HBOR_ST BITS(0x3ff, 16)
#define v_SCALER_HBOR_END(x) BITS_MASK(x, 0xfff, 0)
#define v_SCALER_HBOR_ST(x) BITS_MASK(x, 0x3ff, 16)
#define SCALER_DSP_VBOR_TIMING (0xc0)
#define m_SCALER_VBOR_END BITS(0xfff, 0)
#define m_SCALER_VBOR_ST BITS(0xff, 16)
#define v_SCALER_VBOR_END(x) BITS_MASK(x, 0xfff, 0)
#define v_SCALER_VBOR_ST(x) BITS_MASK(x, 0xff, 16)
/* BCSH Registers */
#define BCSH_CTRL (0xd0)
#define m_BCSH_EN BITS(1, 0)
#define m_BCSH_R2Y_CSC_MODE BITS(1, 1) /* rk312x */
#define m_BCSH_OUT_MODE BITS(3, 2)
#define m_BCSH_Y2R_CSC_MODE BITS(3, 4)
#define m_BCSH_Y2R_EN BITS(1, 6) /* rk312x */
#define m_BCSH_R2Y_EN BITS(1, 7) /* rk312x */
#define v_BCSH_EN(x) BITS_MASK(x, 1, 0)
#define v_BCSH_R2Y_CSC_MODE(x) BITS_MASK(x, 1, 1) /* rk312x */
#define v_BCSH_OUT_MODE(x) BITS_MASK(x, 3, 2)
#define v_BCSH_Y2R_CSC_MODE(x) BITS_MASK(x, 3, 4)
#define v_BCSH_Y2R_EN(x) BITS_MASK(x, 1, 6) /* rk312x */
#define v_BCSH_R2Y_EN(x) BITS_MASK(x, 1, 7) /* rk312x */
#define BCSH_COLOR_BAR (0xd4)
#define m_BCSH_COLOR_BAR_Y BITS(0xff, 0)
#define m_BCSH_COLOR_BAR_U BITS(0xff, 8)
#define m_BCSH_COLOR_BAR_V BITS(0xff, 16)
#define v_BCSH_COLOR_BAR_Y(x) BITS_MASK(x, 0xff, 0)
#define v_BCSH_COLOR_BAR_U(x) BITS_MASK(x, 0xff, 8)
#define v_BCSH_COLOR_BAR_V(x) BITS_MASK(x, 0xff, 16)
#define BCSH_BCS (0xd8)
#define m_BCSH_BRIGHTNESS BITS(0x1f, 0)
#define m_BCSH_CONTRAST BITS(0xff, 8)
#define m_BCSH_SAT_CON BITS(0x1ff, 16)
#define v_BCSH_BRIGHTNESS(x) BITS_MASK(x, 0x1f, 0)
#define v_BCSH_CONTRAST(x) BITS_MASK(x, 0xff, 8)
#define v_BCSH_SAT_CON(x) BITS_MASK(x, 0x1ff, 16)
#define BCSH_H (0xdc)
#define m_BCSH_SIN_HUE BITS(0xff, 0)
#define m_BCSH_COS_HUE BITS(0xff, 8)
#define v_BCSH_SIN_HUE(x) BITS_MASK(x, 0xff, 0)
#define v_BCSH_COS_HUE(x) BITS_MASK(x, 0xff, 8)
#define FRC_LOWER01_0 (0xe0)
#define FRC_LOWER01_1 (0xe4)
#define FRC_LOWER10_0 (0xe8)
#define FRC_LOWER10_1 (0xec)
#define FRC_LOWER11_0 (0xf0)
#define FRC_LOWER11_1 (0xf4)
/* Bus Register */
#define AXI_BUS_CTRL (0x2c)
#define m_IO_PAD_CLK BITS(1, 31)
#define m_CORE_CLK_DIV_EN BITS(1, 30)
#define m_MIPI_DCLK_INVERT BITS(1, 29) /* rk312x */
#define m_MIPI_DCLK_EN BITS(1, 28) /* rk312x */
#define m_LVDS_DCLK_INVERT BITS(1, 27) /* rk312x */
#define m_LVDS_DCLK_EN BITS(1, 26) /* rk312x */
#define m_RGB_DCLK_INVERT BITS(1, 25) /* rk312x */
#define m_RGB_DCLK_EN BITS(1, 24) /* rk312x */
#define m_HDMI_DCLK_INVERT BITS(1, 23)
#define m_HDMI_DCLK_EN BITS(1, 22)
#define m_TVE_DAC_DCLK_INVERT BITS(1, 21)
#define m_TVE_DAC_DCLK_EN BITS(1, 20)
#define m_HDMI_DCLK_DIV_EN BITS(1, 19)
#define m_AXI_OUTSTANDING_MAX_NUM BITS(0x1f, 12)
#define m_AXI_MAX_OUTSTANDING_EN BITS(1, 11)
#define m_MMU_EN BITS(1, 10)
#define m_NOC_HURRY_THRESHOLD BITS(0xf, 6)
#define m_NOC_HURRY_VALUE BITS(3, 4)
#define m_NOC_HURRY_EN BITS(1, 3)
#define m_NOC_QOS_VALUE BITS(3, 1)
#define m_NOC_QOS_EN BITS(1, 0)
#define v_IO_PAD_CLK(x) BITS_MASK(x, 1, 31)
#define v_CORE_CLK_DIV_EN(x) BITS_MASK(x, 1, 30)
#define v_MIPI_DCLK_INVERT(x) BITS_MASK(x, 1, 29)
#define v_MIPI_DCLK_EN(x) BITS_MASK(x, 1, 28)
#define v_LVDS_DCLK_INVERT(x) BITS_MASK(x, 1, 27)
#define v_LVDS_DCLK_EN(x) BITS_MASK(x, 1, 26)
#define v_RGB_DCLK_INVERT(x) BITS_MASK(x, 1, 25)
#define v_RGB_DCLK_EN(x) BITS_MASK(x, 1, 24)
#define v_HDMI_DCLK_INVERT(x) BITS_MASK(x, 1, 23)
#define v_HDMI_DCLK_EN(x) BITS_MASK(x, 1, 22)
#define v_TVE_DAC_DCLK_INVERT(x) BITS_MASK(x, 1, 21)
#define v_TVE_DAC_DCLK_EN(x) BITS_MASK(x, 1, 20)
#define v_HDMI_DCLK_DIV_EN(x) BITS_MASK(x, 1, 19)
#define v_AXI_OUTSTANDING_MAX_NUM(x) BITS_MASK(x, 0x1f, 12)
#define v_AXI_MAX_OUTSTANDING_EN(x) BITS_MASK(x, 1, 11)
#define v_MMU_EN(x) BITS_MASK(x, 1, 10)
#define v_NOC_HURRY_THRESHOLD(x) BITS_MASK(x, 0xf, 6)
#define v_NOC_HURRY_VALUE(x) BITS_MASK(x, 3, 4)
#define v_NOC_HURRY_EN(x) BITS_MASK(x, 1, 3)
#define v_NOC_QOS_VALUE(x) BITS_MASK(x, 3, 1)
#define v_NOC_QOS_EN(x) BITS_MASK(x, 1, 0)
#define GATHER_TRANSFER (0x84)
#define m_WIN1_AXI_GATHER_NUM BITS(0xf, 12)
#define m_WIN0_CBCR_AXI_GATHER_NUM BITS(0x7, 8)
#define m_WIN0_YRGB_AXI_GATHER_NUM BITS(0xf, 4)
#define m_WIN1_AXI_GAHTER_EN BITS(1, 2)
#define m_WIN0_CBCR_AXI_GATHER_EN BITS(1, 1)
#define m_WIN0_YRGB_AXI_GATHER_EN BITS(1, 0)
#define v_WIN1_AXI_GATHER_NUM(x) BITS_MASK(x, 0xf, 12)
#define v_WIN0_CBCR_AXI_GATHER_NUM(x) BITS_MASK(x, 0x7, 8)
#define v_WIN0_YRGB_AXI_GATHER_NUM(x) BITS_MASK(x, 0xf, 4)
#define v_WIN1_AXI_GAHTER_EN(x) BITS_MASK(x, 1, 2)
#define v_WIN0_CBCR_AXI_GATHER_EN(x) BITS_MASK(x, 1, 1)
#define v_WIN0_YRGB_AXI_GATHER_EN(x) BITS_MASK(x, 1, 0)
#define VERSION_INFO (0x94)
#define m_MAJOR BITS(0xff, 24)
#define m_MINOR BITS(0xff, 16)
#define m_BUILD BITS(0xffff)
#define REG_CFG_DONE (0x90)
/* TV Control Registers */
#define TV_CTRL (0x200)
#define TV_SYNC_TIMING (0x204)
#define TV_ACT_TIMING (0x208)
#define TV_ADJ_TIMING (0x20c)
#define TV_FREQ_SC (0x210)
#define TV_FILTER0 (0x214)
#define TV_FILTER1 (0x218)
#define TV_FILTER2 (0x21C)
#define TV_ACT_ST (0x234)
#define TV_ROUTING (0x238)
#define TV_SYNC_ADJUST (0x250)
#define TV_STATUS (0x254)
#define TV_RESET (0x268)
#define TV_SATURATION (0x278)
#define TV_BW_CTRL (0x28C)
#define TV_BRIGHTNESS_CONTRAST (0x290)
/* MMU registers */
#define MMU_DTE_ADDR (0x0300)
#define m_MMU_DTE_ADDR BITS(0xffffffff, 0)
#define v_MMU_DTE_ADDR(x) BITS_MASK(x, 0xffffffff, 0)
#define MMU_STATUS (0x0304)
#define m_PAGING_ENABLED BITS(1, 0)
#define m_PAGE_FAULT_ACTIVE BITS(1, 1)
#define m_STAIL_ACTIVE BITS(1, 2)
#define m_MMU_IDLE BITS(1, 3)
#define m_REPLAY_BUFFER_EMPTY BITS(1, 4)
#define m_PAGE_FAULT_IS_WRITE BITS(1, 5)
#define m_PAGE_FAULT_BUS_ID BITS(0x1f, 6)
#define v_PAGING_ENABLED(x) BITS_MASK(x, 1, 0)
#define v_PAGE_FAULT_ACTIVE(x) BITS_MASK(x, 1, 1)
#define v_STAIL_ACTIVE(x) BITS_MASK(x, 1, 2)
#define v_MMU_IDLE(x) BITS_MASK(x, 1, 3)
#define v_REPLAY_BUFFER_EMPTY(x) BITS_MASK(x, 1, 4)
#define v_PAGE_FAULT_IS_WRITE(x) BITS_MASK(x, 1, 5)
#define v_PAGE_FAULT_BUS_ID(x) BITS_MASK(x, 0x1f, 6)
#define MMU_COMMAND (0x0308)
#define m_MMU_CMD BITS(0x7, 0)
#define v_MMU_CMD(x) BITS_MASK(x, 0x7, 0)
#define MMU_PAGE_FAULT_ADDR (0x030c)
#define m_PAGE_FAULT_ADDR BITS(0xffffffff, 0)
#define v_PAGE_FAULT_ADDR(x) BITS_MASK(x, 0xffffffff, 0)
#define MMU_ZAP_ONE_LINE (0x0310)
#define m_MMU_ZAP_ONE_LINE BITS(0xffffffff, 0)
#define v_MMU_ZAP_ONE_LINE(x) BITS_MASK(x, 0xffffffff, 0)
#define MMU_INT_RAWSTAT (0x0314)
#define m_PAGE_FAULT_RAWSTAT BITS(1, 0)
#define m_READ_BUS_ERROR_RAWSTAT BITS(1, 1)
#define v_PAGE_FAULT_RAWSTAT(x) BITS(x, 1, 0)
#define v_READ_BUS_ERROR_RAWSTAT(x) BITS(x, 1, 1)
#define MMU_INT_CLEAR (0x0318)
#define m_PAGE_FAULT_CLEAR BITS(1, 0)
#define m_READ_BUS_ERROR_CLEAR BITS(1, 1)
#define v_PAGE_FAULT_CLEAR(x) BITS(x, 1, 0)
#define v_READ_BUS_ERROR_CLEAR(x) BITS(x, 1, 1)
#define MMU_INT_MASK (0x031c)
#define m_PAGE_FAULT_MASK BITS(1, 0)
#define m_READ_BUS_ERROR_MASK BITS(1, 1)
#define v_PAGE_FAULT_MASK(x) BITS(x, 1, 0)
#define v_READ_BUS_ERROR_MASK(x) BITS(x, 1, 1)
#define MMU_INT_STATUS (0x0320)
#define m_PAGE_FAULT_STATUS BITS(1, 0)
#define m_READ_BUS_ERROR_STATUS BITS(1, 1)
#define v_PAGE_FAULT_STATUS(x) BITS(x, 1, 0)
#define v_READ_BUS_ERROR_STATUS(x) BITS(x, 1, 1)
#define MMU_AUTO_GATING (0x0324)
#define m_MMU_AUTO_GATING BITS(1, 0)
#define v_MMU_AUTO_GATING(x) BITS(x, 1, 0)
enum _vop_dma_burst {
DMA_BURST_16 = 0,
DMA_BURST_8,
DMA_BURST_4
};
enum _vop_format_e {
VOP_FORMAT_ARGB888 = 0,
VOP_FORMAT_RGB888,
VOP_FORMAT_RGB565,
VOP_FORMAT_YCBCR420 = 4,
VOP_FORMAT_YCBCR422,
VOP_FORMAT_YCBCR444
};
enum _vop_tv_mode {
TV_NTSC,
TV_PAL,
};
enum _vop_r2y_csc_mode {
VOP_R2Y_CSC_BT601 = 0,
VOP_R2Y_CSC_BT709
};
enum _vop_y2r_csc_mode {
VOP_Y2R_CSC_MPEG = 0,
VOP_Y2R_CSC_JPEG,
VOP_Y2R_CSC_HD,
VOP_Y2R_CSC_BYPASS
};
enum _vop_hwc_size {
VOP_HWC_SIZE_32,
VOP_HWC_SIZE_64
};
enum _vop_overlay_mode {
VOP_RGB_DOMAIN,
VOP_YUV_DOMAIN
};
#define CalScale(x, y) ((((u32)(x - 1)) * 0x1000) / (y - 1))
#define INT_STA_MSK (m_HS_INT_STA | m_FS_INT_STA | \
m_LF_INT_STA | m_BUS_ERR_INT_STA)
#define INT_CLR_SHIFT 8
struct rk_lcdc_drvdata {
u8 soc_type;
u32 reserve;
};
struct lcdc_device {
int id;
u8 soc_type;
struct rk_lcdc_driver driver;
struct device *dev;
struct rk_screen *screen;
void __iomem *regs;
void *regsbak; /* back up reg */
u32 reg_phy_base; /* physical basic address of lcdc register */
u32 len; /* physical map length of lcdc register */
spinlock_t reg_lock; /* one time only one process allowed to config the register */
int __iomem *hwc_lut_addr_base;
int __iomem *dsp_lut_addr_base;
int prop; /* used for primary or extended display device */
bool pre_init;
bool pwr18; /* if lcdc use 1.8v power supply */
bool clk_on; /* if aclk or hclk is closed ,acess to register is not allowed */
bool sclk_on; /* if sclk is open or closed */
u8 atv_layer_cnt; /* active layer counter,when atv_layer_cnt = 0,lcdc is disable*/
unsigned int irq;
struct clk *pd; /* lcdc power domain */
struct clk *hclk; /* lcdc AHP clk */
struct clk *dclk; /* lcdc dclk */
struct clk *aclk; /* lcdc share memory frequency */
struct clk *sclk; /* scaler clk */
struct clk *pll_sclk;
u32 pixclock;
u32 s_pixclock;
u32 standby; /* 1:standby,0:work */
struct backlight_device *backlight;
u32 iommu_status;
};
static inline void lcdc_writel(struct lcdc_device *lcdc_dev, u32 offset, u32 v)
{
u32 *_pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
*_pv = v;
writel_relaxed(v, lcdc_dev->regs + offset);
}
static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev, u32 offset)
{
u32 v;
v = readl_relaxed(lcdc_dev->regs + offset);
return v;
}
static inline u32 lcdc_readl_backup(struct lcdc_device *lcdc_dev, u32 offset)
{
u32 v;
u32 *_pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
v = readl_relaxed(lcdc_dev->regs + offset);
*_pv = v;
return v;
}
static inline u32 lcdc_read_bit(struct lcdc_device *lcdc_dev, u32 offset,
u32 msk)
{
u32 _v = readl_relaxed(lcdc_dev->regs + offset);
_v &= msk;
return (_v? 1 : 0);
}
static inline void lcdc_set_bit(struct lcdc_device *lcdc_dev, u32 offset,
u32 msk)
{
u32* _pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
(*_pv) |= msk;
writel_relaxed(*_pv, lcdc_dev->regs + offset);
}
static inline void lcdc_clr_bit(struct lcdc_device *lcdc_dev, u32 offset,
u32 msk)
{
u32* _pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
(*_pv) &= (~msk);
writel_relaxed(*_pv, lcdc_dev->regs + offset);
}
static inline void lcdc_msk_reg(struct lcdc_device *lcdc_dev, u32 offset,
u32 msk, u32 v)
{
u32 *_pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
(*_pv) &= (~msk);
(*_pv) |= v;
writel_relaxed(*_pv, lcdc_dev->regs + offset);
}
static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev)
{
writel_relaxed(0x01, lcdc_dev->regs + REG_CFG_DONE);
dsb();
}
#endif /* _RK312X_LCDC_H_ */

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drivers/video/rockchip/lcdc/rk3188_lcdc.c
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drivers/video/rockchip/lcdc/rk3188_lcdc.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef RK3188_LCDC_H_
#define RK3188_LCDC_H_
#include<linux/rk_fb.h>
#include<linux/io.h>
#include<linux/clk.h>
/*******************register definition**********************/
#define SYS_CTRL (0x00)
#define m_WIN0_EN (1<<0)
#define m_WIN1_EN (1<<1)
#define m_HWC_EN (1<<2)
#define m_WIN0_FORMAT (7<<3)
#define m_WIN1_FORMAT (7<<6)
#define m_HWC_COLOR_MODE (1<<9)
#define m_HWC_SIZE (1<<10)
#define m_WIN0_3D_EN (1<<11)
#define m_WIN0_3D_MODE (7<<12)
#define m_WIN0_RB_SWAP (1<<15)
#define m_WIN0_ALPHA_SWAP (1<<16)
#define m_WIN0_Y8_SWAP (1<<17)
#define m_WIN0_UV_SWAP (1<<18)
#define m_WIN1_RB_SWAP (1<<19)
#define m_WIN1_ALPHA_SWAP (1<<20)
#define m_WIN1_BL_SWAP (1<<21)
#define m_WIN0_OTSD_DISABLE (1<<22)
#define m_WIN1_OTSD_DISABLE (1<<23)
#define m_DMA_BURST_LENGTH (3<<24)
#define m_HWC_LODAD_EN (1<<26)
#define m_WIN1_LUT_EN (1<<27)
#define m_DSP_LUT_EN (1<<28)
#define m_DMA_STOP (1<<29)
#define m_LCDC_STANDBY (1<<30)
#define m_AUTO_GATING_EN (1<<31)
#define v_WIN0_EN(x) (((x)&1)<<0)
#define v_WIN1_EN(x) (((x)&1)<<1)
#define v_HWC_EN(x) (((x)&1)<<2)
#define v_WIN0_FORMAT(x) (((x)&7)<<3)
#define v_WIN1_FORMAT(x) (((x)&7)<<6)
#define v_HWC_COLOR_MODE(x) (((x)&1)<<9)
#define v_HWC_SIZE(x) (((x)&1)<<10)
#define v_WIN0_3D_EN(x) (((x)&1)<<11)
#define v_WIN0_3D_MODE(x) (((x)&7)<<12)
#define v_WIN0_RB_SWAP(x) (((x)&1)<<15)
#define v_WIN0_ALPHA_SWAP(x) (((x)&1)<<16)
#define v_WIN0_Y8_SWAP(x) (((x)&1)<<17)
#define v_WIN0_UV_SWAP(x) (((x)&1)<<18)
#define v_WIN1_RB_SWAP(x) (((x)&1)<<19)
#define v_WIN1_ALPHA_SWAP(x) (((x)&1)<<20)
#define v_WIN1_BL_SWAP(x) (((x)&1)<<21)
#define v_WIN0_OTSD_DISABLE(x) (((x)&1)<<22)
#define v_WIN1_OTSD_DISABLE(x) (((x)&1)<<23)
#define v_DMA_BURST_LENGTH(x) (((x)&3)<<24)
#define v_HWC_LODAD_EN(x) (((x)&1)<<26)
#define v_WIN1_LUT_EN(x) (((x)&1)<<27)
#define v_DSP_LUT_EN(x) (((x)&1)<<28)
#define v_DMA_STOP(x) (((x)&1)<<29)
#define v_LCDC_STANDBY(x) (((x)&1)<<30)
#define v_AUTO_GATING_EN(x) (((x)&1)<<31)
#define DSP_CTRL0 (0x04)
#define m_DSP_OUT_FORMAT (0x0f<<0)
#define m_HSYNC_POL (1<<4)
#define m_VSYNC_POL (1<<5)
#define m_DEN_POL (1<<6)
#define m_DCLK_POL (1<<7)
#define m_WIN0_TOP (1<<8)
#define m_DITHER_UP_EN (1<<9)
#define m_DITHER_DOWN_MODE (1<<10)
#define m_DITHER_DOWN_EN (1<<11)
#define m_INTERLACE_DSP_EN (1<<12)
#define m_INTERLACE_POL (1<<13)
#define m_WIN0_INTERLACE_EN (1<<14)
#define m_WIN1_INTERLACE_EN (1<<15)
#define m_WIN0_YRGB_DEFLICK_EN (1<<16)
#define m_WIN0_CBR_DEFLICK_EN (1<<17)
#define m_WIN0_ALPHA_MODE (1<<18)
#define m_WIN1_ALPHA_MODE (1<<19)
#define m_WIN0_CSC_MODE (3<<20)
#define m_WIN1_CSC_MODE (1<<22)
#define m_WIN0_YUV_CLIP (1<<23)
#define m_DSP_CCIR656_AVG (1<<24)
#define m_DCLK_OUTPUT_MODE (1<<25)
#define m_DCLK_PHASE_LOCK (1<<26)
#define m_DITHER_DOWN_SEL (3<<27)
#define m_ALPHA_MODE_SEL0 (1<<29)
#define m_ALPHA_MODE_SEL1 (1<<30)
#define m_DIFF_DCLK_EN (1<<31)
#define v_DSP_OUT_FORMAT(x) (((x)&0x0f)<<0)
#define v_HSYNC_POL(x) (((x)&1)<<4)
#define v_VSYNC_POL(x) (((x)&1)<<5)
#define v_DEN_POL(x) (((x)&1)<<6)
#define v_DCLK_POL(x) (((x)&1)<<7)
#define v_WIN0_TOP(x) (((x)&1)<<8)
#define v_DITHER_UP_EN(x) (((x)&1)<<9)
#define v_DITHER_DOWN_MODE(x) (((x)&1)<<10)
#define v_DITHER_DOWN_EN(x) (((x)&1)<<11)
#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12)
#define v_INTERLACE_POL(x) (((x)&1)<<13)
#define v_WIN0_INTERLACE_EN(x) (((x)&1)<<14)
#define v_WIN1_INTERLACE_EN(x) (((x)&1)<<15)
#define v_WIN0_YRGB_DEFLICK_EN(x) (((x)&1)<<16)
#define v_WIN0_CBR_DEFLICK_EN(x) (((x)&1)<<17)
#define v_WIN0_ALPHA_MODE(x) (((x)&1)<<18)
#define v_WIN1_ALPHA_MODE(x) (((x)&1)<<19)
#define v_WIN0_CSC_MODE(x) (((x)&3)<<20)
#define v_WIN1_CSC_MODE(x) (((x)&1)<<22)
#define v_WIN0_YUV_CLIP(x) (((x)&1)<<23)
#define v_DSP_CCIR656_AVG(x) (((x)&1)<<24)
#define v_DCLK_OUTPUT_MODE(x) (((x)&1)<<25)
#define v_DCLK_PHASE_LOCK(x) (((x)&1)<<26)
#define v_DITHER_DOWN_SEL(x) (((x)&1)<<27)
#define v_ALPHA_MODE_SEL0(x) (((x)&1)<<29)
#define v_ALPHA_MODE_SEL1(x) (((x)&1)<<30)
#define v_DIFF_DCLK_EN(x) (((x)&1)<<31)
#define DSP_CTRL1 (0x08)
#define m_BG_COLOR (0xffffff<<0)
#define m_BG_B (0xff<<0)
#define m_BG_G (0xff<<8)
#define m_BG_R (0xff<<16)
#define m_BLANK_EN (1<<24)
#define m_BLACK_EN (1<<25)
#define m_DSP_BG_SWAP (1<<26)
#define m_DSP_RB_SWAP (1<<27)
#define m_DSP_RG_SWAP (1<<28)
#define m_DSP_DELTA_SWAP (1<<29)
#define m_DSP_DUMMY_SWAP (1<<30)
#define m_DSP_OUT_ZERO (1<<31)
#define v_BG_COLOR(x) (((x)&0xffffff)<<0)
#define v_BG_B(x) (((x)&0xff)<<0)
#define v_BG_G(x) (((x)&0xff)<<8)
#define v_BG_R(x) (((x)&0xff)<<16)
#define v_BLANK_EN(x) (((x)&1)<<24)
#define v_BLACK_EN(x) (((x)&1)<<25)
#define v_DSP_BG_SWAP(x) (((x)&1)<<26)
#define v_DSP_RB_SWAP(x) (((x)&1)<<27)
#define v_DSP_RG_SWAP(x) (((x)&1)<<28)
#define v_DSP_DELTA_SWAP(x) (((x)&1)<<29)
#define v_DSP_DUMMY_SWAP(x) (((x)&1)<<30)
#define v_DSP_OUT_ZERO(x) (((x)&1)<<31)
#define MCU_CTRL (0x0c)
#define m_MCU_PIX_TOTAL (0x3f<<0)
#define m_MCU_CS_ST (0x0f<<6)
#define m_MCU_CS_END (0x3f<<10)
#define m_MCU_RW_ST (0x0f<<16)
#define m_MCU_RW_END (0x3f<<20)
#define m_MCU_CLK_SEL (1<<26)
#define m_MCU_HOLD_MODE (1<<27)
#define m_MCU_FS_HOLD_STA (1<<28)
#define m_MCU_RS_SELECT (1<<29)
#define m_MCU_BYPASS (1<<30)
#define m_MCU_TYPE (1<<31)
#define v_MCU_PIX_TOTAL(x) (((x)&0x3f)<<0)
#define v_MCU_CS_ST(x) (((x)&0x0f)<<6)
#define v_MCU_CS_END(x) (((x)&0x3f)<<10)
#define v_MCU_RW_ST(x) (((x)&0x0f)<<16)
#define v_MCU_RW_END(x) (((x)&0x3f)<<20)
#define v_MCU_CLK_SEL(x) (((x)&1)<<26)
#define v_MCU_HOLD_MODE(x) (((x)&1)<<27)
#define v_MCU_FS_HOLD_STA(x) (((x)&1)<<28)
#define v_MCU_RS_SELECT(x) (((x)&1)<<29)
#define v_MCU_BYPASS(x) (((x)&1)<<30)
#define v_MCU_TYPE(x) (((x)&1)<<31)
#define INT_STATUS (0x10)
#define m_HS_INT_STA (1<<0) //status
#define m_FS_INT_STA (1<<1)
#define m_LF_INT_STA (1<<2)
#define m_BUS_ERR_INT_STA (1<<3)
#define m_HS_INT_EN (1<<4) //enable
#define m_FS_INT_EN (1<<5)
#define m_LF_INT_EN (1<<6)
#define m_BUS_ERR_INT_EN (1<<7)
#define m_HS_INT_CLEAR (1<<8) //auto clear
#define m_FS_INT_CLEAR (1<<9)
#define m_LF_INT_CLEAR (1<<10)
#define m_BUS_ERR_INT_CLEAR (1<<11)
#define m_LF_INT_NUM (0xfff<<12)
#define v_HS_INT_EN(x) (((x)&1)<<4)
#define v_FS_INT_EN(x) (((x)&1)<<5)
#define v_LF_INT_EN(x) (((x)&1)<<6)
#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7)
#define v_HS_INT_CLEAR(x) (((x)&1)<<8)
#define v_FS_INT_CLEAR(x) (((x)&1)<<9)
#define v_LF_INT_CLEAR(x) (((x)&1)<<10)
#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11)
#define v_LF_INT_NUM(x) (((x)&0xfff)<<12)
#define ALPHA_CTRL (0x14)
#define m_WIN0_ALPHA_EN (1<<0)
#define m_WIN1_ALPHA_EN (1<<1)
#define m_HWC_ALPAH_EN (1<<2)
#define m_WIN0_ALPHA_VAL (0xff<<4)
#define m_WIN1_ALPHA_VAL (0xff<<12)
#define m_HWC_ALPAH_VAL (0x0f<<20)
#define v_WIN0_ALPHA_EN(x) (((x)&1)<<0)
#define v_WIN1_ALPHA_EN(x) (((x)&1)<<1)
#define v_HWC_ALPAH_EN(x) (((x)&1)<<2)
#define v_WIN0_ALPHA_VAL(x) (((x)&0xff)<<4)
#define v_WIN1_ALPHA_VAL(x) (((x)&0xff)<<12)
#define v_HWC_ALPAH_VAL(x) (((x)&0x0f)<<20)
#define WIN0_COLOR_KEY (0x18)
#define m_COLOR_KEY_VAL (0xffffff<<0)
#define m_COLOR_KEY_EN (1<<24)
#define v_COLOR_KEY_VAL(x) (((x)&0xffffff)<<0)
#define v_COLOR_KEY_EN(x) (((x)&1)<<24)
#define WIN1_COLOR_KEY (0x1C)
#define WIN0_YRGB_MST0 (0x20)
#define WIN0_CBR_MST0 (0x24)
#define WIN0_YRGB_MST1 (0x28)
#define WIN0_CBR_MST1 (0x2C)
#define WIN_VIR (0x30)
#define m_WIN0_VIR (0x1fff << 0)
#define m_WIN1_VIR (0x1fff << 16)
#define v_WIN0_VIR_VAL(x) ((x)<<0)
#define v_WIN1_VIR_VAL(x) ((x)<<16)
#define v_ARGB888_VIRWIDTH(x) (((x)&0x1fff)<<0)
#define v_RGB888_VIRWIDTH(x) (((((x*3)>>2)+((x)%3))&0x1fff)<<0)
#define v_RGB565_VIRWIDTH(x) ((DIV_ROUND_UP(x,2)&0x1fff)<<0)
#define v_YUV_VIRWIDTH(x) ((DIV_ROUND_UP(x,4)&0x1fff)<<0)
#define v_WIN1_ARGB888_VIRWIDTH(x) (((x)&0x1fff)<<16)
#define v_WIN1_RGB888_VIRWIDTH(x) (((((x*3)>>2)+((x)%3))&0x1fff)<<16)
#define v_WIN1_RGB565_VIRWIDTH(x) ((DIV_ROUND_UP(x,2)&0x1fff)<<16)
#define WIN0_ACT_INFO (0x34)
#define m_ACT_WIDTH (0x1fff<<0)
#define m_ACT_HEIGHT (0x1fff<<16)
#define v_ACT_WIDTH(x) (((x-1)&0x1fff)<<0)
#define v_ACT_HEIGHT(x) (((x-1)&0x1fff)<<16)
#define WIN0_DSP_INFO (0x38)
#define v_DSP_WIDTH(x) (((x-1)&0x7ff)<<0)
#define v_DSP_HEIGHT(x) (((x-1)&0x7ff)<<16)
#define WIN0_DSP_ST (0x3C)
#define v_DSP_STX(x) (((x)&0xfff)<<0)
#define v_DSP_STY(x) (((x)&0xfff)<<16)
#define WIN0_SCL_FACTOR_YRGB (0x40)
#define v_X_SCL_FACTOR(x) (((x)&0xffff)<<0)
#define v_Y_SCL_FACTOR(x) (((x)&0xffff)<<16)
#define WIN0_SCL_FACTOR_CBR (0x44)
#define WIN0_SCL_OFFSET (0x48)
#define WIN1_MST (0x4C)
#define WIN1_DSP_INFO (0x50)
#define WIN1_DSP_ST (0x54)
#define HWC_MST (0x58)
#define HWC_DSP_ST (0x5C)
#define HWC_COLOR_LUT0 (0x60)
#define HWC_COLOR_LUT1 (0x64)
#define HWC_COLOR_LUT2 (0x68)
#define DSP_HTOTAL_HS_END (0x6C)
#define v_HSYNC(x) (((x)&0xfff)<<0) //hsync pulse width
#define v_HORPRD(x) (((x)&0xfff)<<16) //horizontal period
#define DSP_HACT_ST_END (0x70)
#define v_HAEP(x) (((x)&0xfff)<<0) //horizontal active end point
#define v_HASP(x) (((x)&0xfff)<<16) //horizontal active start point
#define DSP_VTOTAL_VS_END (0x74)
#define v_VSYNC(x) (((x)&0xfff)<<0)
#define v_VERPRD(x) (((x)&0xfff)<<16)
#define DSP_VACT_ST_END (0x78)
#define v_VAEP(x) (((x)&0xfff)<<0)
#define v_VASP(x) (((x)&0xfff)<<16)
#define DSP_VS_ST_END_F1 (0x7C)
#define DSP_VACT_ST_END_F1 (0x80)
#define REG_CFG_DONE (0x90)
#define MCU_BYPASS_WPORT (0x100)
#define MCU_BYPASS_RPORT (0x200)
#define WIN1_LUT_ADDR (0x400)
#define DSP_LUT_ADDR (0x800)
/*
RK3026/RK3028A max output resolution 1920x1080
support IEP instead of 3d
*/
//#ifdef CONFIG_ARCH_RK3026
//SYS_CTRL 0x00
#define m_DIRECT_PATCH_EN (1<<11)
#define m_DIRECT_PATH_LAY_SEL (1<<12)
#define v_DIRECT_PATCH_EN(x) (((x)&1)<<11)
#define v_DIRECT_PATH_LAY_SEL(x) (((x)&1)<<12)
//INT_STATUS 0x10
#define m_WIN0_EMPTY_INTR_EN (1<<24)
#define m_WIN1_EMPTY_INTR_EN (1<<25)
#define m_WIN0_EMPTY_INTR_CLR (1<<26)
#define m_WIN1_EMPTY_INTR_CLR (1<<27)
#define m_WIN0_EMPTY_INTR_STA (1<<28)
#define m_WIN1_EMPTY_INTR_STA (1<<29)
#define v_WIN0_EMPTY_INTR_EN(x) (((x)&1)<<24)
#define v_WIN1_EMPTY_INTR_EN(x) (((x)&1)<<25)
#define v_WIN0_EMPTY_INTR_CLR(x) (((x)&1)<<26)
#define v_WIN1_EMPTY_INTR_CLR(x) (((x)&1)<<27)
#define v_WIN0_EMPTY_INTR_STA(x) (((x)&1)<<28)
#define v_WIN1_EMPTY_INTR_STA(x) (((x)&1)<<29)
//#endif
#define CalScale(x, y) ((((u32)(x-1))*0x1000)/(y-1))
struct lcdc_device{
int id;
struct rk_lcdc_driver driver;
struct device *dev;
struct rk_screen *screen;
void __iomem *regs;
void *regsbak; //back up reg
u32 reg_phy_base; // physical basic address of lcdc register
u32 len; // physical map length of lcdc register
spinlock_t reg_lock; //one time only one process allowed to config the register
int __iomem *dsp_lut_addr_base;
int prop; /*used for primary or extended display device*/
bool pre_init;
bool pwr18; /*if lcdc use 1.8v power supply*/
bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed
u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc
unsigned int irq;
struct clk *pd; //lcdc power domain
struct clk *hclk; //lcdc AHP clk
struct clk *dclk; //lcdc dclk
struct clk *aclk; //lcdc share memory frequency
u32 pixclock;
u32 standby; //1:standby,0:wrok
};
static inline void lcdc_writel(struct lcdc_device *lcdc_dev,u32 offset,u32 v)
{
u32 *_pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
*_pv = v;
writel_relaxed(v,lcdc_dev->regs+offset);
}
static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev,u32 offset)
{
u32 v;
u32 *_pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
v = readl_relaxed(lcdc_dev->regs+offset);
*_pv = v;
return v;
}
static inline u32 lcdc_read_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk)
{
u32 _v = readl_relaxed(lcdc_dev->regs+offset);
_v &= msk;
return (_v?1:0);
}
static inline void lcdc_set_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk)
{
u32* _pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
(*_pv) |= msk;
writel_relaxed(*_pv,lcdc_dev->regs + offset);
}
static inline void lcdc_clr_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk)
{
u32* _pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
(*_pv) &= (~msk);
writel_relaxed(*_pv,lcdc_dev->regs + offset);
}
static inline void lcdc_msk_reg(struct lcdc_device *lcdc_dev,u32 offset,u32 msk,u32 v)
{
u32 *_pv = (u32*)lcdc_dev->regsbak;
_pv += (offset >> 2);
(*_pv) &= (~msk);
(*_pv) |= v;
writel_relaxed(*_pv,lcdc_dev->regs+offset);
}
static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev)
{
writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE);
dsb();
}
#endif

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drivers/video/rockchip/lcdc/rk322x_lcdc.c
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drivers/video/rockchip/lcdc/rk322x_lcdc.h
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drivers/video/rockchip/lcdc/rk3288_lcdc.c
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drivers/video/rockchip/lcdc/rk3288_lcdc.h
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drivers/video/rockchip/lcdc/rk3368_lcdc.c
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drivers/video/rockchip/lcdc/rk3368_lcdc.h
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drivers/video/rockchip/lcdc/rk_vop_lite.c
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drivers/video/rockchip/lcdc/rk_vop_lite.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef RK_VOPLITE_H_
#define RK_VOPLITE_H_
#include <linux/rk_fb.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#define VOP_INPUT_MAX_WIDTH 2048
/*
* Registers in this file
* REG_CFG_DONE: Register config done flag
* VERSION_INFO: Version for vop
* DSP_BG: Background color
* MCU_RESERVED: Reversed
* SYS_CTRL0: System control register0
* SYS_CTRL1: Axi Bus interface control register
* SYS_CTRL2: System control register for immediate reg
* DSP_CTRL0: Display control register0
* DSP_CTRL2: Display control register2
* VOP_STATUS: Some vop module status
* LINE_FLAG: Line flag config register
* INTR_EN: Interrupt enable register
* INTR_CLEAR: Interrupt clear register
* INTR_STATUS: Interrupt raw status and interrupt status
* WIN0_CTRL0: Win0 ctrl register0
* WIN0_CTRL1: Win0 ctrl register1
* WIN0_COLOR_KEY: Win0 color key register
* WIN0_VIR: Win0 virtual stride
* WIN0_YRGB_MST: Win0 YRGB memory start address
* WIN0_CBR_MST: Win0 Cbr memory start address
* WIN0_ACT_INFO: Win0 active window width/height
* WIN0_DSP_INFO: Win0 display width/height on panel
* WIN0_DSP_ST: Win0 display start point on panel
* WIN0_SCL_FACTOR_YRGB: Win0 YRGB scaling factor
* WIN0_SCL_FACTOR_CBR: Win0 Cbr scaling factor
* WIN0_SCL_OFFSET: Win0 scaling start point offset
* WIN0_ALPHA_CTRL: Win0 Blending control register
* WIN1_CTRL0: Win1 ctrl register0
* WIN1_CTRL1: Win1 ctrl register1
* WIN1_VIR: win1 virtual stride
* WIN1_YRGB_MST: Win1 frame buffer memory start address
* WIN1_DSP_INFO: Win1 display width/height on panel
* WIN1_DSP_ST: Win1 display start point on panel
* WIN1_COLOR_KEY: Win1 color key register
* WIN1_ALPHA_CTRL: Win1 Blending control register
* HWC_CTRL0: Hwc ctrl register0
* HWC_CTRL1: Hwc ctrl register1
* HWC_MST: Hwc memory start address
* HWC_DSP_ST: Hwc display start point on panel
* HWC_ALPHA_CTRL: Hwc blending control register
* DSP_HTOTAL_HS_END: Panel scanning horizontal width and hsync pulse end point
* DSP_HACT_ST_END: Panel active horizontal scanning start point and end point
* DSP_VTOTAL_VS_END: Panel scanning vertical height and vsync pulse end point
* DSP_VACT_ST_END: Panel active vertical scanning start point and end point
* DSP_VS_ST_END_F1: Vertical scanning start point and vsync pulse end point
* of even filed in interlace mode
* DSP_VACT_ST_END_F1: Vertical scanning active start point and end point of
* even filed in interlace mode
* BCSH_CTRL: BCSH contrl register
* BCSH_COLOR_BAR: Color bar config register
* BCSH_BCS: Brightness contrast saturation*contrast config register
* BCSH_H: Sin hue and cos hue config register
* FRC_LOWER01_0: FRC lookup table config register010
* FRC_LOWER01_1: FRC lookup table config register011
* FRC_LOWER10_0: FRC lookup table config register100
* FRC_LOWER10_1: FRC lookup table config register101
* FRC_LOWER11_0: FRC lookup table config register110
* FRC_LOWER11_1: FRC lookup table config register111
* DBG_REG_00: Current line number of dsp timing
* BLANKING_VALUE: The value of vsync blanking
* FLAG_REG_FRM_VALID: Flag reg value after frame valid
* FLAG_REG: Flag reg value before frame valid
* HWC_LUT_ADDR: Hwc lut base address
* GAMMA_LUT_ADDR: GAMMA lut base address
*/
static inline u64 val_mask(int val, u64 msk, int shift)
{
return (msk << (shift + 32)) | ((msk & val) << shift);
}
#define VAL_MASK(x, width, shift) val_mask(x, (1 << width) - 1, shift)
#define MASK(x) (V_##x(0) >> 32)
#define REG_CFG_DONE 0x00000000
#define V_REG_LOAD_GLOBAL_EN(x) VAL_MASK(x, 1, 0)
#define V_REG_LOAD_WIN0_EN(x) VAL_MASK(x, 1, 1)
#define V_REG_LOAD_WIN1_EN(x) VAL_MASK(x, 1, 2)
#define V_REG_LOAD_HWC_EN(x) VAL_MASK(x, 1, 3)
#define V_REG_LOAD_IEP_EN(x) VAL_MASK(x, 1, 4)
#define V_REG_LOAD_SYS_EN(x) VAL_MASK(x, 1, 5)
#define VERSION 0x00000004
#define V_BUILD(x) VAL_MASK(x, 16, 0)
#define V_MINOR(x) VAL_MASK(x, 8, 16)
#define V_MAJOR(x) VAL_MASK(x, 8, 24)
#define DSP_BG 0x00000008
#define V_DSP_BG_BLUE(x) VAL_MASK(x, 8, 0)
#define V_DSP_BG_GREEN(x) VAL_MASK(x, 8, 8)
#define V_DSP_BG_RED(x) VAL_MASK(x, 8, 16)
#define MCU_RESERVED 0x0000000c
#define SYS_CTRL0 0x00000010
#define V_DIRECT_PATH_EN(x) VAL_MASK(x, 1, 0)
#define V_DIRECT_PATH_LAYER_SEL(x) VAL_MASK(x, 1, 1)
#define SYS_CTRL1 0x00000014
#define V_SW_NOC_QOS_EN(x) VAL_MASK(x, 1, 0)
#define V_SW_NOC_QOS_VALUE(x) VAL_MASK(x, 2, 1)
#define V_SW_NOC_HURRY_EN(x) VAL_MASK(x, 1, 4)
#define V_SW_NOC_HURRY_VALUE(x) VAL_MASK(x, 2, 5)
#define V_SW_NOC_HURRY_THRESHOLD(x) VAL_MASK(x, 4, 8)
#define V_SW_AXI_MAX_OUTSTAND_EN(x) VAL_MASK(x, 1, 12)
#define V_SW_AXI_MAX_OUTSTAND_NUM(x) VAL_MASK(x, 5, 16)
#define SYS_CTRL2 0x00000018
#define V_IMD_AUTO_GATING_EN(x) VAL_MASK(x, 1, 0)
#define V_IMD_VOP_STANDBY_EN(x) VAL_MASK(x, 1, 1)
#define V_IMD_VOP_DMA_STOP(x) VAL_MASK(x, 1, 2)
#define V_IMD_DSP_OUT_ZERO(x) VAL_MASK(x, 1, 3)
#define V_IMD_YUV_CLIP(x) VAL_MASK(x, 1, 4)
#define V_IMD_DSP_DATA_OUT_MODE(x) VAL_MASK(x, 1, 6)
#define V_SW_IO_PAD_CLK_SEL(x) VAL_MASK(x, 1, 7)
#define V_IMD_DSP_TIMING_IMD(x) VAL_MASK(x, 1, 12)
#define V_IMD_GLOBAL_REGDONE_EN(x) VAL_MASK(x, 1, 13)
#define V_FS_ADDR_MASK_EN(x) VAL_MASK(x, 1, 14)
#define DSP_CTRL0 0x00000020
#define V_RGB_DCLK_EN(x) VAL_MASK(x, 1, 0)
#define V_RGB_DCLK_POL(x) VAL_MASK(x, 1, 1)
#define V_RGB_HSYNC_POL(x) VAL_MASK(x, 1, 2)
#define V_RGB_VSYNC_POL(x) VAL_MASK(x, 1, 3)
#define V_RGB_DEN_POL(x) VAL_MASK(x, 1, 4)
#define V_HDMI_DCLK_EN(x) VAL_MASK(x, 1, 8)
#define V_HDMI_DCLK_POL(x) VAL_MASK(x, 1, 9)
#define V_HDMI_HSYNC_POL(x) VAL_MASK(x, 1, 10)
#define V_HDMI_VSYNC_POL(x) VAL_MASK(x, 1, 11)
#define V_HDMI_DEN_POL(x) VAL_MASK(x, 1, 12)
#define V_SW_CORE_CLK_SEL(x) VAL_MASK(x, 1, 13)
#define V_SW_HDMI_CLK_I_SEL(x) VAL_MASK(x, 1, 14)
#define V_LVDS_DCLK_EN(x) VAL_MASK(x, 1, 16)
#define V_LVDS_DCLK_POL(x) VAL_MASK(x, 1, 17)
#define V_LVDS_HSYNC_POL(x) VAL_MASK(x, 1, 18)
#define V_LVDS_VSYNC_POL(x) VAL_MASK(x, 1, 19)
#define V_LVDS_DEN_POL(x) VAL_MASK(x, 1, 20)
#define V_MIPI_DCLK_EN(x) VAL_MASK(x, 1, 24)
#define V_MIPI_DCLK_POL(x) VAL_MASK(x, 1, 25)
#define V_MIPI_HSYNC_POL(x) VAL_MASK(x, 1, 26)
#define V_MIPI_VSYNC_POL(x) VAL_MASK(x, 1, 27)
#define V_MIPI_DEN_POL(x) VAL_MASK(x, 1, 28)
#define DSP_CTRL2 0x00000028
#define V_DSP_INTERLACE(x) VAL_MASK(x, 1, 0)
#define V_INTERLACE_FIELD_POL(x) VAL_MASK(x, 1, 1)
#define V_DITHER_UP(x) VAL_MASK(x, 1, 2)
#define V_DSP_WIN0_TOP(x) VAL_MASK(x, 1, 3)
#define V_SW_OVERLAY_MODE(x) VAL_MASK(x, 1, 4)
#define V_DSP_LUT_EN(x) VAL_MASK(x, 1, 5)
#define V_DITHER_DOWN_MODE(x) VAL_MASK(x, 1, 6)
#define V_DITHER_DOWN_SEL(x) VAL_MASK(x, 1, 7)
#define V_DITHER_DOWN(x) VAL_MASK(x, 1, 8)
#define V_DSP_BG_SWAP(x) VAL_MASK(x, 1, 9)
#define V_DSP_DELTA_SWAP(x) VAL_MASK(x, 1, 10)
#define V_DSP_RB_SWAP(x) VAL_MASK(x, 1, 11)
#define V_DSP_RG_SWAP(x) VAL_MASK(x, 1, 12)
#define V_DSP_DUMMY_SWAP(x) VAL_MASK(x, 1, 13)
#define V_DSP_BLANK_EN(x) VAL_MASK(x, 1, 14)
#define V_DSP_BLACK_EN(x) VAL_MASK(x, 1, 15)
#define V_DSP_OUT_MODE(x) VAL_MASK(x, 4, 16)
#define VOP_STATUS 0x0000002c
#define V_DSP_BLANKING_EN_ASYNC_AFF2(x) VAL_MASK(x, 1, 0)
#define V_IDLE_MMU_FF1(x) VAL_MASK(x, 1, 1)
#define V_INT_RAW_DMA_FINISH(x) VAL_MASK(x, 1, 2)
#define V_DMA_STOP_VALID(x) VAL_MASK(x, 1, 4)
#define LINE_FLAG 0x00000030
#define V_DSP_LINE_FLAG0_NUM(x) VAL_MASK(x, 12, 0)
#define V_DSP_LINE_FLAG1_NUM(x) VAL_MASK(x, 12, 16)
#define INTR_EN 0x00000034
#define V_FS0_INTR_EN(x) VAL_MASK(x, 1, 0)
#define V_FS1_INTR_EN(x) VAL_MASK(x, 1, 1)
#define V_ADDR_SAME_INTR_EN(x) VAL_MASK(x, 1, 2)
#define V_LINE_FLAG0_INTR_EN(x) VAL_MASK(x, 1, 3)
#define V_LINE_FLAG1_INTR_EN(x) VAL_MASK(x, 1, 4)
#define V_BUS_ERROR_INTR_EN(x) VAL_MASK(x, 1, 5)
#define V_WIN0_EMPTY_INTR_EN(x) VAL_MASK(x, 1, 6)
#define V_WIN1_EMPTY_INTR_EN(x) VAL_MASK(x, 1, 7)
#define V_DSP_HOLD_VALID_INTR_EN(x) VAL_MASK(x, 1, 8)
#define V_DMA_FRM_FSH_INTR_EN(x) VAL_MASK(x, 1, 9)
#define INTR_CLEAR 0x00000038
#define V_FS0_INTR_CLR(x) VAL_MASK(x, 1, 0)
#define V_FS1_INTR_CLR(x) VAL_MASK(x, 1, 1)
#define V_ADDR_SAME_INTR_CLR(x) VAL_MASK(x, 1, 2)
#define V_LINE_FLAG0_INTR_CLR(x) VAL_MASK(x, 1, 3)
#define V_LINE_FLAG1_INTR_CLR(x) VAL_MASK(x, 1, 4)
#define V_BUS_ERROR_INTR_CLR(x) VAL_MASK(x, 1, 5)
#define V_WIN0_EMPTY_INTR_CLR(x) VAL_MASK(x, 1, 6)
#define V_WIN1_EMPTY_INTR_CLR(x) VAL_MASK(x, 1, 7)
#define V_DSP_HOLD_VALID_INTR_CLR(x) VAL_MASK(x, 1, 8)
#define V_DMA_FRM_FSH_INTR_CLR(x) VAL_MASK(x, 1, 9)
#define INTR_STATUS 0x0000003c
#define V_FS0_INTR_STS(x) VAL_MASK(x, 1, 0)
#define V_FS1_INTR_STS(x) VAL_MASK(x, 1, 1)
#define V_ADDR_SAME_INTR_STS(x) VAL_MASK(x, 1, 2)
#define V_LINE_FLAG0_INTR_STS(x) VAL_MASK(x, 1, 3)
#define V_LINE_FLAG1_INTR_STS(x) VAL_MASK(x, 1, 4)
#define V_BUS_ERROR_INTR_STS(x) VAL_MASK(x, 1, 5)
#define V_WIN0_EMPTY_INTR_STS(x) VAL_MASK(x, 1, 6)
#define V_WIN1_EMPTY_INTR_STS(x) VAL_MASK(x, 1, 7)
#define V_DSP_HOLD_VALID_INTR_STS(x) VAL_MASK(x, 1, 8)
#define V_DMA_FRM_FSH_INTR_STS(x) VAL_MASK(x, 1, 9)
#define V_MMU_INTR_STATUS(x) VAL_MASK(x, 1, 15)
#define V_FS0_INTR_RAW_STS(x) VAL_MASK(x, 1, 16)
#define V_FS1_INTR_RAW_STS(x) VAL_MASK(x, 1, 17)
#define V_ADDR_SAME_INTR_RAW_STS(x) VAL_MASK(x, 1, 18)
#define V_LINE_FLAG0_INTR_RAW_STS(x) VAL_MASK(x, 1, 19)
#define V_LINE_FLAG1_INTR_RAW_STS(x) VAL_MASK(x, 1, 20)
#define V_BUS_ERROR_INTR_RAW_STS(x) VAL_MASK(x, 1, 21)
#define V_WIN0_EMPTY_INTR_RAW_STS(x) VAL_MASK(x, 1, 22)
#define V_WIN1_EMPTY_INTR_RAW_STS(x) VAL_MASK(x, 1, 23)
#define V_DSP_HOLD_VALID_INTR_RAW_STS(x) VAL_MASK(x, 1, 24)
#define V_DMA_FRM_FSH_INTR_RAW_STS(x) VAL_MASK(x, 1, 25)
#define WIN0_CTRL0 0x00000050
#define V_WIN0_EN(x) VAL_MASK(x, 1, 0)
#define V_WIN0_DATA_FMT(x) VAL_MASK(x, 3, 1)
#define V_WIN0_INTERLACE_READ(x) VAL_MASK(x, 1, 8)
#define V_WIN0_NO_OUTSTANDING(x) VAL_MASK(x, 1, 9)
#define V_WIN0_CSC_MODE(x) VAL_MASK(x, 2, 10)
#define V_WIN0_RB_SWAP(x) VAL_MASK(x, 1, 12)
#define V_WIN0_ALPHA_SWAP(x) VAL_MASK(x, 1, 13)
#define V_WIN0_MID_SWAP(x) VAL_MASK(x, 1, 14)
#define V_WIN0_UV_SWAP(x) VAL_MASK(x, 1, 15)
#define V_WIN0_YRGB_DEFLICK(x) VAL_MASK(x, 1, 18)
#define V_WIN0_CBR_DEFLICK(x) VAL_MASK(x, 1, 19)
#define WIN0_CTRL1 0x00000054
#define V_WIN0_YRGB_AXI_GATHER_EN(x) VAL_MASK(x, 1, 0)
#define V_WIN0_CBR_AXI_GATHER_EN(x) VAL_MASK(x, 1, 1)
#define V_WIN0_DMA_BURST_LENGTH(x) VAL_MASK(x, 2, 2)
#define V_WIN0_YRGB_AXI_GATHER_NUM(x) VAL_MASK(x, 4, 4)
#define V_WIN0_CBR_AXI_GATHER_NUM(x) VAL_MASK(x, 3, 8)
#define V_SW_WIN0_YRGB0_RID(x) VAL_MASK(x, 4, 12)
#define V_SW_WIN0_CBR0_RID(x) VAL_MASK(x, 4, 16)
#define WIN0_COLOR_KEY 0x00000058
#define V_WIN0_KEY_COLOR(x) VAL_MASK(x, 24, 0)
#define V_WIN0_KEY_EN(x) VAL_MASK(x, 1, 24)
#define WIN0_VIR 0x0000005c
#define V_WIN0_YRGB_VIR_STRIDE(x) VAL_MASK(x, 13, 0)
#define V_WIN0_CBR_VIR_STRIDE(x) VAL_MASK(x, 13, 16)
#define WIN0_YRGB_MST 0x00000060
#define WIN0_CBR_MST 0x00000064
#define WIN0_ACT_INFO 0x00000068
#define V_WIN0_ACT_WIDTH(x) VAL_MASK(x, 13, 0)
#define V_WIN0_ACT_HEIGHT(x) VAL_MASK(x, 13, 16)
#define WIN0_DSP_INFO 0x0000006c
#define V_WIN0_DSP_WIDTH(x) VAL_MASK(x, 11, 0)
#define V_WIN0_DSP_HEIGHT(x) VAL_MASK(x, 11, 16)
#define WIN0_DSP_ST 0x00000070
#define V_WIN0_DSP_XST(x) VAL_MASK(x, 12, 0)
#define V_WIN0_DSP_YST(x) VAL_MASK(x, 12, 16)
#define WIN0_SCL_FACTOR_YRGB 0x00000074
#define V_WIN0_HS_FACTOR_YRGB(x) VAL_MASK(x, 16, 0)
#define V_WIN0_VS_FACTOR_YRGB(x) VAL_MASK(x, 16, 16)
#define WIN0_SCL_FACTOR_CBR 0x00000078
#define V_WIN0_HS_FACTOR_CBR(x) VAL_MASK(x, 16, 0)
#define V_WIN0_VS_FACTOR_CBR(x) VAL_MASK(x, 16, 16)
#define WIN0_SCL_OFFSET 0x0000007c
#define V_WIN0_HS_OFFSET_YRGB(x) VAL_MASK(x, 8, 0)
#define V_WIN0_HS_OFFSET_CBR(x) VAL_MASK(x, 8, 8)
#define V_WIN0_VS_OFFSET_YRGB(x) VAL_MASK(x, 8, 16)
#define V_WIN0_VS_OFFSET_CBR(x) VAL_MASK(x, 8, 24)
#define WIN0_ALPHA_CTRL 0x00000080
#define V_WIN0_ALPHA_EN(x) VAL_MASK(x, 1, 0)
#define V_WIN0_ALPHA_MODE(x) VAL_MASK(x, 1, 1)
#define V_WIN0_ALPHA_PRE_MUL(x) VAL_MASK(x, 1, 2)
#define V_WIN0_ALPHA_SAT_MODE(x) VAL_MASK(x, 1, 3)
#define V_WIN0_ALPHA_VALUE(x) VAL_MASK(x, 8, 4)
#define WIN1_CTRL0 0x00000090
#define V_WIN1_EN(x) VAL_MASK(x, 1, 0)
#define V_WIN1_CSC_MODE(x) VAL_MASK(x, 1, 2)
#define V_WIN1_DATA_FMT(x) VAL_MASK(x, 3, 4)
#define V_WIN1_INTERLACE_READ(x) VAL_MASK(x, 1, 8)
#define V_WIN1_NO_OUTSTANDING(x) VAL_MASK(x, 1, 9)
#define V_WIN1_RB_SWAP(x) VAL_MASK(x, 1, 12)
#define V_WIN1_ALPHA_SWAP(x) VAL_MASK(x, 1, 13)
#define V_WIN1_ENDIAN_SWAP(x) VAL_MASK(x, 1, 14)
#define WIN1_CTRL1 0x00000094
#define V_WIN1_AXI_GATHER_EN(x) VAL_MASK(x, 1, 0)
#define V_WIN1_DMA_BURST_LENGTH(x) VAL_MASK(x, 2, 2)
#define V_WIN1_AXI_GATHER_NUM(x) VAL_MASK(x, 4, 4)
#define V_SW_WIN1_RID(x) VAL_MASK(x, 4, 8)
#define WIN1_VIR 0x00000098
#define V_WIN1_VIR_STRIDE(x) VAL_MASK(x, 13, 0)
#define WIN1_YRGB_MST 0x000000a0
#define WIN1_DSP_INFO 0x000000a4
#define V_WIN1_DSP_WIDTH(x) VAL_MASK(x, 11, 0)
#define V_WIN1_DSP_HEIGHT(x) VAL_MASK(x, 11, 16)
#define WIN1_DSP_ST 0x000000a8
#define V_WIN1_DSP_XST(x) VAL_MASK(x, 12, 0)
#define V_WIN1_DSP_YST(x) VAL_MASK(x, 12, 16)
#define WIN1_COLOR_KEY 0x000000ac
#define V_WIN1_KEY_COLOR(x) VAL_MASK(x, 24, 0)
#define V_WIN1_KEY_EN(x) VAL_MASK(x, 1, 24)
#define WIN1_ALPHA_CTRL 0x000000bc
#define V_WIN1_ALPHA_EN(x) VAL_MASK(x, 1, 0)
#define V_WIN1_ALPHA_MODE(x) VAL_MASK(x, 1, 1)
#define V_WIN1_ALPHA_PRE_MUL(x) VAL_MASK(x, 1, 2)
#define V_WIN1_ALPHA_SAT_MODE(x) VAL_MASK(x, 1, 3)
#define V_WIN1_ALPHA_VALUE(x) VAL_MASK(x, 8, 4)
#define HWC_CTRL0 0x000000e0
#define V_HWC_EN(x) VAL_MASK(x, 1, 0)
#define V_HWC_SIZE(x) VAL_MASK(x, 1, 1)
#define V_HWC_LOAD_EN(x) VAL_MASK(x, 1, 2)
#define V_HWC_LUT_EN(x) VAL_MASK(x, 1, 3)
#define V_SW_HWC_RID(x) VAL_MASK(x, 4, 4)
#define HWC_CTRL1 0x000000e4
#define HWC_MST 0x000000e8
#define HWC_DSP_ST 0x000000ec
#define V_HWC_DSP_XST(x) VAL_MASK(x, 12, 0)
#define V_HWC_DSP_YST(x) VAL_MASK(x, 12, 16)
#define HWC_ALPHA_CTRL 0x000000f0
#define V_HWC_ALPHA_EN(x) VAL_MASK(x, 1, 0)
#define V_HWC_ALPHA_MODE(x) VAL_MASK(x, 1, 1)
#define V_HWC_ALPHA_PRE_MUL(x) VAL_MASK(x, 1, 2)
#define V_HWC_ALPHA_SAT_MODE(x) VAL_MASK(x, 1, 3)
#define V_HWC_ALPHA_VALUE(x) VAL_MASK(x, 8, 4)
#define DSP_HTOTAL_HS_END 0x00000100
#define V_DSP_HS_END(x) VAL_MASK(x, 12, 0)
#define V_DSP_HTOTAL(x) VAL_MASK(x, 12, 16)
#define DSP_HACT_ST_END 0x00000104
#define V_DSP_HACT_END(x) VAL_MASK(x, 12, 0)
#define V_DSP_HACT_ST(x) VAL_MASK(x, 12, 16)
#define DSP_VTOTAL_VS_END 0x00000108
#define V_DSP_VS_END(x) VAL_MASK(x, 12, 0)
#define V_DSP_VTOTAL(x) VAL_MASK(x, 12, 16)
#define DSP_VACT_ST_END 0x0000010c
#define V_DSP_VACT_END(x) VAL_MASK(x, 12, 0)
#define V_DSP_VACT_ST(x) VAL_MASK(x, 12, 16)
#define DSP_VS_ST_END_F1 0x00000110
#define V_DSP_VS_END_F1(x) VAL_MASK(x, 12, 0)
#define V_DSP_VS_ST_F1(x) VAL_MASK(x, 12, 16)
#define DSP_VACT_ST_END_F1 0x00000114
#define V_DSP_VACT_END_F1(x) VAL_MASK(x, 12, 0)
#define V_DSP_VACT_ST_F1(x) VAL_MASK(x, 12, 16)
#define BCSH_CTRL 0x00000160
#define V_BCSH_EN(x) VAL_MASK(x, 1, 0)
#define V_SW_BCSH_R2Y_CSC_MODE(x) VAL_MASK(x, 1, 1)
#define V_VIDEO_MODE(x) VAL_MASK(x, 2, 2)
#define V_SW_BCSH_Y2R_CSC_MODE(x) VAL_MASK(x, 2, 4)
#define V_SW_BCSH_Y2R_EN(x) VAL_MASK(x, 1, 6)
#define V_SW_BCSH_R2Y_EN(x) VAL_MASK(x, 1, 7)
#define BCSH_COL_BAR 0x00000164
#define V_COLOR_BAR_Y(x) VAL_MASK(x, 8, 0)
#define V_COLOR_BAR_U(x) VAL_MASK(x, 8, 8)
#define V_COLOR_BAR_V(x) VAL_MASK(x, 8, 16)
#define BCSH_BCS 0x00000168
#define V_BRIGHTNESS(x) VAL_MASK(x, 6, 0)
#define V_CONTRAST(x) VAL_MASK(x, 8, 8)
#define V_SAT_CON(x) VAL_MASK(x, 9, 16)
#define BCSH_H 0x0000016c
#define V_SIN_HUE(x) VAL_MASK(x, 8, 0)
#define V_COS_HUE(x) VAL_MASK(x, 8, 8)
#define FRC_LOWER01_0 0x00000170
#define V_LOWER01_FRM0(x) VAL_MASK(x, 16, 0)
#define V_LOWER01_FRM1(x) VAL_MASK(x, 16, 16)
#define FRC_LOWER01_1 0x00000174
#define V_LOWER01_FRM2(x) VAL_MASK(x, 16, 0)
#define V_LOWER01_FRM3(x) VAL_MASK(x, 16, 16)
#define FRC_LOWER10_0 0x00000178
#define V_LOWER10_FRM0(x) VAL_MASK(x, 16, 0)
#define V_LOWER10_FRM1(x) VAL_MASK(x, 16, 16)
#define FRC_LOWER10_1 0x0000017c
#define V_LOWER10_FRM2(x) VAL_MASK(x, 16, 0)
#define V_LOWER10_FRM3(x) VAL_MASK(x, 16, 16)
#define FRC_LOWER11_0 0x00000180
#define V_LOWER11_FRM0(x) VAL_MASK(x, 16, 0)
#define V_LOWER11_FRM1(x) VAL_MASK(x, 16, 16)
#define FRC_LOWER11_1 0x00000184
#define V_LOWER11_FRM2(x) VAL_MASK(x, 16, 0)
#define V_LOWER11_FRM3(x) VAL_MASK(x, 16, 16)
#define DBG_REG_000 0x00000190
#define BLANKING_VALUE 0x000001f4
#define V_SW_BLANKING_VALUE(x) VAL_MASK(x, 24, 0)
#define V_BLANKING_VALUE_CONFIG_EN(x) VAL_MASK(x, 1, 24)
#define FLAG_REG_FRM_VALID 0x000001f8
#define FLAG_REG 0x000001fc
#define HWC_LUT_ADDR 0x00000600
#define GAMMA_LUT_ADDR 0x00000a00
#define MMU_DTE_ADDR 0x00000f00
#define MMU_STATUS 0x00000f04
#define V_PAGING_ENABLED(x) VAL_MASK(x, 1, 0)
#define V_PAGE_FAULT_ACTIVE(x) VAL_MASK(x, 1, 1)
#define V_STAIL_ACTIVE(x) VAL_MASK(x, 1, 2)
#define V_MMU_IDLE(x) VAL_MASK(x, 1, 3)
#define V_REPLAY_BUFFER_EMPTY(x) VAL_MASK(x, 1, 4)
#define V_PAGE_FAULT_IS_WRITE(x) VAL_MASK(x, 1, 5)
#define MMU_COMMAND 0x00000f08
#define MMU_PAGE_FAULT_ADDR 0x00000f0c
#define MMU_ZAP_ONE_LINE 0x00000f10
#define MMU_INT_RAWSTAT 0x00000f14
#define V_PAGE_FAULT(x) VAL_MASK(x, 1, 0)
#define MMU_INT_CLEAR 0x00000f18
#define V_PAGE_FAULT(x) VAL_MASK(x, 1, 0)
#define MMU_INT_MASK 0x00000f1c
#define V_PAGE_FAULT(x) VAL_MASK(x, 1, 0)
#define MMU_INT_STATUS 0x00000f20
#define V_PAGE_FAULT(x) VAL_MASK(x, 1, 0)
#define MMU_AUTO_GATING 0x00000f24
#define V_MMU_AUTO_GATING(x) VAL_MASK(x, 1, 0)
#define MMU_CFG_DONE 0x00000f28
#define INTR_FS0 BIT(0)
#define INTR_FS1 BIT(1)
#define INTR_ADDR_SAME BIT(2)
#define INTR_LINE_FLAG0 BIT(3)
#define INTR_LINE_FLAG1 BIT(4)
#define INTR_BUS_ERROR BIT(5)
#define INTR_WIN0_EMPTY BIT(6)
#define INTR_WIN1_EMPTY BIT(7)
#define INTR_DSP_HOLD_VALID BIT(8)
#define INTR_DMA_FINISH BIT(9)
#define INTR_MMU_STATUS BIT(15)
#define INTR_MASK (INTR_FS0 | INTR_FS1 | INTR_ADDR_SAME | INTR_LINE_FLAG0 | \
INTR_LINE_FLAG1 | INTR_BUS_ERROR | INTR_WIN0_EMPTY | \
INTR_WIN1_EMPTY | INTR_DSP_HOLD_VALID | INTR_DMA_FINISH)
/* GRF register for VOP source select */
#define GRF_WEN_SHIFT(x) (BIT(x) << 16)
#define GRF_SOC_CON0 0x0400
#define V_LVDS_VOP_SEL(x) (((x) << 0) | GRF_WEN_SHIFT(0))
#define V_HDMI_VOP_SEL(x) (((x) << 1) | GRF_WEN_SHIFT(1))
#define V_DSI0_VOP_SEL(x) (((x) << 2) | GRF_WEN_SHIFT(2))
#define GRF_SOC_CON5 0x0414
#define V_RGB_VOP_SEL(x) (((x) << 4) | GRF_WEN_SHIFT(4))
#define GRF_IO_VSEL 0x0900
#define V_VOP_IOVOL_SEL(x) (((x) << 0) | GRF_WEN_SHIFT(0))
struct vop_sync_obj_s {
struct completion stdbyfin; /* standby finish */
int stdbyfin_to;
struct completion frmst; /* frame start */
int frmst_to;
};
struct vop_device {
int id;
struct rk_lcdc_driver driver;
struct device *dev;
struct rk_screen *screen;
void __iomem *regs;
void *regsbak;
u32 reg_phy_base;
u32 len;
void __iomem *hwc_lut_addr_base;
void __iomem *dsp_lut_addr_base;
struct regmap *grf_base;
/* one time only one process allowed to config the register */
spinlock_t reg_lock;
int prop; /* used for primary or extended display device */
bool pre_init;
bool pwr18; /* if lcdc use 1.8v power supply */
/* if aclk or hclk is closed, access to register is not allowed */
bool clk_on;
/* active layer counter,when atv_layer_cnt = 0,disable lcdc */
u8 atv_layer_cnt;
unsigned int irq;
struct clk *hclk; /* lcdc AHP clk */
struct clk *dclk; /* lcdc dclk */
struct clk *aclk; /* lcdc share memory frequency */
u32 pixclock;
u32 standby; /* 1:standby,0:wrok */
u32 iommu_status;
struct backlight_device *backlight;
/* lock vop irq reg */
spinlock_t irq_lock;
struct vop_sync_obj_s sync;
};
static inline int vop_completion_timeout_ms(struct completion *comp, int to)
{
long jiffies = msecs_to_jiffies(to);
return wait_for_completion_timeout(comp, jiffies);
}
static inline void vop_writel(struct vop_device *vop_dev, u32 offset, u32 v)
{
u32 *_pv = (u32 *)vop_dev->regsbak;
_pv += (offset >> 2);
*_pv = v;
writel_relaxed(v, vop_dev->regs + offset);
}
static inline u32 vop_readl(struct vop_device *vop_dev, u32 offset)
{
u32 v;
v = readl_relaxed(vop_dev->regs + offset);
return v;
}
static inline u32 vop_readl_backup(struct vop_device *vop_dev, u32 offset)
{
u32 v;
u32 *_pv = (u32 *)vop_dev->regsbak;
_pv += (offset >> 2);
v = readl_relaxed(vop_dev->regs + offset);
*_pv = v;
return v;
}
static inline u32 vop_read_bit(struct vop_device *vop_dev, u32 offset, u64 v)
{
u32 _v = readl_relaxed(vop_dev->regs + offset);
_v &= v >> 32;
v = (_v ? 1 : 0);
return v;
}
static inline void vop_set_bit(struct vop_device *vop_dev, u32 offset, u64 v)
{
u32 *_pv = (u32 *)vop_dev->regsbak;
_pv += (offset >> 2);
(*_pv) |= v >> 32;
writel_relaxed(*_pv, vop_dev->regs + offset);
}
static inline void vop_clr_bit(struct vop_device *vop_dev, u32 offset, u64 v)
{
u32 *_pv = (u32 *)vop_dev->regsbak;
_pv += (offset >> 2);
(*_pv) &= (~(v >> 32));
writel_relaxed(*_pv, vop_dev->regs + offset);
}
static inline void vop_msk_reg(struct vop_device *vop_dev, u32 offset, u64 v)
{
u32 *_pv = (u32 *)vop_dev->regsbak;
_pv += (offset >> 2);
(*_pv) &= (~(v >> 32));
(*_pv) |= (u32)v;
writel_relaxed(*_pv, vop_dev->regs + offset);
}
static inline void vop_mask_writel(struct vop_device *vop_dev, u32 offset,
u32 mask, u32 v)
{
v = mask << 16 | v;
writel_relaxed(v, vop_dev->regs + offset);
}
static inline void vop_cfg_done(struct vop_device *vop_dev)
{
writel_relaxed(0x001f001f, vop_dev->regs + REG_CFG_DONE);
dsb(sy);
}
static inline int vop_grf_writel(struct regmap *base, u32 offset, u32 val)
{
if (base)
regmap_write(base, offset, val);
dsb(sy);
return 0;
}
static inline int vop_cru_writel(struct regmap *base, u32 offset, u32 val)
{
if (base)
regmap_write(base, offset, val);
dsb(sy);
return 0;
}
static inline int vop_cru_readl(struct regmap *base, u32 offset)
{
u32 v;
if (base)
regmap_read(base, offset, &v);
return v;
}
enum dither_down_mode {
DITHER_888_565 = 0x0,
DITHER_888_666 = 0x1,
};
enum dither_down_sel {
DITHER_SEL_ALLEGRO = 0x0,
DITHER_SEL_FRC = 0x1,
};
enum _vop_r2y_csc_mode {
VOP_R2Y_CSC_BT601 = 0,
VOP_R2Y_CSC_BT709
};
enum _vop_y2r_csc_mode {
VOP_Y2R_CSC_MPEG = 0,
VOP_Y2R_CSC_HD,
VOP_Y2R_CSC_JPEG,
VOP_Y2R_CSC_BYPASS
};
enum _vop_format {
VOP_FORMAT_ARGB888 = 0,
VOP_FORMAT_RGB888,
VOP_FORMAT_RGB565,
VOP_FORMAT_YCBCR420 = 4,
VOP_FORMAT_YCBCR422,
VOP_FORMAT_YCBCR444
};
enum _bcsh_video_mode {
BCSH_MODE_BLACK = 0,
BCSH_MODE_BLUE,
BCSH_MODE_COLORBAR,
BCSH_MODE_VIDEO,
};
#define IS_YUV(x) ((x) >= VOP_FORMAT_YCBCR420)
enum _vop_overlay_mode {
VOP_RGB_DOMAIN,
VOP_YUV_DOMAIN
};
/*************************************************************/
#define CALSCALE(x, y) \
(1 == (y) ? 0x1000 : ((((u32)((x) - 1)) * 0x1000) / ((y) - 1)))
#endif

4723
drivers/video/rockchip/rk_fb.c
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File diff suppressed because it is too large Load Diff

1352
drivers/video/rockchip/rkfb_sysfs.c
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File diff suppressed because it is too large Load Diff

4
drivers/video/rockchip/screen/.gitignore vendored
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@ -1,4 +0,0 @@
#
# Generated files
#
*lcd.h

14
drivers/video/rockchip/screen/Kconfig
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@ -1,14 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
choice
depends on FB_ROCKCHIP || DRM_ROCKCHIP
prompt "LCD Panel Select"
config LCD_GENERAL
bool "General lcd panel"
help
select if the panel do not need initialization
config LCD_MIPI
bool "rk mipi dsi lcd"
endchoice

21
drivers/video/rockchip/screen/Makefile
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@ -1,21 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_LCD_GENERAL) += lcd_general.o
obj-$(CONFIG_LCD_MIPI) += lcd_mipi.o
quiet_cmd_gen = GEN $@
cmd_gen = cmp -s $< $@ || cp $< $@
lcd-obj := $(filter lcd_%.o,$(obj-y))
lcd-cfile := $(patsubst %.o,%.c,$(lcd-obj))
lcd-cpath := $(src)/$(lcd-cfile)
obj-y := $(filter-out $(lcd-obj),$(obj-y))
$(obj)/lcd.h: $(lcd-cpath) FORCE
$(call if_changed,gen)
$(obj)/rk_screen.o: $(obj)/lcd.h
obj-y += rk_screen.o
clean-files := lcd.h

9
drivers/video/rockchip/screen/lcd_general.c
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@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LCD_NULL__
#define __LCD_NULL__
#endif

747
drivers/video/rockchip/screen/lcd_mipi.c
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@ -1,747 +0,0 @@
/*
* Copyright (C) 2014 ROCKCHIP, Inc.
* drivers/video/rockchip/screen/lcd_mipi.c
* author: libing@rock-chips.com
* create date: 2014-04-10
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef CONFIG_LCD_MIPI
#include <common.h>
#endif
#ifdef CONFIG_LCD_MIPI
#include "../transmitter/mipi_dsi.h"
#include <linux/delay.h>
#endif
#ifdef CONFIG_RK_3288_DSI_UBOOT
#include <common.h>
#include <asm/io.h>
#include <errno.h>
#include <malloc.h>
#include <fdtdec.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/rkplat.h>
#include <lcd.h>
#include "../transmitter/mipi_dsi.h"
#endif
#ifdef CONFIG_RK_3288_DSI_UBOOT
#define MIPI_SCREEN_DBG(x...) /* printf(x) */
#elif defined CONFIG_LCD_MIPI
#define MIPI_SCREEN_DBG(x...) /* printk(KERN_ERR x) */
#else
#define MIPI_SCREEN_DBG(x...)
#endif
#ifdef CONFIG_RK_3288_DSI_UBOOT
DECLARE_GLOBAL_DATA_PTR;
#define printk(x...) /* printf(x) */
#endif
static struct mipi_screen *gmipi_screen;
static inline void mipidelay(unsigned int msecs)
{
usleep_range(msecs * 1000, msecs * 1000 + 200);
}
static void rk_mipi_screen_pwr_disable(struct mipi_screen *screen)
{
if (screen->lcd_en_gpio != INVALID_GPIO) {
gpio_direction_output(screen->lcd_en_gpio, !screen->lcd_en_atv_val);
mipidelay(screen->lcd_en_delay);
} else{
MIPI_SCREEN_DBG("lcd_en_gpio is null");
}
if (screen->lcd_rst_gpio != INVALID_GPIO) {
gpio_direction_output(screen->lcd_rst_gpio, !screen->lcd_rst_atv_val);
mipidelay(screen->lcd_rst_delay);
} else {
MIPI_SCREEN_DBG("lcd_rst_gpio is null");
}
}
static void rk_mipi_screen_pwr_enable(struct mipi_screen *screen)
{
if (screen->lcd_en_gpio != INVALID_GPIO) {
gpio_direction_output(screen->lcd_en_gpio, !screen->lcd_en_atv_val);
mipidelay(screen->lcd_en_delay);
gpio_direction_output(screen->lcd_en_gpio, screen->lcd_en_atv_val);
mipidelay(screen->lcd_en_delay);
} else
MIPI_SCREEN_DBG("lcd_en_gpio is null\n");
if (screen->lcd_rst_gpio != INVALID_GPIO) {
gpio_direction_output(screen->lcd_rst_gpio, !screen->lcd_rst_atv_val);
mipidelay(screen->lcd_rst_delay);
gpio_direction_output(screen->lcd_rst_gpio, screen->lcd_rst_atv_val);
mipidelay(screen->lcd_rst_delay);
} else
MIPI_SCREEN_DBG("lcd_rst_gpio is null\n");
}
static void rk_mipi_screen_cmd_init(struct mipi_screen *screen)
{
u8 len, i;
u8 *cmds;
struct list_head *screen_pos;
struct mipi_dcs_cmd_ctr_list *dcs_cmd;
#ifdef CONFIG_RK_3288_DSI_UBOOT
cmds = calloc(1, 0x400);
if (!cmds) {
printf("request cmds fail!\n");
return;
}
#endif
#ifdef CONFIG_LCD_MIPI
cmds = kmalloc(0x400, GFP_KERNEL);
if (!cmds) {
printk("request cmds fail!\n");
return ;
}
#endif
list_for_each(screen_pos, &screen->cmdlist_head) {
dcs_cmd = list_entry(screen_pos, struct mipi_dcs_cmd_ctr_list, list);
len = dcs_cmd->dcs_cmd.cmd_len + 1;
for (i = 1; i < len ; i++) {
cmds[i] = dcs_cmd->dcs_cmd.cmds[i-1];
}
MIPI_SCREEN_DBG("dcs_cmd.name:%s\n", dcs_cmd->dcs_cmd.name);
if (dcs_cmd->dcs_cmd.type == LPDT) {
cmds[0] = LPDT;
if (dcs_cmd->dcs_cmd.dsi_id == 0) {
MIPI_SCREEN_DBG("dcs_cmd.dsi_id == 0 line=%d\n", __LINE__);
dsi_send_packet(0, cmds, len);
} else if (dcs_cmd->dcs_cmd.dsi_id == 1) {
MIPI_SCREEN_DBG("dcs_cmd.dsi_id == 1 line=%d\n", __LINE__);
dsi_send_packet(1, cmds, len);
} else if (dcs_cmd->dcs_cmd.dsi_id == 2) {
MIPI_SCREEN_DBG("dcs_cmd.dsi_id == 2 line=%d\n", __LINE__);
dsi_send_packet(0, cmds, len);
dsi_send_packet(1, cmds, len);
} else {
MIPI_SCREEN_DBG("dsi is err.\n");
}
if (dcs_cmd->dcs_cmd.delay)
mipidelay(dcs_cmd->dcs_cmd.delay);
} else if (dcs_cmd->dcs_cmd.type == HSDT) {
cmds[0] = HSDT;
if (dcs_cmd->dcs_cmd.dsi_id == 0) {
MIPI_SCREEN_DBG("dcs_cmd.dsi_id == 0 line=%d\n", __LINE__);
dsi_send_packet(0, cmds, len);
} else if (dcs_cmd->dcs_cmd.dsi_id == 1) {
MIPI_SCREEN_DBG("dcs_cmd.dsi_id == 1 line=%d\n", __LINE__);
dsi_send_packet(1, cmds, len);
} else if (dcs_cmd->dcs_cmd.dsi_id == 2) {
MIPI_SCREEN_DBG("dcs_cmd.dsi_id == 2 line=%d\n", __LINE__);
dsi_send_packet(0, cmds, len);
dsi_send_packet(1, cmds, len);
} else {
MIPI_SCREEN_DBG("dsi is err.");
}
if (dcs_cmd->dcs_cmd.delay)
mipidelay(dcs_cmd->dcs_cmd.delay);
} else
MIPI_SCREEN_DBG("cmd type err.\n");
}
#ifdef CONFIG_RK_3288_DSI_UBOOT
free(cmds);
#endif
#ifdef CONFIG_LCD_MIPI
kfree(cmds);
#endif
}
int rk_mipi_screen(void)
{
u8 dcs[16] = {0}, rk_dsi_num;
rk_dsi_num = gmipi_screen->mipi_dsi_num;
if (gmipi_screen->screen_init == 0) {
rk_mipi_screen_pwr_enable(gmipi_screen);
dsi_enable_hs_clk(0, 1);
if (rk_dsi_num == 2) {
dsi_enable_hs_clk(1, 1);
}
dsi_enable_command_mode(0, 1);
if (rk_dsi_num == 2) {
dsi_enable_command_mode(1, 1);
}
dcs[0] = LPDT;
dcs[1] = DTYPE_DCS_SWRITE_0P;
dcs[2] = dcs_exit_sleep_mode;
dsi_send_packet(0, dcs, 3);
if (rk_dsi_num == 2)
dsi_send_packet(1, dcs, 3);
mipidelay(20);
dcs[0] = LPDT;
dcs[1] = DTYPE_DCS_SWRITE_0P;
dcs[2] = dcs_set_display_on;
dsi_send_packet(0, dcs, 3);
if (rk_dsi_num == 2)
dsi_send_packet(1, dcs, 3);
mipidelay(20);
} else {
rk_mipi_screen_pwr_enable(gmipi_screen);
dsi_enable_hs_clk(0, 1);
if (rk_dsi_num == 2) {
dsi_enable_hs_clk(1, 1);
}
dsi_enable_command_mode(0, 1);
if (rk_dsi_num == 2) {
dsi_enable_command_mode(1, 1);
}
rk_mipi_screen_cmd_init(gmipi_screen);
}
MIPI_SCREEN_DBG("++++++++++++++++%s:%d\n", __func__, __LINE__);
return 0;
}
int rk_mipi_screen_standby(u8 enable)
{
u8 dcs[16] = {0}, rk_dsi_num;
rk_dsi_num = gmipi_screen->mipi_dsi_num;
if (dsi_is_active(0) != 1)
return -1;
if (rk_dsi_num == 2)
if ((dsi_is_active(0) != 1) || (dsi_is_active(1) != 1))
return -1;
if (enable) {
/* below is changeable */
dcs[0] = LPDT;
dcs[1] = DTYPE_DCS_SWRITE_0P;
dcs[2] = dcs_set_display_off;
dsi_send_packet(0, dcs, 3);
if (rk_dsi_num == 2)
dsi_send_packet(1, dcs, 3);
mipidelay(30);
dcs[0] = LPDT;
dcs[1] = DTYPE_DCS_SWRITE_0P;
dcs[2] = dcs_enter_sleep_mode;
dsi_send_packet(0, dcs, 3);
if (rk_dsi_num == 2)
dsi_send_packet(1, dcs, 3);
mipidelay(100);
rk_mipi_screen_pwr_disable(gmipi_screen);
MIPI_SCREEN_DBG("++++enable++++++++++++%s:%d\n", __func__, __LINE__);
} else {
rk_mipi_screen();
}
return 0;
}
#ifdef CONFIG_LCD_MIPI
static int rk_mipi_screen_init_dt(struct device *dev,
struct mipi_screen *screen)
{
struct device_node *childnode, *grandchildnode, *root;
struct mipi_dcs_cmd_ctr_list *dcs_cmd;
struct list_head *pos;
struct property *prop;
enum of_gpio_flags flags;
u32 value, i, debug, gpio, ret, length;
memset(screen, 0, sizeof(*screen));
INIT_LIST_HEAD(&screen->cmdlist_head);
childnode = of_find_node_by_name(NULL, "mipi_dsi_init");
if (!childnode) {
MIPI_SCREEN_DBG("%s: Can not get child => mipi_init.\n", __func__);
} else {
ret = of_property_read_u32(childnode, "rockchip,screen_init", &value);
if (ret) {
MIPI_SCREEN_DBG("%s: Can not read property: screen_init.\n", __func__);
} else {
if ((value != 0) && (value != 1)) {
printk("err: rockchip,mipi_dsi_init not match.\n");
return -1;
} else
screen->screen_init = value ;
MIPI_SCREEN_DBG("%s: lcd->screen_init = %d.\n", __func__, screen->screen_init);
}
ret = of_property_read_u32(childnode, "rockchip,dsi_lane", &value);
if (ret) {
MIPI_SCREEN_DBG("%s: Can not read property: dsi_lane.\n", __func__);
} else {
screen->dsi_lane = value;
MIPI_SCREEN_DBG("%s: mipi_lcd->dsi_lane = %d.\n", __func__, screen->dsi_lane);
}
ret = of_property_read_u32(childnode, "rockchip,dsi_hs_clk", &value);
if (ret) {
MIPI_SCREEN_DBG("%s: Can not read property: dsi_hs_clk.\n", __func__);
} else {
if ((value <= 90) || (value >= 1500)) {
printk("err: rockchip,hs_tx_clk not match.");
return -1;
} else {
screen->hs_tx_clk = value*MHz;
}
MIPI_SCREEN_DBG("%s: lcd->screen->hs_tx_clk = %d.\n", __func__, screen->hs_tx_clk);
}
ret = of_property_read_u32(childnode, "rockchip,mipi_dsi_num", &value);
if (ret) {
MIPI_SCREEN_DBG("%s: Can not read property: mipi_dsi_num.\n", __func__);
} else {
if ((value != 1) && (value != 2)) {
printk("err: rockchip,mipi_dsi_num not match.\n");
return -1;
} else {
screen->mipi_dsi_num = value ;
}
MIPI_SCREEN_DBG("%s: lcd->screen.mipi_dsi_num = %d.\n", __func__, screen->mipi_dsi_num);
}
}
childnode = of_find_node_by_name(NULL, "mipi_power_ctr");
if (!childnode) {
screen->lcd_rst_gpio = INVALID_GPIO;
screen->lcd_en_gpio = INVALID_GPIO;
MIPI_SCREEN_DBG("%s: Can not get child => mipi_power_ctr.\n", __func__);
} else {
grandchildnode = of_find_node_by_name(childnode, "mipi_lcd_rst");
if (!grandchildnode) {
screen->lcd_rst_gpio = INVALID_GPIO;
MIPI_SCREEN_DBG("%s: Can not read property: mipi_lcd_rst.\n", __func__);
} else {
ret = of_property_read_u32(grandchildnode, "rockchip,delay", &value);
if (ret) {
MIPI_SCREEN_DBG("%s: Can not read property: delay.\n", __func__);
} else {
screen->lcd_rst_delay = value;
MIPI_SCREEN_DBG("%s: lcd->screen->lcd_rst_delay = %d.\n", __func__, screen->lcd_rst_delay);
}
gpio = of_get_named_gpio_flags(grandchildnode, "rockchip,gpios", 0, &flags);
if (!gpio_is_valid(gpio)) {
MIPI_SCREEN_DBG("rest: Can not read property: %s->gpios.\n", __func__);
}
ret = gpio_request(gpio, "mipi_lcd_rst");
if (ret) {
screen->lcd_rst_gpio = INVALID_GPIO;
MIPI_SCREEN_DBG("request mipi_lcd_rst gpio fail:%d\n", gpio);
return -1;
}
screen->lcd_rst_gpio = gpio;
screen->lcd_rst_atv_val = (flags == GPIO_ACTIVE_HIGH) ? 1:0;
MIPI_SCREEN_DBG("lcd->lcd_rst_gpio=%d,dsi->lcd_rst_atv_val=%d\n", screen->lcd_rst_gpio, screen->lcd_rst_atv_val);
}
grandchildnode = of_find_node_by_name(childnode, "mipi_lcd_en");
if (!grandchildnode) {
screen->lcd_en_gpio = INVALID_GPIO;
MIPI_SCREEN_DBG("%s: Can not read property: mipi_lcd_en.\n", __func__);
} else {
ret = of_property_read_u32(grandchildnode, "rockchip,delay", &value);
if (ret) {
MIPI_SCREEN_DBG("%s: Can not read property: mipi_lcd_en-delay.\n", __func__);
} else {
screen->lcd_en_delay = value;
MIPI_SCREEN_DBG("%s: lcd->screen.lcd_en_delay = %d.\n", __func__, screen->lcd_en_delay);
}
gpio = of_get_named_gpio_flags(grandchildnode, "rockchip,gpios", 0, &flags);
if (!gpio_is_valid(gpio)) {
MIPI_SCREEN_DBG("rest: Can not read property: %s->gpios.\n", __func__);
}
ret = gpio_request(gpio, "mipi_lcd_en");
if (ret) {
screen->lcd_en_gpio = INVALID_GPIO;
MIPI_SCREEN_DBG("request mipi_lcd_en gpio fail:%d\n", gpio);
return -1;
}
screen->lcd_en_gpio = gpio;
screen->lcd_en_atv_val = (flags == GPIO_ACTIVE_HIGH) ? 1:0;
MIPI_SCREEN_DBG("dsi->lcd_en_gpio=%d, dsi->screen.lcd_en_atv_val=%d\n", screen->lcd_en_gpio, screen->lcd_en_atv_val);
}
}
root = of_find_node_by_name(NULL, "screen-on-cmds");
if (!root) {
MIPI_SCREEN_DBG("can't find screen-on-cmds node\n");
} else {
for_each_child_of_node(root, childnode) {
dcs_cmd = kmalloc(sizeof(struct mipi_dcs_cmd_ctr_list), GFP_KERNEL);
strcpy(dcs_cmd->dcs_cmd.name, childnode->name);
prop = of_find_property(childnode, "rockchip,cmd", &length);
if (!prop) {
MIPI_SCREEN_DBG("Can not read property: cmds\n");
return -EINVAL;
}
MIPI_SCREEN_DBG("\n childnode->name =%s:length=%d\n", childnode->name, (length / sizeof(u32)));
dcs_cmd->dcs_cmd.cmds =
devm_kzalloc(dev, length, GFP_KERNEL);
if (!dcs_cmd->dcs_cmd.cmds) {
pr_err("malloc cmds fail!\n");
return -ENOMEM;
}
ret = of_property_read_u32_array(childnode,
"rockchip,cmd",
dcs_cmd->dcs_cmd.cmds,
length / sizeof(u32));
if (ret < 0) {
MIPI_SCREEN_DBG("%s: Can not read property: %s--->cmds\n", __func__, childnode->name);
kfree(dcs_cmd->dcs_cmd.cmds);
dcs_cmd->dcs_cmd.cmds = NULL;
return ret;
} else {
dcs_cmd->dcs_cmd.cmd_len = length / sizeof(u32);
}
ret = of_property_read_u32(childnode, "rockchip,dsi_id", &value);
if (ret) {
MIPI_SCREEN_DBG("%s: Can not read property: %s--->cmd_type\n", __func__, childnode->name);
} else {
if (screen->mipi_dsi_num == 1) {
if (value != 0) {
printk("err: rockchip,dsi_id not match.\n");
} else {
dcs_cmd->dcs_cmd.dsi_id = value;
}
} else {
if ((value < 0) || (value > 2))
printk("err: rockchip,dsi_id not match.\n");
else
dcs_cmd->dcs_cmd.dsi_id = value;
}
}
ret = of_property_read_u32(childnode, "rockchip,cmd_type", &value);
if (ret) {
MIPI_SCREEN_DBG("%s: Can not read property: %s--->cmd_type\n", __func__, childnode->name);
} else {
if ((value != 0) && (value != 1)) {
printk("err: rockchip, cmd_type not match.\n");
} else {
dcs_cmd->dcs_cmd.type = value;
}
}
ret = of_property_read_u32(childnode, "rockchip,cmd_delay", &value);
if (ret)
MIPI_SCREEN_DBG("%s: Can not read property: %s--->cmd_delay\n", __func__, childnode->name);
else
dcs_cmd->dcs_cmd.delay = value;
list_add_tail(&dcs_cmd->list, &screen->cmdlist_head);
}
}
ret = of_property_read_u32(root, "rockchip,cmd_debug", &debug);
if (ret) {
MIPI_SCREEN_DBG("%s: Can not read property: rockchip,cmd_debug.\n", __func__);
} else {
if (debug) {
list_for_each(pos, &screen->cmdlist_head) {
dcs_cmd = list_entry(pos, struct mipi_dcs_cmd_ctr_list, list);
printk("\n dcs_name:%s,dcs_type:%d,side_id:%d,cmd_len:%d,delay:%d\n\n",
dcs_cmd->dcs_cmd.name,
dcs_cmd->dcs_cmd.type,
dcs_cmd->dcs_cmd.dsi_id,
dcs_cmd->dcs_cmd.cmd_len,
dcs_cmd->dcs_cmd.delay);
for (i = 0; i < (dcs_cmd->dcs_cmd.cmd_len); i++) {
printk("[%d]=%02x,", i+1, dcs_cmd->dcs_cmd.cmds[i]);
}
}
} else {
MIPI_SCREEN_DBG("---close cmd debug---\n");
}
}
return 0;
}
#endif
int rk_mipi_get_dsi_num(void)
{
return gmipi_screen->mipi_dsi_num;
}
#ifdef CONFIG_LCD_MIPI
EXPORT_SYMBOL(rk_mipi_get_dsi_num);
#endif
int rk_mipi_get_dsi_lane(void)
{
return gmipi_screen->dsi_lane;
}
#ifdef CONFIG_LCD_MIPI
EXPORT_SYMBOL(rk_mipi_get_dsi_lane);
#endif
int rk_mipi_get_dsi_clk(void)
{
return gmipi_screen->hs_tx_clk;
}
#ifdef CONFIG_LCD_MIPI
EXPORT_SYMBOL(rk_mipi_get_dsi_clk);
#endif
#ifdef CONFIG_RK_3288_DSI_UBOOT
#ifdef CONFIG_OF_LIBFDT
static int rk_mipi_screen_init_dt(struct mipi_screen *screen)
{
struct mipi_dcs_cmd_ctr_list *dcs_cmd;
u32 i;
int length;
int err;
int node;
const void *blob;
struct fdt_gpio_state gpio_val;
int noffset;
INIT_LIST_HEAD(&screen->cmdlist_head);
blob = gd->fdt_blob; /* getenv_hex("fdtaddr", 0); */
node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_MIPI_INIT);
if (node < 0) {
MIPI_SCREEN_DBG("Can not get node of COMPAT_ROCKCHIP_MIPI_INIT\n");
}
screen->screen_init = fdtdec_get_int(blob, node, "rockchip,screen_init", -1);
if (screen->screen_init < 0) {
MIPI_SCREEN_DBG("Can not get screen_init\n");
}
screen->dsi_lane = fdtdec_get_int(blob, node, "rockchip,dsi_lane", -1);
if (screen->dsi_lane < 0) {
MIPI_SCREEN_DBG("Can not get dsi_lane\n");
}
screen->hs_tx_clk = fdtdec_get_int(blob, node, "rockchip,dsi_hs_clk", -1);
if (screen->hs_tx_clk < 0) {
MIPI_SCREEN_DBG("Can not get dsi_hs_clk\n");
} else {
screen->hs_tx_clk = screen->hs_tx_clk*MHZ;
}
screen->mipi_dsi_num = fdtdec_get_int(blob, node, "rockchip,mipi_dsi_num", -1);
if (screen->mipi_dsi_num < 0) {
MIPI_SCREEN_DBG("Can't get mipi_dsi_num\n");
}
#if 0
node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_MIPI_PWR);
if (node < 0) {
printf("Can not get node of COMPAT_ROCKCHIP_MIPI_PWR\n");
}
#endif
#if 0
/*get the lcd rst status
handle = fdt_getprop_u32_default(blob, "/mipi_power_ctr", "mipi_lcd_rst", -1);
node = fdt_node_offset_by_phandle(blob, handle);
*/
node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_MIPI_PWR);
if (node < 0) {
printf("Can not get node of COMPAT_ROCKCHIP_MIPI_PWR\n");
} else {
subnode = fdtdec_next_compatible_subnode(blob, node,
COMPAT_ROCKCHIP_MIPI_LCD_RST, &depth);
if (subnode <= 0) {
screen->lcd_rst_gpio = INVALID_GPIO;
printf("Can't get pin of mipi_lcd_rst\n");
} else {
err = fdtdec_decode_gpio(blob, subnode, "rockchip,gpios", &gpio_val);
gpio_val.gpio = rk_gpio_base_to_bank(gpio_val.gpio & RK_GPIO_BANK_MASK) | (gpio_val.gpio & RK_GPIO_PIN_MASK);
if (err < 0) {
screen->lcd_rst_gpio = INVALID_GPIO;
printf("Can't find GPIO rst\n");
} else {
screen->lcd_rst_gpio = gpio_val.gpio;
screen->lcd_rst_atv_val = !(gpio_val.flags & OF_GPIO_ACTIVE_LOW);
}
screen->lcd_rst_delay = fdtdec_get_int(blob, subnode, "rockchip,delay", -1);
if (screen->lcd_rst_delay < 0) {
printf("Can't get delay of rst delay\n");
}
printf("Get lcd rst gpio and delay successfully!\n");
}
}
#endif
/* get the lcd rst & en status */
node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_MIPI_PWR);
if (node < 0) {
MIPI_SCREEN_DBG("Can not get node of COMPAT_ROCKCHIP_MIPI_PWR\n");
} else {
#if 0
noffset = fdt_first_subnode(blob, node);
const char *name = fdt_get_name(blob, noffset, NULL);
printf("XJH_DEBUG1:%s\n", name);
noffset = fdt_next_subnode(blob, noffset);
const char *name1 = fdt_get_name(blob, noffset, NULL);
printf("XJH_DEBUG2:%s\n", name1);
#endif
for (noffset = fdt_first_subnode(blob, node);
noffset >= 0;
noffset = fdt_next_subnode(blob, noffset)) {
if (0 == fdt_node_check_compatible(blob, noffset, "rockchip,lcd_rst")) {
err = fdtdec_decode_gpio(blob, noffset, "rockchip,gpios", &gpio_val);
gpio_val.gpio = rk_gpio_base_to_bank(gpio_val.gpio & RK_GPIO_BANK_MASK) | (gpio_val.gpio & RK_GPIO_PIN_MASK);
if (err < 0) {
screen->lcd_rst_gpio = INVALID_GPIO;
MIPI_SCREEN_DBG("Can't find GPIO rst\n");
} else {
screen->lcd_rst_gpio = gpio_val.gpio;
screen->lcd_rst_atv_val = !(gpio_val.flags & OF_GPIO_ACTIVE_LOW);
}
screen->lcd_rst_delay = fdtdec_get_int(blob, noffset, "rockchip,delay", -1);
if (screen->lcd_rst_delay < 0) {
MIPI_SCREEN_DBG("Can't get delay of rst delay\n");
}
MIPI_SCREEN_DBG("Get lcd rst gpio and delay successfully!\n");
}
if (0 == fdt_node_check_compatible(blob, noffset, "rockchip,lcd_en")) {
err = fdtdec_decode_gpio(blob, noffset, "rockchip,gpios", &gpio_val);
gpio_val.gpio = rk_gpio_base_to_bank(gpio_val.gpio & RK_GPIO_BANK_MASK) | (gpio_val.gpio & RK_GPIO_PIN_MASK);
if (err < 0) {
screen->lcd_en_gpio = INVALID_GPIO;
MIPI_SCREEN_DBG("Can't find GPIO en\n");
} else {
screen->lcd_en_gpio = gpio_val.gpio;
screen->lcd_en_atv_val = !(gpio_val.flags & OF_GPIO_ACTIVE_LOW);
}
screen->lcd_en_delay = fdtdec_get_int(blob, noffset, "rockchip,delay", -1);
if (screen->lcd_en_delay < 0) {
MIPI_SCREEN_DBG("Can't get delay of lcd_en delay\n");
}
MIPI_SCREEN_DBG("Get lcd en gpio and delay successfully:delay %d!\n", screen->lcd_en_delay);
}
}
}
/*get the initial command list*/
node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_MIPI_SONCMDS);
if (node < 0) {
MIPI_SCREEN_DBG("Can not get node of COMPAT_ROCKCHIP_MIPI_SONCMDS\n");
} else {
for (noffset = fdt_first_subnode(blob, node);
noffset >= 0;
noffset = fdt_next_subnode(blob, noffset)) {
MIPI_SCREEN_DBG("build MIPI LCD init cmd tables\n");
/*
subnode = fdtdec_next_compatible_subnode(blob, node,
COMPAT_ROCKCHIP_MIPI_ONCMDS, &depth);
if (noffset < 0)
break;
*/
dcs_cmd = calloc(1, sizeof(struct mipi_dcs_cmd_ctr_list));
/* node = fdt_node_offset_by_phandle(blob, handle); */
strcpy(dcs_cmd->dcs_cmd.name, fdt_get_name(blob, noffset, NULL));
MIPI_SCREEN_DBG("%s\n", dcs_cmd->dcs_cmd.name);
dcs_cmd->dcs_cmd.type = fdtdec_get_int(blob, noffset, "rockchip,cmd_type", -1);
MIPI_SCREEN_DBG("dcs_cmd.type=%02x\n", dcs_cmd->dcs_cmd.type);
dcs_cmd->dcs_cmd.dsi_id = fdtdec_get_int(blob, noffset, "rockchip,dsi_id", -1);
MIPI_SCREEN_DBG("dcs_cmd.dsi_id=%02x\n", dcs_cmd->dcs_cmd.dsi_id);
fdt_getprop(blob, noffset, "rockchip,cmd", &length);
dcs_cmd->dcs_cmd.cmd_len = length / sizeof(u32) ;
dcs_cmd->dcs_cmd.cmds = calloc(1, length);
if (!dcs_cmd->dcs_cmd.cmds) {
pr_err("calloc cmds fail!\n");
return -1;
}
err = fdtdec_get_int_array(blob, noffset,
"rockchip,cmd",
dcs_cmd->dcs_cmd.cmds,
dcs_cmd->dcs_cmd.cmd_len);
dcs_cmd->dcs_cmd.delay = fdtdec_get_int(blob, noffset, "rockchip,cmd_delay", -1);
MIPI_SCREEN_DBG("dcs_cmd.delay=%d\n", dcs_cmd->dcs_cmd.delay);
list_add_tail(&dcs_cmd->list, &screen->cmdlist_head);
}
}
return 0;
}
#endif /* CONFIG_OF_LIBFDT */
int rk_mipi_screen_probe(void)
{
int ret = 0;
gmipi_screen = calloc(1, sizeof(struct mipi_screen));
if (!gmipi_screen) {
printf("request struct screen fail!\n");
return -ENOMEM;
}
#ifdef CONFIG_OF_LIBFDT
ret = rk_mipi_screen_init_dt(gmipi_screen);
if (ret < 0) {
printf(" rk_mipi_screen_init_dt fail!\n");
return -1;
}
#endif /* CONFIG_OF_LIBFDT */
MIPI_SCREEN_DBG("---rk_mipi_screen_probe--end\n");
return 0;
}
#endif /* CONFIG_RK_3288_DSI_UBOOT */
#ifdef CONFIG_LCD_MIPI
static int __init rk_mipi_screen_probe(struct platform_device *pdev)
{
static int ret;
gmipi_screen = devm_kzalloc(&pdev->dev, sizeof(struct mipi_screen), GFP_KERNEL);
if (!gmipi_screen) {
dev_err(&pdev->dev, "request struct screen fail!\n");
return -ENOMEM;
}
ret = rk_mipi_screen_init_dt(&pdev->dev, gmipi_screen);
if (ret < 0) {
dev_err(&pdev->dev, " rk_mipi_screen_init_dt fail!\n");
return -1;
}
MIPI_SCREEN_DBG("---rk_mipi_screen_probe--end\n");
return 0;
}
static struct platform_driver mipi_screen_platform_driver = {
.driver = {
.name = "rk_mipi_screen",
},
};
static int __init rk_mipi_screen_init(void)
{
platform_device_register_simple("rk_mipi_screen", -1, NULL, 0);
return platform_driver_probe(&mipi_screen_platform_driver, rk_mipi_screen_probe);
}
static void __exit rk_mipi_screen_exit(void)
{
platform_driver_unregister(&mipi_screen_platform_driver);
}
subsys_initcall_sync(rk_mipi_screen_init);
module_exit(rk_mipi_screen_exit);
#endif

121
drivers/video/rockchip/screen/rk_screen.c
View File

@ -1,121 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/module.h>
#include <linux/rk_fb.h>
#include <linux/device.h>
#include "lcd.h"
#include "../hdmi/rockchip-hdmi.h"
static struct rk_screen *rk_screen;
int rk_fb_get_extern_screen(struct rk_screen *screen)
{
if (unlikely(!rk_screen) || unlikely(!screen))
return -1;
memcpy(screen, rk_screen, sizeof(struct rk_screen));
screen->dsp_lut = NULL;
screen->cabc_lut = NULL;
screen->type = SCREEN_NULL;
return 0;
}
int rk_fb_get_prmry_screen(struct rk_screen *screen)
{
if (unlikely(!rk_screen) || unlikely(!screen))
return -1;
memcpy(screen, rk_screen, sizeof(struct rk_screen));
return 0;
}
int rk_fb_set_prmry_screen(struct rk_screen *screen)
{
if (unlikely(!rk_screen) || unlikely(!screen))
return -1;
rk_screen->lcdc_id = screen->lcdc_id;
rk_screen->screen_id = screen->screen_id;
rk_screen->x_mirror = screen->x_mirror;
rk_screen->y_mirror = screen->y_mirror;
rk_screen->overscan.left = screen->overscan.left;
rk_screen->overscan.top = screen->overscan.left;
rk_screen->overscan.right = screen->overscan.left;
rk_screen->overscan.bottom = screen->overscan.left;
return 0;
}
size_t get_fb_size(u8 reserved_fb)
{
size_t size = 0;
u32 xres = 0;
u32 yres = 0;
if (unlikely(!rk_screen))
return 0;
xres = rk_screen->mode.xres;
yres = rk_screen->mode.yres;
/* align as 64 bytes(16*4) in an odd number of times */
xres = ALIGN_64BYTE_ODD_TIMES(xres, ALIGN_PIXEL_64BYTE_RGB8888);
if (reserved_fb == 1) {
size = (xres * yres << 2) << 1;/*two buffer*/
} else {
#if defined(CONFIG_THREE_FB_BUFFER)
size = (xres * yres << 2) * 3; /* three buffer */
#else
size = (xres * yres << 2) << 1; /* two buffer */
#endif
}
return ALIGN(size, SZ_1M);
}
static int rk_screen_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
int ret;
if (!np) {
dev_err(&pdev->dev, "Missing device tree node.\n");
return -EINVAL;
}
rk_screen = devm_kzalloc(&pdev->dev,
sizeof(struct rk_screen), GFP_KERNEL);
if (!rk_screen) {
dev_err(&pdev->dev, "kmalloc for rk screen fail!");
return -ENOMEM;
}
ret = rk_fb_prase_timing_dt(np, rk_screen);
dev_info(&pdev->dev, "rockchip screen probe %s\n",
ret ? "failed" : "success");
return ret;
}
static const struct of_device_id rk_screen_dt_ids[] = {
{ .compatible = "rockchip,screen", },
{}
};
static struct platform_driver rk_screen_driver = {
.probe = rk_screen_probe,
.driver = {
.name = "rk-screen",
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(rk_screen_dt_ids),
},
};
static int __init rk_screen_init(void)
{
return platform_driver_register(&rk_screen_driver);
}
static void __exit rk_screen_exit(void)
{
platform_driver_unregister(&rk_screen_driver);
}
fs_initcall(rk_screen_init);
module_exit(rk_screen_exit);

30
include/dt-bindings/display/screen-timing/lcd-86v-rgb1024x600.dtsi
View File

@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* RockChip. LCD_RGB1024x600 FOR 86V
*
*/
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen-type = <SCREEN_RGB>;
out-face = <OUT_P666>;
clock-frequency = <60000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <100>;
hfront-porch = <120>;
vback-porch = <10>;
vfront-porch = <15>;
hsync-len = <100>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};

124
include/dt-bindings/display/screen-timing/lcd-F402.dtsi
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@ -1,124 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* RockChip. DisplayPort screen LP097QX1
*
*/
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen-type = <SCREEN_EDP>;
out-face = <OUT_P666>;
clock-frequency = <205000000>;
hactive = <1536>;
vactive = <2048>;
hback-porch = <48>;
hfront-porch = <12>;
vback-porch = <8>;
vfront-porch = <8>;
hsync-len = <16>;
vsync-len = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
dsp-lut = <0x00000000 0x00010101 0x00020202 0x00030303 0x00040404 0x00050505 0x00060606 0x00070707 0x00080808 0x00090909
0x000a0a0a 0x000b0b0b 0x000c0c0c 0x000d0d0d 0x000e0e0e 0x000f0f0f 0x00101010 0x00111111 0x00121212 0x00131313
0x00141414 0x00151515 0x00161616 0x00171717 0x00181818 0x00191919 0x001a1a1a 0x001b1b1b 0x001c1c1c 0x001d1d1d
0x001e1e1e 0x001f1f1f 0x00202020 0x00212121 0x00222222 0x00232323 0x00242424 0x00252525 0x00262626 0x00272727
0x00282828 0x00292929 0x002a2a2a 0x002b2b2b 0x002c2c2c 0x002d2d2d 0x002e2e2e 0x002f2f2f 0x00303030 0x00313131
0x00323232 0x00333333 0x00343434 0x00353535 0x00363636 0x00373737 0x00383838 0x00393939 0x003a3a3a 0x003b3b3b
0x003c3c3c 0x003d3d3d 0x003e3e3e 0x003f3f3f 0x00404040 0x00414141 0x00424242 0x00434343 0x00444444 0x00454545
0x00464646 0x00474747 0x00484848 0x00494949 0x004a4a4a 0x004b4b4b 0x004c4c4c 0x004d4d4d 0x004e4e4e 0x004f4f4f
0x00505050 0x00515151 0x00525252 0x00535353 0x00545454 0x00555555 0x00565656 0x00575757 0x00585858 0x00595959
0x005a5a5a 0x005b5b5b 0x005c5c5c 0x005d5d5d 0x005e5e5e 0x005f5f5f 0x00606060 0x00616161 0x00626262 0x00636363
0x00646464 0x00656565 0x00666666 0x00676767 0x00686868 0x00696969 0x006a6a6a 0x006b6b6b 0x006c6c6c 0x006d6d6d
0x006e6e6e 0x006f6f6f 0x00707070 0x00717171 0x00727272 0x00737373 0x00747474 0x00757575 0x00767676 0x00777777
0x00787878 0x00797979 0x007a7a7a 0x007b7b7b 0x007c7c7c 0x007d7d7d 0x007e7e7e 0x007f7f7f 0x00808080 0x00818181
0x00828282 0x00838383 0x00848484 0x00858585 0x00868686 0x00878787 0x00888888 0x00898989 0x008a8a8a 0x008b8b8b
0x008c8c8c 0x008d8d8d 0x008e8e8e 0x008f8f8f 0x00909090 0x00919191 0x00929292 0x00939393 0x00949494 0x00959595
0x00969696 0x00979797 0x00989898 0x00999999 0x009a9a9a 0x009b9b9b 0x009c9c9c 0x009d9d9d 0x009e9e9e 0x009f9f9f
0x00a0a0a0 0x00a1a1a1 0x00a2a2a2 0x00a3a3a3 0x00a4a4a4 0x00a5a5a5 0x00a6a6a6 0x00a7a7a7 0x00a8a8a8 0x00a9a9a9
0x00aaaaaa 0x00ababab 0x00acacac 0x00adadad 0x00aeaeae 0x00afafaf 0x00b0b0b0 0x00b1b1b1 0x00b2b2b2 0x00b3b3b3
0x00b4b4b4 0x00b5b5b5 0x00b6b6b6 0x00b7b7b7 0x00b8b8b8 0x00b9b9b9 0x00bababa 0x00bbbbbb 0x00bcbcbc 0x00bdbdbd
0x00bebebe 0x00bfbfbf 0x00c0c0c0 0x00c1c1c1 0x00c2c2c2 0x00c3c3c3 0x00c4c4c4 0x00c5c5c5 0x00c6c6c6 0x00c7c7c7
0x00c8c8c8 0x00c9c9c9 0x00cacaca 0x00cbcbcb 0x00cccccc 0x00cdcdcd 0x00cecece 0x00cfcfcf 0x00d0d0d0 0x00d1d1d1
0x00d2d2d2 0x00d3d3d3 0x00d4d4d4 0x00d5d5d5 0x00d6d6d6 0x00d7d7d7 0x00d8d8d8 0x00d9d9d9 0x00dadada 0x00dbdbdb
0x00dcdcdc 0x00dddddd 0x00dedede 0x00dfdfdf 0x00e0e0e0 0x00e1e1e1 0x00e2e2e2 0x00e3e3e3 0x00e4e4e4 0x00e5e5e5
0x00e6e6e6 0x00e7e7e7 0x00e8e8e8 0x00e9e9e9 0x00eaeaea 0x00ebebeb 0x00ececec 0x00ededed 0x00eeeeee 0x00efefef
0x00f0f0f0 0x00f1f1f1 0x00f2f2f2 0x00f3f3f3 0x00f4f4f4 0x00f5f5f5 0x00f6f6f6 0x00f7f7f7 0x00f8f8f8 0x00f9f9f9
0x00fafafa 0x00fbfbfb 0x00fcfcfc 0x00fdfdfd 0x00fefefe 0x00ffffff>;
cabc-lut = <
/*gamma = 2.2*/
0x00000383 0x00000392 0x000003a2 0x000003b2 0x000003c2 0x000003d2 0x000003e2 0x000003f3
0x00000403 0x00000414 0x00000425 0x00000436 0x00000447 0x00000458 0x0000046a 0x0000047b
0x0000048d 0x0000049f 0x000004b1 0x000004c3 0x000004d5 0x000004e8 0x000004fa 0x0000050d
0x00000520 0x00000533 0x00000546 0x0000055a 0x0000056d 0x00000581 0x00000595 0x000005a9
0x000005bd 0x000005d1 0x000005e5 0x000005fa 0x0000060f 0x00000624 0x00000639 0x0000064e
0x00000663 0x00000679 0x0000068e 0x000006a4 0x000006ba 0x000006d0 0x000006e6 0x000006fd
0x00000713 0x0000072a 0x00000741 0x00000758 0x0000076f 0x00000786 0x0000079e 0x000007b6
0x000007cd 0x000007e5 0x000007fd 0x00000816 0x0000082e 0x00000847 0x0000085f 0x00000878
0x00000891 0x000008ab 0x000008c4 0x000008de 0x000008f7 0x00000911 0x0000092b 0x00000945
0x00000960 0x0000097a 0x00000995 0x000009af 0x000009ca 0x000009e6 0x00000a01 0x00000a1c
0x00000a38 0x00000a54 0x00000a6f 0x00000a8c 0x00000aa8 0x00000ac4 0x00000ae1 0x00000afd
0x00000b1a 0x00000b37 0x00000b54 0x00000b72 0x00000b8f 0x00000bad 0x00000bcb 0x00000be9
0x00000c07 0x00000c25 0x00000c44 0x00000c62 0x00000c81 0x00000ca0 0x00000cbf 0x00000cdf
0x00000cfe 0x00000d1e 0x00000d3e 0x00000d5d 0x00000d7e 0x00000d9e 0x00000dbe 0x00000ddf
0x00000e00 0x00000e21 0x00000e42 0x00000e63 0x00000e84 0x00000ea6 0x00000ec8 0x00000eea
0x00000f0c 0x00000f2e 0x00000f50 0x00000f73 0x00000f96 0x00000fb9 0x00000fdc 0x00000fff
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
cabc-gamma-base = <
/*gamma = 2.2*/
0x00010000 0x0000fdd0 0x0000fba8 0x0000f986 0x0000f76a 0x0000f556 0x0000f347 0x0000f140
0x0000ef3e 0x0000ed43 0x0000eb4e 0x0000e95e 0x0000e775 0x0000e592 0x0000e3b4 0x0000e1dc
0x0000e009 0x0000de3c 0x0000dc74 0x0000dab2 0x0000d8f4 0x0000d73c 0x0000d589 0x0000d3db
0x0000d232 0x0000d08d 0x0000ceee 0x0000cd53 0x0000cbbc 0x0000ca2b 0x0000c89d 0x0000c714
0x0000c590 0x0000c410 0x0000c294 0x0000c11c 0x0000bfa8 0x0000be39 0x0000bccd 0x0000bb65
0x0000ba01 0x0000b8a1 0x0000b745 0x0000b5ed 0x0000b498 0x0000b347 0x0000b1f9 0x0000b0af
0x0000af68 0x0000ae25 0x0000ace5 0x0000aba8 0x0000aa6f 0x0000a939 0x0000a806 0x0000a6d7
0x0000a5aa 0x0000a480 0x0000a35a 0x0000a236 0x0000a116 0x00009ff8 0x00009edd 0x00009dc5
0x00009cb0 0x00009b9e 0x00009a8e 0x00009981 0x00009877 0x0000976f 0x0000966a 0x00009567
0x00009467 0x0000936a 0x0000926f 0x00009176 0x00009080 0x00008f8c 0x00008e9a 0x00008dab
0x00008cbe 0x00008bd3 0x00008aea 0x00008a04 0x00008920 0x0000883e 0x0000875e 0x00008680
0x000085a4 0x000084ca 0x000083f3 0x0000831d 0x00008249 0x00008177 0x000080a7 0x00007fd9
0x00007f0d 0x00007e42 0x00007d7a 0x00007cb3 0x00007bee 0x00007b2b 0x00007a6a 0x000079aa
0x000078ec 0x0000782f 0x00007775 0x000076bc 0x00007604 0x0000754f 0x0000749a 0x000073e8
0x00007337 0x00007287 0x000071d9 0x0000712c 0x00007081 0x00006fd8 0x00006f30 0x00006e89
0x00006de4 0x00006d40 0x00006c9d 0x00006bfc 0x00006b5c 0x00006abe 0x00006a21 0x00006985
0x000068ea 0x00006851 0x000067b9 0x00006722 0x0000668d 0x000065f9 0x00006566 0x000064d4
0x00006443 0x000063b4 0x00006325 0x00006298 0x0000620c 0x00006181 0x000060f8 0x0000606f
0x00005fe7 0x00005f61 0x00005edb 0x00005e57 0x00005dd4 0x00005d51 0x00005cd0 0x00005c50
0x00005bd1 0x00005b52 0x00005ad5 0x00005a59 0x000059de 0x00005963 0x000058ea 0x00005871
0x000057fa 0x00005783 0x0000570d 0x00005699 0x00005625 0x000055b2 0x0000553f 0x000054ce
0x0000545d 0x000053ee 0x0000537f 0x00005311 0x000052a4 0x00005238 0x000051cc 0x00005161
0x000050f7 0x0000508e 0x00005026 0x00004fbe 0x00004f57 0x00004ef1 0x00004e8c 0x00004e27
0x00004dc3 0x00004d60 0x00004cfe 0x00004c9c 0x00004c3b 0x00004bdb 0x00004b7b 0x00004b1c
0x00004abe 0x00004a60 0x00004a03 0x000049a7 0x0000494b 0x000048f0 0x00004896 0x0000483c
0x000047e3 0x0000478a 0x00004733 0x000046db 0x00004685 0x0000462f 0x000045d9 0x00004584
0x00004530 0x000044dc 0x00004489 0x00004437 0x000043e5 0x00004393 0x00004342 0x000042f2
0x000042a2 0x00004253 0x00004204 0x000041b6 0x00004169 0x0000411b 0x000040cf 0x00004083
0x00004037 0x00003fec 0x00003fa1 0x00003f57 0x00003f0e 0x00003ec5 0x00003e7c 0x00003e34
0x00003dec 0x00003da5 0x00003d5e 0x00003d18 0x00003cd2 0x00003c8c 0x00003c48 0x00003c03
0x00003bbf 0x00003b7b 0x00003b38 0x00003af5 0x00003ab3 0x00003a71 0x00003a30 0x000039ef
0x000039ae 0x0000396e 0x0000392e 0x000038ee 0x000038af 0x00003871 0x00003832 0x000037f5>;
};
};

30
include/dt-bindings/display/screen-timing/lcd-LP097Qx1.dtsi
View File

@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* RockChip. DisplayPort screen LP097QX1
*
*/
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen-type = <SCREEN_EDP>;
out-face = <OUT_P666>;
clock-frequency = <205000000>;
hactive = <2048>;
vactive = <1536>;
hback-porch = <5>;
hfront-porch = <150>;
vback-porch = <9>;
vfront-porch = <3>;
hsync-len = <5>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};

106
include/dt-bindings/display/screen-timing/lcd-LP097Qx2.dtsi
View File

@ -1,106 +0,0 @@
/*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* include/dt-bindings/display/screen-timing/lcd-LP097QX2.dtsi
* author: xbl@rock-chips.com
* create date: 2016-05-16
* screen type: edp
* lcd model: lp097qx2
* resolution: 1536 * 2048
*/
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen-type = <SCREEN_EDP>;
out-face = <OUT_P888>;
clock-frequency = <200000000>;
hactive = <1536>;
vactive = <2048>;
hback-porch = <52>;
hfront-porch = <16>;
vback-porch = <3>;
vfront-porch = <7>;
hsync-len = <15>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
cabc-lut = <
/*gamma = 2.2*/
0x00000383 0x00000392 0x000003a2 0x000003b2 0x000003c2 0x000003d2 0x000003e2 0x000003f3
0x00000403 0x00000414 0x00000425 0x00000436 0x00000447 0x00000458 0x0000046a 0x0000047b
0x0000048d 0x0000049f 0x000004b1 0x000004c3 0x000004d5 0x000004e8 0x000004fa 0x0000050d
0x00000520 0x00000533 0x00000546 0x0000055a 0x0000056d 0x00000581 0x00000595 0x000005a9
0x000005bd 0x000005d1 0x000005e5 0x000005fa 0x0000060f 0x00000624 0x00000639 0x0000064e
0x00000663 0x00000679 0x0000068e 0x000006a4 0x000006ba 0x000006d0 0x000006e6 0x000006fd
0x00000713 0x0000072a 0x00000741 0x00000758 0x0000076f 0x00000786 0x0000079e 0x000007b6
0x000007cd 0x000007e5 0x000007fd 0x00000816 0x0000082e 0x00000847 0x0000085f 0x00000878
0x00000891 0x000008ab 0x000008c4 0x000008de 0x000008f7 0x00000911 0x0000092b 0x00000945
0x00000960 0x0000097a 0x00000995 0x000009af 0x000009ca 0x000009e6 0x00000a01 0x00000a1c
0x00000a38 0x00000a54 0x00000a6f 0x00000a8c 0x00000aa8 0x00000ac4 0x00000ae1 0x00000afd
0x00000b1a 0x00000b37 0x00000b54 0x00000b72 0x00000b8f 0x00000bad 0x00000bcb 0x00000be9
0x00000c07 0x00000c25 0x00000c44 0x00000c62 0x00000c81 0x00000ca0 0x00000cbf 0x00000cdf
0x00000cfe 0x00000d1e 0x00000d3e 0x00000d5d 0x00000d7e 0x00000d9e 0x00000dbe 0x00000ddf
0x00000e00 0x00000e21 0x00000e42 0x00000e63 0x00000e84 0x00000ea6 0x00000ec8 0x00000eea
0x00000f0c 0x00000f2e 0x00000f50 0x00000f73 0x00000f96 0x00000fb9 0x00000fdc 0x00000fff
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
};
};

82
include/dt-bindings/display/screen-timing/lcd-b080xan03.0-mipi.dtsi
View File

@ -1,82 +0,0 @@
/*
* Copyright (C) 2014 ROCKCHIP, Inc.
* Licensed under GPLv2 or later.
* arch/arm/boot/dts/lcd-b080xan03.0-mipi.dtsi
* author: chenyf@rock-chips.com
* create date: 2014-09-11
* lcd model: b080xan03.0
* resolution: 768 X 1024
* mipi channel: single
*/
/* about mipi */
disp_mipi_init: mipi_dsi_init{
compatible = "rockchip,mipi_dsi_init";
rockchip,screen_init = <0>;
rockchip,dsi_lane = <4>;
rockchip,dsi_hs_clk = <528>;
rockchip,mipi_dsi_num = <1>;
};
disp_mipi_power_ctr: mipi_power_ctr {
compatible = "rockchip,mipi_power_ctr";
mipi_lcd_rst:mipi_lcd_rst{
compatible = "rockchip,lcd_rst";
rockchip,gpios = <&gpio2 GPIO_C2 GPIO_ACTIVE_HIGH>;
rockchip,delay = <20>;
};
/* mipi_lcd_en:mipi_lcd_en {
compatible = "rockchip,lcd_en";
rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>;
rockchip,delay = <100>;
};*/
};
disp_mipi_init_cmds: screen-on-cmds {
compatible = "rockchip,screen-on-cmds";
/*rockchip,cmd_debug = <1>;
rockchip,on-cmds1 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <HSDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0xb0 0x02>;
rockchip,cmd_delay = <0>;
};
*/
};
disp_timings: display-timings {
native-mode = <&timing0>;
compatible = "rockchip,display-timings";
timing0: timing0 {
screen-type = <SCREEN_MIPI>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_P666>;
clock-frequency = <67000000>;
hactive = <768>;
vactive = <1024>;
hback-porch = <56>;
hfront-porch = <60>;
vback-porch = <30>;
vfront-porch = <36>;
hsync-len = <64>;
vsync-len = <14>;
/*
hactive = <1024>;
vactive = <768>;
hback-porch = <56>;
hfront-porch = <60>;
vback-porch = <30>;
vfront-porch = <36>;
hsync-len = <64>;
vsync-len = <14>;
*/
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};

66
include/dt-bindings/display/screen-timing/lcd-b101ew05.dtsi
View File

@ -1,66 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* RockChip. LCD_B101ew05
*
*/
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen-type = <SCREEN_LVDS>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_D888_P666>;
color-mode = <COLOR_RGB>;
clock-frequency = <71000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <100>;
hfront-porch = <18>;
vback-porch = <8>;
vfront-porch = <6>;
hsync-len = <10>;
vsync-len = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
cabc-lut = <
/*gamma = 2.0*/
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000002
0x00000002 0x00000002 0x00000002 0x00000002 0x00000003 0x00000003 0x00000003 0x00000003
0x00000004 0x00000004 0x00000004 0x00000004 0x00000005 0x00000005 0x00000005 0x00000005
0x00000006 0x00000006 0x00000006 0x00000007 0x00000007 0x00000007 0x00000008 0x00000008
0x00000009 0x00000009 0x00000009 0x0000000a 0x0000000a 0x0000000b 0x0000000b 0x0000000b
0x0000000c 0x0000000c 0x0000000d 0x0000000d 0x0000000e 0x0000000e 0x0000000f 0x0000000f
0x00000010 0x00000010 0x00000011 0x00000011 0x00000012 0x00000012 0x00000013 0x00000013
0x00000014 0x00000014 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018
0x00000019 0x00000019 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001d 0x0000001d
0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000021 0x00000021 0x00000022 0x00000023
0x00000024 0x00000024 0x00000025 0x00000026 0x00000027 0x00000028 0x00000028 0x00000029
0x0000002a 0x0000002b 0x0000002c 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030
0x00000031 0x00000032 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037
0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f
0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047
0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004f 0x00000050
0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000057 0x00000058 0x00000059
0x0000005a 0x0000005b 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000063
0x00000064 0x00000065 0x00000066 0x00000068 0x00000069 0x0000006a 0x0000006c 0x0000006d
0x0000006e 0x00000070 0x00000071 0x00000072 0x00000074 0x00000075 0x00000076 0x00000078
0x00000079 0x0000007a 0x0000007c 0x0000007d 0x0000007f 0x00000080 0x00000081 0x00000083
0x00000084 0x00000086 0x00000087 0x00000089 0x0000008a 0x0000008c 0x0000008d 0x0000008f
0x00000090 0x00000092 0x00000093 0x00000095 0x00000096 0x00000098 0x00000099 0x0000009b
0x0000009c 0x0000009e 0x000000a0 0x000000a1 0x000000a3 0x000000a4 0x000000a6 0x000000a8
0x000000a9 0x000000ab 0x000000ac 0x000000ae 0x000000b0 0x000000b1 0x000000b3 0x000000b5
0x000000b6 0x000000b8 0x000000ba 0x000000bc 0x000000bd 0x000000bf 0x000000c1 0x000000c3
0x000000c4 0x000000c6 0x000000c8 0x000000ca 0x000000cb 0x000000cd 0x000000cf 0x000000d1
0x000000d3 0x000000d4 0x000000d6 0x000000d8 0x000000da 0x000000dc 0x000000de 0x000000e0
0x000000e1 0x000000e3 0x000000e5 0x000000e7 0x000000e9 0x000000eb 0x000000ed 0x000000ef
0x000000f1 0x000000f3 0x000000f5 0x000000f7 0x000000f9 0x000000fb 0x000000fd 0x000000ff>;
};
};

99
include/dt-bindings/display/screen-timing/lcd-box.dtsi
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@ -1,99 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* RockChip. LCD_BOX
*
*/
disp_power_ctr: power_ctr {
/* rockchip,debug = <0>;
lcd_en:lcd_en {
rockchip,power_type = <GPIO>;
gpios = <&gpio0 GPIO_B0 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
bl_en:bl_en {
rockchip,power_type = <GPIO>;
gpios = <&gpio0 GPIO_A2 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
bl_ctr:bl_ctr {
rockchip,power_type = <GPIO>;
gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
lcd_rst:lcd_rst {
rockchip,power_type = <REGULATOR>;
rockchip,delay = <5>;
};*/
};
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen-type = <SCREEN_RGB>;
out-face = <OUT_P888>;
color-mode = <COLOR_YCBCR>;
clock-frequency = <74250000>;
hactive = <1280>;
vactive = <720>;
hback-porch = <220>;
hfront-porch = <110>;
vback-porch = <20>;
vfront-porch = <5>;
hsync-len = <40>;
vsync-len = <5>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
timing1: timing1 {
screen-type = <SCREEN_RGB>;
out-face = <OUT_P888>;
color-mode = <COLOR_YCBCR>;
clock-frequency = <148500000>;
hactive = <1920>;
vactive = <1080>;
hback-porch = <148>;
hfront-porch = <88>;
vback-porch = <36>;
vfront-porch = <4>;
hsync-len = <44>;
vsync-len = <5>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
timing2: timing2 {
screen-type = <SCREEN_RGB>;
out-face = <OUT_P888>;
color-mode = <COLOR_YCBCR>;
clock-frequency = <297000000>;
hactive = <3840>;
vactive = <2160>;
hback-porch = <296>;
hfront-porch = <176>;
vback-porch = <72>;
vfront-porch = <8>;
hsync-len = <88>;
vsync-len = <10>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};

101
include/dt-bindings/display/screen-timing/lcd-fpga-800x480-rgb.dtsi
View File

@ -1,101 +0,0 @@
/*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen-type = <SCREEN_RGB>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_D888_P666>;
color-mode = <COLOR_RGB>;
clock-frequency = <71000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <206>;
hfront-porch = <1>;
vback-porch = <25>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
cabc-lut = <
/*gamma = 2.0*/
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000002
0x00000002 0x00000002 0x00000002 0x00000002 0x00000003 0x00000003 0x00000003 0x00000003
0x00000004 0x00000004 0x00000004 0x00000004 0x00000005 0x00000005 0x00000005 0x00000005
0x00000006 0x00000006 0x00000006 0x00000007 0x00000007 0x00000007 0x00000008 0x00000008
0x00000009 0x00000009 0x00000009 0x0000000a 0x0000000a 0x0000000b 0x0000000b 0x0000000b
0x0000000c 0x0000000c 0x0000000d 0x0000000d 0x0000000e 0x0000000e 0x0000000f 0x0000000f
0x00000010 0x00000010 0x00000011 0x00000011 0x00000012 0x00000012 0x00000013 0x00000013
0x00000014 0x00000014 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018
0x00000019 0x00000019 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001d 0x0000001d
0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000021 0x00000021 0x00000022 0x00000023
0x00000024 0x00000024 0x00000025 0x00000026 0x00000027 0x00000028 0x00000028 0x00000029
0x0000002a 0x0000002b 0x0000002c 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030
0x00000031 0x00000032 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037
0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f
0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047
0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004f 0x00000050
0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000057 0x00000058 0x00000059
0x0000005a 0x0000005b 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000063
0x00000064 0x00000065 0x00000066 0x00000068 0x00000069 0x0000006a 0x0000006c 0x0000006d
0x0000006e 0x00000070 0x00000071 0x00000072 0x00000074 0x00000075 0x00000076 0x00000078
0x00000079 0x0000007a 0x0000007c 0x0000007d 0x0000007f 0x00000080 0x00000081 0x00000083
0x00000084 0x00000086 0x00000087 0x00000089 0x0000008a 0x0000008c 0x0000008d 0x0000008f
0x00000090 0x00000092 0x00000093 0x00000095 0x00000096 0x00000098 0x00000099 0x0000009b
0x0000009c 0x0000009e 0x000000a0 0x000000a1 0x000000a3 0x000000a4 0x000000a6 0x000000a8
0x000000a9 0x000000ab 0x000000ac 0x000000ae 0x000000b0 0x000000b1 0x000000b3 0x000000b5
0x000000b6 0x000000b8 0x000000ba 0x000000bc 0x000000bd 0x000000bf 0x000000c1 0x000000c3
0x000000c4 0x000000c6 0x000000c8 0x000000ca 0x000000cb 0x000000cd 0x000000cf 0x000000d1
0x000000d3 0x000000d4 0x000000d6 0x000000d8 0x000000da 0x000000dc 0x000000de 0x000000e0
0x000000e1 0x000000e3 0x000000e5 0x000000e7 0x000000e9 0x000000eb 0x000000ed 0x000000ef
0x000000f1 0x000000f3 0x000000f5 0x000000f7 0x000000f9 0x000000fb 0x000000fd 0x000000ff>;
};
};

317
include/dt-bindings/display/screen-timing/lcd-h381dln01-1080x1200-double.dtsi
View File

@ -1,317 +0,0 @@
/*
*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
* author: xubilv <xbl@rock-chips.com>
* create date: 2016-08-11
* resolution: 1080 X 1200
* mipi channel: double
*/
/* about mipi */
disp_mipi_init: mipi_dsi_init {
compatible = "rockchip,mipi_dsi_init";
rockchip,screen_init = <1>;
rockchip,dsi_lane = <4>;
rockchip,dsi_hs_clk = <970>;
rockchip,mipi_dsi_num = <2>;
};
disp_mipi_power_ctr: mipi_power_ctr {
compatible = "rockchip,mipi_power_ctr";
/*mipi_lcd_rst:mipi_lcd_rst {
compatible = "rockchip,lcd_rst";
rockchip,gpios = <&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>;
rockchip,delay = <0>;
};
mipi_lcd_avdd:mipi_lcd_avdd {
compatible = "rockchip,lcd_avdd";
rockchip,gpios = <&gpio7 GPIO_A2 GPIO_ACTIVE_HIGH>;
rockchip,delay = <0>;
};
mipi_lcd_ovdd:mipi_lcd_ovdd {
compatible = "rockchip,lcd_ovdd";
rockchip,gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>;
rockchip,delay = <0>;
};
mipi_lcd_ovss:mipi_lcd_ovss {
compatible = "rockchip,lcd_ovss";
rockchip,gpios = <&gpio7 GPIO_B0 GPIO_ACTIVE_HIGH>;
rockchip,delay = <0>;
};
mipi_lcd_rst:mipi_lcd_rst{
compatible = "rockchip,lcd_rst";
rockchip,gpios = <&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>;
rockchip,delay = <100>;
};
mipi_lcd_en:mipi_lcd_en {
compatible = "rockchip,lcd_en";
rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>;
rockchip,delay = <100>;
};*/
};
disp_mipi_init_cmds: screen-on-cmds {
compatible = "rockchip,screen-on-cmds";
rockchip,cmd_debug = <0>;
rockchip,on-cmds1 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xFE 0x07>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds2 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x00 0xEC>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds3 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x0B 0xEC>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds4 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x16 0xEC>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds5 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x21 0xEC>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds6 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x2D 0xEC>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds7 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xA9 0xBA>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds8 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xAB 0x06>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds9 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xBB 0x84>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds10 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xBC 0x1C>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds11 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xFE 0x08>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds12 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x07 0x1A>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds13 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xFE 0x0A>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds14 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x2A 0x1B>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds15 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xFE 0x0D>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds16 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x02 0x65>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds17 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x4D 0x41>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds18 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x4B 0x0F>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds19 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x53 0xFE>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds20 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xFE 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds21 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xC2 0x03>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds22 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x51 0xFF>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds23 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x05 0x11>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds24 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x05 0x29>;
rockchip,cmd_delay = <10>;
};
};
disp_timings: display-timings {
native-mode = <&timing0>;
compatible = "rockchip,display-timings";
timing0: timing0 {
screen-type = <SCREEN_DUAL_MIPI>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_P888>;
clock-frequency = <231795000>; /* 185436000 60fps, 231795000 75fps, 278154000 90fps */
hactive = <2160>; //1080
vactive = <1200>;
hback-porch = <180>;
hfront-porch = <200>;
vback-porch = <3>;
vfront-porch = <6>;
hsync-len = <10>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
screen-width = <130>;
screen-hight = <72>;
};
};

314
include/dt-bindings/display/screen-timing/lcd-h381dln01-1080x1200.dtsi
View File

@ -1,314 +0,0 @@
/*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
* author: xubilv <xbl@rock-chips.com>
* create date: 2016-08-11
* resolution: 1080 X 1200
* mipi channel: single
*/
disp_mipi_init: mipi_dsi_init {
compatible = "rockchip,mipi_dsi_init";
rockchip,screen_init = <1>;
rockchip,dsi_lane = <4>;
rockchip,dsi_hs_clk = <970>;
rockchip,mipi_dsi_num = <1>;
};
disp_mipi_power_ctr: mipi_power_ctr {
compatible = "rockchip,mipi_power_ctr";
/*mipi_lcd_rst:mipi_lcd_rst {
compatible = "rockchip,lcd_rst";
rockchip,gpios = <&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>;
rockchip,delay = <0>;
};
mipi_lcd_avdd:mipi_lcd_avdd {
compatible = "rockchip,lcd_avdd";
rockchip,gpios = <&gpio7 GPIO_A2 GPIO_ACTIVE_HIGH>;
rockchip,delay = <0>;
};
mipi_lcd_ovdd:mipi_lcd_ovdd {
compatible = "rockchip,lcd_ovdd";
rockchip,gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>;
rockchip,delay = <0>;
};
mipi_lcd_ovss:mipi_lcd_ovss {
compatible = "rockchip,lcd_ovss";
rockchip,gpios = <&gpio7 GPIO_B0 GPIO_ACTIVE_HIGH>;
rockchip,delay = <0>;
};
mipi_lcd_rst:mipi_lcd_rst {
compatible = "rockchip,lcd_rst";
rockchip,gpios = <&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>;
rockchip,delay = <100>;
};
mipi_lcd_en:mipi_lcd_en {
compatible = "rockchip,lcd_en";
rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>;
rockchip,delay = <100>;
};*/
};
disp_mipi_init_cmds: screen-on-cmds {
compatible = "rockchip,screen-on-cmds";
rockchip,cmd_debug = <0>;
rockchip,on-cmds1 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0xFE 0x07>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds2 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0x00 0xEC>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds3 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0x0B 0xEC>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds4 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0x16 0xEC>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds5 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0x21 0xEC>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds6 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0x2D 0xEC>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds7 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0xA9 0xBA>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds8 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0xAB 0x06>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds9 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0xBB 0x84>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds10 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0xBC 0x1C>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds11 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0xFE 0x08>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds12 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0x07 0x1A>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds13 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0xFE 0x0A>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds14 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0x2A 0x1B>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds15 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0xFE 0x0D>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds16 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0x02 0x65>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds17 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0x4D 0x41>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds18 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0x4B 0x0F>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds19 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0x53 0xFE>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds20 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0xFE 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds21 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0xC2 0x03>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds22 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0x51 0xFF>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds23 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x05 0x11>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds24 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x05 0x29>;
rockchip,cmd_delay = <10>;
};
};
disp_timings: display-timings {
native-mode = <&timing0>;
compatible = "rockchip,display-timings";
timing0: timing0 {
screen-type = <SCREEN_MIPI>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_P888>;
clock-frequency = <139000000>;//139
hactive = <1080>;
vactive = <1200>;
hback-porch = <90>;
hfront-porch = <100>;
vback-porch = <3>;
vfront-porch = <6>;
hsync-len = <5>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};

174
include/dt-bindings/display/screen-timing/lcd-h546dlb01-mipi.dtsi
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@ -1,174 +0,0 @@
/*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* include/dt-bindings/display/screen-timing/lcd-h546dlb01-mipi.dtsi
* author: bivvy.bi@rock-chips.com
* create date: 2016-09-02
* lcd Model: AUO h546dlb01
* resolution: 1080 X 1920
* mipi channel: single
*/
disp_mipi_init: mipi_dsi_init {
compatible = "rockchip,mipi_dsi_init";
rockchip,screen_init = <1>;
rockchip,dsi_lane = <4>;
rockchip,dsi_hs_clk = <1050>;
rockchip,mipi_dsi_num = <1>;
};
disp_mipi_power_ctr: mipi_power_ctr {
compatible = "rockchip,mipi_power_ctr";
};
disp_mipi_init_cmds: screen-on-cmds {
compatible = "rockchip,screen-on-cmds";
rockchip,cmd_debug = <1>;
rockchip,on-cmds1 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x23 0xFE 0x08>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds2 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x23 0x03 0x40>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds3 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x23 0x07 0x1a>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds4 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x23 0xfe 0x0d>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds5 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x23 0x53 0xfe>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds6 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x23 0xfe 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds7 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x23 0x51 0xff>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds8 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x23 0xc2 0x03>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds9 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x05 dcs_exit_sleep_mode>;
rockchip,cmd_delay = <120>;
};
rockchip,on-cmds10 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x05 dcs_set_display_on>;
rockchip,cmd_delay = <0>;
};
};
disp_timings: display-timings {
native-mode = <&timing0>;
compatible = "rockchip,display-timings";
timing0: timing0 {
screen-type = <SCREEN_MIPI>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_P888>;
clock-frequency = <153000000>;
hactive = <1080>;
vactive = <1920>;
hback-porch = <24>;
hfront-porch = <8>;
vback-porch = <7>;
vfront-porch = <12>;
hsync-len = <5>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
screen-width = <68>;
screen-hight = <120>;
};
};

139
include/dt-bindings/display/screen-timing/lcd-ld089wu1-mipi.dtsi
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@ -1,139 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2014 ROCKCHIP, Inc.
* arch/arm/boot/dts/lcd-lq070m1sx01-mipi.dtsi
* author: libing@rock-chips.com
* create date: 2014-04-15
* lcd model: ld089wu1
* resolution: 1920 X 1200
* mipi channel: single
*/
/* about mipi */
disp_mipi_init: mipi_dsi_init{
compatible = "rockchip,mipi_dsi_init";
rockchip,screen_init = <0>;
rockchip,dsi_lane = <4>;
rockchip,dsi_hs_clk = <1000>;
rockchip,mipi_dsi_num = <1>;
};
disp_mipi_power_ctr: mipi_power_ctr {
compatible = "rockchip,mipi_power_ctr";
/*mipi_lcd_rst:mipi_lcd_rst{
compatible = "rockchip,lcd_rst";
rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_LOW>;
rockchip,delay = <100>;
};
mipi_lcd_en:mipi_lcd_en {
compatible = "rockchip,lcd_en";
rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>;
rockchip,delay = <100>;
};*/
};
disp_mipi_init_cmds: screen-on-cmds {
compatible = "rockchip,screen-on-cmds";
/*rockchip,cmd_debug = <1>;
rockchip,on-cmds1 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <HSDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0xb0 0x02>;
rockchip,cmd_delay = <0>;
};
*/
};
disp_timings: display-timings {
native-mode = <&timing0>;
compatible = "rockchip,display-timings";
timing0: timing0 {
screen-type = <SCREEN_MIPI>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_P888>;
clock-frequency = <145000000>;
hactive = <1920>;
vactive = <1200>;
hback-porch = <16>;
hfront-porch = <24>;
vback-porch = <10>;
vfront-porch = <16>;
hsync-len = <10>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
cabc-lut = <
/*gamma = 2.2*/
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001
0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001
0x00000001 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002
0x00000003 0x00000003 0x00000003 0x00000003 0x00000003 0x00000004 0x00000004 0x00000004
0x00000004 0x00000005 0x00000005 0x00000005 0x00000005 0x00000006 0x00000006 0x00000006
0x00000006 0x00000007 0x00000007 0x00000007 0x00000008 0x00000008 0x00000008 0x00000009
0x00000009 0x00000009 0x0000000a 0x0000000a 0x0000000b 0x0000000b 0x0000000b 0x0000000c
0x0000000c 0x0000000d 0x0000000d 0x0000000d 0x0000000e 0x0000000e 0x0000000f 0x0000000f
0x00000010 0x00000010 0x00000011 0x00000011 0x00000012 0x00000012 0x00000013 0x00000013
0x00000014 0x00000014 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018
0x00000019 0x00000019 0x0000001a 0x0000001a 0x0000001b 0x0000001c 0x0000001c 0x0000001d
0x0000001e 0x0000001e 0x0000001f 0x00000020 0x00000021 0x00000021 0x00000022 0x00000023
0x00000023 0x00000024 0x00000025 0x00000026 0x00000027 0x00000027 0x00000028 0x00000029
0x0000002a 0x0000002b 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030
0x00000031 0x00000031 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037
0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f
0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047
0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004e 0x0000004f 0x00000051
0x00000052 0x00000053 0x00000054 0x00000055 0x00000057 0x00000058 0x00000059 0x0000005a
0x0000005b 0x0000005d 0x0000005e 0x0000005f 0x00000061 0x00000062 0x00000063 0x00000064
0x00000066 0x00000067 0x00000069 0x0000006a 0x0000006b 0x0000006d 0x0000006e 0x0000006f
0x00000071 0x00000072 0x00000074 0x00000075 0x00000077 0x00000078 0x00000079 0x0000007b
0x0000007c 0x0000007e 0x0000007f 0x00000081 0x00000082 0x00000084 0x00000085 0x00000087
0x00000089 0x0000008a 0x0000008c 0x0000008d 0x0000008f 0x00000091 0x00000092 0x00000094
0x00000095 0x00000097 0x00000099 0x0000009a 0x0000009c 0x0000009e 0x0000009f 0x000000a1
0x000000a3 0x000000a5 0x000000a6 0x000000a8 0x000000aa 0x000000ac 0x000000ad 0x000000af
0x000000b1 0x000000b3 0x000000b5 0x000000b6 0x000000b8 0x000000ba 0x000000bc 0x000000be
0x000000c0 0x000000c2 0x000000c4 0x000000c5 0x000000c7 0x000000c9 0x000000cb 0x000000cd
0x000000cf 0x000000d1 0x000000d3 0x000000d5 0x000000d7 0x000000d9 0x000000db 0x000000dd
0x000000df 0x000000e1 0x000000e3 0x000000e5 0x000000e7 0x000000ea 0x000000ec 0x000000ee
0x000000f0 0x000000f2 0x000000f4 0x000000f6 0x000000f8 0x000000fb 0x000000fd 0x000000ff>;
cabc-gamma-base = <
/*gamma = 2.2*/
0x00010000 0x0000fdd0 0x0000fba8 0x0000f986 0x0000f76a 0x0000f556 0x0000f347 0x0000f140
0x0000ef3e 0x0000ed43 0x0000eb4e 0x0000e95e 0x0000e775 0x0000e592 0x0000e3b4 0x0000e1dc
0x0000e009 0x0000de3c 0x0000dc74 0x0000dab2 0x0000d8f4 0x0000d73c 0x0000d589 0x0000d3db
0x0000d232 0x0000d08d 0x0000ceee 0x0000cd53 0x0000cbbc 0x0000ca2b 0x0000c89d 0x0000c714
0x0000c590 0x0000c410 0x0000c294 0x0000c11c 0x0000bfa8 0x0000be39 0x0000bccd 0x0000bb65
0x0000ba01 0x0000b8a1 0x0000b745 0x0000b5ed 0x0000b498 0x0000b347 0x0000b1f9 0x0000b0af
0x0000af68 0x0000ae25 0x0000ace5 0x0000aba8 0x0000aa6f 0x0000a939 0x0000a806 0x0000a6d7
0x0000a5aa 0x0000a480 0x0000a35a 0x0000a236 0x0000a116 0x00009ff8 0x00009edd 0x00009dc5
0x00009cb0 0x00009b9e 0x00009a8e 0x00009981 0x00009877 0x0000976f 0x0000966a 0x00009567
0x00009467 0x0000936a 0x0000926f 0x00009176 0x00009080 0x00008f8c 0x00008e9a 0x00008dab
0x00008cbe 0x00008bd3 0x00008aea 0x00008a04 0x00008920 0x0000883e 0x0000875e 0x00008680
0x000085a4 0x000084ca 0x000083f3 0x0000831d 0x00008249 0x00008177 0x000080a7 0x00007fd9
0x00007f0d 0x00007e42 0x00007d7a 0x00007cb3 0x00007bee 0x00007b2b 0x00007a6a 0x000079aa
0x000078ec 0x0000782f 0x00007775 0x000076bc 0x00007604 0x0000754f 0x0000749a 0x000073e8
0x00007337 0x00007287 0x000071d9 0x0000712c 0x00007081 0x00006fd8 0x00006f30 0x00006e89
0x00006de4 0x00006d40 0x00006c9d 0x00006bfc 0x00006b5c 0x00006abe 0x00006a21 0x00006985
0x000068ea 0x00006851 0x000067b9 0x00006722 0x0000668d 0x000065f9 0x00006566 0x000064d4
0x00006443 0x000063b4 0x00006325 0x00006298 0x0000620c 0x00006181 0x000060f8 0x0000606f
0x00005fe7 0x00005f61 0x00005edb 0x00005e57 0x00005dd4 0x00005d51 0x00005cd0 0x00005c50
0x00005bd1 0x00005b52 0x00005ad5 0x00005a59 0x000059de 0x00005963 0x000058ea 0x00005871
0x000057fa 0x00005783 0x0000570d 0x00005699 0x00005625 0x000055b2 0x0000553f 0x000054ce
0x0000545d 0x000053ee 0x0000537f 0x00005311 0x000052a4 0x00005238 0x000051cc 0x00005161
0x000050f7 0x0000508e 0x00005026 0x00004fbe 0x00004f57 0x00004ef1 0x00004e8c 0x00004e27
0x00004dc3 0x00004d60 0x00004cfe 0x00004c9c 0x00004c3b 0x00004bdb 0x00004b7b 0x00004b1c
0x00004abe 0x00004a60 0x00004a03 0x000049a7 0x0000494b 0x000048f0 0x00004896 0x0000483c
0x000047e3 0x0000478a 0x00004733 0x000046db 0x00004685 0x0000462f 0x000045d9 0x00004584
0x00004530 0x000044dc 0x00004489 0x00004437 0x000043e5 0x00004393 0x00004342 0x000042f2
0x000042a2 0x00004253 0x00004204 0x000041b6 0x00004169 0x0000411b 0x000040cf 0x00004083
0x00004037 0x00003fec 0x00003fa1 0x00003f57 0x00003f0e 0x00003ec5 0x00003e7c 0x00003e34
0x00003dec 0x00003da5 0x00003d5e 0x00003d18 0x00003cd2 0x00003c8c 0x00003c48 0x00003c03
0x00003bbf 0x00003b7b 0x00003b38 0x00003af5 0x00003ab3 0x00003a71 0x00003a30 0x000039ef
0x000039ae 0x0000396e 0x0000392e 0x000038ee 0x000038af 0x00003871 0x00003832 0x000037f5>;
};
};

129
include/dt-bindings/display/screen-timing/lcd-lq070m1sx01-mipi.dtsi
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@ -1,129 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2014 ROCKCHIP, Inc.
* arch/arm/boot/dts/lcd-lq070m1sx01-mipi.dtsi
* author: libing@rock-chips.com
* create date: 2014-04-15
* lcd model: lq070m1sx01
* resolution: 1920 X 1200
* mipi channel: dual
*/
/* about mipi */
disp_mipi_init: mipi_dsi_init{
compatible = "rockchip,mipi_dsi_init";
rockchip,screen_init = <1>;
rockchip,dsi_lane = <2>;
rockchip,dsi_hs_clk = <1000>;
rockchip,mipi_dsi_num = <2>;
};
disp_mipi_power_ctr: mipi_power_ctr {
compatible = "rockchip,mipi_power_ctr";
mipi_lcd_rst:mipi_lcd_rst{
compatible = "rockchip,lcd_rst";
rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
mipi_lcd_en:mipi_lcd_en {
compatible = "rockchip,lcd_en";
rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
};
disp_mipi_init_cmds: screen-on-cmds {
rockchip,cmd_debug = <0>;
compatible = "rockchip,screen-on-cmds";
rockchip,on-cmds1 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xb0 0x02>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds2 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xb1 0x21>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds3 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xb0 0x06>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds4 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xb1 0x21>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds5 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xb4 0x15>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds6 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xb9 0x40>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds7 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0xb0 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds8 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x05 dcs_set_display_on>;
rockchip,cmd_delay = <10>;
};
rockchip,on-cmds9 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,data_type = <DATA_TYPE_DCS>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x05 dcs_exit_sleep_mode>;
rockchip,cmd_delay = <10>;
};
};
disp_timings: display-timings {
native-mode = <&timing0>;
compatible = "rockchip,display-timings";
timing0: timing0 {
screen-type = <SCREEN_DUAL_MIPI>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_P888>;
clock-frequency = <150000000>;
hactive = <1200>;
vactive = <1920>;
hsync-len = <8>;
hback-porch = <32>;
hfront-porch = <156>;
vsync-len = <2>;
vback-porch = <6>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};

170
include/dt-bindings/display/screen-timing/lcd-ls055r1sx04-mipi.dtsi
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@ -1,170 +0,0 @@
/*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* include/dt-bindings/display/screen-timing/lcd-ls055r1sx04-mipi.dtsi
* author: xbl@rock-chips.com
* create date: 2016-05-16
* lcd model: sharp ls055r1sx04
* resolution: 1440 * 2560
* mipi channel: double
*/
/* about mipi */
disp_mipi_init: mipi_dsi_init{
compatible = "rockchip,mipi_dsi_init";
rockchip,screen_init = <1>;
rockchip,dsi_lane = <4>;
rockchip,dsi_hs_clk = <850>;
rockchip,mipi_dsi_num = <2>;
};
disp_mipi_power_ctr: mipi_power_ctr {
compatible = "rockchip,mipi_power_ctr";
/* mipi_lcd_rst:mipi_lcd_rst{
compatible = "rockchip,lcd_rst";
rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_LOW>;
rockchip,delay = <100>;
};
mipi_lcd_en:mipi_lcd_en {
compatible = "rockchip,lcd_en";
rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>;
rockchip,delay = <100>;
};
*/
};
disp_mipi_init_cmds: screen-on-cmds {
compatible = "rockchip,screen-on-cmds";
rockchip,cmd_debug = <1>;
rockchip,on-cmds1 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xb0 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds2 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xd6 0x01>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds3 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xb3 0x18>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds4 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x39 0x51 0xff>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds5 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x39 0x53 0x0c>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds6 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x39 0x35 0x00>;
rockchip,cmd_delay = <0>;
};
/*
rockchip,on-cmds7 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xb0 0x03>;
rockchip,cmd_delay = <0>;
};
*/
rockchip,on-cmds7 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x05 dcs_set_display_on>;
rockchip,cmd_delay = <10>;
};
rockchip,on-cmds8 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x05 dcs_exit_sleep_mode>;
rockchip,cmd_delay = <10>;
};
};
disp_timings: display-timings {
native-mode = <&timing0>;
compatible = "rockchip,display-timings";
timing0: timing0 {
screen-type = <SCREEN_DUAL_MIPI>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_P888>;
clock-frequency = <245000000>;
hactive = <1440>;
vactive = <2560>;
hback-porch = <40>;
hfront-porch = <100>;
vback-porch = <3>;
vfront-porch = <4>;
hsync-len = <6>;
vsync-len = <1>;
screen-width = <68>;
screen-hight = <120>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};

288
include/dt-bindings/display/screen-timing/lcd-mipi-RK055AUWI5003-1440X2560.dtsi
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@ -1,288 +0,0 @@
/*
*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
* author: lyx@rock-chips.com
* create date: 2016-04-05
* resolution: 1440 X 2560
* mipi channel: single
*/
/* about mipi */
disp_mipi_init: mipi_dsi_init{
compatible = "rockchip,mipi_dsi_init";
rockchip,screen_init = <1>;
rockchip,dsi_lane = <4>;
rockchip,dsi_hs_clk = <1000>;
rockchip,mipi_dsi_num = <2>;
};
disp_mipi_power_ctr: mipi_power_ctr {
compatible = "rockchip,mipi_power_ctr";
/*
mipi_lcd_rst:mipi_lcd_rst {
compatible = "rockchip,lcd_rst";
rockchip,gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
rockchip,delay = <100>;
};
mipi_lcd_en:mipi_lcd_en {
compatible = "rockchip,lcd_en";
rockchip,gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
rockchip,delay = <20>;
};
*/
};
disp_mipi_init_cmds: screen-on-cmds {
rockchip,cmd_debug = <0>;
compatible = "rockchip,screen-on-cmds";
rockchip,on-cmds1 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x23 0xb0 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds2 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x23 0xd6 0x01>;
rockchip,cmd_delay = <120>;
};
rockchip,on-cmds3 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xb3 0x18 0x00 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds4 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x23 0xb4 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds5 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xb6 0x3a 0xd3>;
rockchip,cmd_delay = <20>;
};
rockchip,on-cmds6 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x23 0xbe 0x04>;
rockchip,cmd_delay = <120>;
};
rockchip,on-cmds7 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xc3 0x00 0x00 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds8 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x23 0xc5 0x00>;
rockchip,cmd_delay = <20>;
};
rockchip,on-cmds9 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xc0 0x00 0x00 0x00 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds10 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xc1 0x00 0x61 0x00 0x30 0x29 0x10 0x19 0x63 0x61 0xb4 0xe6 0xdc 0x7b 0xef 0x39 0xd7 0xda 0x08 0x8c 0xb1 0x08 0x54 0x82 0x00 0x00 0x00 0x00 0x00 0x02 0x63 0x27 0x03 0x00 0xff 0x11>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds11 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xc2 0x08 0x0a 0x00 0x04 0x04 0xf0 0x00 0x04>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds12 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xc4 0x70 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x05 0x01>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds13 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xc6 0x5a 0x00 0x2d 0x03 0x01 0x02 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0x15 0x08 0x5a>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds14 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xcb 0xff 0xff 0xff 0xff 0x00 0x00 0x00 0x00 0x54 0xe0 0x07 0x2a 0xe0 0x00 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds15 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x23 0xcc 0x32>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds16 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xd7 0x82 0xff 0x21 0x8e 0x8c 0xf1 0x87 0x3f 0x7e 0x10 0x00 0x00 0x8f>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds17 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xd9 0x00 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds18 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xd0 0x11 0x17 0x14 0xfd>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds19 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xd2 0xcd 0x2b 0x2b 0x33 0x12 0x33 0x33 0x33 0x77 0x77 0x33 0x33 0x33 0x00 0x00 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds20 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xd5 0x06 0x00 0x00 0x01 0x40 0x01 0x40>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds21 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xc7 0x00 0x10 0x17 0x21 0x2f 0x3d 0x48 0x58 0x3c 0x44 0x50 0x5d 0x66 0x6c 0x75 0x00 0x10 0x17 0x21 0x2f 0x3d 0x48 0x58 0x3c 0x44 0x50 0x5d 0x66 0x6c 0x75>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds22 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x05 0x29>;
rockchip,cmd_delay = <120>;
};
rockchip,on-cmds23 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x05 0x11>;
rockchip,cmd_delay = <100>;
};
};
disp_timings: display-timings {
native-mode = <&timing0>;
compatible = "rockchip,display-timings";
timing0: timing0 {
screen-type = <SCREEN_DUAL_MIPI>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_P888>;
clock-frequency = <245000000>;
hactive = <1440>;
vactive = <2560>;
hback-porch = <16>;
hfront-porch = <50>;
vback-porch = <20>;
vfront-porch = <20>;
hsync-len = <20>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
screen-width = <68>;
screen-hight = <120>;
};
};

34
include/dt-bindings/display/screen-timing/lcd-rk3128-86v-LVDS1024x600.dtsi
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@ -1,34 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* RockChip. LCD_LVDS1024x600 FOR rk3128-86V
*
*/
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen-type = <SCREEN_LVDS>;
lvds-format = <LVDS_8BIT_1>;
out-face = <OUT_P888>;
/* Min Typ Max Unit
* Clock Frequency fclk 44.9 51.2 63 MHz
*/
clock-frequency = <60000000>;
hactive = <1024>; /* Horizontal display area thd 1024 DCLK */
vactive = <600>; /* Vertical display area tvd 600 H */
hback-porch = <90>; /* HS Width +Back Porch 160 160 160 DCLK (Thw+ thbp)*/
hfront-porch = <160>; /* HS front porch thfp 16 160 216 DCLK */
vback-porch = <13>; /* VS front porch tvfp 1 12 127 H */
vfront-porch = <12>; /* VS Width+Back Porch 23 23 23 H (Tvw+ tvbp) */
hsync-len = <70>; /* HS Pulse Width thw 1 - 140 DCLK */
vsync-len = <10>; /* VS Pulse Width tvw 1 - 20 H */
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};

30
include/dt-bindings/display/screen-timing/lcd-td043mgeal.dtsi
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@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* RockChip. LCD_TD043MGEA1 FOR FPGA
*
*/
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen-type = <SCREEN_RGB>;
out-face = <OUT_P888>;
clock-frequency = <27000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <206>;
hfront-porch = <40>;
vback-porch = <25>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};

139
include/dt-bindings/display/screen-timing/lcd-tv080wum-mipi.dtsi
View File

@ -1,139 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2014 ROCKCHIP, Inc.
* arch/arm/boot/dts/lcd-lq070m1sx01-mipi.dtsi
* author: libing@rock-chips.com
* create date: 2014-04-15
* lcd model: ld089wu1
* resolution: 1920 X 1200
* mipi channel: single
*/
/* about mipi */
disp_mipi_init: mipi_dsi_init{
compatible = "rockchip,mipi_dsi_init";
rockchip,screen_init = <0>;
rockchip,dsi_lane = <4>;
rockchip,dsi_hs_clk = <1000>;
rockchip,mipi_dsi_num = <1>;
};
disp_mipi_power_ctr: mipi_power_ctr {
compatible = "rockchip,mipi_power_ctr";
/*mipi_lcd_rst:mipi_lcd_rst{
compatible = "rockchip,lcd_rst";
rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_LOW>;
rockchip,delay = <100>;
};
mipi_lcd_en:mipi_lcd_en {
compatible = "rockchip,lcd_en";
rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>;
rockchip,delay = <100>;
};*/
};
disp_mipi_init_cmds: screen-on-cmds {
compatible = "rockchip,screen-on-cmds";
/*rockchip,cmd_debug = <1>;
rockchip,on-cmds1 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <HSDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0xb0 0x02>;
rockchip,cmd_delay = <0>;
};
*/
};
disp_timings: display-timings {
native-mode = <&timing0>;
compatible = "rockchip,display-timings";
timing0: timing0 {
screen-type = <SCREEN_MIPI>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_P888>;
clock-frequency = <150000000>;
hactive = <1200>;
vactive = <1920>;
hback-porch = <80>;
hfront-porch = <81>;
vback-porch = <21>;
vfront-porch = <21>;
hsync-len = <10>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
cabc-lut = <
/*gamma = 2.2*/
0x00000383 0x00000392 0x000003a2 0x000003b2 0x000003c2 0x000003d2 0x000003e2 0x000003f3
0x00000403 0x00000414 0x00000425 0x00000436 0x00000447 0x00000458 0x0000046a 0x0000047b
0x0000048d 0x0000049f 0x000004b1 0x000004c3 0x000004d5 0x000004e8 0x000004fa 0x0000050d
0x00000520 0x00000533 0x00000546 0x0000055a 0x0000056d 0x00000581 0x00000595 0x000005a9
0x000005bd 0x000005d1 0x000005e5 0x000005fa 0x0000060f 0x00000624 0x00000639 0x0000064e
0x00000663 0x00000679 0x0000068e 0x000006a4 0x000006ba 0x000006d0 0x000006e6 0x000006fd
0x00000713 0x0000072a 0x00000741 0x00000758 0x0000076f 0x00000786 0x0000079e 0x000007b6
0x000007cd 0x000007e5 0x000007fd 0x00000816 0x0000082e 0x00000847 0x0000085f 0x00000878
0x00000891 0x000008ab 0x000008c4 0x000008de 0x000008f7 0x00000911 0x0000092b 0x00000945
0x00000960 0x0000097a 0x00000995 0x000009af 0x000009ca 0x000009e6 0x00000a01 0x00000a1c
0x00000a38 0x00000a54 0x00000a6f 0x00000a8c 0x00000aa8 0x00000ac4 0x00000ae1 0x00000afd
0x00000b1a 0x00000b37 0x00000b54 0x00000b72 0x00000b8f 0x00000bad 0x00000bcb 0x00000be9
0x00000c07 0x00000c25 0x00000c44 0x00000c62 0x00000c81 0x00000ca0 0x00000cbf 0x00000cdf
0x00000cfe 0x00000d1e 0x00000d3e 0x00000d5d 0x00000d7e 0x00000d9e 0x00000dbe 0x00000ddf
0x00000e00 0x00000e21 0x00000e42 0x00000e63 0x00000e84 0x00000ea6 0x00000ec8 0x00000eea
0x00000f0c 0x00000f2e 0x00000f50 0x00000f73 0x00000f96 0x00000fb9 0x00000fdc 0x00000fff
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
cabc-gamma-base = <
/*gamma = 2.2*/
0x00010000 0x0000fdd0 0x0000fba8 0x0000f986 0x0000f76a 0x0000f556 0x0000f347 0x0000f140
0x0000ef3e 0x0000ed43 0x0000eb4e 0x0000e95e 0x0000e775 0x0000e592 0x0000e3b4 0x0000e1dc
0x0000e009 0x0000de3c 0x0000dc74 0x0000dab2 0x0000d8f4 0x0000d73c 0x0000d589 0x0000d3db
0x0000d232 0x0000d08d 0x0000ceee 0x0000cd53 0x0000cbbc 0x0000ca2b 0x0000c89d 0x0000c714
0x0000c590 0x0000c410 0x0000c294 0x0000c11c 0x0000bfa8 0x0000be39 0x0000bccd 0x0000bb65
0x0000ba01 0x0000b8a1 0x0000b745 0x0000b5ed 0x0000b498 0x0000b347 0x0000b1f9 0x0000b0af
0x0000af68 0x0000ae25 0x0000ace5 0x0000aba8 0x0000aa6f 0x0000a939 0x0000a806 0x0000a6d7
0x0000a5aa 0x0000a480 0x0000a35a 0x0000a236 0x0000a116 0x00009ff8 0x00009edd 0x00009dc5
0x00009cb0 0x00009b9e 0x00009a8e 0x00009981 0x00009877 0x0000976f 0x0000966a 0x00009567
0x00009467 0x0000936a 0x0000926f 0x00009176 0x00009080 0x00008f8c 0x00008e9a 0x00008dab
0x00008cbe 0x00008bd3 0x00008aea 0x00008a04 0x00008920 0x0000883e 0x0000875e 0x00008680
0x000085a4 0x000084ca 0x000083f3 0x0000831d 0x00008249 0x00008177 0x000080a7 0x00007fd9
0x00007f0d 0x00007e42 0x00007d7a 0x00007cb3 0x00007bee 0x00007b2b 0x00007a6a 0x000079aa
0x000078ec 0x0000782f 0x00007775 0x000076bc 0x00007604 0x0000754f 0x0000749a 0x000073e8
0x00007337 0x00007287 0x000071d9 0x0000712c 0x00007081 0x00006fd8 0x00006f30 0x00006e89
0x00006de4 0x00006d40 0x00006c9d 0x00006bfc 0x00006b5c 0x00006abe 0x00006a21 0x00006985
0x000068ea 0x00006851 0x000067b9 0x00006722 0x0000668d 0x000065f9 0x00006566 0x000064d4
0x00006443 0x000063b4 0x00006325 0x00006298 0x0000620c 0x00006181 0x000060f8 0x0000606f
0x00005fe7 0x00005f61 0x00005edb 0x00005e57 0x00005dd4 0x00005d51 0x00005cd0 0x00005c50
0x00005bd1 0x00005b52 0x00005ad5 0x00005a59 0x000059de 0x00005963 0x000058ea 0x00005871
0x000057fa 0x00005783 0x0000570d 0x00005699 0x00005625 0x000055b2 0x0000553f 0x000054ce
0x0000545d 0x000053ee 0x0000537f 0x00005311 0x000052a4 0x00005238 0x000051cc 0x00005161
0x000050f7 0x0000508e 0x00005026 0x00004fbe 0x00004f57 0x00004ef1 0x00004e8c 0x00004e27
0x00004dc3 0x00004d60 0x00004cfe 0x00004c9c 0x00004c3b 0x00004bdb 0x00004b7b 0x00004b1c
0x00004abe 0x00004a60 0x00004a03 0x000049a7 0x0000494b 0x000048f0 0x00004896 0x0000483c
0x000047e3 0x0000478a 0x00004733 0x000046db 0x00004685 0x0000462f 0x000045d9 0x00004584
0x00004530 0x000044dc 0x00004489 0x00004437 0x000043e5 0x00004393 0x00004342 0x000042f2
0x000042a2 0x00004253 0x00004204 0x000041b6 0x00004169 0x0000411b 0x000040cf 0x00004083
0x00004037 0x00003fec 0x00003fa1 0x00003f57 0x00003f0e 0x00003ec5 0x00003e7c 0x00003e34
0x00003dec 0x00003da5 0x00003d5e 0x00003d18 0x00003cd2 0x00003c8c 0x00003c48 0x00003c03
0x00003bbf 0x00003b7b 0x00003b38 0x00003af5 0x00003ab3 0x00003a71 0x00003a30 0x000039ef
0x000039ae 0x0000396e 0x0000392e 0x000038ee 0x000038af 0x00003871 0x00003832 0x000037f5>;
};
};

179
include/dt-bindings/display/screen-timing/lcd-tv080wum-nl0-mipi.dtsi
View File

@ -1,179 +0,0 @@
/*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* include/dt-bindings/display/screen-timing/lcd-tv080wum-nl0-mipi.dtsi
* author: hjc@rock-chips.com
* create date: 2016-03-28
* lcd model: tv080wum-n10
* resolution: 1200 * 1920
* mipi channel: single
*/
/* about mipi */
disp_mipi_init: mipi_dsi_init{
compatible = "rockchip,mipi_dsi_init";
rockchip,screen_init = <0>;
rockchip,dsi_lane = <4>;
rockchip,dsi_hs_clk = <1200>;
rockchip,mipi_dsi_num = <1>;
};
disp_mipi_power_ctr: mipi_power_ctr {
compatible = "rockchip,mipi_power_ctr";
/* mipi_lcd_rst:mipi_lcd_rst{
compatible = "rockchip,lcd_rst";
rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_LOW>;
rockchip,delay = <100>;
};
mipi_lcd_en:mipi_lcd_en {
compatible = "rockchip,lcd_en";
rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>;
rockchip,delay = <100>;
};
*/
};
disp_mipi_init_cmds: screen-on-cmds {
compatible = "rockchip,screen-on-cmds";
/* rockchip,cmd_debug = <1>;
rockchip,on-cmds1 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <HSDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0xb0 0x02>;
rockchip,cmd_delay = <0>;
};
*/
};
disp_timings: display-timings {
native-mode = <&timing0>;
compatible = "rockchip,display-timings";
timing0: timing0 {
screen-type = <SCREEN_MIPI>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_P888>;
clock-frequency = <160000000>;
hactive = <1200>;
vactive = <1920>;
hback-porch = <21>;
hfront-porch = <120>;
vback-porch = <18>;
vfront-porch = <21>;
hsync-len = <20>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
cabc-lut = <
/*gamma = 2.2*/
0x00000383 0x00000392 0x000003a2 0x000003b2 0x000003c2 0x000003d2 0x000003e2 0x000003f3
0x00000403 0x00000414 0x00000425 0x00000436 0x00000447 0x00000458 0x0000046a 0x0000047b
0x0000048d 0x0000049f 0x000004b1 0x000004c3 0x000004d5 0x000004e8 0x000004fa 0x0000050d
0x00000520 0x00000533 0x00000546 0x0000055a 0x0000056d 0x00000581 0x00000595 0x000005a9
0x000005bd 0x000005d1 0x000005e5 0x000005fa 0x0000060f 0x00000624 0x00000639 0x0000064e
0x00000663 0x00000679 0x0000068e 0x000006a4 0x000006ba 0x000006d0 0x000006e6 0x000006fd
0x00000713 0x0000072a 0x00000741 0x00000758 0x0000076f 0x00000786 0x0000079e 0x000007b6
0x000007cd 0x000007e5 0x000007fd 0x00000816 0x0000082e 0x00000847 0x0000085f 0x00000878
0x00000891 0x000008ab 0x000008c4 0x000008de 0x000008f7 0x00000911 0x0000092b 0x00000945
0x00000960 0x0000097a 0x00000995 0x000009af 0x000009ca 0x000009e6 0x00000a01 0x00000a1c
0x00000a38 0x00000a54 0x00000a6f 0x00000a8c 0x00000aa8 0x00000ac4 0x00000ae1 0x00000afd
0x00000b1a 0x00000b37 0x00000b54 0x00000b72 0x00000b8f 0x00000bad 0x00000bcb 0x00000be9
0x00000c07 0x00000c25 0x00000c44 0x00000c62 0x00000c81 0x00000ca0 0x00000cbf 0x00000cdf
0x00000cfe 0x00000d1e 0x00000d3e 0x00000d5d 0x00000d7e 0x00000d9e 0x00000dbe 0x00000ddf
0x00000e00 0x00000e21 0x00000e42 0x00000e63 0x00000e84 0x00000ea6 0x00000ec8 0x00000eea
0x00000f0c 0x00000f2e 0x00000f50 0x00000f73 0x00000f96 0x00000fb9 0x00000fdc 0x00000fff
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
cabc-gamma-base = <
/*gamma = 2.2*/
0x00010000 0x0000fdd0 0x0000fba8 0x0000f986 0x0000f76a 0x0000f556 0x0000f347 0x0000f140
0x0000ef3e 0x0000ed43 0x0000eb4e 0x0000e95e 0x0000e775 0x0000e592 0x0000e3b4 0x0000e1dc
0x0000e009 0x0000de3c 0x0000dc74 0x0000dab2 0x0000d8f4 0x0000d73c 0x0000d589 0x0000d3db
0x0000d232 0x0000d08d 0x0000ceee 0x0000cd53 0x0000cbbc 0x0000ca2b 0x0000c89d 0x0000c714
0x0000c590 0x0000c410 0x0000c294 0x0000c11c 0x0000bfa8 0x0000be39 0x0000bccd 0x0000bb65
0x0000ba01 0x0000b8a1 0x0000b745 0x0000b5ed 0x0000b498 0x0000b347 0x0000b1f9 0x0000b0af
0x0000af68 0x0000ae25 0x0000ace5 0x0000aba8 0x0000aa6f 0x0000a939 0x0000a806 0x0000a6d7
0x0000a5aa 0x0000a480 0x0000a35a 0x0000a236 0x0000a116 0x00009ff8 0x00009edd 0x00009dc5
0x00009cb0 0x00009b9e 0x00009a8e 0x00009981 0x00009877 0x0000976f 0x0000966a 0x00009567
0x00009467 0x0000936a 0x0000926f 0x00009176 0x00009080 0x00008f8c 0x00008e9a 0x00008dab
0x00008cbe 0x00008bd3 0x00008aea 0x00008a04 0x00008920 0x0000883e 0x0000875e 0x00008680
0x000085a4 0x000084ca 0x000083f3 0x0000831d 0x00008249 0x00008177 0x000080a7 0x00007fd9
0x00007f0d 0x00007e42 0x00007d7a 0x00007cb3 0x00007bee 0x00007b2b 0x00007a6a 0x000079aa
0x000078ec 0x0000782f 0x00007775 0x000076bc 0x00007604 0x0000754f 0x0000749a 0x000073e8
0x00007337 0x00007287 0x000071d9 0x0000712c 0x00007081 0x00006fd8 0x00006f30 0x00006e89
0x00006de4 0x00006d40 0x00006c9d 0x00006bfc 0x00006b5c 0x00006abe 0x00006a21 0x00006985
0x000068ea 0x00006851 0x000067b9 0x00006722 0x0000668d 0x000065f9 0x00006566 0x000064d4
0x00006443 0x000063b4 0x00006325 0x00006298 0x0000620c 0x00006181 0x000060f8 0x0000606f
0x00005fe7 0x00005f61 0x00005edb 0x00005e57 0x00005dd4 0x00005d51 0x00005cd0 0x00005c50
0x00005bd1 0x00005b52 0x00005ad5 0x00005a59 0x000059de 0x00005963 0x000058ea 0x00005871
0x000057fa 0x00005783 0x0000570d 0x00005699 0x00005625 0x000055b2 0x0000553f 0x000054ce
0x0000545d 0x000053ee 0x0000537f 0x00005311 0x000052a4 0x00005238 0x000051cc 0x00005161
0x000050f7 0x0000508e 0x00005026 0x00004fbe 0x00004f57 0x00004ef1 0x00004e8c 0x00004e27
0x00004dc3 0x00004d60 0x00004cfe 0x00004c9c 0x00004c3b 0x00004bdb 0x00004b7b 0x00004b1c
0x00004abe 0x00004a60 0x00004a03 0x000049a7 0x0000494b 0x000048f0 0x00004896 0x0000483c
0x000047e3 0x0000478a 0x00004733 0x000046db 0x00004685 0x0000462f 0x000045d9 0x00004584
0x00004530 0x000044dc 0x00004489 0x00004437 0x000043e5 0x00004393 0x00004342 0x000042f2
0x000042a2 0x00004253 0x00004204 0x000041b6 0x00004169 0x0000411b 0x000040cf 0x00004083
0x00004037 0x00003fec 0x00003fa1 0x00003f57 0x00003f0e 0x00003ec5 0x00003e7c 0x00003e34
0x00003dec 0x00003da5 0x00003d5e 0x00003d18 0x00003cd2 0x00003c8c 0x00003c48 0x00003c03
0x00003bbf 0x00003b7b 0x00003b38 0x00003af5 0x00003ab3 0x00003a71 0x00003a30 0x000039ef
0x000039ae 0x0000396e 0x0000392e 0x000038ee 0x000038af 0x00003871 0x00003832 0x000037f5>;
};
};

74
include/dt-bindings/display/screen-timing/lcd-vga.dtsi
View File

@ -1,74 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* RockChip. VGA timing
*
*/
disp_timings: display-timings {
native-mode = <&timing1>;
timing0: timing0 {
screen-type = <SCREEN_RGB>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_D888_P666>;
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <160>;
hfront-porch = <24>;
vback-porch = <29>;
vfront-porch = <3>;
hsync-len = <136>;
vsync-len = <6>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
timing1: timing1 {
screen-type = <SCREEN_RGB>;
out-face = <OUT_D888_P666>;
lvds-format = <LVDS_8BIT_2>;
clock-frequency = <88750000>;
hactive = <1440>;
vactive = <900>;
hback-porch = <80>;
hfront-porch = <48>;
vback-porch = <17>;
vfront-porch = <3>;
hsync-len = <32>;
vsync-len = <6>;
hsync-active = <1>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
timing2: timing2 {
screen-type = <SCREEN_RGB>;
out-face = <OUT_D888_P666>;
lvds-format = <LVDS_8BIT_2>;
clock-frequency = <106500000>;
hactive = <1440>;
vactive = <900>;
hback-porch = <232>;
hfront-porch = <80>;
vback-porch = <25>;
vfront-porch = <3>;
hsync-len = <152>;
vsync-len = <6>;
hsync-active = <0>;
vsync-active = <1>;
de-active = <0>;
pixelclk-active = <1>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};

205
include/dt-bindings/display/screen-timing/lcd-wqxga-mipi.dtsi
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@ -1,205 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2014 ROCKCHIP, Inc.
* arch/arm/boot/dts/lcd-lq070m1sx01-mipi.dtsi
* author: libing@rock-chips.com
* create date: 2014-04-15
* lcd model: wqxga
* resolution: 2560 X 1600
* mipi channel: dual
*/
/* about mipi */
disp_mipi_init: mipi_dsi_init{
compatible = "rockchip,mipi_dsi_init";
rockchip,screen_init = <1>;
rockchip,dsi_lane = <4>;
rockchip,dsi_hs_clk = <940>;
rockchip,mipi_dsi_num = <2>;
};
disp_mipi_power_ctr: mipi_power_ctr {
compatible = "rockchip,mipi_power_ctr";
mipi_lcd_rst:mipi_lcd_rst{
compatible = "rockchip,lcd_rst";
rockchip,gpios = <&gpio7 GPIO_B2 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
mipi_lcd_en:mipi_lcd_en {
compatible = "rockchip,lcd_en";
rockchip,gpios = <&gpio6 GPIO_A7 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
};
disp_mipi_init_cmds: screen-on-cmds {
rockchip,cmd_debug = <0>;
compatible = "rockchip,screen-on-cmds";
rockchip,on-cmds1 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x05 0x01>; //set soft reset
rockchip,cmd_delay = <10>;
};
rockchip,on-cmds2 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x05 0x01>; //set soft reset
rockchip,cmd_delay = <10>;
};
rockchip,on-cmds3 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x3a 0x77>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds4 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x39 0x2a 0x00 0x00 0x04 0xff>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds5 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x39 0x2b 0x00 0x00 0x06 0x3f>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds6 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x15 0x35 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds7 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <0>;
rockchip,cmd = <0x39 0x44 0x00 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds8 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x51 0xff>; //0xff
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds9 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x53 0x04>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds10 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x51 0xff>; //0xff
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds11 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x53 0x04>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds12 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x15 0x55 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds13 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x05 dcs_exit_sleep_mode>;
rockchip,cmd_delay = <120>;
};
rockchip,on-cmds14 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x23 0xb0 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds15 { //video
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xb3 0x1c>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds16 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x29 0xce 0x7d 0x40 0x48 0x56 0x67 0x78 0x88 0x98 0xa7 0xb5 0xc3 0xd1 0xde 0xe9 0xf2 0xfa 0xff 0x04 0x00>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds17 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x23 0xb0 0x03>;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds18 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x39 0x2c >;
rockchip,cmd_delay = <0>;
};
rockchip,on-cmds19 {
compatible = "rockchip,on-cmds";
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x05 dcs_set_display_on>;
rockchip,cmd_delay = <10>;
};
};
disp_timings: display-timings {
native-mode = <&timing0>;
compatible = "rockchip,display-timings";
timing0: timing0 {
screen-type = <SCREEN_DUAL_MIPI>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_P888>;
clock-frequency = <265000000>;
hactive = <2560>;
vactive = <1600>;
hsync-len = <38>;//19
hback-porch = <40>;//40
hfront-porch = <108>;//123
vsync-len = <4>;
vback-porch = <4>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};

30
include/dt-bindings/display/screen-timing/lcd-y81349.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* RockChip. LCD_Y81349 FOR 86V
*
*/
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen-type = <SCREEN_RGB>;
out-face = <OUT_P666>;
clock-frequency = <33000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <10>;
hfront-porch = <210>;
vback-porch = <10>;
vfront-porch = <22>;
hsync-len = <30>;
vsync-len = <13>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};

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include/linux/rk_fb.h
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/* drivers/video/rk_fb.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_RK30_FB_H
#define __ARCH_ARM_MACH_RK30_FB_H
#include <linux/fb.h>
#include <linux/platform_device.h>
#include <linux/completion.h>
#include <linux/spinlock.h>
#include <asm/atomic.h>
#include <linux/rk_screen.h>
#if defined(CONFIG_OF)
#include <dt-bindings/display/rk_fb.h>
#endif
#include "../../drivers/staging/android/sw_sync.h"
#include <linux/file.h>
#include <linux/kthread.h>
#include <linux/pm_runtime.h>
#include <linux/version.h>
#define RK30_MAX_LCDC_SUPPORT 2
#define RK30_MAX_LAYER_SUPPORT 5
#define RK_MAX_FB_SUPPORT 5
#define RK_WIN_MAX_AREA 4
#define RK_MAX_BUF_NUM 11
#define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
#define FB0_IOCTL_SET_PANEL 0x6002
#ifdef CONFIG_FB_WIMO
#define FB_WIMO_FLAG
#endif
#ifdef FB_WIMO_FLAG
#define FB0_IOCTL_SET_BUF 0x6017
#define FB0_IOCTL_COPY_CURBUF 0x6018
#define FB0_IOCTL_CLOSE_BUF 0x6019
#endif
#define RK_FBIOGET_PANEL_SIZE 0x5001
#define RK_FBIOSET_YUV_ADDR 0x5002
#define RK_FBIOGET_SCREEN_STATE 0X4620
#define RK_FBIOGET_16OR32 0X4621
#define RK_FBIOGET_IDLEFBUff_16OR32 0X4622
#define RK_FBIOSET_COMPOSE_LAYER_COUNTS 0X4623
#define RK_FBIOSET_HWC_ADDR 0x4624
#define RK_FBIOGET_DMABUF_FD 0x5003
#define RK_FBIOSET_DMABUF_FD 0x5004
#define RK_FB_IOCTL_SET_I2P_ODD_ADDR 0x5005
#define RK_FB_IOCTL_SET_I2P_EVEN_ADDR 0x5006
#define RK_FBIOSET_OVERLAY_STA 0x5018
#define RK_FBIOGET_OVERLAY_STA 0X4619
#define RK_FBIOSET_ENABLE 0x5019
#define RK_FBIOGET_ENABLE 0x5020
#define RK_FBIOSET_CONFIG_DONE 0x4628
#define RK_FBIOSET_VSYNC_ENABLE 0x4629
#define RK_FBIOPUT_NUM_BUFFERS 0x4625
#define RK_FBIOPUT_COLOR_KEY_CFG 0x4626
#define RK_FBIOGET_DSP_ADDR 0x4630
#define RK_FBIOGET_LIST_STA 0X4631
#define RK_FBIOGET_IOMMU_STA 0x4632
#define RK_FBIOSET_CLEAR_FB 0x4633
/**rk fb events**/
#define RK_LF_STATUS_FC 0xef
#define RK_LF_STATUS_FR 0xee
#define RK_LF_STATUS_NC 0xfe
#define RK_LF_MAX_TIMEOUT (1600000UL << 6) //>0.64s
/**
* pixel align value for gpu,align as 64 bytes in an odd number of times
*/
#define ALIGN_PIXEL_64BYTE_RGB565 32 /* 64/2*/
#define ALIGN_PIXEL_64BYTE_RGB8888 16 /* 64/4*/
#define ALIGN_N_TIMES(x, align) (((x) % (align) == 0) ? (x) : (((x) + ((align) - 1)) & (~((align) - 1))))
#define ALIGN_ODD_TIMES(x, align) (((x) % ((align) * 2) == 0) ? ((x) + (align)) : (x))
#define ALIGN_64BYTE_ODD_TIMES(x, align) ALIGN_ODD_TIMES(ALIGN_N_TIMES(x, align), align)
#define DUMP_FRAME_NUM 3
//#define USE_ION_MMU 1
#if defined(CONFIG_ION_ROCKCHIP)
extern struct ion_client *rockchip_ion_client_create(const char *name);
#endif
extern int rk_fb_poll_prmry_screen_vblank(void);
extern u32 rk_fb_get_prmry_screen_ft(void);
extern u32 rk_fb_get_prmry_screen_vbt(void);
extern u64 rk_fb_get_prmry_screen_framedone_t(void);
extern int rk_fb_set_prmry_screen_status(int status);
extern bool rk_fb_poll_wait_frame_complete(void);
enum {
CSC_BT601,
CSC_BT709,
CSC_BT2020,
};
#define CSC_SHIFT 6
#define CSC_MASK (0x3 << CSC_SHIFT)
#define CSC_FORMAT(x) (((x) & CSC_MASK) >> CSC_SHIFT)
#define BT601(x) ((CSC_BT601 << CSC_SHIFT) | ((x) & ~CSC_MASK))
#define BT709(x) ((CSC_BT709 << CSC_SHIFT) | ((x) & ~CSC_MASK))
#define BT2020(x) ((CSC_BT2020 << CSC_SHIFT) | ((x) & ~CSC_MASK))
enum {
SDR_DATA,
HDR_DATA,
};
/**
* pixel format definitions,this is copy from android/system/core/include/system/graphics.h
*/
enum {
HAL_PIXEL_FORMAT_RGBA_8888 = 1,
HAL_PIXEL_FORMAT_RGBX_8888 = 2,
HAL_PIXEL_FORMAT_RGB_888 = 3,
HAL_PIXEL_FORMAT_RGB_565 = 4,
HAL_PIXEL_FORMAT_BGRA_8888 = 5,
HAL_PIXEL_FORMAT_RGBA_5551 = 6,
HAL_PIXEL_FORMAT_RGBA_4444 = 7,
/* 0x8 - 0xFF range unavailable */
/*
* 0x100 - 0x1FF
*
* This range is reserved for pixel formats that are specific to the HAL
* implementation. Implementations can use any value in this range to
* communicate video pixel formats between their HAL modules. These formats
* must not have an alpha channel. Additionally, an EGLimage created from a
* gralloc buffer of one of these formats must be supported for use with the
* GL_OES_EGL_image_external OpenGL ES extension.
*/
/*
* Android YUV format:
*
* This format is exposed outside of the HAL to software decoders and
* applications. EGLImageKHR must support it in conjunction with the
* OES_EGL_image_external extension.
*
* YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed
* by (W/2) x (H/2) Cr and Cb planes.
*
* This format assumes
* - an even width
* - an even height
* - a horizontal stride multiple of 16 pixels
* - a vertical stride equal to the height
*
* y_size = stride * height
* c_size = ALIGN(stride/2, 16) * height/2
* size = y_size + c_size * 2
* cr_offset = y_size
* cb_offset = y_size + c_size
*
*/
HAL_PIXEL_FORMAT_YV12 = 0x32315659, // YCrCb 4:2:0 Planar
/* Legacy formats (deprecated), used by ImageFormat.java */
/*
* YCbCr format default is BT601.
*/
HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10, // NV16
HAL_PIXEL_FORMAT_YCrCb_420_SP = 0x11, // NV21
HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14, // YUY2
HAL_PIXEL_FORMAT_YCrCb_NV12 = 0x20, // YUY2
HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO = 0x21, // YUY2
HAL_PIXEL_FORMAT_YCrCb_NV12_10 = 0x22, // YUV420_1obit
HAL_PIXEL_FORMAT_YCbCr_422_SP_10 = 0x23, // YUV422_1obit
HAL_PIXEL_FORMAT_YCrCb_444_SP_10 = 0x24, //YUV444_1obit
HAL_PIXEL_FORMAT_YCrCb_444 = 0x25, //yuv444
HAL_PIXEL_FORMAT_FBDC_RGB565 = 0x26,
HAL_PIXEL_FORMAT_FBDC_U8U8U8U8 = 0x27, /*ARGB888*/
HAL_PIXEL_FORMAT_FBDC_U8U8U8 = 0x28, /*RGBP888*/
HAL_PIXEL_FORMAT_FBDC_RGBA888 = 0x29, /*ABGR888*/
HAL_PIXEL_FORMAT_BGRX_8888 = 0x30,
HAL_PIXEL_FORMAT_BGR_888 = 0x31,
HAL_PIXEL_FORMAT_BGR_565 = 0x32,
HAL_PIXEL_FORMAT_YUYV422 = 0x33,
HAL_PIXEL_FORMAT_YUYV420 = 0x34,
HAL_PIXEL_FORMAT_UYVY422 = 0x35,
HAL_PIXEL_FORMAT_UYVY420 = 0x36,
HAL_PIXEL_FORMAT_YCrCb_NV12_BT709 =
BT709(HAL_PIXEL_FORMAT_YCrCb_NV12),
HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO_BT709 =
BT709(HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO),
HAL_PIXEL_FORMAT_YCbCr_422_SP_BT709 =
BT709(HAL_PIXEL_FORMAT_YCbCr_422_SP),
HAL_PIXEL_FORMAT_YCrCb_444_BT709 =
BT709(HAL_PIXEL_FORMAT_YCrCb_444),
HAL_PIXEL_FORMAT_YCrCb_NV12_10_BT709 =
BT709(HAL_PIXEL_FORMAT_YCrCb_NV12_10),
HAL_PIXEL_FORMAT_YCbCr_422_SP_10_BT709 =
BT709(HAL_PIXEL_FORMAT_YCbCr_422_SP_10),
HAL_PIXEL_FORMAT_YCrCb_420_SP_10_BT709 =
BT709(HAL_PIXEL_FORMAT_YCrCb_444_SP_10),
HAL_PIXEL_FORMAT_YCrCb_NV12_10_BT2020 =
BT2020(HAL_PIXEL_FORMAT_YCrCb_NV12_10),
HAL_PIXEL_FORMAT_YCbCr_422_SP_10_BT2020 =
BT2020(HAL_PIXEL_FORMAT_YCbCr_422_SP_10),
HAL_PIXEL_FORMAT_YCrCb_420_SP_10_BT2020 =
BT2020(HAL_PIXEL_FORMAT_YCrCb_444_SP_10),
};
//display data format
enum data_format {
ARGB888,/*don't update and insert other format*/
RGB888, /*don't update and insert other format*/
RGB565, /*don't update and insert other format*/
BGR888,
XRGB888,
XBGR888,
ABGR888,
BGR565,
FBDC_RGB_565,
FBDC_ARGB_888,
FBDC_RGBX_888,
FBDC_ABGR_888,
YUV420,
YUV422,
YUV444,
YUV420_A,
YUV422_A,
YUV444_A,
YUV420_NV21,
YUYV422,
YUYV420,
UYVY422,
UYVY420
};
#define IS_YUV_FMT(fmt) ((fmt >= YUV420) ? 1 : 0)
#define IS_RGB_FMT(fmt) ((fmt < YUV420) ? 1 : 0)
#define IS_FBDC_FMT(fmt) \
(((fmt >= FBDC_RGB_565) && (fmt <= FBDC_ABGR_888)) ? 1 : 0)
enum
{
SCALE_NONE = 0x0,
SCALE_UP = 0x1,
SCALE_DOWN = 0x2
};
typedef enum {
BRIGHTNESS = 0x0,
CONTRAST = 0x1,
SAT_CON = 0x2
} bcsh_bcs_mode;
typedef enum {
H_SIN = 0x0,
H_COS = 0x1
} bcsh_hue_mode;
typedef enum {
SCREEN_PREPARE_DDR_CHANGE = 0x0,
SCREEN_UNPREPARE_DDR_CHANGE,
} screen_status;
typedef enum {
GET_PAGE_FAULT = 0x0,
CLR_PAGE_FAULT = 0x1,
UNMASK_PAGE_FAULT = 0x2,
UPDATE_CABC_PWM = 0x3,
SET_DSP_MIRROR = 0x4
} extern_func;
enum rk_vop_feature {
SUPPORT_VOP_IDENTIFY = BIT(0),
SUPPORT_IFBDC = BIT(1),
SUPPORT_AFBDC = BIT(2),
SUPPORT_WRITE_BACK = BIT(3),
SUPPORT_YUV420_OUTPUT = BIT(4)
};
struct rk_vop_property {
u32 feature;
u32 max_output_x;
u32 max_output_y;
};
enum rk_win_feature {
SUPPORT_WIN_IDENTIFY = BIT(0),
SUPPORT_HW_EXIST = BIT(1),
SUPPORT_SCALE = BIT(2),
SUPPORT_YUV = BIT(3),
SUPPORT_YUV10BIT = BIT(4),
SUPPORT_MULTI_AREA = BIT(5),
SUPPORT_HWC_LAYER = BIT(6)
};
struct rk_win_property {
u32 feature;
u32 max_input_x;
u32 max_input_y;
};
struct rk_fb_rgb {
struct fb_bitfield red;
struct fb_bitfield green;
struct fb_bitfield blue;
struct fb_bitfield transp;
};
struct rk_fb_frame_time {
u64 last_framedone_t;
u64 framedone_t;
u32 ft;
};
struct rk_fb_vsync {
wait_queue_head_t wait;
ktime_t timestamp;
int active;
bool irq_stop;
int irq_refcount;
struct mutex irq_lock;
struct task_struct *thread;
};
struct color_key_cfg {
u32 win0_color_key_cfg;
u32 win1_color_key_cfg;
u32 win2_color_key_cfg;
};
struct pwr_ctr {
char name[32];
int type;
int is_rst;
int gpio;
int atv_val;
const char *rgl_name;
int volt;
int delay;
};
struct rk_disp_pwr_ctr_list {
struct list_head list;
struct pwr_ctr pwr_ctr;
};
typedef enum _TRSP_MODE {
TRSP_CLOSE = 0,
TRSP_FMREG,
TRSP_FMREGEX,
TRSP_FMRAM,
TRSP_FMRAMEX,
TRSP_MASK,
TRSP_INVAL
} TRSP_MODE;
struct rk_lcdc_post_cfg {
u32 xpos;
u32 ypos;
u32 xsize;
u32 ysize;
};
struct rk_fb_wb_cfg {
u8 data_format;
short ion_fd;
u32 phy_addr;
u16 xsize;
u16 ysize;
u8 reserved0;
u32 reversed1;
};
struct rk_lcdc_bcsh {
bool enable;
u16 brightness;
u16 contrast;
u16 sat_con;
u16 sin_hue;
u16 cos_hue;
};
struct rk_lcdc_win_area {
bool state;
enum data_format format;
u8 data_space; /* SDR or HDR */
u8 fmt_cfg;
u8 yuyv_fmt;
u8 swap_rb;
u8 swap_uv;
u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
u16 ypos;
u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
u16 ysize;
u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
u16 yact;
u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
u16 yvir;
u16 xoff; /*mem offset*/
u16 yoff;
unsigned long smem_start;
unsigned long cbr_start; /*Cbr memory start address*/
#if defined(CONFIG_ION_ROCKCHIP)
struct ion_handle *ion_hdl;
int dma_buf_fd;
struct dma_buf *dma_buf;
#endif
u16 dsp_stx;
u16 dsp_sty;
u16 y_vir_stride;
u16 uv_vir_stride;
u32 y_addr;
u32 uv_addr;
u8 fbdc_en;
u8 fbdc_cor_en;
u8 fbdc_data_format;
u8 fbdc_dsp_width_ratio;
u8 fbdc_fmt_cfg;
u16 fbdc_mb_vir_width;
u16 fbdc_mb_vir_height;
u16 fbdc_mb_width;
u16 fbdc_mb_height;
u16 fbdc_mb_xst;
u16 fbdc_mb_yst;
u16 fbdc_num_tiles;
u16 fbdc_cmp_index_init;
};
struct rk_lcdc_win {
char name[5];
int id;
struct rk_win_property property;
bool state; /*on or off*/
bool last_state; /*on or off*/
u32 pseudo_pal[16];
int z_order; /*win sel layer*/
u8 fmt_10;
u8 colorspace;
u32 reserved;
u32 area_num;
u32 scale_yrgb_x;
u32 scale_yrgb_y;
u32 scale_cbcr_x;
u32 scale_cbcr_y;
bool support_3d;
u8 win_lb_mode;
u8 bic_coe_el;
u8 yrgb_hor_scl_mode;//h 01:scale up ;10:down
u8 yrgb_ver_scl_mode;//v 01:scale up ;10:down
u8 yrgb_hsd_mode;//h scale down mode
u8 yrgb_vsu_mode;//v scale up mode
u8 yrgb_vsd_mode;//v scale down mode
u8 cbr_hor_scl_mode;
u8 cbr_ver_scl_mode;
u8 cbr_hsd_mode;
u8 cbr_vsu_mode;
u8 cbr_vsd_mode;
u8 vsd_yrgb_gt4;
u8 vsd_yrgb_gt2;
u8 vsd_cbr_gt4;
u8 vsd_cbr_gt2;
u8 alpha_en;
u8 alpha_mode;
u16 g_alpha_val;
u32 color_key_val;
u8 csc_mode;
u8 xmirror;
u8 ymirror;
struct rk_lcdc_win_area area[RK_WIN_MAX_AREA];
struct rk_lcdc_post_cfg post_cfg;
};
struct rk_lcdc_driver;
struct rk_fb_trsm_ops {
int (*enable)(void);
int (*disable)(void);
int (*dsp_pwr_on) (void);
int (*dsp_pwr_off) (void);
void (*refresh)(unsigned int xpos, unsigned int ypos,
unsigned int xsize, unsigned int ysize);
};
struct rk_lcdc_drv_ops {
int (*open) (struct rk_lcdc_driver *dev_drv, int layer_id, bool open);
int (*win_direct_en)(struct rk_lcdc_driver *dev_drv, int win_id, int en);
int (*init_lcdc) (struct rk_lcdc_driver *dev_drv);
int (*ioctl) (struct rk_lcdc_driver *dev_drv, unsigned int cmd,
unsigned long arg, int layer_id);
int (*suspend) (struct rk_lcdc_driver *dev_drv);
int (*resume) (struct rk_lcdc_driver *dev_drv);
int (*blank) (struct rk_lcdc_driver *dev_drv, int layer_id,
int blank_mode);
int (*set_par) (struct rk_lcdc_driver *dev_drv, int layer_id);
int (*pan_display) (struct rk_lcdc_driver *dev_drv, int layer_id);
int (*direct_set_addr)(struct rk_lcdc_driver *drv, int win_id, u32 addr);
int (*lcdc_reg_update) (struct rk_lcdc_driver *dev_drv);
ssize_t(*get_disp_info) (struct rk_lcdc_driver *dev_drv, char *buf,
int layer_id);
int (*load_screen) (struct rk_lcdc_driver *dev_drv, bool initscreen);
int (*get_dspbuf_info) (struct rk_lcdc_driver *dev_drv,
u16 *xact, u16 *yact, int *format,
u32 *dsp_addr, int *ymirror);
int (*post_dspbuf)(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
int format, u16 xact, u16 yact, u16 xvir,
int ymirror);
int (*get_win_state) (struct rk_lcdc_driver *dev_drv, int layer_id, int area_id);
int (*ovl_mgr) (struct rk_lcdc_driver *dev_drv, int swap, bool set); /*overlay manager*/
int (*fps_mgr) (struct rk_lcdc_driver *dev_drv, int fps, bool set);
int (*fb_get_win_id) (struct rk_lcdc_driver *dev_drv, const char *id); /*find layer for fb*/
int (*fb_win_remap) (struct rk_lcdc_driver *dev_drv,
u16 fb_win_map_order);
int (*set_dsp_lut) (struct rk_lcdc_driver *dev_drv, int *lut);
int (*set_cabc_lut)(struct rk_lcdc_driver *dev_drv, int *lut);
int (*set_hwc_lut) (struct rk_lcdc_driver *dev_drv, int *hwc_lut, int mode);
int (*read_dsp_lut) (struct rk_lcdc_driver *dev_drv, int *lut);
int (*lcdc_hdmi_process) (struct rk_lcdc_driver *dev_drv, int mode); /*some lcdc need to some process in hdmi mode*/
int (*set_irq_to_cpu)(struct rk_lcdc_driver *dev_drv,int enable);
int (*poll_vblank) (struct rk_lcdc_driver *dev_drv);
int (*lcdc_rst) (struct rk_lcdc_driver *dev_drv);
int (*dpi_open) (struct rk_lcdc_driver *dev_drv, bool open);
int (*dpi_win_sel) (struct rk_lcdc_driver *dev_drv, int layer_id);
int (*dpi_status) (struct rk_lcdc_driver *dev_drv);
int (*get_dsp_addr)(struct rk_lcdc_driver *dev_drv, unsigned int dsp_addr[][4]);
int (*set_dsp_cabc) (struct rk_lcdc_driver *dev_drv, int mode, int calc, int up, int down, int global);
int (*set_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue);
int (*set_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value);
int (*get_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode);
int (*get_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode);
int (*open_bcsh)(struct rk_lcdc_driver *dev_drv, bool open);
int (*set_screen_scaler) (struct rk_lcdc_driver *dev_drv, struct rk_screen *screen, bool enable);
int (*dump_reg) (struct rk_lcdc_driver *dev_drv);
int (*mmu_en) (struct rk_lcdc_driver *dev_drv);
int (*cfg_done) (struct rk_lcdc_driver *dev_drv);
int (*set_overscan) (struct rk_lcdc_driver *dev_drv,
struct overscan *overscan);
int (*dsp_black) (struct rk_lcdc_driver *dev_drv, int enable);
int (*backlight_close)(struct rk_lcdc_driver *dev_drv, int enable);
int (*area_support_num)(struct rk_lcdc_driver *dev_drv, unsigned int *area_support);
int (*extern_func)(struct rk_lcdc_driver *dev_drv, int cmd);
int (*wait_frame_start)(struct rk_lcdc_driver *dev_drv, int enable);
int (*set_wb)(struct rk_lcdc_driver *dev_drv);
};
struct rk_fb_area_par {
u8 data_format; /*layer data fmt*/
short ion_fd;
u32 phy_addr;
short acq_fence_fd;
u16 x_offset;
u16 y_offset;
u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
u16 ypos;
u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
u16 ysize;
u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
u16 yact;
u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
u16 yvir;
u8 fbdc_en;
u8 fbdc_cor_en;
u8 fbdc_data_format;
u16 data_space; /* SDR or HDR */
u32 reserved0;
};
struct rk_fb_win_par {
u8 win_id;
u8 z_order; /*win sel layer*/
u8 alpha_mode;
u16 g_alpha_val;
u8 mirror_en;
struct rk_fb_area_par area_par[RK_WIN_MAX_AREA];
u32 reserved0;
};
struct rk_fb_win_cfg_data {
u8 wait_fs;
short ret_fence_fd;
short rel_fence_fd[RK_MAX_BUF_NUM];
struct rk_fb_win_par win_par[RK30_MAX_LAYER_SUPPORT];
struct rk_fb_wb_cfg wb_cfg;
};
struct rk_fb_reg_wb_data {
bool state;
u8 data_format;
struct ion_handle *ion_handle;
unsigned long smem_start;
unsigned long cbr_start; /*Cbr memory start address*/
u16 xsize;
u16 ysize;
};
struct rk_fb_reg_area_data {
struct sync_fence *acq_fence;
u8 data_format; /*layer data fmt*/
u8 data_space; /* indicate SDR or HDR */
u8 index_buf; /*judge if the buffer is index*/
u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
u32 y_vir_stride;
u32 uv_vir_stride;
u32 buff_len;
u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
u16 ypos;
u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
u16 ysize;
u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
u16 yact;
u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
u16 yvir;
u16 xoff; /*mem offset*/
u16 yoff;
unsigned long smem_start;
unsigned long cbr_start; /*Cbr memory start address*/
u32 line_length;
struct ion_handle *ion_handle;
#ifdef USE_ION_MMU
struct dma_buf *dma_buf;
struct dma_buf_attachment *attachment;
struct sg_table *sg_table;
dma_addr_t dma_addr;
#endif
u8 fbdc_en;
u8 fbdc_cor_en;
u8 fbdc_data_format;
};
struct rk_fb_reg_win_data {
int win_id;
int z_order; /*win sel layer*/
u32 area_num; /*maybe two region have the same dma buff,*/
u32 area_buf_num; /*so area_num maybe not equal to area_buf_num*/
u8 alpha_en;
u8 alpha_mode;
u16 g_alpha_val;
u8 mirror_en;
u8 colorspace;
struct rk_fb_reg_area_data reg_area_data[RK_WIN_MAX_AREA];
};
struct rk_fb_reg_data {
struct list_head list;
int win_num;
int buf_num;
int acq_num;
struct rk_fb_reg_win_data reg_win_data[RK30_MAX_LAYER_SUPPORT];
struct rk_fb_reg_wb_data reg_wb_data;
};
struct rk_lcdc_driver {
char name[6];
int te_irq;
int id;
int prop;
struct device *dev;
u32 version;
struct rk_vop_property property;
struct rk_lcdc_win *win[RK_MAX_FB_SUPPORT];
struct rk_fb_reg_wb_data wb_data;
int lcdc_win_num;
int num_buf; //the num_of buffer
int atv_layer_cnt;
int fb_index_base; //the first fb index of the lcdc device
struct rk_screen *screen0; //some platform have only one lcdc,but extend
struct rk_screen *screen1; //two display devices for dual display,such as rk2918,rk2928
struct rk_screen *cur_screen; //screen0 is primary screen ,like lcd panel,screen1 is extend screen,like hdmi
u32 pixclock;
u16 rotate_mode;
u16 cabc_mode;
u16 overlay_mode;
u16 pre_overlay;
u16 output_color;
u16 fb_win_map;
char fb0_win_id;
char fb1_win_id;
char fb2_win_id;
char fb3_win_id;
char fb4_win_id;
char mmu_dts_name[40];
struct device *mmu_dev;
int iommu_enabled;
int dsp_mode;
bool hot_plug_state;
struct rk_fb_reg_area_data reg_area_data;
/*
* front_regs means this config is scaning on the devices.
*/
struct rk_fb_reg_data *front_regs;
struct mutex front_lock;
struct mutex fb_win_id_mutex;
struct mutex win_config;
struct mutex switch_screen; /*for switch screen*/
struct completion frame_done; /*sync for pan_display,whe we set a new
frame address to lcdc register,we must
make sure the frame begain to display*/
spinlock_t cpl_lock; /*lock for completion frame done */
int first_frame;
struct rk_fb_vsync vsync_info;
struct rk_fb_frame_time frame_time;
int wait_fs; /*wait for new frame start in kernel */
struct sw_sync_timeline *timeline;
int timeline_max;
int suspend_flag;
int shutdown_flag;
int standby;
struct list_head update_regs_list;
struct list_head saved_list;
struct mutex update_regs_list_lock;
struct kthread_worker update_regs_worker;
struct task_struct *update_regs_thread;
struct kthread_work update_regs_work;
wait_queue_head_t update_regs_wait;
struct mutex output_lock;
struct rk29fb_info *screen_ctr_info;
struct list_head pwrlist_head;
struct rk_lcdc_drv_ops *ops;
struct rk_fb_trsm_ops *trsm_ops;
#ifdef CONFIG_DRM_ROCKCHIP
void (*irq_call_back)(struct rk_lcdc_driver *driver);
#endif
struct overscan overscan;
struct rk_lcdc_bcsh bcsh;
int *hwc_lut;
int uboot_logo;
int bcsh_init_status;
bool cabc_pwm_pol;
u8 reserved_fb;
/*1:hdmi switch uncomplete,0:complete*/
bool hdmi_switch;
void *trace_buf;
struct rk_fb_win_cfg_data tmp_win_cfg[DUMP_FRAME_NUM];
struct rk_fb_reg_data tmp_regs[DUMP_FRAME_NUM];
unsigned int area_support[RK30_MAX_LAYER_SUPPORT];
};
struct rk_fb_par {
int id;
u32 state;
unsigned long fb_phy_base; /* Start of fb address (physical address) */
char __iomem *fb_virt_base; /* Start of fb address (virt address) */
u32 fb_size;
struct rk_lcdc_driver *lcdc_drv;
#if defined(CONFIG_ION_ROCKCHIP)
struct ion_handle *ion_hdl;
#endif
u32 reserved[2];
};
/*disp_mode: dual display mode
* NO_DUAL,no dual display,
ONE_DUAL,use one lcdc + rk61x for dual display
DUAL,use 2 lcdcs for dual display
num_fb: the total number of fb
num_lcdc: the total number of lcdc
*/
struct rk_fb {
int disp_mode;
int disp_policy;
struct rk29fb_info *mach_info;
struct fb_info *fb[RK_MAX_FB_SUPPORT*2];
int num_fb;
struct rk_lcdc_driver *lcdc_dev_drv[RK30_MAX_LCDC_SUPPORT];
int num_lcdc;
#if defined(CONFIG_ION_ROCKCHIP)
struct ion_client *ion_client;
#endif
};
extern int rk_fb_trsm_ops_register(struct rk_fb_trsm_ops *ops, int type);
extern struct rk_fb_trsm_ops *rk_fb_trsm_ops_get(int type);
extern int rk_fb_register(struct rk_lcdc_driver *dev_drv,
struct rk_lcdc_win *win, int id);
extern int rk_fb_unregister(struct rk_lcdc_driver *dev_drv);
extern struct rk_lcdc_driver *rk_get_lcdc_drv(char *name);
extern int rk_fb_get_extern_screen(struct rk_screen *screen);
extern int rk_fb_set_vop_pwm(void);
extern int rk_fb_get_prmry_screen( struct rk_screen *screen);
extern int rk_fb_set_prmry_screen(struct rk_screen *screen);
extern u32 rk_fb_get_prmry_screen_pixclock(void);
extern int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv);
extern int rk_disp_pwr_enable(struct rk_lcdc_driver *dev_drv);
extern int rk_disp_pwr_disable(struct rk_lcdc_driver *dev_drv);
extern bool is_prmry_rk_lcdc_registered(void);
extern int rk_fb_prase_timing_dt(struct device_node *np,
struct rk_screen *screen);
extern int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv);
extern int rk_fb_dpi_open(bool open);
extern int rk_fb_dpi_layer_sel(int layer_id);
extern int rk_fb_dpi_status(void);
extern int rk_fb_switch_screen(struct rk_screen *screen, int enable, int lcdc_id);
extern int rk_fb_disp_scale(u8 scale_x, u8 scale_y, u8 lcdc_id);
extern int rkfb_create_sysfs(struct fb_info *fbi);
extern char *get_format_string(enum data_format, char *fmt);
extern int support_uboot_display(void);
extern int rk_fb_calc_fps(struct rk_screen *screen, u32 pixclock);
extern int rk_get_real_fps(int time);
extern struct device *rk_fb_get_sysmmu_device_by_compatible(const char *compt);
extern void rk_fb_platform_set_sysmmu(struct device *sysmmu,
struct device *dev);
int rk_fb_get_display_policy(void);
int rk_fb_pixel_width(int data_format);
void trace_buffer_dump(struct device *dev,
struct rk_lcdc_driver *dev_drv);
int rk_fb_set_car_reverse_status(struct rk_lcdc_driver *dev_drv, int status);
extern int rockchip_get_screen_type(void);
#endif

155
include/linux/rk_screen.h
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@ -1,155 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _SCREEN_H
#define _SCREEN_H
typedef enum _REFRESH_STAGE {
REFRESH_PRE = 0,
REFRESH_END,
} REFRESH_STAGE;
typedef enum _MCU_IOCTL {
MCU_WRCMD = 0,
MCU_WRDATA,
MCU_SETBYPASS,
} MCU_IOCTL;
typedef enum _MCU_STATUS {
MS_IDLE = 0,
MS_MCU,
MS_EBOOK,
MS_EWAITSTART,
MS_EWAITEND,
MS_EEND,
} MCU_STATUS;
struct rk29_fb_setting_info {
u8 data_num;
u8 vsync_en;
u8 den_en;
u8 mcu_fmk_en;
u8 disp_on_en;
u8 standby_en;
};
struct rk29lcd_info {
u32 lcd_id;
u32 txd_pin;
u32 clk_pin;
u32 cs_pin;
u32 reset_pin;
int (*io_init)(void);
int (*io_deinit)(void);
int (*io_enable)(void);
int (*io_disable)(void);
};
struct overscan {
unsigned char left;
unsigned char top;
unsigned char right;
unsigned char bottom;
};
/* Screen description
*type:LVDS,RGB,MIPI,MCU
*lvds_fromat:lvds data format,set it if the screen is lvds
*face:thi display output face,18bit,24bit,etc
*ft: the time need to display one frame time
*/
struct rk_screen {
u16 type;
u16 refresh_mode;
u16 lvds_format;
u16 face;
u16 color_mode;
u8 data_space;
u8 lcdc_id;
u8 screen_id;
struct fb_videomode mode;
u32 post_dsp_stx;
u32 post_dsp_sty;
u32 post_xsize;
u32 post_ysize;
u16 x_mirror;
u16 y_mirror;
int interlace;
int pixelrepeat; //For 480i/576i format, pixel is repeated twice.
u16 width;
u16 height;
u8 ft;
int *dsp_lut;
int *cabc_lut;
int *cabc_gamma_base;
#if defined(CONFIG_MFD_RK616) || defined(CONFIG_LCDC_RK312X)
u32 pll_cfg_val; //bellow are for jettaB
u32 frac;
u16 scl_vst;
u16 scl_hst;
u16 vif_vst;
u16 vif_hst;
#endif
u8 hdmi_resolution;
u8 mcu_wrperiod;
u8 mcu_usefmk;
u8 mcu_frmrate;
u8 pin_hsync;
u8 pin_vsync;
u8 pin_den;
u8 pin_dclk;
/* Swap rule */
u8 swap_gb;
u8 swap_rg;
u8 swap_rb;
u8 swap_delta;
u8 swap_dumy;
#if defined(CONFIG_MIPI_DSI)
/* MIPI DSI */
u8 dsi_lane;
u8 dsi_video_mode;
u32 hs_tx_clk;
#endif
int xpos; //horizontal display start position on the sceen ,then can be changed by application
int ypos;
int xsize; //horizontal and vertical display size on he screen,they can be changed by application
int ysize;
struct overscan overscan;
struct rk_screen *ext_screen;
/* Operation function*/
int (*init)(void);
int (*standby)(u8 enable);
int (*refresh)(u8 arg);
int (*scandir)(u16 dir);
int (*disparea)(u8 area);
int (*sscreen_get)(struct rk_screen *screen, u8 resolution);
int (*sscreen_set)(struct rk_screen *screen, bool type);// 1: use scaler 0:bypass
};
struct rk29fb_info {
u32 fb_id;
int prop; //display device property,like PRMRY,EXTEND
u32 mcu_fmk_pin;
struct rk29lcd_info *lcd_info;
int (*io_init)(struct rk29_fb_setting_info *fb_setting);
int (*io_deinit)(void);
int (*io_enable)(void);
int (*io_disable)(void);
void (*set_screen_info)(struct rk_screen *screen, struct rk29lcd_info *lcd_info );
};
extern void set_lcd_info(struct rk_screen *screen, struct rk29lcd_info *lcd_info);
extern size_t get_fb_size(u8 reserved_fb);
extern void set_tv_info(struct rk_screen *screen);
extern void set_hdmi_info(struct rk_screen *screen);
#endif