diff --git a/drivers/video/rockchip/bmp_helper.c b/drivers/video/rockchip/bmp_helper.c deleted file mode 100755 index e8f74b7da4f4..000000000000 --- a/drivers/video/rockchip/bmp_helper.c +++ /dev/null @@ -1,389 +0,0 @@ -/* - * linux/drivers/video/rockchip/bmp_helper.c - * - * Copyright (C) 2012 Rockchip Corporation - * Author: Mark Yao - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include -#include -#include -#include - -#include "bmp_helper.h" - -static void draw_unencoded_bitmap(uint16_t **dst, uint8_t *bmap, uint16_t *cmap, - uint32_t cnt) -{ - while (cnt > 0) { - *(*dst)++ = cmap[*bmap++]; - cnt--; - } -} - -static void draw_encoded_bitmap(uint16_t **dst, uint16_t c, uint32_t cnt) -{ - uint16_t *fb = *dst; - int cnt_8copy = cnt >> 3; - - cnt -= cnt_8copy << 3; - while (cnt_8copy > 0) { - *fb++ = c; - *fb++ = c; - *fb++ = c; - *fb++ = c; - *fb++ = c; - *fb++ = c; - *fb++ = c; - *fb++ = c; - cnt_8copy--; - } - while (cnt > 0) { - *fb++ = c; - cnt--; - } - *dst = fb; -} - -static void yuv_to_rgb(int y, int u, int v, int *r, int *g, int *b) -{ - int rdif, invgdif, bdif; - - u -= 128; - v -= 128; - rdif = v + ((v * 103) >> 8); - invgdif = ((u * 88) >> 8) + ((v * 183) >> 8); - bdif = u + ((u*198) >> 8); - *r = range(y + rdif, 0, 0xff); - *g = range(y - invgdif, 0, 0xff); - *b = range(y + bdif, 0, 0xff); -} - -int bmpencoder(void *__iomem *vaddr, int width, int height, u8 data_format, - void *data, void (*fn)(void *, void *, int)) -{ - uint32_t *d = NULL, *d1 = NULL, *d2 = NULL; - uint8_t *dst = NULL, *yrgb = NULL, *uv = NULL, *y1 = NULL, *y2 = NULL; - int y = 0, u = 0, v = 0, r = 0, g = 0, b = 0; - - int yu = width * 4 % 4; - int byteperline; - unsigned int size; - BITMAPHEADER header; - BITMAPINFOHEADER infoheader; - void *buf; - int i, j; - - yu = yu != 0 ? 4 - yu : yu; - byteperline = width * 4 + yu; - size = byteperline * height + 54; - memset(&header, 0, sizeof(header)); - memset(&infoheader, 0, sizeof(infoheader)); - header.type = 'M'<<8|'B'; - header.size = size; - header.offset = 54; - - infoheader.size = 40; - infoheader.width = width; - infoheader.height = 0 - height; - infoheader.bitcount = 4 * 8; - infoheader.compression = 0; - infoheader.imagesize = byteperline * height; - infoheader.xpelspermeter = 0; - infoheader.ypelspermeter = 0; - infoheader.colors = 0; - infoheader.colorsimportant = 0; - fn(data, (void *)&header, sizeof(header)); - fn(data, (void *)&infoheader, sizeof(infoheader)); - - /* - * if data_format is ARGB888 or XRGB888, not need convert. - */ - if (data_format == ARGB888 || data_format == XRGB888) { - fn(data, (char *)vaddr, width * height * 4); - return 0; - } - /* - * alloc 2 line buffer. - */ - buf = kmalloc(width * 2 * 4, GFP_KERNEL); - if (!buf) - return -ENOMEM; - yrgb = (uint8_t *)vaddr; - uv = yrgb + width * height; - for (j = 0; j < height; j++) { - if (j % 2 == 0) { - dst = buf; - y1 = yrgb + j * width; - y2 = y1 + width; - d1 = buf; - d2 = d1 + width; - } - - for (i = 0; i < width; i++) { - switch (data_format) { - case XBGR888: - case ABGR888: - dst[0] = yrgb[2]; - dst[1] = yrgb[1]; - dst[2] = yrgb[0]; - dst[3] = yrgb[3]; - dst += 4; - yrgb += 4; - break; - case RGB888: - dst[0] = yrgb[0]; - dst[1] = yrgb[1]; - dst[2] = yrgb[2]; - dst[3] = 0xff; - dst += 4; - yrgb += 3; - break; - case RGB565: - dst[0] = (yrgb[0] & 0x1f) << 3; - dst[1] = (yrgb[0] & 0xe0) >> 3 | - (yrgb[1] & 0x7) << 5; - dst[2] = yrgb[1] & 0xf8; - dst[3] = 0xff; - dst += 4; - yrgb += 2; - break; - case YUV420: - case YUV422: - case YUV444: - if (data_format == YUV420) { - if (i % 2 == 0) { - d = d1++; - y = *y1++; - } else { - d = d2++; - y = *y2++; - } - if (i % 4 == 0) { - u = *uv++; - v = *uv++; - } - } else if (data_format == YUV422) { - if (i % 2 == 0) { - u = *uv++; - v = *uv++; - } - d = d1++; - } else { - u = *uv++; - v = *uv++; - d = d1++; - } - yuv_to_rgb(y, u, v, &r, &g, &b); - *d = 0xff<<24 | r << 16 | g << 8 | b; - break; - case YUV422_A: - case YUV444_A: - default: - pr_err("unsupport now\n"); - return -EINVAL; - } - } - if (j % 2 == 1) - fn(data, (char *)buf, 2 * width * 4); - } - - return 0; -} - -static void decode_rle8_bitmap(uint8_t *psrc, uint8_t *pdst, uint16_t *cmap, - unsigned int width, unsigned int height, - int bits, int x_off, int y_off, bool flip) -{ - uint32_t cnt, runlen; - int x = 0, y = 0; - int decode = 1; - uint8_t *bmap = psrc; - uint8_t *dst = pdst; - int linesize = width * 2; - - if (flip) { - y = height - 1; - dst = pdst + y * linesize; - } - - while (decode) { - if (bmap[0] == BMP_RLE8_ESCAPE) { - switch (bmap[1]) { - case BMP_RLE8_EOL: - /* end of line */ - bmap += 2; - x = 0; - if (flip) { - y--; - dst -= linesize * 2; - } else { - y++; - } - break; - case BMP_RLE8_EOBMP: - /* end of bitmap */ - decode = 0; - break; - case BMP_RLE8_DELTA: - /* delta run */ - x += bmap[2]; - if (flip) { - y -= bmap[3]; - dst -= bmap[3] * linesize; - dst += bmap[2] * 2; - } else { - y += bmap[3]; - dst += bmap[3] * linesize; - dst += bmap[2] * 2; - } - bmap += 4; - break; - default: - /* unencoded run */ - runlen = bmap[1]; - bmap += 2; - if (y >= height || x >= width) { - decode = 0; - break; - } - if (x + runlen > width) - cnt = width - x; - else - cnt = runlen; - draw_unencoded_bitmap((uint16_t **)&dst, bmap, - cmap, cnt); - x += runlen; - bmap += runlen; - if (runlen & 1) - bmap++; - } - } else { - /* encoded run */ - if (y < height) { - runlen = bmap[0]; - if (x < width) { - /* aggregate the same code */ - while (bmap[0] == 0xff && - bmap[2] != BMP_RLE8_ESCAPE && - bmap[1] == bmap[3]) { - runlen += bmap[2]; - bmap += 2; - } - if (x + runlen > width) - cnt = width - x; - else - cnt = runlen; - draw_encoded_bitmap((uint16_t **)&dst, - cmap[bmap[1]], cnt); - } - x += runlen; - } - bmap += 2; - } - } -} - -int bmpdecoder(void *bmp_addr, void *pdst, int *width, int *height, int *bits) -{ - BITMAPHEADER header; - BITMAPINFOHEADER infoheader; - uint16_t *bmp_logo_palette; - uint32_t size; - uint16_t linesize; - int stride; - char *cmap_base; - char *src = bmp_addr; - char *dst = pdst; - int i; - bool flip = false; - - memcpy(&header, src, sizeof(header)); - src += sizeof(header); - - if (header.type != 0x4d42) { - pr_err("not bmp file type[%x], can't support\n", header.type); - return -1; - } - memcpy(&infoheader, src, sizeof(infoheader)); - *width = infoheader.width; - *height = infoheader.height; - - if (*height < 0) - *height = 0 - *height; - else - flip = true; - - size = header.size - header.offset; - linesize = *width * infoheader.bitcount >> 3; - cmap_base = src + sizeof(infoheader); - src = bmp_addr + header.offset; - - switch (infoheader.bitcount) { - case 8: - bmp_logo_palette = kmalloc(sizeof(bmp_logo_palette) * 256, GFP_KERNEL); - - /* Set color map */ - for (i = 0; i < 256; i++) { - ushort colreg = ((cmap_base[2] << 8) & 0xf800) | - ((cmap_base[1] << 3) & 0x07e0) | - ((cmap_base[0] >> 3) & 0x001f) ; - cmap_base += 4; - bmp_logo_palette[i] = colreg; - } - - /* - * only support convert 8bit bmap file to RGB565. - */ - decode_rle8_bitmap(src, dst, bmp_logo_palette, - infoheader.width, infoheader.height, - infoheader.bitcount, 0, 0, flip); - kfree(bmp_logo_palette); - *bits = 16; - break; - case 16: - /* - * Todo - */ - pr_info("unsupport bit=%d now\n", infoheader.bitcount); - break; - case 24: - stride = ALIGN(*width * 3, 4); - if (flip) - src += stride * (*height - 1); - - for (i = 0; i < *height; i++) { - memcpy(dst, src, 3 * (*width)); - dst += stride; - src += stride; - if (flip) - src -= stride * 2; - } - - *bits = 24; - break; - case 32: - /* - * Todo - */ - pr_info("unsupport bit=%d now\n", infoheader.bitcount); - break; - default: - pr_info("unsupport bit=%d now\n", infoheader.bitcount); - break; - } - - return 0; -} diff --git a/drivers/video/rockchip/bmp_helper.h b/drivers/video/rockchip/bmp_helper.h deleted file mode 100644 index fd1ad43f6d71..000000000000 --- a/drivers/video/rockchip/bmp_helper.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * drivers/video/rockchip/bmp_helper.h - * - * Copyright (C) 2012 Rockchip Corporation - * Author: Mark Yao - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#ifndef _BMP_HELPER_H_ -#define _BMP_HELPER_H_ - -typedef struct bmpheader { - unsigned short type; - unsigned int size; - unsigned int reserved; - unsigned int offset; -}__attribute__((packed)) BITMAPHEADER; - -typedef struct bmpinfoheader { - unsigned int size; - unsigned int width; - unsigned int height; - unsigned short planes; - unsigned short bitcount; - unsigned int compression; - unsigned int imagesize; - unsigned int xpelspermeter; - unsigned int ypelspermeter; - unsigned int colors; - unsigned int colorsimportant; -}__attribute__((packed)) BITMAPINFOHEADER; - -#define BMP_RLE8_ESCAPE 0 -#define BMP_RLE8_EOL 0 -#define BMP_RLE8_EOBMP 1 -#define BMP_RLE8_DELTA 2 - -#define range(x, min, max) ((x) < (min)) ? (min) : (((x) > (max)) ? (max) : (x)) - -int bmpencoder(void *__iomem *vaddr,int width, int height, u8 data_format, - void *data, void (*fn)(void *, void *, int)); -int bmpdecoder(void *bmp_addr, void *dst, int *width, int *height, int *bits); -#endif /* _BMP_HELPER_H_ */ diff --git a/drivers/video/rockchip/display-sys.c b/drivers/video/rockchip/display-sys.c deleted file mode 100644 index 6c03b2795840..000000000000 --- a/drivers/video/rockchip/display-sys.c +++ /dev/null @@ -1,793 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#include -#include -#include -#include -#include -#include - -static struct list_head main_display_device_list; -static struct list_head aux_display_device_list; - -static ssize_t name_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - - return snprintf(buf, PAGE_SIZE, "%s\n", dsp->name); -} - -static DEVICE_ATTR_RO(name); - -static ssize_t type_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - - return snprintf(buf, PAGE_SIZE, "%s\n", dsp->type); -} - -static DEVICE_ATTR_RO(type); - -static ssize_t property_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - - return snprintf(buf, PAGE_SIZE, "%d\n", dsp->property); -} - -static DEVICE_ATTR_RO(property); - -static ssize_t enable_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - int enable; - - if (dsp->ops && dsp->ops->getenable) - enable = dsp->ops->getenable(dsp); - else - return 0; - return snprintf(buf, PAGE_SIZE, "%d\n", enable); -} - -static ssize_t enable_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - int enable; - - if (kstrtoint(buf, 0, &enable)) - return size; - if (dsp->ops && dsp->ops->setenable) - dsp->ops->setenable(dsp, enable); - return size; -} - -static DEVICE_ATTR_RW(enable); - -static ssize_t connect_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - int connect; - - if (dsp->ops && dsp->ops->getstatus) - connect = dsp->ops->getstatus(dsp); - else - return 0; - return snprintf(buf, PAGE_SIZE, "%d\n", connect); -} - -static DEVICE_ATTR_RO(connect); - -static int mode_string(char *buf, unsigned int offset, - const struct fb_videomode *mode) -{ - char v = 'p'; - - if (!buf || !mode) { - pr_err("%s parameter error\n", __func__); - return 0; - } - if (mode->xres == 0 && mode->yres == 0) - return snprintf(&buf[offset], PAGE_SIZE - offset, "auto\n"); - if (mode->vmode & FB_VMODE_INTERLACED) - v = 'i'; - if (mode->vmode & FB_VMODE_DOUBLE) - v = 'd'; - if (mode->flag) - return snprintf(&buf[offset], PAGE_SIZE - offset, - "%dx%d%c-%d(YCbCr420)\n", - mode->xres, mode->yres, v, mode->refresh); - else - return snprintf(&buf[offset], PAGE_SIZE - offset, - "%dx%d%c-%d\n", - mode->xres, mode->yres, v, mode->refresh); -} - -static ssize_t modes_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - struct list_head *modelist, *pos; - struct display_modelist *display_modelist; - const struct fb_videomode *mode; - int i; - - mutex_lock(&dsp->lock); - if (dsp->ops && dsp->ops->getmodelist) { - if (dsp->ops->getmodelist(dsp, &modelist)) { - mutex_unlock(&dsp->lock); - return -EINVAL; - } - } else { - mutex_unlock(&dsp->lock); - return 0; - } - i = 0; - if (dsp->priority == DISPLAY_PRIORITY_HDMI) - i += snprintf(buf, PAGE_SIZE, "auto\n"); - - list_for_each(pos, modelist) { - display_modelist = list_entry(pos, - struct display_modelist, - list); - mode = &display_modelist->mode; - i += mode_string(buf, i, mode); - } - mutex_unlock(&dsp->lock); - return i; -} - -static DEVICE_ATTR_RO(modes); - -static ssize_t mode_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - struct fb_videomode mode; - - if (dsp->ops && dsp->ops->getmode) - if (dsp->ops->getmode(dsp, &mode) == 0) - return mode_string(buf, 0, &mode); - return 0; -} - -static ssize_t mode_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - char mstr[100]; - struct list_head *modelist, *pos; - struct display_modelist *display_modelist; - struct fb_videomode *mode; - size_t i; - - mutex_lock(&dsp->lock); - if (!memcmp(buf, "auto", 4)) { - if (dsp->ops && dsp->ops->setmode) - dsp->ops->setmode(dsp, NULL); - mutex_unlock(&dsp->lock); - return count; - } - - if (dsp->ops && dsp->ops->getmodelist) { - if (dsp->ops && dsp->ops->getmodelist) { - if (dsp->ops->getmodelist(dsp, &modelist)) { - mutex_unlock(&dsp->lock); - return -EINVAL; - } - } - list_for_each(pos, modelist) { - display_modelist = list_entry(pos, - struct display_modelist, - list); - mode = &display_modelist->mode; - i = mode_string(mstr, 0, mode); - if (strncmp(mstr, buf, max(count, i)) == 0) { - if (dsp->ops && dsp->ops->setmode) - dsp->ops->setmode(dsp, mode); - mutex_unlock(&dsp->lock); - return count; - } - } - } - mutex_unlock(&dsp->lock); - return -EINVAL; -} - -static DEVICE_ATTR_RW(mode); - -static ssize_t scale_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - int xscale, yscale; - - if (dsp->ops && dsp->ops->getscale) { - xscale = dsp->ops->getscale(dsp, DISPLAY_SCALE_X); - yscale = dsp->ops->getscale(dsp, DISPLAY_SCALE_Y); - if (xscale && yscale) - return snprintf(buf, PAGE_SIZE, - "xscale=%d yscale=%d\n", - xscale, yscale); - } - return -EINVAL; -} - -static ssize_t scale_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - int scale = 100; - - if (dsp->ops && dsp->ops->setscale) { - if (!strncmp(buf, "xscale", 6)) { - if (!kstrtoint(buf, 0, &scale)) - dsp->ops->setscale(dsp, - DISPLAY_SCALE_X, - scale); - } else if (!strncmp(buf, "yscale", 6)) { - if (!kstrtoint(buf, 0, &scale)) - dsp->ops->setscale(dsp, - DISPLAY_SCALE_Y, - scale); - } else { - if (!kstrtoint(buf, 0, &scale)) { - dsp->ops->setscale(dsp, - DISPLAY_SCALE_X, - scale); - dsp->ops->setscale(dsp, - DISPLAY_SCALE_Y, - scale); - } - } - return count; - } - return -EINVAL; -} - -static DEVICE_ATTR_RW(scale); - -static ssize_t mode3d_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - struct list_head *modelist, *pos; - struct display_modelist *display_modelist; - struct fb_videomode mode; - int i = 0, cur_3d_mode = -1; - char mode_str[128]; - int mode_strlen, format_3d; - - mutex_lock(&dsp->lock); - if (dsp->ops && dsp->ops->getmodelist) { - if (dsp->ops->getmodelist(dsp, &modelist)) { - mutex_unlock(&dsp->lock); - return -EINVAL; - } - } else { - mutex_unlock(&dsp->lock); - return 0; - } - - if (dsp->ops && dsp->ops->getmode) { - if (dsp->ops->getmode(dsp, &mode)) { - mutex_unlock(&dsp->lock); - return -EINVAL; - } - } else { - mutex_unlock(&dsp->lock); - return 0; - } - - list_for_each(pos, modelist) { - display_modelist = list_entry(pos, - struct display_modelist, - list); - if (!fb_mode_is_equal(&mode, &display_modelist->mode)) - display_modelist = NULL; - else - break; - } - if (display_modelist) - i = snprintf(buf, PAGE_SIZE, "3dmodes=%d\n", - display_modelist->format_3d); - else - i = snprintf(buf, PAGE_SIZE, "3dmodes=0\n"); - - if (dsp->ops && dsp->ops->get3dmode) - cur_3d_mode = dsp->ops->get3dmode(dsp); - i += snprintf(buf + i, PAGE_SIZE - i, "cur3dmode=%d\n", cur_3d_mode); - - list_for_each(pos, modelist) { - display_modelist = list_entry(pos, - struct display_modelist, - list); - mode_strlen = mode_string(mode_str, 0, - &display_modelist->mode); - mode_str[mode_strlen - 1] = 0; - format_3d = display_modelist->format_3d; - i += snprintf(buf + i, PAGE_SIZE, "%s,%d\n", - mode_str, format_3d); - } - mutex_unlock(&dsp->lock); - return i; -} - -static ssize_t mode3d_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - int mode; - - mutex_lock(&dsp->lock); - if (dsp->ops && dsp->ops->set3dmode) { - if (!kstrtoint(buf, 0, &mode)) - dsp->ops->set3dmode(dsp, mode); - mutex_unlock(&dsp->lock); - return count; - } - mutex_unlock(&dsp->lock); - return -EINVAL; -} - -static DEVICE_ATTR_RW(mode3d); - -static ssize_t color_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - int ret = 0; - - mutex_lock(&dsp->lock); - if (dsp->ops && dsp->ops->getcolor) - ret = dsp->ops->getcolor(dsp, buf); - mutex_unlock(&dsp->lock); - return ret; -} - -static ssize_t color_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - - mutex_lock(&dsp->lock); - if (dsp->ops && dsp->ops->setcolor) { - if (!dsp->ops->setcolor(dsp, buf, count)) { - mutex_unlock(&dsp->lock); - return count; - } - } - mutex_unlock(&dsp->lock); - return -EINVAL; -} - -static DEVICE_ATTR_RW(color); - -static ssize_t audioinfo_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - char audioinfo[200]; - int ret = 0; - - mutex_lock(&dsp->lock); - if (dsp->ops && dsp->ops->getedidaudioinfo) { - ret = dsp->ops->getedidaudioinfo(dsp, audioinfo, 200); - if (!ret) { - mutex_unlock(&dsp->lock); - return snprintf(buf, PAGE_SIZE, "%s\n", audioinfo); - } - } - mutex_unlock(&dsp->lock); - return -EINVAL; -} - -static DEVICE_ATTR_RO(audioinfo); - -static ssize_t monspecs_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - struct fb_monspecs monspecs; - int ret = 0; - - mutex_lock(&dsp->lock); - if (dsp->ops && dsp->ops->getmonspecs) { - ret = dsp->ops->getmonspecs(dsp, &monspecs); - if (!ret) { - mutex_unlock(&dsp->lock); - memcpy(buf, &monspecs, sizeof(struct fb_monspecs)); - return sizeof(struct fb_monspecs); - } - } - mutex_unlock(&dsp->lock); - return -EINVAL; -} - -static DEVICE_ATTR_RO(monspecs); - -static ssize_t debug_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - int ret = -EINVAL; - - mutex_lock(&dsp->lock); - if (dsp->ops && dsp->ops->getdebug) - ret = dsp->ops->getdebug(dsp, buf); - mutex_unlock(&dsp->lock); - return ret; -} - -static ssize_t debug_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - int cmd, ret = -EINVAL; - struct rk_display_device *dsp = dev_get_drvdata(dev); - - mutex_lock(&dsp->lock); - if (dsp->ops && dsp->ops->setdebug) { - if (kstrtoint(buf, 0, &cmd) == 0) - dsp->ops->setdebug(dsp, cmd); - ret = count; - } - mutex_unlock(&dsp->lock); - return ret; -} - -static DEVICE_ATTR_RW(debug); - -static ssize_t prop_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - int ret = -EINVAL; - - mutex_lock(&dsp->lock); - if (dsp->ops && dsp->ops->getvrinfo) - ret = dsp->ops->getvrinfo(dsp, buf); - mutex_unlock(&dsp->lock); - - return ret; -} - -static DEVICE_ATTR_RO(prop); - -static struct attribute *display_device_attrs[] = { - &dev_attr_name.attr, - &dev_attr_type.attr, - &dev_attr_property.attr, - &dev_attr_enable.attr, - &dev_attr_connect.attr, - &dev_attr_modes.attr, - &dev_attr_mode.attr, - &dev_attr_scale.attr, - &dev_attr_mode3d.attr, - &dev_attr_color.attr, - &dev_attr_audioinfo.attr, - &dev_attr_monspecs.attr, - &dev_attr_debug.attr, - &dev_attr_prop.attr, - NULL, -}; - -ATTRIBUTE_GROUPS(display_device); - -static int display_suspend(struct device *dev, pm_message_t state) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - - mutex_lock(&dsp->lock); - if (likely(dsp->driver->suspend)) - dsp->driver->suspend(dsp, state); - mutex_unlock(&dsp->lock); - return 0; -}; - -static int display_resume(struct device *dev) -{ - struct rk_display_device *dsp = dev_get_drvdata(dev); - - mutex_lock(&dsp->lock); - if (likely(dsp->driver->resume)) - dsp->driver->resume(dsp); - mutex_unlock(&dsp->lock); - return 0; -}; - -int display_add_videomode(const struct fb_videomode *mode, - struct list_head *head) -{ - struct list_head *pos; - struct display_modelist *modelist; - struct fb_videomode *m; - int found = 0; - - list_for_each(pos, head) { - modelist = list_entry(pos, struct display_modelist, list); - m = &modelist->mode; - if (fb_mode_is_equal(m, mode)) { - found = 1; - break; - } - } - if (!found) { - modelist = kmalloc(sizeof(*modelist), - GFP_KERNEL); - - if (!modelist) - return -ENOMEM; - modelist->mode = *mode; - list_add(&modelist->list, head); - } - return 0; -} - -void rk_display_device_enable(struct rk_display_device *ddev) -{ - struct list_head *pos, *head; - struct rk_display_device *dev = NULL, *dev_enabled = NULL; - struct rk_display_device *dev_enable = NULL; - int enable = 0, connect; - - if (ddev->property == DISPLAY_MAIN) - head = &main_display_device_list; - else - head = &aux_display_device_list; - - list_for_each(pos, head) { - dev = list_entry(pos, struct rk_display_device, list); - enable = dev->ops->getenable(dev); - connect = dev->ops->getstatus(dev); - if (connect) - dev_enable = dev; - if (enable == 1) - dev_enabled = dev; - } - /* If no device is connected, enable highest priority device. */ - if (!dev_enable) { - dev->ops->setenable(dev, 1); - return; - } - - if (dev_enable == dev_enabled) { - if (dev_enable != ddev) - ddev->ops->setenable(ddev, 0); - } else { - if (dev_enabled && - dev_enabled->priority != DISPLAY_PRIORITY_HDMI) - dev_enabled->ops->setenable(dev_enabled, 0); - dev_enable->ops->setenable(dev_enable, 1); - } -} -EXPORT_SYMBOL(rk_display_device_enable); - -void rk_display_device_enable_other(struct rk_display_device *ddev) -{ -#ifndef CONFIG_DISPLAY_AUTO_SWITCH - return; -#else - struct list_head *pos, *head; - struct rk_display_device *dev; - int connect = 0; - - if (ddev->property == DISPLAY_MAIN) - head = &main_display_device_list; - else - head = &aux_display_device_list; - - list_for_each_prev(pos, head) { - dev = list_entry(pos, struct rk_display_device, list); - if (dev != ddev) { - connect = dev->ops->getstatus(dev); - if (connect) { - dev->ops->setenable(dev, 1); - return; - } - } - } -#endif -} -EXPORT_SYMBOL(rk_display_device_enable_other); - -void rk_display_device_disable_other(struct rk_display_device *ddev) -{ -#ifndef CONFIG_DISPLAY_AUTO_SWITCH - return; -#else - struct list_head *pos, *head; - struct rk_display_device *dev; - int enable = 0; - - if (ddev->property == DISPLAY_MAIN) - head = &main_display_device_list; - else - head = &aux_display_device_list; - - list_for_each(pos, head) { - dev = list_entry(pos, struct rk_display_device, list); - if (dev != ddev) { - enable = dev->ops->getenable(dev); - if (enable) - dev->ops->setenable(dev, 0); - } - } - ddev->ops->setenable(ddev, 1); -#endif -} -EXPORT_SYMBOL(rk_display_device_disable_other); - -void rk_display_device_select(int property, int priority) -{ - struct list_head *pos, *head; - struct rk_display_device *dev; - int enable, found = 0; - - if (property == DISPLAY_MAIN) - head = &main_display_device_list; - else - head = &aux_display_device_list; - - list_for_each(pos, head) { - dev = list_entry(pos, struct rk_display_device, list); - if (dev->priority == priority) - found = 1; - } - - if (!found) { - pr_err("[%s] select display interface %d not exist\n", - __func__, priority); - return; - } - - list_for_each(pos, head) { - dev = list_entry(pos, struct rk_display_device, list); - enable = dev->ops->getenable(dev); - if (dev->priority == priority) { - if (!enable) - dev->ops->setenable(dev, 1); - } else if (enable) { - dev->ops->setenable(dev, 0); - } - } -} -EXPORT_SYMBOL(rk_display_device_select); -static struct mutex allocated_dsp_lock; -static DEFINE_IDR(allocated_dsp); -static struct class *display_class; - -struct rk_display_device - *rk_display_device_register(struct rk_display_driver *driver, - struct device *parent, void *devdata) -{ - struct rk_display_device *new_dev = NULL; - int ret = -EINVAL; - - if (unlikely(!driver)) - return ERR_PTR(ret); - - new_dev = kzalloc(sizeof(*new_dev), GFP_KERNEL); - if (likely(new_dev) && unlikely(driver->probe(new_dev, devdata))) { - /* Reserve the index for this display */ - mutex_lock(&allocated_dsp_lock); - new_dev->idx = idr_alloc(&allocated_dsp, new_dev, - 0, 0, GFP_KERNEL); - mutex_unlock(&allocated_dsp_lock); - - if (new_dev->idx >= 0) { - struct list_head *pos, *head; - struct rk_display_device *dev; - int i = 0; - - head = &main_display_device_list; - list_for_each_entry(dev, head, list) { - if (strcmp(dev->type, new_dev->type) == 0) - i++; - } - head = &aux_display_device_list; - list_for_each_entry(dev, head, list) { - if (strcmp(dev->type, new_dev->type) == 0) - i++; - } - if (i == 0) - new_dev->dev = - device_create(display_class, parent, - MKDEV(0, 0), new_dev, - "%s", new_dev->type); - else - new_dev->dev = - device_create(display_class, parent, - MKDEV(0, 0), new_dev, - "%s%d", new_dev->type, i); - - if (!IS_ERR(new_dev->dev)) { - new_dev->parent = parent; - new_dev->driver = driver; - if (parent) - new_dev->dev->driver = parent->driver; - mutex_init(&new_dev->lock); - /* Add new device to display device list. */ - if (new_dev->property == DISPLAY_MAIN) - head = &main_display_device_list; - else - head = &aux_display_device_list; - - list_for_each(pos, head) { - dev = - list_entry(pos, - struct rk_display_device, - list); - if (dev->priority > new_dev->priority) - break; - } - list_add_tail(&new_dev->list, pos); - return new_dev; - } - mutex_lock(&allocated_dsp_lock); - idr_remove(&allocated_dsp, new_dev->idx); - mutex_unlock(&allocated_dsp_lock); - ret = -EINVAL; - } - } - kfree(new_dev); - return ERR_PTR(ret); -} -EXPORT_SYMBOL(rk_display_device_register); - -void rk_display_device_unregister(struct rk_display_device *ddev) -{ - if (!ddev) - return; - /* Free device */ - mutex_lock(&ddev->lock); - device_unregister(ddev->dev); - mutex_unlock(&ddev->lock); - /* Mark device index as available */ - mutex_lock(&allocated_dsp_lock); - idr_remove(&allocated_dsp, ddev->idx); - mutex_unlock(&allocated_dsp_lock); - list_del(&ddev->list); - kfree(ddev); -} -EXPORT_SYMBOL(rk_display_device_unregister); - -static int __init rk_display_class_init(void) -{ - display_class = class_create(THIS_MODULE, "display"); - if (IS_ERR(display_class)) { - pr_err("Failed to create display class\n"); - display_class = NULL; - return -EINVAL; - } - display_class->dev_groups = display_device_groups; - display_class->suspend = display_suspend; - display_class->resume = display_resume; - mutex_init(&allocated_dsp_lock); - INIT_LIST_HEAD(&main_display_device_list); - INIT_LIST_HEAD(&aux_display_device_list); - return 0; -} - -static void __exit rk_display_class_exit(void) -{ - class_destroy(display_class); -} - -subsys_initcall(rk_display_class_init); -module_exit(rk_display_class_exit); - -MODULE_AUTHOR("zhengyang@rock-chips.com"); -MODULE_DESCRIPTION("Driver for rk display device"); -MODULE_LICENSE("GPL"); diff --git a/drivers/video/rockchip/lcdc/Kconfig b/drivers/video/rockchip/lcdc/Kconfig deleted file mode 100644 index f57a508bcba5..000000000000 --- a/drivers/video/rockchip/lcdc/Kconfig +++ /dev/null @@ -1,66 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config LCDC_RK2928 - tristate "rk2928 lcdc support" - depends on (DRM_ROCKCHIP || FB_ROCKCHIP) && ARCH_RK2928 - help - Driver for rk2928 lcdc . - -config LCDC_RK30 - tristate "rk30 lcdc support" - depends on (DRM_ROCKCHIP || FB_ROCKCHIP) && ARCH_RK30XX - help - Driver for rk30 lcdc .There are two lcd controllers on rk30 - -config LCDC_RK3066B - tristate "rk3066b lcdc support" - depends on (DRM_ROCKCHIP || FB_ROCKCHIP) && ARCH_RK3066B - help - Driver for rk3066b lcdc. - -config LCDC_RK3188 - bool "rk3188 lcdc support" - depends on DRM_ROCKCHIP || FB_ROCKCHIP - depends on ARM - help - Driver for rk3188/rk302x/rk319x lcdc.There are two lcd controllers on rk3188 - -config LCDC_RK3288 - bool "rk3288 lcdc support" - depends on DRM_ROCKCHIP || FB_ROCKCHIP - depends on ARM - help - Driver for rk3288 lcdc.There are two lcd controllers on rk3288 - -config LCDC_RK3036 - bool "rk3036 lcdc support" - depends on DRM_ROCKCHIP || FB_ROCKCHIP - depends on ARM - help - Driver for rk3036 lcdc. - -config LCDC_RK312X - bool "rk312x lcdc support" - depends on DRM_ROCKCHIP || FB_ROCKCHIP - depends on ARM - help - Driver for rk312x lcdc. - -config LCDC_RK3368 - bool "rk3368 lcdc support" - depends on DRM_ROCKCHIP || FB_ROCKCHIP - depends on ARM64 - help - Driver for rk3368 lcdc.There are one lcd controllers on rk3368 - -config LCDC_RK322X - bool "rk322x lcdc support" - depends on FB_ROCKCHIP - help - Driver for rk322x lcdc.There are one lcd controllers on rk322x - -config LCDC_LITE_RK3X - bool "rk lcdc lite support" - depends on FB_ROCKCHIP - help - Driver for rk lcdc lite.There are one lcd controllers on rk3366 or - on other chips in future diff --git a/drivers/video/rockchip/lcdc/Makefile b/drivers/video/rockchip/lcdc/Makefile deleted file mode 100644 index 1c2522c949e0..000000000000 --- a/drivers/video/rockchip/lcdc/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_LCDC_RK30) += rk30_lcdc.o -obj-$(CONFIG_LCDC_RK2928) += rk2928_lcdc.o -obj-$(CONFIG_LCDC_RK3066B) += rk3066b_lcdc.o -obj-$(CONFIG_LCDC_RK3188) += rk3188_lcdc.o -obj-$(CONFIG_LCDC_RK3288) += rk3288_lcdc.o -obj-$(CONFIG_LCDC_RK3036) += rk3036_lcdc.o -obj-$(CONFIG_LCDC_RK312X) += rk312x_lcdc.o -obj-$(CONFIG_LCDC_RK3368) += rk3368_lcdc.o -obj-$(CONFIG_LCDC_RK322X) += rk322x_lcdc.o -obj-$(CONFIG_LCDC_LITE_RK3X) += rk_vop_lite.o diff --git a/drivers/video/rockchip/lcdc/rk2928_lcdc.c b/drivers/video/rockchip/lcdc/rk2928_lcdc.c deleted file mode 100755 index 561fa6866a3a..000000000000 --- a/drivers/video/rockchip/lcdc/rk2928_lcdc.c +++ /dev/null @@ -1,1422 +0,0 @@ -/* - * drivers/video/rockchip/chips/rk2928_lcdc.c - * - * Copyright (C) 2012 ROCKCHIP, Inc. - *Author:yzq - * yxj - *This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk2928_lcdc.h" -#include "../transmitter/rk2928_lvds.h" - - - - - -static int dbg_thresd = 0; -module_param(dbg_thresd, int, S_IRUGO|S_IWUSR); -#define DBG(level,x...) do { if(unlikely(dbg_thresd >= level)) printk(KERN_INFO x); } while (0) - - - -//rk2928 lcdc iomux,mode:0,gpio,1 lcdc io -static int rk2928_lcdc_iomux(rk_screen *screen,int mode) -{ - int ret = 0; - int i=0; - if((screen->type == SCREEN_RGB)&&(mode)) //iomux for RGB screen - { - for(i=0;i<8;i++) - { - gpio_free(RK2928_PIN2_PB0 + i); - } - for(i=0;i<4;i++) - { - gpio_free(RK2928_PIN2_PC0 + i); - } - - if(screen->lcdc_id == 0) - { - rk30_mux_api_set(GPIO2B0_LCDC0_DCLK_LCDC1_DCLK_NAME, GPIO2B_LCDC0_DCLK); - rk30_mux_api_set(GPIO2B1_LCDC0_HSYNC_LCDC1_HSYNC_NAME, GPIO2B_LCDC0_HSYNC); - rk30_mux_api_set(GPIO2B2_LCDC0_VSYNC_LCDC1_VSYNC_NAME, GPIO2B_LCDC0_VSYNC); - rk30_mux_api_set(GPIO2B3_LCDC0_DEN_LCDC1_DEN_NAME, GPIO2B_LCDC0_DEN); - rk30_mux_api_set(GPIO2B4_LCDC0_D10_LCDC1_D10_NAME, GPIO2B_LCDC0_D10); - rk30_mux_api_set(GPIO2B5_LCDC0_D11_LCDC1_D11_NAME, GPIO2B_LCDC0_D11); - rk30_mux_api_set(GPIO2B6_LCDC0_D12_LCDC1_D12_NAME, GPIO2B_LCDC0_D12); - rk30_mux_api_set(GPIO2B7_LCDC0_D13_LCDC1_D13_NAME, GPIO2B_LCDC0_D13); - rk30_mux_api_set(GPIO2C0_LCDC0_D14_LCDC1_D14_NAME, GPIO2C_LCDC0_D14); - rk30_mux_api_set(GPIO2C1_LCDC0_D15_LCDC1_D15_NAME, GPIO2C_LCDC0_D15); - rk30_mux_api_set(GPIO2C2_LCDC0_D16_LCDC1_D16_NAME, GPIO2C_LCDC0_D16); - rk30_mux_api_set(GPIO2C3_LCDC0_D17_LCDC1_D17_NAME, GPIO2C_LCDC0_D17); - } - else if(screen->lcdc_id == 1) - { - rk30_mux_api_set(GPIO2B0_LCDC0_DCLK_LCDC1_DCLK_NAME, GPIO2B_LCDC1_DCLK); - rk30_mux_api_set(GPIO2B1_LCDC0_HSYNC_LCDC1_HSYNC_NAME, GPIO2B_LCDC1_HSYNC); - rk30_mux_api_set(GPIO2B2_LCDC0_VSYNC_LCDC1_VSYNC_NAME, GPIO2B_LCDC1_VSYNC); - rk30_mux_api_set(GPIO2B3_LCDC0_DEN_LCDC1_DEN_NAME, GPIO2B_LCDC1_DEN); - rk30_mux_api_set(GPIO2B4_LCDC0_D10_LCDC1_D10_NAME, GPIO2B_LCDC1_D10); - rk30_mux_api_set(GPIO2B5_LCDC0_D11_LCDC1_D11_NAME, GPIO2B_LCDC1_D11); - rk30_mux_api_set(GPIO2B6_LCDC0_D12_LCDC1_D12_NAME, GPIO2B_LCDC1_D12); - rk30_mux_api_set(GPIO2B7_LCDC0_D13_LCDC1_D13_NAME, GPIO2B_LCDC1_D13); - rk30_mux_api_set(GPIO2C0_LCDC0_D14_LCDC1_D14_NAME, GPIO2C_LCDC1_D14); - rk30_mux_api_set(GPIO2C1_LCDC0_D15_LCDC1_D15_NAME, GPIO2C_LCDC1_D15); - rk30_mux_api_set(GPIO2C2_LCDC0_D16_LCDC1_D16_NAME, GPIO2C_LCDC1_D16); - rk30_mux_api_set(GPIO2C3_LCDC0_D17_LCDC1_D17_NAME, GPIO2C_LCDC1_D17); - } - else - { - printk(KERN_WARNING "%s>>>no such interface:%d\n",__func__,screen->lcdc_id); - return -1; - } - } - else if((screen->type == SCREEN_RGB)&&(!mode)) - { - rk30_mux_api_set(GPIO2B0_LCDC0_DCLK_LCDC1_DCLK_NAME, GPIO2B_GPIO2B0 ); - rk30_mux_api_set(GPIO2B1_LCDC0_HSYNC_LCDC1_HSYNC_NAME,GPIO2B_GPIO2B1); - rk30_mux_api_set(GPIO2B2_LCDC0_VSYNC_LCDC1_VSYNC_NAME, GPIO2B_GPIO2B2); - rk30_mux_api_set(GPIO2B3_LCDC0_DEN_LCDC1_DEN_NAME, GPIO2B_GPIO2B3); - rk30_mux_api_set(GPIO2B4_LCDC0_D10_LCDC1_D10_NAME, GPIO2B_GPIO2B4 ); - rk30_mux_api_set(GPIO2B5_LCDC0_D11_LCDC1_D11_NAME, GPIO2B_GPIO2B5 ); - rk30_mux_api_set(GPIO2B6_LCDC0_D12_LCDC1_D12_NAME, GPIO2B_GPIO2B6 ); - rk30_mux_api_set(GPIO2B7_LCDC0_D13_LCDC1_D13_NAME, GPIO2B_GPIO2B7 ); - rk30_mux_api_set(GPIO2C0_LCDC0_D14_LCDC1_D14_NAME, GPIO2C_GPIO2C0); - rk30_mux_api_set(GPIO2C1_LCDC0_D15_LCDC1_D15_NAME, GPIO2C_GPIO2C1); - rk30_mux_api_set(GPIO2C2_LCDC0_D16_LCDC1_D16_NAME, GPIO2C_GPIO2C2); - rk30_mux_api_set(GPIO2C3_LCDC0_D17_LCDC1_D17_NAME, GPIO2C_GPIO2C3); - for(i=0;i<8;i++) - { - ret += gpio_request(RK2928_PIN2_PB0 + i, NULL); - gpio_direction_output(RK2928_PIN2_PB0 + i, 0); - } - for(i=0;i<4;i++) - { - ret += gpio_request(RK2928_PIN2_PC0 + i, NULL); - gpio_direction_output(RK2928_PIN2_PC0 + i, 0); - } - if(ret < 0) - { - printk("%s:some gpio request fail\n",__func__); - } - } - return 0; -} -static int init_rk2928_lcdc(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - if(lcdc_dev->id == 0) //lcdc0 - { - lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0"); - lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0"); - lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0"); - lcdc_dev->sclk = clk_get(NULL,"sclk_lcdc0"); - } - else - { - printk(KERN_ERR "invalid lcdc device!\n"); - return -EINVAL; - } - if (IS_ERR(lcdc_dev->sclk) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) - { - printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id); - } - - clk_enable(lcdc_dev->pd); - clk_enable(lcdc_dev->hclk); //enable aclk and hclk for register config - clk_enable(lcdc_dev->aclk); - lcdc_dev->clk_on = 1; - LcdSetBit(lcdc_dev,SYS_CFG, m_LCDC_AXICLK_AUTO_ENABLE);//eanble axi-clk auto gating for low power - LcdMskReg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR | m_BUS_ERR_INT_CLEAR | m_LINE_FLAG_INT_EN | - m_FRM_START_INT_EN | m_HOR_START_INT_EN,v_FRM_START_INT_CLEAR(1) | v_BUS_ERR_INT_CLEAR(0) | - v_LINE_FLAG_INT_EN(0) | v_FRM_START_INT_EN(0) | v_HOR_START_INT_EN(0)); //enable frame start interrupt for sync - //LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective - return 0; -} - -static int rk2928_lcdc_deinit(struct rk2928_lcdc_device *lcdc_dev) -{ - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_dev->clk_on = 0; - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); - LcdMskReg(lcdc_dev, INT_STATUS, m_HOR_START_INT_EN | m_FRM_START_INT_EN | - m_LINE_FLAG_INT_EN | m_BUS_ERR_INT_EN,v_HOR_START_INT_EN(0) | v_FRM_START_INT_EN(0) | - v_LINE_FLAG_INT_EN(0) | v_BUS_ERR_INT_EN(0)); //disable all lcdc interrupt - LcdSetBit(lcdc_dev,SYS_CFG,m_LCDC_STANDBY); - LCDC_REG_CFG_DONE(); - spin_unlock(&lcdc_dev->reg_lock); - } - else //clk already disabled - { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - mdelay(1); - - return 0; -} - -static int rk2928_load_screen(struct rk_lcdc_device_driver *dev_drv, bool initscreen) -{ - int ret = -EINVAL; - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - rk_screen *screen = dev_drv->cur_screen; - rk_screen *screen0 = dev_drv->screen0; - u64 ft; - int fps; - u16 face; - u16 right_margin = screen->right_margin; - u16 lower_margin = screen->lower_margin; - u16 x_res = screen->x_res, y_res = screen->y_res; - DBG(1,"left_margin:%d>>hsync_len:%d>>xres:%d>>right_margin:%d>>upper_margin:%d>>vsync_len:%d>>yres:%d>>lower_margin:%d\n", - screen->left_margin,screen->hsync_len,screen->x_res,screen->right_margin,screen->upper_margin,screen->vsync_len,screen->y_res, - screen->lower_margin); - // set the rgb or mcu - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(screen->type==SCREEN_MCU) - { - printk(KERN_ERR "MCU Screen is not supported by RK2928\n"); - - } - - switch (screen->face) - { - case OUT_P565: - face = OUT_P565; - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); - break; - case OUT_P666: - face = OUT_P666; - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); - break; - case OUT_D888_P565: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); - break; - case OUT_D888_P666: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); - break; - case OUT_P888: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_UP_EN, v_DITHER_UP_EN(0)); - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); - break; - default: - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_UP_EN, v_DITHER_UP_EN(0)); - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); - face = screen->face; - break; - } - - //use default overlay,set vsyn hsync den dclk polarity - LcdMskReg(lcdc_dev, DSP_CTRL,m_DISPLAY_FORMAT | m_HSYNC_POLARITY | m_VSYNC_POLARITY | - m_DEN_POLARITY |m_DCLK_POLARITY | m_OUTPUT_RB_SWAP | m_OUTPUT_RG_SWAP | m_BLACK_MODE, - v_DISPLAY_FORMAT(face) | v_HSYNC_POLARITY(screen->pin_hsync) | - v_VSYNC_POLARITY(screen->pin_vsync) | v_DEN_POLARITY(screen->pin_den) | - v_DCLK_POLARITY(screen->pin_dclk) | v_OUTPUT_RB_SWAP(screen->swap_rb) | - v_OUTPUT_RG_SWAP(screen->swap_rg) |v_BLACK_MODE(0)); - - //set background color to black,set swap according to the screen panel,disable blank mode - LcdMskReg(lcdc_dev, BG_COLOR, m_BG_COLOR ,v_BG_COLOR(0x000000)); - - - LcdWrReg(lcdc_dev, DSP_HTOTAL_HS_END,v_HSYNC(screen->hsync_len) | - v_HORPRD(screen->hsync_len + screen->left_margin + x_res + right_margin)); - LcdWrReg(lcdc_dev, DSP_HACT_ST_END, v_HAEP(screen->hsync_len + screen->left_margin + x_res) | - v_HASP(screen->hsync_len + screen->left_margin)); - - LcdWrReg(lcdc_dev, DSP_VTOTAL_VS_END, v_VSYNC(screen->vsync_len) | - v_VERPRD(screen->vsync_len + screen->upper_margin + y_res + lower_margin)); - LcdWrReg(lcdc_dev, DSP_VACT_ST_END, v_VAEP(screen->vsync_len + screen->upper_margin+y_res)| - v_VASP(screen->vsync_len + screen->upper_margin)); - -#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) - if(dev_drv->screen0->lcdc_id == 1) - { - //set register for scaller - LcdMskReg(lcdc_dev,SCL_REG0,m_SCL_DSP_ZERO | m_SCL_DEN_INVERT | - m_SCL_SYNC_INVERT | m_SCL_DCLK_INVERT | m_SCL_EN,v_SCL_DSP_ZERO(0) | - v_SCL_DEN_INVERT(screen0->s_den_inv) | v_SCL_SYNC_INVERT(screen0->s_hv_sync_inv) | - v_SCL_DCLK_INVERT(screen0->s_clk_inv) | v_SCL_EN(1)); - LcdWrReg(lcdc_dev,SCL_REG2,v_HASP(screen0->s_vsync_st) | v_HAEP(screen0->s_hsync_st)); - LcdWrReg(lcdc_dev,SCL_REG3,v_HASP(screen0->s_hsync_len) | - v_HAEP(screen0->s_hsync_len + screen0->s_left_margin + - screen0->x_res + screen0->s_right_margin)); - LcdWrReg(lcdc_dev,SCL_REG4,v_HASP(screen0->s_hsync_len + screen0->s_left_margin) | - v_HAEP(screen0->s_hsync_len + screen0->s_left_margin + screen0->x_res)); - LcdWrReg(lcdc_dev,SCL_REG5,v_VASP(screen0->s_vsync_len) | - v_VAEP(screen0->s_vsync_len + screen0->s_upper_margin + - screen0->y_res + screen0->s_lower_margin)); - LcdWrReg(lcdc_dev,SCL_REG6,v_VASP(screen0->s_vsync_len + - screen0->s_upper_margin) | v_VAEP(screen0->s_vsync_len + - screen0->s_upper_margin + screen0->y_res )); - LcdWrReg(lcdc_dev,SCL_REG8,v_VASP(screen0->s_vsync_len + screen0->s_upper_margin) | - v_VAEP(screen0->s_vsync_len + screen0->s_upper_margin + screen0->y_res)); - LcdWrReg(lcdc_dev,SCL_REG7,v_HASP(screen0->s_hsync_len + screen0->s_left_margin) | - v_HAEP(screen0->s_hsync_len + screen0->s_left_margin + screen0->x_res )); - LcdWrReg(lcdc_dev,SCL_REG1,v_SCL_V_FACTOR(0x1000)|v_SCL_H_FACTOR(0x1000)); - } -#endif - // let above to take effect - //LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - -#ifdef CONFIG_RK2928_LVDS - rk_lvds_register(dev_drv->screen0); -#endif - if(dev_drv->screen0->type == SCREEN_RGB) //iomux for RGB screen - { - - if(dev_drv->screen0->lcdc_id == 0) - { - rk30_mux_api_set(GPIO2B0_LCDC0_DCLK_LCDC1_DCLK_NAME, GPIO2B_LCDC0_DCLK); - rk30_mux_api_set(GPIO2B1_LCDC0_HSYNC_LCDC1_HSYNC_NAME, GPIO2B_LCDC0_HSYNC); - rk30_mux_api_set(GPIO2B2_LCDC0_VSYNC_LCDC1_VSYNC_NAME, GPIO2B_LCDC0_VSYNC); - rk30_mux_api_set(GPIO2B3_LCDC0_DEN_LCDC1_DEN_NAME, GPIO2B_LCDC0_DEN); - rk30_mux_api_set(GPIO2B4_LCDC0_D10_LCDC1_D10_NAME, GPIO2B_LCDC0_D10); - rk30_mux_api_set(GPIO2B5_LCDC0_D11_LCDC1_D11_NAME, GPIO2B_LCDC0_D11); - rk30_mux_api_set(GPIO2B6_LCDC0_D12_LCDC1_D12_NAME, GPIO2B_LCDC0_D12); - rk30_mux_api_set(GPIO2B7_LCDC0_D13_LCDC1_D13_NAME, GPIO2B_LCDC0_D13); - rk30_mux_api_set(GPIO2C0_LCDC0_D14_LCDC1_D14_NAME, GPIO2C_LCDC0_D14); - rk30_mux_api_set(GPIO2C1_LCDC0_D15_LCDC1_D15_NAME, GPIO2C_LCDC0_D15); - rk30_mux_api_set(GPIO2C2_LCDC0_D16_LCDC1_D16_NAME, GPIO2C_LCDC0_D16); - rk30_mux_api_set(GPIO2C3_LCDC0_D17_LCDC1_D17_NAME, GPIO2C_LCDC0_D17); - } - else if(dev_drv->screen0->lcdc_id == 1) - { - rk30_mux_api_set(GPIO2B0_LCDC0_DCLK_LCDC1_DCLK_NAME, GPIO2B_LCDC1_DCLK); - rk30_mux_api_set(GPIO2B1_LCDC0_HSYNC_LCDC1_HSYNC_NAME, GPIO2B_LCDC1_HSYNC); - rk30_mux_api_set(GPIO2B2_LCDC0_VSYNC_LCDC1_VSYNC_NAME, GPIO2B_LCDC1_VSYNC); - rk30_mux_api_set(GPIO2B3_LCDC0_DEN_LCDC1_DEN_NAME, GPIO2B_LCDC1_DEN); - rk30_mux_api_set(GPIO2B4_LCDC0_D10_LCDC1_D10_NAME, GPIO2B_LCDC1_D10); - rk30_mux_api_set(GPIO2B5_LCDC0_D11_LCDC1_D11_NAME, GPIO2B_LCDC1_D11); - rk30_mux_api_set(GPIO2B6_LCDC0_D12_LCDC1_D12_NAME, GPIO2B_LCDC1_D12); - rk30_mux_api_set(GPIO2B7_LCDC0_D13_LCDC1_D13_NAME, GPIO2B_LCDC1_D13); - rk30_mux_api_set(GPIO2C0_LCDC0_D14_LCDC1_D14_NAME, GPIO2C_LCDC1_D14); - rk30_mux_api_set(GPIO2C1_LCDC0_D15_LCDC1_D15_NAME, GPIO2C_LCDC1_D15); - rk30_mux_api_set(GPIO2C2_LCDC0_D16_LCDC1_D16_NAME, GPIO2C_LCDC1_D16); - rk30_mux_api_set(GPIO2C3_LCDC0_D17_LCDC1_D17_NAME, GPIO2C_LCDC1_D17); - } - else - { - printk(KERN_WARNING "%s>>>no such interface:%d\n",__func__,dev_drv->cur_screen->lcdc_id); - return -1; - } - - //rk30_mux_api_set(GPIO2C4_LCDC0_D18_LCDC1_D18_I2C2_SDA_NAME, GPIO2C_LCDC1_D18); - //rk30_mux_api_set(GPIO2C5_LCDC0_D19_LCDC1_D19_I2C2_SCL_NAME, GPIO2C_LCDC1_D19); - //rk30_mux_api_set(GPIO2C6_LCDC0_D20_LCDC1_D20_UART2_SIN_NAME, GPIO2C_LCDC1_D20); - //rk30_mux_api_set(GPIO2C7_LCDC0_D21_LCDC1_D21_UART2_SOUT_NAME, GPIO2C_LCDC1_D21); - //rk30_mux_api_set(GPIO2D0_LCDC0_D22_LCDC1_D22_NAME, GPIO2D_LCDC1_D22); - //rk30_mux_api_set(GPIO2D1_LCDC0_D23_LCDC1_D23_NAME, GPIO2D_LCDC1_D23); - printk("RGB screen connect to rk2928 lcdc interface%d\n",dev_drv->screen0->lcdc_id); - - } - - ret = clk_set_rate(lcdc_dev->dclk, screen->pixclock); - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); - } - lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - clk_enable(lcdc_dev->dclk); -#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) - - if(dev_drv->screen0->lcdc_id == 1) //if connect to output interface 1,need scale - { - ret = clk_set_rate(lcdc_dev->sclk, screen0->s_pixclock); - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc%d sclk failed\n",lcdc_dev->id); - } - //lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->sclk)); - //printk("%s: sclk:%lu>>need:%d",lcdc_dev->driver.name,,screen0->s_pixclock); - clk_enable(lcdc_dev->sclk); - } -#endif - ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* - (dev_drv->pixclock); // one frame time ,(pico seconds) - fps = div64_u64(1000000000000llu,ft); - screen->ft = 1000/fps; - printk("%s: dclk:%lu>>fps:%d ",lcdc_dev->driver.name,clk_get_rate(lcdc_dev->dclk), - fps); - - if(screen->init) - { - screen->init(); - } - - printk("%s for lcdc%d ok!\n",__func__,lcdc_dev->id); - return 0; -} - - -//enable layer,open:1,enable;0 disable -static int win0_open(struct rk2928_lcdc_device *lcdc_dev,bool open) -{ - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(open) - { - if(!lcdc_dev->atv_layer_cnt) - { - LcdClrBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); - } - lcdc_dev->atv_layer_cnt++; - } - else - { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.layer_par[0]->state = open; - - LcdMskReg(lcdc_dev, SYS_CFG, m_W0_EN, v_W0_EN(open)); - if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc - { - LcdSetBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); - } - //LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - printk(KERN_INFO "lcdc%d win0 %s\n",lcdc_dev->id,open?"open":"closed"); - return 0; -} -static int win1_open(struct rk2928_lcdc_device *lcdc_dev,bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(open) - { - if(!lcdc_dev->atv_layer_cnt) - { - printk("lcdc%d wakeup from stanby\n",lcdc_dev->id); - LcdClrBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); - } - lcdc_dev->atv_layer_cnt++; - } - else - { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.layer_par[1]->state = open; - - LcdMskReg(lcdc_dev, SYS_CFG, m_W1_EN, v_W1_EN(open)); - if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc - { - printk(KERN_INFO "no layer of lcdc%d is used,go to standby!",lcdc_dev->id); - LcdSetBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); - } - //LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - printk(KERN_INFO "lcdc%d win1 %s\n",lcdc_dev->id,open?"open":"closed"); - return 0; -} - - -static int rk2928_lcdc_blank(struct rk_lcdc_device_driver*lcdc_drv,int layer_id,int blank_mode) -{ - struct rk2928_lcdc_device * lcdc_dev = container_of(lcdc_drv,struct rk2928_lcdc_device ,driver); - - printk(KERN_INFO "%s>>>>>%d\n",__func__, blank_mode); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - switch(blank_mode) - { - case FB_BLANK_UNBLANK: - LcdMskReg(lcdc_dev,DSP_CTRL,m_BLANK_MODE ,v_BLANK_MODE(0)); - break; - case FB_BLANK_NORMAL: - LcdMskReg(lcdc_dev,DSP_CTRL,m_BLANK_MODE ,v_BLANK_MODE(1)); - break; - default: - LcdMskReg(lcdc_dev,DSP_CTRL,m_BLANK_MODE ,v_BLANK_MODE(1)); - break; - } - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win0_display(struct rk2928_lcdc_device *lcdc_dev,struct layer_par *par ) -{ - u32 y_addr; - u32 uv_addr; - y_addr = par->smem_start + par->y_offset; - uv_addr = par->cbr_start + par->c_offset; - DBG(2,KERN_INFO "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN0_YRGB_MST,y_addr); - LcdWrReg(lcdc_dev, WIN0_CBR_MST,uv_addr); - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_display(struct rk2928_lcdc_device *lcdc_dev,struct layer_par *par ) -{ - u32 y_addr; - u32 uv_addr; - y_addr = par->smem_start + par->y_offset; - uv_addr = par->cbr_start + par->c_offset; - DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN1_RGB_MST, y_addr); - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win0_set_par(struct rk2928_lcdc_device *lcdc_dev,rk_screen *screen, - struct layer_par *par ) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u32 ScaleYrgbX = 0x1000; - u32 ScaleYrgbY = 0x1000; - u32 ScaleCbrX = 0x1000; - u32 ScaleCbrY = 0x1000; - u8 fmt_cfg = 0; - - xact = par->xact; //active (origin) picture window width/height - yact = par->yact; - xvir = par->xvir; // virtual resolution - yvir = par->yvir; - xpos = par->xpos+screen->left_margin + screen->hsync_len; - ypos = par->ypos+screen->upper_margin + screen->vsync_len; - - ScaleYrgbX = CalScale(xact, par->xsize); //both RGB and yuv need this two factor - ScaleYrgbY = CalScale(yact, par->ysize); - - DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); - switch (par->format) - { - case XBGR888: - case ABGR888: - case ARGB888: - fmt_cfg = 0; - break; - case RGB888: - fmt_cfg = 1; - break; - case RGB565: - fmt_cfg = 2; - break; - case YUV422:// yuv422 - fmt_cfg = 5; - ScaleCbrX = CalScale((xact/2), par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - case YUV420: // yuv420 - fmt_cfg = 4; - ScaleCbrX = CalScale(xact/2, par->xsize); - ScaleCbrY = CalScale(yact/2, par->ysize); - break; - case YUV444:// yuv444 - fmt_cfg = 6; - ScaleCbrX = CalScale(xact, par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - default: - printk("%s:un supported format\n",__func__); - break; - } - - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_YRGB, v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY)); - LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX)| v_Y_SCL_FACTOR(ScaleCbrY)); - LcdMskReg(lcdc_dev, SYS_CFG, m_W0_FORMAT, v_W0_FORMAT(fmt_cfg)); //(inf->video_mode==0) - LcdWrReg(lcdc_dev, WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact)); - LcdWrReg(lcdc_dev, WIN0_DSP_ST, v_DSP_STX(xpos) | v_DSP_STY(ypos)); - LcdWrReg(lcdc_dev, WIN0_DSP_INFO, v_DSP_WIDTH(par->xsize)| v_DSP_HEIGHT(par->ysize)); - LcdMskReg(lcdc_dev,WIN0_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR, - v_COLORKEY_EN(1) | v_KEYCOLOR(0)); - switch(par->format) - { - case XBGR888: - LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_ARGB888_VIRWIDTH(xvir)); - LcdMskReg(lcdc_dev,SYS_CFG,m_W0_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); - break; - case ARGB888: - LcdMskReg(lcdc_dev,WIN_VIR,m_WIN0_VIR,v_WIN0_ARGB888_VIRWIDTH(xvir)); - LcdMskReg(lcdc_dev,SYS_CFG,m_W0_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(0)); - break; - case ABGR888: - LcdMskReg(lcdc_dev,WIN_VIR,m_WIN0_VIR,v_WIN0_ARGB888_VIRWIDTH(xvir)); - LcdMskReg(lcdc_dev,SYS_CFG,m_W0_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); - break; - case RGB888: //rgb888 - LcdMskReg(lcdc_dev,WIN_VIR,m_WIN0_VIR,v_WIN0_RGB888_VIRWIDTH(xvir)); - LcdMskReg(lcdc_dev,SYS_CFG,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(0)); - break; - case RGB565: //rgb565 - LcdMskReg(lcdc_dev,WIN_VIR,m_WIN0_VIR,v_WIN0_RGB565_VIRWIDTH(xvir)); - LcdMskReg(lcdc_dev,DSP_CTRL,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(0)); - break; - case YUV422: - case YUV420: - LcdMskReg(lcdc_dev,WIN_VIR,m_WIN0_VIR,v_WIN0_YUV_VIRWIDTH(xvir)); - LcdMskReg(lcdc_dev,SYS_CFG,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(0)); - break; - default: - printk("%s:un supported format\n",__func__); - break; - } - - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_set_par(struct rk2928_lcdc_device *lcdc_dev,rk_screen *screen, - struct layer_par *par ) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u32 ScaleYrgbX = 0x1000; - u32 ScaleYrgbY = 0x1000; - u32 ScaleCbrX = 0x1000; - u32 ScaleCbrY = 0x1000; - u8 fmt_cfg = 0; - - xact = par->xact; - yact = par->yact; - xvir = par->xvir; - yvir = par->yvir; - xpos = par->xpos+screen->left_margin + screen->hsync_len; - ypos = par->ypos+screen->upper_margin + screen->vsync_len; - - DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); - - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN1_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos)); - LcdWrReg(lcdc_dev, WIN1_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize)); - // enable win1 color key and set the color to black(rgb=0) - LcdMskReg(lcdc_dev, WIN1_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,v_COLORKEY_EN(1) | v_KEYCOLOR(0)); - - - switch(par->format) - { - case XBGR888: - fmt_cfg = 0; - LcdMskReg(lcdc_dev,WIN_VIR,m_WIN1_VIR,v_WIN1_ARGB888_VIRWIDTH(xvir)); - LcdMskReg(lcdc_dev,SYS_CFG,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); - break; - case ABGR888: - fmt_cfg = 0; - LcdMskReg(lcdc_dev,WIN_VIR,m_WIN1_VIR,v_WIN1_ARGB888_VIRWIDTH(xvir)); - LcdMskReg(lcdc_dev,SYS_CFG,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); - break; - case ARGB888: - fmt_cfg = 0; - LcdMskReg(lcdc_dev,WIN_VIR,m_WIN1_VIR,v_WIN1_ARGB888_VIRWIDTH(xvir)); - LcdMskReg(lcdc_dev,SYS_CFG,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(0)); - break; - case RGB888: //rgb888 - fmt_cfg = 1; - LcdMskReg(lcdc_dev,WIN_VIR,m_WIN1_VIR,v_WIN1_RGB888_VIRWIDTH(xvir)); - LcdMskReg(lcdc_dev,DSP_CTRL,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(0)); - break; - case RGB565: //rgb565 - fmt_cfg = 2; - LcdMskReg(lcdc_dev,WIN_VIR,m_WIN1_VIR,v_WIN1_RGB565_VIRWIDTH(xvir)); - LcdMskReg(lcdc_dev,SYS_CFG,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(0)); - break; - default: - printk("%s:un supported format\n",__func__); - break; - } - - LcdMskReg(lcdc_dev,SYS_CFG, m_W1_FORMAT, v_W1_FORMAT(fmt_cfg)); - //LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk2928_lcdc_open(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - - if(open) - { - rk2928_load_screen(dev_drv,1); - } - if(layer_id == 0) - { - win0_open(lcdc_dev,open); - } - else if(layer_id == 1) - { - win1_open(lcdc_dev,open); - } - - return 0; -} - -static int rk2928_lcdc_set_par(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - struct layer_par *par = NULL; - rk_screen *screen = dev_drv->cur_screen; - rk_screen *screen0 = dev_drv->screen0; - u32 Scl_X = 0x1000; - u32 Scl_Y = 0x1000; - - if(!screen) - { - printk(KERN_ERR "screen is null!\n"); - return -ENOENT; - } - if(layer_id==0) - { - par = dev_drv->layer_par[0]; - win0_set_par(lcdc_dev,screen,par); - } - else if(layer_id==1) - { - par = dev_drv->layer_par[1]; - win1_set_par(lcdc_dev,screen,par); - } - Scl_X = CalScale(screen->x_res - 1,screen0->x_res - 1); - if((screen->y_res-1)/(screen0->x_res -1) < 2) - { - - Scl_Y = CalScale(screen->y_res - 1 ,screen0->y_res - 1); - } - else - { - Scl_Y = CalScale(screen->y_res - 2 ,screen0->y_res - 1); - } - LcdWrReg(lcdc_dev,SCL_REG1,v_SCL_V_FACTOR(Scl_Y)|v_SCL_H_FACTOR(Scl_X)); - - return 0; -} - -int rk2928_lcdc_pan_display(struct rk_lcdc_device_driver * dev_drv,int layer_id) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - struct layer_par *par = NULL; - rk_screen *screen = dev_drv->cur_screen; - unsigned long flags; - int timeout; - if(!screen) - { - printk(KERN_ERR "screen is null!\n"); - return -ENOENT; - } - if(layer_id==0) - { - par = dev_drv->layer_par[0]; - win0_display(lcdc_dev,par); - } - else if(layer_id==1) - { - par = dev_drv->layer_par[1]; - win1_display(lcdc_dev,par); - } - if((dev_drv->first_frame)) //this is the first frame of the system ,enable frame start interrupt - { - dev_drv->first_frame = 0; - LcdMskReg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR |m_FRM_START_INT_EN , - v_FRM_START_INT_CLEAR(1) | v_FRM_START_INT_EN(1)); - LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective - - } - - if(dev_drv->num_buf < 3) //3buffer ,no need to wait for sysn - { - spin_lock_irqsave(&dev_drv->cpl_lock,flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock,flags); - timeout = wait_for_completion_timeout(&dev_drv->frame_done,msecs_to_jiffies(dev_drv->cur_screen->ft+5)); - if(!timeout&&(!dev_drv->frame_done.done)) - { - //printk(KERN_ERR "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } - } - - return 0; -} - -int rk2928_lcdc_ioctl(struct rk_lcdc_device_driver * dev_drv,unsigned int cmd, unsigned long arg,int layer_id) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - u32 panel_size[2]; - void __user *argp = (void __user *)arg; - int ret = 0; - switch(cmd) - { - case RK_FBIOGET_PANEL_SIZE: //get panel size - panel_size[0] = dev_drv->screen0->x_res; - panel_size[1] = dev_drv->screen0->y_res; - if(copy_to_user(argp, panel_size, 8)) - return -EFAULT; - break; - default: - break; - } - - return ret; -} -static int rk2928_lcdc_get_layer_state(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - struct layer_par *par = dev_drv->layer_par[layer_id]; - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) - { - if(layer_id == 0) - { - par->state = LcdReadBit(lcdc_dev,SYS_CFG,m_W0_EN); - } - else if( layer_id == 1) - { - par->state = LcdReadBit(lcdc_dev,SYS_CFG,m_W1_EN); - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return par->state; - -} - -/*********************************** -overlay manager -swap:1 win0 on the top of win1 - 0 win1 on the top of win0 -set : 1 set overlay - 0 get overlay state -************************************/ -static int rk2928_lcdc_ovl_mgr(struct rk_lcdc_device_driver *dev_drv,int swap,bool set) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - int ovl; - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) - { - if(set) //set overlay - { - LcdMskReg(lcdc_dev,DSP_CTRL,m_W0W1_POSITION_SWAP,v_W0W1_POSITION_SWAP(swap)); - LCDC_REG_CFG_DONE(); - ovl = swap; - } - else //get overlay - { - ovl = LcdReadBit(lcdc_dev,DSP_CTRL,m_W0W1_POSITION_SWAP); - } - } - else - { - ovl = -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - - return ovl; -} - -static ssize_t dump_win0_disp_info(struct rk2928_lcdc_device *lcdc_dev,char *buf) -{ - char format[9] = "NULL"; - u32 fmt_id = LcdRdReg(lcdc_dev,SYS_CFG); - u32 xvir,act_info,dsp_info,dsp_st,factor; - u16 x_act,y_act,x_dsp,y_dsp,x_factor,y_factor; - u16 x_scale,y_scale; - switch((fmt_id&m_W0_FORMAT)>>3) - { - case 0: - strcpy(format,"ARGB888"); - break; - case 1: - strcpy(format,"RGB888"); - break; - case 2: - strcpy(format,"RGB565"); - break; - case 4: - strcpy(format,"YCbCr422"); - break; - case 5: - strcpy(format,"YCbCr420"); - break; - case 6: - strcpy(format,"YCbCr444"); - break; - default: - strcpy(format,"inval\n"); - break; - } - - xvir = LcdRdReg(lcdc_dev,WIN_VIR)&0xffff; - act_info = LcdRdReg(lcdc_dev,WIN0_ACT_INFO); - dsp_info = LcdRdReg(lcdc_dev,WIN0_DSP_INFO); - dsp_st = LcdRdReg(lcdc_dev,WIN0_DSP_ST); - factor = LcdRdReg(lcdc_dev,WIN0_SCL_FACTOR_YRGB); - x_act = (act_info&0xffff) + 1; - y_act = (act_info>>16) + 1; - x_dsp = (dsp_info&0xffff) + 1; - y_dsp = (dsp_info>>16) + 1; - x_factor = factor&0xffff; - y_factor = factor>>16; - x_scale = 4096*100/x_factor; - y_scale = 4096*100/y_factor; - return snprintf(buf,PAGE_SIZE,"xvir:%d\nxact:%d\nyact:%d\nxdsp:%d\nydsp:%d\nx_st:%d\ny_st:%d\nx_scale:%d.%d\ny_scale:%d.%d\nformat:%s\n", - xvir,x_act,y_act,x_dsp,y_dsp,dsp_st&0xffff,dsp_st>>16,x_scale/100,x_scale%100,y_scale/100,y_scale%100,format); - -} - -static ssize_t dump_win1_disp_info(struct rk2928_lcdc_device *lcdc_dev,char *buf) -{ - char format[9] = "NULL"; - u32 fmt_id = LcdRdReg(lcdc_dev,SYS_CFG); - u32 xvir,act_info,dsp_info,dsp_st,factor; - u16 x_act,y_act,x_dsp,y_dsp,x_factor,y_factor; - u16 x_scale,y_scale; - switch((fmt_id&m_W1_FORMAT)>>6) - { - case 0: - strcpy(format,"ARGB888"); - break; - case 1: - strcpy(format,"RGB888"); - break; - case 2: - strcpy(format,"RGB565"); - break; - default: - strcpy(format,"inval\n"); - break; - } - - xvir = (LcdRdReg(lcdc_dev,WIN_VIR)>>16)&0xfff; - dsp_info = LcdRdReg(lcdc_dev,WIN1_DSP_INFO); - dsp_st = LcdRdReg(lcdc_dev,WIN1_DSP_ST); - - x_dsp = dsp_info&0xffff; - y_dsp = dsp_info>>16; - - return snprintf(buf,PAGE_SIZE,"xvir:%d\nxdsp:%d\nydsp:%d\nx_st:%d\ny_st:%d\nformat:%s\n", - xvir,x_dsp,y_dsp,dsp_st&0xffff,dsp_st>>16,format); -} - -static ssize_t rk2928_lcdc_get_disp_info(struct rk_lcdc_device_driver *dev_drv,char *buf,int layer_id) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - if(layer_id == 0) - { - return dump_win0_disp_info(lcdc_dev,buf); - } - else if(layer_id == 1) - { - return dump_win1_disp_info(lcdc_dev,buf); - } - - return 0; -} - - - -/******************************************* -lcdc fps manager,set or get lcdc fps -set:0 get - 1 set -********************************************/ -static int rk2928_lcdc_fps_mgr(struct rk_lcdc_device_driver *dev_drv,int fps,bool set) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - rk_screen * screen = dev_drv->cur_screen; - u64 ft = 0; - u32 dotclk; - int ret; - - if(set) - { - ft = div_u64(1000000000000llu,fps); - dev_drv->pixclock = div_u64(ft,(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)); - dotclk = div_u64(1000000000000llu,dev_drv->pixclock); - ret = clk_set_rate(lcdc_dev->dclk, dotclk); - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); - } - dev_drv->pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - - } - - ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* - (dev_drv->pixclock); // one frame time ,(pico seconds) - fps = div64_u64(1000000000000llu,ft); - screen->ft = 1000/fps ; //one frame time in ms - return fps; -} - - -static int rk2928_fb_layer_remap(struct rk_lcdc_device_driver *dev_drv, - enum fb_win_map_order order) -{ - mutex_lock(&dev_drv->fb_win_id_mutex); - if(order == FB_DEFAULT_ORDER) - { - order = FB0_WIN0_FB1_WIN1_FB2_WIN2; - } - dev_drv->fb2_win_id = order/100; - dev_drv->fb1_win_id = (order/10)%10; - dev_drv->fb0_win_id = order%10; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - printk("fb0:win%d\nfb1:win%d\nfb2:win%d\n",dev_drv->fb0_win_id,dev_drv->fb1_win_id, - dev_drv->fb2_win_id); - - return 0; -} - -static int rk2928_fb_get_layer(struct rk_lcdc_device_driver *dev_drv,const char *id) -{ - int layer_id = 0; - mutex_lock(&dev_drv->fb_win_id_mutex); - if(!strcmp(id,"fb0")) - { - layer_id = dev_drv->fb0_win_id; - } - else if(!strcmp(id,"fb1")) - { - layer_id = dev_drv->fb1_win_id; - } - else if(!strcmp(id,"fb2")) - { - layer_id = dev_drv->fb2_win_id; - } - else - { - printk(KERN_ERR "%s>>un supported %s\n",__func__,id); - layer_id = -1; - } - mutex_unlock(&dev_drv->fb_win_id_mutex); - //printk("%s %s win%d\n",__func__,id,layer_id); - return layer_id; -} - -static int rk2928_lcdc_hdmi_process(struct rk_lcdc_device_driver *dev_drv,int mode) -{ -#if !defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) - printk("%s>>>>>>>>mode:%d\n",__func__,mode); - if(mode) - { - rk2928_lcdc_iomux(dev_drv->screen0,0); //switch to gpio mode,to avoid current leakage - if(dev_drv->screen_ctr_info->io_disable) - dev_drv->screen_ctr_info->io_disable(); - } - else - { - rk2928_lcdc_iomux(dev_drv->screen0,1); //switch to gpio mode,to avoid current leakage - if(dev_drv->screen_ctr_info->io_enable) - dev_drv->screen_ctr_info->io_enable(); - } -#endif - - return 0; - -} -int rk2928_lcdc_early_suspend(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - - if(dev_drv->screen0->standby) - dev_drv->screen0->standby(1); - if(dev_drv->screen_ctr_info->io_disable) - dev_drv->screen_ctr_info->io_disable(); - - if(dev_drv->cur_screen->sscreen_set) - dev_drv->cur_screen->sscreen_set(dev_drv->cur_screen , 0); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_dev->clk_on = 0; - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); - LcdSetBit(lcdc_dev,DSP_CTRL,m_BLACK_MODE); - LcdMskReg(lcdc_dev, SYS_CFG,m_DSP_OUT_ZERO | m_LCDC_STANDBY, - v_DSP_OUT_ZERO(1) | v_LCDC_STANDBY(1)); - LCDC_REG_CFG_DONE(); - spin_unlock(&lcdc_dev->reg_lock); - } - else //clk already disabled - { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - - - mdelay(10); - rk2928_lcdc_iomux(dev_drv->screen0,0); //switch to gpio mode,to avoid current leakage - clk_disable(lcdc_dev->dclk); - clk_disable(lcdc_dev->hclk); - clk_disable(lcdc_dev->aclk); - clk_disable(lcdc_dev->pd); - - return 0; -} - - - -int rk2928_lcdc_early_resume(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - - if(dev_drv->screen_ctr_info->io_enable) //power on - dev_drv->screen_ctr_info->io_enable(); - - if(!lcdc_dev->clk_on) - { - clk_enable(lcdc_dev->pd); - clk_enable(lcdc_dev->hclk); - clk_enable(lcdc_dev->dclk); - clk_enable(lcdc_dev->aclk); - } - rk2928_lcdc_iomux(dev_drv->screen0,1); //switch to lcdc io - memcpy((u8*)lcdc_dev->preg, (u8*)&lcdc_dev->regbak, 0xc4); //resume reg - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->atv_layer_cnt) - { - LcdMskReg(lcdc_dev, SYS_CFG,m_DSP_OUT_ZERO | m_LCDC_STANDBY, - v_DSP_OUT_ZERO(0) | v_LCDC_STANDBY(0)); - LcdClrBit(lcdc_dev,DSP_CTRL,m_BLACK_MODE); - LCDC_REG_CFG_DONE(); - } - lcdc_dev->clk_on = 1; - spin_unlock(&lcdc_dev->reg_lock); - - - if(dev_drv->cur_screen->sscreen_set) - dev_drv->cur_screen->sscreen_set(dev_drv->cur_screen , 1); - - if(dev_drv->screen0->standby) - dev_drv->screen0->standby(0); //screen wake up - - - return 0; -} -static irqreturn_t rk2928_lcdc_isr(int irq, void *dev_id) -{ - struct rk2928_lcdc_device *lcdc_dev = (struct rk2928_lcdc_device *)dev_id; - - ktime_t timestamp = ktime_get(); - - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); - //LCDC_REG_CFG_DONE(); - //LcdMskReg(lcdc_dev, INT_STATUS, m_LINE_FLAG_INT_CLEAR, v_LINE_FLAG_INT_CLEAR(1)); - - if(lcdc_dev->driver.num_buf < 3) //three buffer ,no need to wait for sync - { - spin_lock(&(lcdc_dev->driver.cpl_lock)); - complete(&(lcdc_dev->driver.frame_done)); - spin_unlock(&(lcdc_dev->driver.cpl_lock)); - } - - lcdc_dev->driver.vsync_info.timestamp = timestamp; - wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait); - return IRQ_HANDLED; -} - -static struct layer_par lcdc_layer[] = { - [0] = { - .name = "win0", - .id = 0, - .support_3d = true, - }, - [1] = { - .name = "win1", - .id = 1, - .support_3d = false, - }, -}; - -static struct rk_lcdc_device_driver lcdc_driver = { - .name = "lcdc", - .def_layer_par = lcdc_layer, - .num_layer = ARRAY_SIZE(lcdc_layer), - .open = rk2928_lcdc_open, - .init_lcdc = init_rk2928_lcdc, - .ioctl = rk2928_lcdc_ioctl, - .suspend = rk2928_lcdc_early_suspend, - .resume = rk2928_lcdc_early_resume, - .set_par = rk2928_lcdc_set_par, - .blank = rk2928_lcdc_blank, - .pan_display = rk2928_lcdc_pan_display, - .load_screen = rk2928_load_screen, - .get_layer_state = rk2928_lcdc_get_layer_state, - .ovl_mgr = rk2928_lcdc_ovl_mgr, - .get_disp_info = rk2928_lcdc_get_disp_info, - .fps_mgr = rk2928_lcdc_fps_mgr, - .fb_get_layer = rk2928_fb_get_layer, - .fb_layer_remap = rk2928_fb_layer_remap, - .lcdc_hdmi_process = rk2928_lcdc_hdmi_process, -}; -#ifdef CONFIG_PM -static int rk2928_lcdc_suspend(struct platform_device *pdev, pm_message_t state) -{ - return 0; -} - -static int rk2928_lcdc_resume(struct platform_device *pdev) -{ - return 0; -} - -#else -#define rk2928_lcdc_suspend NULL -#define rk2928_lcdc_resume NULL -#endif - -static int __devinit rk2928_lcdc_probe (struct platform_device *pdev) -{ - struct rk2928_lcdc_device *lcdc_dev=NULL; - rk_screen *screen0; - rk_screen *screen1; - struct rk29fb_info *screen_ctr_info; - struct resource *res = NULL; - struct resource *mem; - int ret = 0; - - /*************Malloc rk2928lcdc_inf and set it to pdev for drvdata**********/ - lcdc_dev = kzalloc(sizeof(struct rk2928_lcdc_device), GFP_KERNEL); - if(!lcdc_dev) - { - dev_err(&pdev->dev, ">>rk2928 lcdc device kmalloc fail!"); - return -ENOMEM; - } - platform_set_drvdata(pdev, lcdc_dev); - lcdc_dev->id = pdev->id; - screen_ctr_info = (struct rk29fb_info * )pdev->dev.platform_data; - screen0 = kzalloc(sizeof(rk_screen), GFP_KERNEL); //rk2928 has one lcdc but two outputs - if(!screen0) - { - dev_err(&pdev->dev, ">>rk2928 lcdc screen1 kmalloc fail!"); - ret = -ENOMEM; - goto err0; - } - screen0->lcdc_id = 0; //this id can be changed dynamic - screen0->screen_id = 0; //this id is fixed - screen1 = kzalloc(sizeof(rk_screen), GFP_KERNEL); - if(!screen1) - { - dev_err(&pdev->dev, ">>rk2928 lcdc screen1 kmalloc fail!"); - ret = -ENOMEM; - goto err0; - } - screen1->lcdc_id = 1; - screen1->screen_id = 1; - - /****************get lcdc0 reg *************************/ - res = platform_get_resource(pdev, IORESOURCE_MEM,0); - if (res == NULL) - { - dev_err(&pdev->dev, "failed to get io resource for lcdc%d \n",lcdc_dev->id); - ret = -ENOENT; - goto err1; - } - lcdc_dev->reg_phy_base = res->start; - lcdc_dev->len = resource_size(res); - mem = request_mem_region(lcdc_dev->reg_phy_base, resource_size(res), pdev->name); - if (mem == NULL) - { - dev_err(&pdev->dev, "failed to request mem region for lcdc%d\n",lcdc_dev->id); - ret = -ENOENT; - goto err1; - } - lcdc_dev->reg_vir_base = ioremap(lcdc_dev->reg_phy_base, resource_size(res)); - if (lcdc_dev->reg_vir_base == NULL) - { - dev_err(&pdev->dev, "cannot map IO\n"); - ret = -ENXIO; - goto err2; - } - - lcdc_dev->preg = (LCDC_REG*)lcdc_dev->reg_vir_base; - printk("lcdc%d:reg_phy_base = 0x%08x,reg_vir_base:0x%p\n",pdev->id,lcdc_dev->reg_phy_base, lcdc_dev->preg); - lcdc_dev->driver.dev=&pdev->dev; - lcdc_dev->driver.screen0 = screen0; //direct out put - lcdc_dev->driver.screen1 = screen1; //out put from scale - lcdc_dev->driver.cur_screen = screen0; - lcdc_dev->driver.screen_ctr_info = screen_ctr_info; - spin_lock_init(&lcdc_dev->reg_lock); - lcdc_dev->irq = platform_get_irq(pdev, 0); - if(lcdc_dev->irq < 0) - { - dev_err(&pdev->dev, "cannot find IRQ\n"); - goto err3; - } - ret = request_irq(lcdc_dev->irq, rk2928_lcdc_isr, IRQF_DISABLED,dev_name(&pdev->dev),lcdc_dev); - if (ret) - { - dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", lcdc_dev->irq, ret); - ret = -EBUSY; - goto err3; - } - - if(screen_ctr_info->set_screen_info) - { - screen_ctr_info->set_screen_info(screen0,screen_ctr_info->lcd_info); - if(SCREEN_NULL==screen0->type) - { - printk(KERN_WARNING "no display device on lcdc%d!?\n",lcdc_dev->id); - ret = -ENODEV; - } - if(screen_ctr_info->io_init) - screen_ctr_info->io_init(NULL); - } - else - { - printk(KERN_WARNING "no display device on lcdc%d!?\n",lcdc_dev->id); - ret = -ENODEV; - goto err4; - } - - ret = rk_fb_register(&(lcdc_dev->driver),&lcdc_driver,lcdc_dev->id); - if(ret < 0) - { - printk(KERN_ERR "register fb for lcdc%d failed!\n",lcdc_dev->id); - goto err4; - } - printk("rk2928 lcdc%d probe ok!\n",lcdc_dev->id); - - return 0; - -err4: - free_irq(lcdc_dev->irq,lcdc_dev); -err3: - iounmap(lcdc_dev->reg_vir_base); -err2: - release_mem_region(lcdc_dev->reg_phy_base,resource_size(res)); -err1: - kfree(screen0); -err0: - platform_set_drvdata(pdev, NULL); - kfree(lcdc_dev); - return ret; - -} -static int __devexit rk2928_lcdc_remove(struct platform_device *pdev) -{ - struct rk2928_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - rk_fb_unregister(&(lcdc_dev->driver)); - rk2928_lcdc_deinit(lcdc_dev); - iounmap(lcdc_dev->reg_vir_base); - release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); - kfree(lcdc_dev->screen); - kfree(lcdc_dev); - return 0; -} - -static void rk2928_lcdc_shutdown(struct platform_device *pdev) -{ - struct rk2928_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - if(lcdc_dev->driver.cur_screen->standby) //standby the screen if necessary - lcdc_dev->driver.cur_screen->standby(1); - if(lcdc_dev->driver.screen_ctr_info->io_disable) //power off the screen if necessary - lcdc_dev->driver.screen_ctr_info->io_disable(); - if(lcdc_dev->driver.cur_screen->sscreen_set) //turn off lvds - lcdc_dev->driver.cur_screen->sscreen_set(lcdc_dev->driver.cur_screen , 0); - //rk_fb_unregister(&(lcdc_dev->driver)); - rk2928_lcdc_deinit(lcdc_dev); - /*iounmap(lcdc_dev->reg_vir_base); - release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); - kfree(lcdc_dev->screen); - kfree(lcdc_dev);*/ -} - - -static struct platform_driver rk2928lcdc_driver = { - .probe = rk2928_lcdc_probe, - .remove = __devexit_p(rk2928_lcdc_remove), - .driver = { - .name = "rk2928-lcdc", - .owner = THIS_MODULE, - }, - .suspend = rk2928_lcdc_suspend, - .resume = rk2928_lcdc_resume, - .shutdown = rk2928_lcdc_shutdown, -}; - -static int __init rk2928_lcdc_init(void) -{ - return platform_driver_register(&rk2928lcdc_driver); -} - -static void __exit rk2928_lcdc_exit(void) -{ - platform_driver_unregister(&rk2928lcdc_driver); -} - - - -fs_initcall(rk2928_lcdc_init); -module_exit(rk2928_lcdc_exit); - - - diff --git a/drivers/video/rockchip/lcdc/rk2928_lcdc.h b/drivers/video/rockchip/lcdc/rk2928_lcdc.h deleted file mode 100644 index 2339a71259bc..000000000000 --- a/drivers/video/rockchip/lcdc/rk2928_lcdc.h +++ /dev/null @@ -1,527 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef RK2928_LCDC_H_ -#define RK2928_LCDC_H_ - -#include - -#define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk)) -#define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val) -#define LcdRdReg(inf, addr) (inf->preg->addr) -#define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk)) -#define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk)) -#define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk)) -#define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val)) -#define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb() - -/******************************************************************** -** ½á¹¹¶¨Òå * -********************************************************************/ -/* LCDCµÄ¼Ä´æÆ÷½á¹¹ */ - -typedef volatile struct tagLCDC_REG -{ - /* offset 0x00~0xc0 */ - unsigned int SYS_CFG; //0x00 system config register - unsigned int DSP_CTRL; //0x0c display control register - unsigned int BG_COLOR; //back ground color register - unsigned int ALPHA_CTRL; //alpha control register - unsigned int INT_STATUS; //0x10 Interrupt status register - unsigned int WIN0_COLOR_KEY_CTRL; //0x1c Win0 blending control register - unsigned int WIN1_COLOR_KEY_CTRL; //0x20 Win1 blending control register - unsigned int WIN0_YRGB_MST; //0x28 Win0 active YRGB memory start address0 - unsigned int WIN0_CBR_MST; //0x2c Win0 active Cbr memory start address0 - unsigned int WIN_VIR; //0x38 WIN0 virtual display width/height - unsigned int WIN0_ACT_INFO; //0x3C Win0 active window width/height - unsigned int WIN0_DSP_INFO; //0x40 Win0 display width/height on panel - unsigned int WIN0_DSP_ST; //0x44 Win0 display start point on panel - unsigned int WIN0_SCL_FACTOR_YRGB; //0x48Win0 YRGB scaling factor setting - unsigned int WIN0_SCL_FACTOR_CBR; //0x4c Win0 YRGB scaling factor setting - unsigned int WIN0_SCL_OFFSET; //0x50 Win0 Cbr scaling start point offset - unsigned int WIN1_RGB_MST; //0x54 Win1 active YRGB memory start address - unsigned int WIN1_DSP_INFO; //0x64 Win1 display width/height on panel - unsigned int WIN1_DSP_ST; //0x68 Win1 display start point on panel - unsigned int HWC_MST; //0x88 HWC memory start address - unsigned int HWC_DSP_ST; //0x8C HWC display start point on panel - unsigned int HWC_COLOR_LUT0; //0x90 Hardware cursor color 2¡¯b01 look up table 0 - unsigned int HWC_COLOR_LUT1; //0x94 Hardware cursor color 2¡¯b10 look up table 1 - unsigned int HWC_COLOR_LUT2; //0x98 Hardware cursor color 2¡¯b11 look up table 2 - unsigned int DSP_HTOTAL_HS_END; //0x9c Panel scanning horizontal width and hsync pulse end point - unsigned int DSP_HACT_ST_END; //0xa0 Panel active horizontal scanning start/end point - unsigned int DSP_VTOTAL_VS_END; //0xa4 Panel scanning vertical height and vsync pulse end point - unsigned int DSP_VACT_ST_END; //0xa8 Panel active vertical scanning start/end point - unsigned int SCL_REG0; //scaler register - unsigned int SCL_REG1; - unsigned int SCL_REG2; - unsigned int SCL_REG3; - unsigned int SCL_REG4; - unsigned int SCL_REG5; - unsigned int SCL_REG6; - unsigned int SCL_REG7; - unsigned int SCL_REG8; - unsigned int reserve[3]; - unsigned int REG_CFG_DONE; //0xc0 REGISTER CONFIG FINISH - -} LCDC_REG, *pLCDC_REG; - - -/* SYS_CONFIG */ - -#define m_W0_EN (1<<0) -#define m_W1_EN (1<<1) -#define m_HWC_EN (1<<2) -#define m_W0_FORMAT (7<<3) -#define m_W1_FORMAT (7<<6) -#define m_W0_RGB_RB_SWAP (1<<10) -#define m_W1_RGB_RB_SWAP (1<<14) - -#define m_W0_AXI_OUTSTANDING_DISABLE (1<<16) -#define m_W1_AXI_OUTSTANDING_DISABLE (1<<17) -#define m_DMA_BURST_LENGTH (3<<18) -#define m_LCDC_STANDBY (1<<22) - -#define m_LCDC_AXICLK_AUTO_ENABLE (1<<24) //eanble for low power -#define m_DSP_OUT_ZERO (1<<25) - -#define v_W0_EN(x) (((x)&1)<<0) -#define v_W1_EN(x) (((x)&1)<<1) -#define v_HWC_EN(x) (((x)&1)<<2) -#define v_W0_FORMAT(x) (((x)&7)<<3) -#define v_W1_FORMAT(x) (((x)&7)<<6) -#define v_W0_RGB_RB_SWAP(x) (((x)&1)<<10) -#define v_W1_RGB_RB_SWAP(x) (((x)&1)<<14) - -#define v_LCDC_STANDBY(x) (((x)&1)<<22) -#define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<24) -#define v_DSP_OUT_ZERO(x) (((x)&1)<<25) - - -#define v_LCDC_DMA_STOP(x) (((x)&1)<<0) -#define v_HWC_RELOAD_EN(x) (((x)&1)<<2) -#define v_W0_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<3) -#define v_W1_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<4) -#define v_W2_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<5) -#define v_DMA_BURST_LENGTH(x) (((x)&3)<<6) -#define v_WIN0_YRGB_CHANNEL0_ID(x) (((x)&7)<<8) -#define v_WIN0_CBR_CHANNEL0_ID(x) (((x)&7)<<11) -#define v_WIN0_YRGB_CHANNEL1_ID(x) (((x)&7)<<14) -#define v_WIN0_CBR_CHANNEL1_ID(x) (((x)&7)<<17) -#define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&7)<<20) -#define v_WIN1_CBR_CHANNEL_ID(x) (((x)&7)<<23) -#define v_WIN2_CHANNEL_ID(x) (((x)&7)<<26) -#define v_HWC_CHANNEL_ID(x) (((x)&7)<<29) - - - -//LCDC_DSP_CTRL_REG -#define m_DISPLAY_FORMAT (3<<0) -#define m_BLANK_MODE (1<<2) -#define m_BLACK_MODE (1<<3) -#define m_HSYNC_POLARITY (1<<4) -#define m_VSYNC_POLARITY (1<<5) -#define m_DEN_POLARITY (1<<6) -#define m_DCLK_POLARITY (1<<7) -#define m_W0W1_POSITION_SWAP (1<<8) -#define m_OUTPUT_BG_SWAP (1<<9) -#define m_OUTPUT_RB_SWAP (1<<10) -#define m_OUTPUT_RG_SWAP (1<<11) -#define m_DITHER_UP_EN (1<<12) -#define m_DITHER_DOWN_MODE (1<<13) -#define m_DITHER_DOWN_EN (1<<14) - - -#define m_W1_INTERLACE_READ_MODE (1<<15) -#define m_W2_INTERLACE_READ_MODE (1<<16) -#define m_W0_YRGB_DEFLICK_MODE (1<<17) -#define m_W0_CBR_DEFLICK_MODE (1<<18) -#define m_W1_YRGB_DEFLICK_MODE (1<<19) -#define m_W1_CBR_DEFLICK_MODE (1<<20) -#define m_W0_ALPHA_MODE (1<<21) -#define m_W1_ALPHA_MODE (1<<22) -#define m_W2_ALPHA_MODE (1<<23) -#define m_W0_COLOR_SPACE_CONVERSION (3<<24) -#define m_W1_COLOR_SPACE_CONVERSION (3<<26) -#define m_W2_COLOR_SPACE_CONVERSION (1<<28) -#define m_YCRCB_CLIP_EN (1<<29) -#define m_CBR_FILTER_656 (1<<30) - -#define v_DISPLAY_FORMAT(x) (((x)&0x3)<<0) -#define v_BLANK_MODE(x) (((x)&1)<<2) -#define v_BLACK_MODE(x) (((x)&1)<<3) -#define v_HSYNC_POLARITY(x) (((x)&1)<<4) -#define v_VSYNC_POLARITY(x) (((x)&1)<<5) -#define v_DEN_POLARITY(x) (((x)&1)<<6) -#define v_DCLK_POLARITY(x) (((x)&1)<<7) -#define v_W0W1_POSITION_SWAP(x) (((x)&1)<<8) -#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<9) -#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<10) -#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<11) -#define v_DITHER_UP_EN(x) (((x)&1)<<12) -#define v_DITHER_DOWN_MODE(x) (((x)&1)<<13) -#define v_DITHER_DOWN_EN(x) (((x)&1)<<14) - -#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12) -#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13) -#define v_W0_INTERLACE_READ_MODE(x) (((x)&1)<<14) -#define v_W1_INTERLACE_READ_MODE(x) (((x)&1)<<15) -#define v_W2_INTERLACE_READ_MODE(x) (((x)&1)<<16) -#define v_W0_YRGB_DEFLICK_MODE(x) (((x)&1)<<17) -#define v_W0_CBR_DEFLICK_MODE(x) (((x)&1)<<18) -#define v_W1_YRGB_DEFLICK_MODE(x) (((x)&1)<<19) -#define v_W1_CBR_DEFLICK_MODE(x) (((x)&1)<<20) -#define v_W0_ALPHA_MODE(x) (((x)&1)<<21) -#define v_W1_ALPHA_MODE(x) (((x)&1)<<22) -#define v_W2_ALPHA_MODE(x) (((x)&1)<<23) -#define v_W0_COLOR_SPACE_CONVERSION(x) (((x)&3)<<24) -#define v_W1_COLOR_SPACE_CONVERSION(x) (((x)&3)<<26) -#define v_W2_COLOR_SPACE_CONVERSION(x) (((x)&1)<<28) -#define v_YCRCB_CLIP_EN(x) (((x)&1)<<29) -#define v_CBR_FILTER_656(x) (((x)&1)<<30) - -//LCDC_BG_COLOR -#define m_BG_COLOR (0xffffff<<0) -#define m_BG_B (0xff<<0) -#define m_BG_G (0xff<<8) -#define m_BG_R (0xff<<16) -#define v_BG_COLOR(x) (((x)&0xffffff)<<0) -#define v_BG_B(x) (((x)&0xff)<<0) -#define v_BG_G(x) (((x)&0xff)<<8) -#define v_BG_R(x) (((x)&0xff)<<16) - - - - -//LCDC_ BLEND_CTRL -#define m_HWC_BLEND_EN (1<<0) -#define m_W2_BLEND_EN (1<<1) -#define m_W1_BLEND_EN (1<<2) -#define m_W0_BLEND_EN (1<<3) -#define m_HWC_BLEND_FACTOR (15<<4) -#define m_W2_BLEND_FACTOR (0xff<<8) -#define m_W1_BLEND_FACTOR (0xff<<16) -#define m_W0_BLEND_FACTOR (0xff<<24) - -#define v_HWC_BLEND_EN(x) (((x)&1)<<0) -#define v_W2_BLEND_EN(x) (((x)&1)<<1) -#define v_W1_BLEND_EN(x) (((x)&1)<<2) -#define v_W0_BLEND_EN(x) (((x)&1)<<3) -#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4) -#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8) -#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16) -#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24) - -//LCDC_INT_STATUS -#define v_HOR_START_INT_STA (1<<0) //status -#define v_FRM_START_INT_STA (1<<1) -#define v_LINE_FLAG_INT_STA (1<<2) -#define v_BUS_ERR_INT_STA (1<<3) -#define m_HOR_START_INT_EN (1<<4) //enable -#define m_FRM_START_INT_EN (1<<5) -#define m_LINE_FLAG_INT_EN (1<<6) -#define m_BUS_ERR_INT_EN (1<<7) -#define m_HOR_START_INT_CLEAR (1<<8) //auto clear -#define m_FRM_START_INT_CLEAR (1<<9) -#define m_LINE_FLAG_INT_CLEAR (1<<10) -#define m_BUS_ERR_INT_CLEAR (1<<11) -#define m_LINE_FLAG_NUM (0xfff<<12) -#define v_HOR_START_INT_EN(x) (((x)&1)<<4) -#define v_FRM_START_INT_EN(x) (((x)&1)<<5) -#define v_LINE_FLAG_INT_EN(x) (((x)&1)<<6) -#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7) -#define v_HOR_START_INT_CLEAR(x) (((x)&1)<<8) -#define v_FRM_START_INT_CLEAR(x) (((x)&1)<<9) -#define v_LINE_FLAG_INT_CLEAR(x) (((x)&1)<<10) -#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11) -#define v_LINE_FLAG_NUM(x) (((x)&0xfff)<<12) - - -//LCDC_WIN_VIR -#define m_WIN0_VIR (0xfff << 0) -#define m_WIN1_VIR (0xfff << 16) -//LCDC_WINx_VIR ,x is number of words of win0 virtual width -#define v_WIN0_ARGB888_VIRWIDTH(x) (x) -#define v_WIN0_RGB888_VIRWIDTH(x) (((x*3)>>2)+((x)%3)) -#define v_WIN0_RGB565_VIRWIDTH(x) (((x)>>1) + ((x%2)?1:0)) -#define v_WIN0_YUV_VIRWIDTH(x) (((x)>>2) +((x%4)?1:0)) - -#define v_WIN1_ARGB888_VIRWIDTH(x) (x << 16) -#define v_WIN1_RGB888_VIRWIDTH(x) ((((x*3)>>2)+((x)%3)) << 16) -#define v_WIN1_RGB565_VIRWIDTH(x) ((((x)>>1) + ((x%2)?1:0)) << 16) -#define v_WIN1_YUV_VIRWIDTH(x) ((((x)>>2) +((x%4)?1:0)) << 16 ) - - -//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL -#define m_KEYCOLOR (0xffffff<<0) -#define m_KEYCOLOR_B (0xff<<0) -#define m_KEYCOLOR_G (0xff<<8) -#define m_KEYCOLOR_R (0xff<<16) -#define m_COLORKEY_EN (1<<24) -#define v_KEYCOLOR(x) (((x)&0xffffff)<<0) -#define v_KEYCOLOR_B(x) (((x)&0xff)<<0) -#define v_KEYCOLOR_G(x) (((x)&0xff)<<8) -#define v_KEYCOLOR_R(x) (((x)&0xff)<<16) -#define v_COLORKEY_EN(x) (((x)&1)<<24) - -//LCDC_DEFLICKER_SCL_OFFSET -#define m_W0_YRGB_VSD_OFFSET (0xff<<0) -#define m_W0_YRGB_VSP_OFFSET (0xff<<8) -#define m_W1_VSD_OFFSET (0xff<<16) -#define m_W1_VSP_OFFSET (0xff<<24) -#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0) -#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8) -#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16) -#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24) - - - - - -//AXI MS ID -#define m_W0_YRGB_CH_ID (0xF<<0) -#define m_W0_CBR_CH_ID (0xF<<4) -#define m_W1_YRGB_CH_ID (0xF<<8) -#define m_W2_CH_ID (0xF<<12) -#define m_HWC_CH_ID (0xF<<16) -#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0) -#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4) -#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8) -#define v_W2_CH_ID(x) (((x)&0xF)<<12) -#define v_HWC_CH_ID(x) (((x)&0xF)<<16) - - -/* Low Bits Mask */ -#define m_WORDLO (0xffff<<0) -#define m_WORDHI (0xffff<<16) -#define v_WORDLO(x) (((x)&0xffff)<<0) -#define v_WORDHI(x) (((x)&0xffff)<<16) - - -//LCDC_WINx_SCL_FACTOR_Y/CBCR -#define v_X_SCL_FACTOR(x) ((x)<<0) -#define v_Y_SCL_FACTOR(x) ((x)<<16) - -//LCDC_DSP_HTOTAL_HS_END -#define v_HSYNC(x) ((x)<<0) //hsync pulse width -#define v_HORPRD(x) ((x)<<16) //horizontal period - - -//LCDC_DSP_HACT_ST_END -#define v_HAEP(x) ((x)<<0) //horizontal active end point -#define v_HASP(x) ((x)<<16) //horizontal active start point - -//LCDC_DSP_VTOTAL_VS_END -#define v_VSYNC(x) ((x)<<0) -#define v_VERPRD(x) ((x)<<16) - -//LCDC_DSP_VACT_ST_END -#define v_VAEP(x) ((x)<<0) -#define v_VASP(x) ((x)<<16) - - - -#define m_ACTWIDTH (0xffff<<0) -#define m_ACTHEIGHT (0xffff<<16) -#define v_ACTWIDTH(x) (((x)&0xffff)<<0) -#define v_ACTHEIGHT(x) (((x)&0xffff)<<16) - -#define m_VIRST_X (0xffff<<0) -#define m_VIRST_Y (0xffff<<16) -#define v_VIRST_X(x) (((x)&0xffff)<<0) -#define v_VIRST_Y(x) (((x)&0xffff)<<16) - -#define m_PANELST_X (0x3ff<<0) -#define m_PANELST_Y (0x3ff<<16) -#define v_PANELST_X(x) (((x)&0x3ff)<<0) -#define v_PANELST_Y(x) (((x)&0x3ff)<<16) - -#define m_PANELWIDTH (0x3ff<<0) -#define m_PANELHEIGHT (0x3ff<<16) -#define v_PANELWIDTH(x) (((x)&0x3ff)<<0) -#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16) - -#define m_HWC_B (0xff<<0) -#define m_HWC_G (0xff<<8) -#define m_HWC_R (0xff<<16) -#define m_W0_YRGB_HSP_OFFSET (0xff<<24) -#define m_W0_YRGB_HSD_OFFSET (0xff<<24) -#define v_HWC_B(x) (((x)&0xff)<<0) -#define v_HWC_G(x) (((x)&0xff)<<8) -#define v_HWC_R(x) (((x)&0xff)<<16) -#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24) -#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24) - -//LCDC_WIN0_ACT_INFO -#define v_ACT_WIDTH(x) ((x-1)<<0) -#define v_ACT_HEIGHT(x) ((x-1)<<16) - -//LCDC_WIN0_DSP_INFO -#define v_DSP_WIDTH(x) ((x-1)<<0) -#define v_DSP_HEIGHT(x) ((x-1)<<16) - -//LCDC_WIN0_DSP_ST //x,y start point of the panel scanning -#define v_DSP_STX(x) (x<<0) -#define v_DSP_STY(x) (x<<16) - -//Panel display scanning -#define m_PANEL_HSYNC_WIDTH (0x3ff<<0) -#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16) -#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0) -#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16) - -#define m_PANEL_END (0x3ff<<0) -#define m_PANEL_START (0x3ff<<16) -#define v_PANEL_END(x) (((x)&0x3ff)<<0) -#define v_PANEL_START(x) (((x)&0x3ff)<<16) - -#define m_PANEL_VSYNC_WIDTH (0x3ff<<0) -#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16) -#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0) -#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16) -//----------- - -#define m_HSCALE_FACTOR (0xffff<<0) -#define m_VSCALE_FACTOR (0xffff<<16) -#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0) -#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16) - -#define m_W0_CBR_HSD_OFFSET (0xff<<0) -#define m_W0_CBR_HSP_OFFSET (0xff<<8) -#define m_W0_CBR_VSD_OFFSET (0xff<<16) -#define m_W0_CBR_VSP_OFFSET (0xff<<24) -#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0) -#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8) -#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16) -#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24) - - -//LCDC_SCL_REG0 -#define m_SCL_DSP_ZERO (1<<4) -#define m_SCL_DEN_INVERT (1<<3) -#define m_SCL_SYNC_INVERT (1<<2) -#define m_SCL_DCLK_INVERT (1<<1) -#define m_SCL_EN (1<<0) -#define v_SCL_DSP_ZERO(x) (((x)&1)<<4) -#define v_SCL_DEN_INVERT(x) (((x)&1)<<3) -#define v_SCL_SYNC_INVERT(x) (((x)&1)<<2) -#define v_SCL_DCLK_INVERT(x) (((x)&1)<<1) -#define v_SCL_EN(x) (((x)&1)<<0) - -//LCDC_SCL_REG1 -#define m_SCL_V_FACTOR (0x3fff<<16) -#define m_SCL_H_FACTOR (0x3fff<<0) -#define v_SCL_V_FACTOR(x) (((x)&0x3fff)<<16) -#define v_SCL_H_FACTOR(x) (((x)&0x3fff)<<0) - - -//LCDC_SCL_REG2 -#define m_SCL_DSP_FRAME_VST (0xfff<<16) -#define m_SCL_DSP_FRAME_HST (0xfff<<0) -#define v_SCL_DSP_FRAME_VST(x) (((x)&0xfff)<<16) -#define v_SCL_DSP_FRAME_HST(x) (((x)&0xfff)<<0) - -//LCDC_SCL_REG3 -#define m_SCL_DSP_HS_END (0xff<<16) -#define m_SCL_DSP_HTOTAL (0xfff<<0) -#define v_SCL_DSP_HS_END(x) (((x)&0xff)<<16) -#define v_SCL_DSP_HTOTAL(x) (((x)&0xfff)<<0) - -//LCDC_SCL_REG4 -#define m_SCL_DSP_HACT_ST (0x3ff<<16) -#define m_SCL_DSP_HACT_END (0xfff<<0) -#define v_SCL_DSP_HACT_ST(x) (((x)&0x3ff)<<16) -#define v_SCL_DSP_HACT_END(x) (((x)&0xfff)<<0) - -//LCDC_SCL_REG5 -#define m_SCL_DSP_VS_END (0xff<<16) -#define m_SCL_DSP_VTOTAL (0xfff<<0) -#define v_SCL_DSP_VS_END(x) (((x)&0xff)<<16) -#define v_SCL_DSP_VTOTAL(x) (((x)&0xfff)<<0) - -//LCDC_SCL_REG6 -#define m_SCL_DSP_VACT_ST (0xff<<16) -#define m_SCL_DSP_VACT_END (0xfff<<0) -#define v_SCL_DSP_VACT_ST(x) (((x)&0xff)<<16) -#define v_SCL_DSP_VACT_END(x) (((x)&0xfff)<<0) - - -//LCDC_SCL_REG7 -#define m_SCL_DSP_HBOR_ST (0x3ff<<16) -#define m_SCL_DSP_HBOR_END (0xfff<<0) -#define v_SCL_DSP_HBOR_ST(x) (((x)&0x3ff)<<16) -#define v_SCL_DSP_HBOR_END(x) (((x)&0xfff)<<0) - -//LCDC_SCL_REG8 - -#define m_SCL_DSP_VBOR_ST (0xff<<16) -#define m_SCL_DSP_VBOR_END (0xfff<<0) -#define v_SCL_DSP_VBOR_ST(x) (((x)&0xff)<<16) -#define v_SCL_DSP_VBOR_END(x) (((x)&0xfff)<<0) - - - - - -#define CalScale(x, y) (((u32)(x)*0x1000)/(y)) -struct rk2928_lcdc_device{ - int id; - struct rk_lcdc_device_driver driver; - rk_screen *screen; - - LCDC_REG *preg; // LCDC reg base address and backup reg - LCDC_REG regbak; - - void __iomem *reg_vir_base; // virtual basic address of lcdc register - u32 reg_phy_base; // physical basic address of lcdc register - u32 len; // physical map length of lcdc register - spinlock_t reg_lock; //one time only one process allowed to config the register - bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed - u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc - unsigned int irq; - - struct clk *pd; //lcdc power domain - struct clk *hclk; //lcdc AHP clk - struct clk *dclk; //lcdc dclk - struct clk *aclk; //lcdc share memory frequency - struct clk *sclk; //scale clk - struct clk *aclk_parent; //lcdc aclk divider frequency source - struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable. - struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable. - struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable. - struct clk *pd_display; // display power domain - u32 pixclock; -}; - -struct lcdc_info{ -/*LCD CLK*/ - struct rk2928_lcdc_device lcdc0; - -}; - - -struct win_set { - volatile u32 y_offset; - volatile u32 c_offset; -}; - -struct win0_par { - u32 refcount; - u32 pseudo_pal[16]; - u32 y_offset; - u32 c_offset; - u32 xpos; //size in panel - u32 ypos; - u32 xsize; //start point in panel - u32 ysize; - enum data_format format; - - wait_queue_head_t wait; - struct win_set mirror; - struct win_set displ; - struct win_set done; - - u8 par_seted; - u8 addr_seted; -}; - -#endif - - diff --git a/drivers/video/rockchip/lcdc/rk3036_lcdc.c b/drivers/video/rockchip/lcdc/rk3036_lcdc.c deleted file mode 100755 index dbaf15bfafe4..000000000000 --- a/drivers/video/rockchip/lcdc/rk3036_lcdc.c +++ /dev/null @@ -1,1688 +0,0 @@ -/* - * drivers/video/rockchip/lcdc/rk3036_lcdc.c - * - * Copyright (C) 2014 ROCKCHIP, Inc. - * Author:zhengyang - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_ION_ROCKCHIP) -#include -#endif -#include "rk3036_lcdc.h" - -static int dbg_thresd; -module_param(dbg_thresd, int, S_IRUGO | S_IWUSR); - -#define DBG(level, x...) do { \ - if (unlikely(dbg_thresd >= level)) \ - dev_info(dev_drv->dev, x); \ - } while (0) - -#define grf_writel(offset, v) do { \ - writel_relaxed(v, RK_GRF_VIRT + offset); \ - dsb(); \ - } while (0) - -static struct rk_lcdc_win lcdc_win[] = { - [0] = { - .name = "win0", - .id = 0, - .support_3d = false, - }, - [1] = { - .name = "win1", - .id = 1, - .support_3d = false, - }, - [2] = { - .name = "hwc", - .id = 2, - .support_3d = false, - }, -}; - -static irqreturn_t rk3036_lcdc_isr(int irq, void *dev_id) -{ - struct lcdc_device *lcdc_dev = - (struct lcdc_device *)dev_id; - ktime_t timestamp = ktime_get(); - u32 int_reg = lcdc_readl(lcdc_dev, INT_STATUS); - - if (int_reg & m_FS_INT_STA) { - timestamp = ktime_get(); - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR, - v_FS_INT_CLEAR(1)); - /*if (lcdc_dev->driver.wait_fs) {*/ - if (0) { - spin_lock(&(lcdc_dev->driver.cpl_lock)); - complete(&(lcdc_dev->driver.frame_done)); - spin_unlock(&(lcdc_dev->driver.cpl_lock)); - } - lcdc_dev->driver.vsync_info.timestamp = timestamp; - wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait); - - } else if (int_reg & m_LF_INT_STA) { - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR, - v_LF_INT_CLEAR(1)); - } - return IRQ_HANDLED; -} - -static int rk3036_lcdc_clk_enable(struct lcdc_device *lcdc_dev) -{ -#ifdef CONFIG_RK_FPGA - lcdc_dev->clk_on = 1; - return 0; -#endif - if (!lcdc_dev->clk_on) { - clk_prepare_enable(lcdc_dev->hclk); - clk_prepare_enable(lcdc_dev->dclk); - clk_prepare_enable(lcdc_dev->aclk); -/* clk_prepare_enable(lcdc_dev->pd);*/ - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 1; - spin_unlock(&lcdc_dev->reg_lock); - } - - return 0; -} - -static int rk3036_lcdc_clk_disable(struct lcdc_device *lcdc_dev) -{ -#ifdef CONFIG_RK_FPGA - lcdc_dev->clk_on = 0; - return 0; -#endif - if (lcdc_dev->clk_on) { - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 0; - spin_unlock(&lcdc_dev->reg_lock); - mdelay(25); - clk_disable_unprepare(lcdc_dev->dclk); - clk_disable_unprepare(lcdc_dev->hclk); - clk_disable_unprepare(lcdc_dev->aclk); -/* clk_disable_unprepare(lcdc_dev->pd);*/ - } - - return 0; -} - -static int rk3036_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv) -{ - u32 mask, val; - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - mask = m_FS_INT_CLEAR | m_FS_INT_EN; - val = v_FS_INT_CLEAR(1) | v_FS_INT_EN(1); - lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val); - return 0; -} -/* -static int rk3036_lcdc_disable_irq(struct lcdc_device *lcdc_dev) -{ - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - mask = m_FS_INT_CLEAR | m_FS_INT_EN; - val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0); - lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val); - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - } - mdelay(1); - return 0; -}*/ - -static void rk_lcdc_read_reg_defalut_cfg(struct lcdc_device - *lcdc_dev) -{ - int reg = 0; - u32 value = 0; - - spin_lock(&lcdc_dev->reg_lock); - for (reg = 0; reg < 0xe0; reg += 4) - value = lcdc_readl(lcdc_dev, reg); - - spin_unlock(&lcdc_dev->reg_lock); -} - -static int rk3036_lcdc_alpha_cfg(struct lcdc_device *lcdc_dev) -{ - int win0_top = 0; - u32 mask, val; - enum data_format win0_format = lcdc_dev->driver.win[0]->area[0].format; - enum data_format win1_format = lcdc_dev->driver.win[1]->area[0].format; - - int win0_alpha_en = ((win0_format == ARGB888) || - (win0_format == ABGR888)) ? 1 : 0; - int win1_alpha_en = ((win1_format == ARGB888) || - (win1_format == ABGR888)) ? 1 : 0; - int atv_layer_cnt = lcdc_dev->driver.win[0]->state + - lcdc_dev->driver.win[1]->state; - u32 *_pv = (u32 *)lcdc_dev->regsbak; - - _pv += (DSP_CTRL0 >> 2); - win0_top = ((*_pv) & (m_WIN0_TOP)) >> 8; - - if (win0_top && (atv_layer_cnt >= 2) && (win0_alpha_en)) { - mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN | - m_WIN1_PREMUL_SCALE; - val = v_WIN0_ALPHA_EN(1) | v_WIN1_ALPHA_EN(0) | - v_WIN1_PREMUL_SCALE(0); - lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val); - - mask = m_WIN0_ALPHA_MODE | m_PREMUL_ALPHA_ENABLE | - m_ALPHA_MODE_SEL1; - val = v_WIN0_ALPHA_MODE(1) | v_PREMUL_ALPHA_ENABLE(1) | - v_ALPHA_MODE_SEL1(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - } else if ((!win0_top) && (atv_layer_cnt >= 2) && - (win1_alpha_en)) { - mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN | - m_WIN1_PREMUL_SCALE; - val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(1) | - v_WIN1_PREMUL_SCALE(0); - lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val); - - mask = m_WIN1_ALPHA_MODE | m_PREMUL_ALPHA_ENABLE | - m_ALPHA_MODE_SEL1; - val = v_WIN1_ALPHA_MODE(1) | v_PREMUL_ALPHA_ENABLE(1) | - v_ALPHA_MODE_SEL1(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - } else { - mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN; - val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(0); - lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val); - } - - if (lcdc_dev->driver.win[2]->state == 1) { - mask = m_HWC_ALPAH_EN; - val = v_HWC_ALPAH_EN(1); - lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val); - - mask = m_HWC_ALPHA_MODE; - val = v_HWC_ALPHA_MODE(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - } else { - mask = m_HWC_ALPAH_EN; - val = v_HWC_ALPAH_EN(0); - lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val); - } - - return 0; -} - -static void lcdc_layer_update_regs(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 mask, val; - int hwc_size; - - if (win->state == 1) { - if (win->id == 0) { - mask = m_WIN0_EN | m_WIN0_FORMAT | m_WIN0_RB_SWAP; - val = v_WIN0_EN(win->state) | - v_WIN0_FORMAT(win->area[0].fmt_cfg) | - v_WIN0_RB_SWAP(win->area[0].swap_rb); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB, - v_X_SCL_FACTOR(win->scale_yrgb_x) | - v_Y_SCL_FACTOR(win->scale_yrgb_y)); - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR, - v_X_SCL_FACTOR(win->scale_cbcr_x) | - v_Y_SCL_FACTOR(win->scale_cbcr_y)); - lcdc_msk_reg(lcdc_dev, WIN0_VIR, - m_YRGB_VIR | m_CBBR_VIR, - v_YRGB_VIR(win->area[0].y_vir_stride) | - v_CBBR_VIR(win->area[0].uv_vir_stride)); - lcdc_writel(lcdc_dev, WIN0_ACT_INFO, - v_ACT_WIDTH(win->area[0].xact) | - v_ACT_HEIGHT(win->area[0].yact)); - lcdc_writel(lcdc_dev, WIN0_DSP_ST, - v_DSP_STX(win->area[0].dsp_stx) | - v_DSP_STY(win->area[0].dsp_sty)); - lcdc_writel(lcdc_dev, WIN0_DSP_INFO, - v_DSP_WIDTH(win->post_cfg.xsize) | - v_DSP_HEIGHT(win->post_cfg.ysize)); - - lcdc_writel(lcdc_dev, WIN0_YRGB_MST, - win->area[0].y_addr); - lcdc_writel(lcdc_dev, WIN0_CBR_MST, - win->area[0].uv_addr); - } else if (win->id == 1) { - mask = m_WIN1_EN | m_WIN1_FORMAT | m_WIN1_RB_SWAP; - val = v_WIN1_EN(win->state) | - v_WIN1_FORMAT(win->area[0].fmt_cfg) | - v_WIN1_RB_SWAP(win->area[0].swap_rb); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_YRGB, - v_X_SCL_FACTOR(win->scale_yrgb_x) | - v_Y_SCL_FACTOR(win->scale_yrgb_y)); - - lcdc_msk_reg(lcdc_dev, WIN1_VIR, m_YRGB_VIR, - v_YRGB_VIR(win->area[0].y_vir_stride)); - lcdc_writel(lcdc_dev, WIN1_ACT_INFO, - v_ACT_WIDTH(win->area[0].xact) | - v_ACT_HEIGHT(win->area[0].yact)); - lcdc_writel(lcdc_dev, WIN1_DSP_INFO, - v_DSP_WIDTH(win->post_cfg.xsize) | - v_DSP_HEIGHT(win->post_cfg.ysize)); - lcdc_writel(lcdc_dev, WIN1_DSP_ST, - v_DSP_STX(win->area[0].dsp_stx) | - v_DSP_STY(win->area[0].dsp_sty)); - lcdc_writel(lcdc_dev, WIN1_MST, win->area[0].y_addr); - } else if (win->id == 2) { - mask = m_HWC_EN | m_HWC_LODAD_EN; - val = v_HWC_EN(win->state) | v_HWC_LODAD_EN(1); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - if ((win->area[0].xsize == 32) && - (win->area[0].ysize == 32)) - hwc_size = 0; - else if ((win->area[0].xsize == 64) && - (win->area[0].ysize == 64)) - hwc_size = 1; - else - dev_err(lcdc_dev->dev, - "unsupport hwc size:x=%d,y=%d\n", - win->area[0].xsize, - win->area[0].ysize); - lcdc_writel(lcdc_dev, HWC_DSP_ST, - v_DSP_STX(win->area[0].dsp_stx) | - v_DSP_STY(win->area[0].dsp_sty)); - lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr); - } - } else { - win->area[0].y_addr = 0; - win->area[0].uv_addr = 0; - if (win->id == 0) { - lcdc_msk_reg(lcdc_dev, - SYS_CTRL, m_WIN0_EN, v_WIN0_EN(0)); - lcdc_writel(lcdc_dev, WIN0_YRGB_MST, - win->area[0].y_addr); - lcdc_writel(lcdc_dev, WIN0_CBR_MST, - win->area[0].uv_addr); - } else if (win->id == 1) { - lcdc_msk_reg(lcdc_dev, - SYS_CTRL, m_WIN1_EN, v_WIN1_EN(0)); - lcdc_writel(lcdc_dev, WIN1_MST, win->area[0].y_addr); - } else if (win->id == 2) { - lcdc_msk_reg(lcdc_dev, - SYS_CTRL, m_HWC_EN | m_HWC_LODAD_EN, - v_HWC_EN(0) | v_HWC_LODAD_EN(0)); - lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr); - } - } - rk3036_lcdc_alpha_cfg(lcdc_dev); -} - -static void lcdc_layer_enable(struct lcdc_device *lcdc_dev, - unsigned int win_id, bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on) && - lcdc_dev->driver.win[win_id]->state != open) { - if (open) { - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, - "wakeup from standby!\n"); - lcdc_dev->standby = 0; - } - lcdc_dev->atv_layer_cnt |= (1 << win_id); - } else if ((lcdc_dev->atv_layer_cnt & (1 << win_id)) && (!open)) { - lcdc_dev->atv_layer_cnt &= ~(1 << win_id); - } - lcdc_dev->driver.win[win_id]->state = open; - if (!open) { - lcdc_layer_update_regs(lcdc_dev, - lcdc_dev->driver.win[win_id]); - lcdc_cfg_done(lcdc_dev); - } - /*if no layer used,disable lcdc*/ - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, - "no layer is used, go to standby!\n"); - lcdc_dev->standby = 1; - } - } - spin_unlock(&lcdc_dev->reg_lock); -} -/* -static int rk3036_lcdc_reg_update(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0]; - struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1]; - int timeout; - unsigned long flags; - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY, - v_LCDC_STANDBY(lcdc_dev->standby)); - lcdc_layer_update_regs(lcdc_dev, win0); - lcdc_layer_update_regs(lcdc_dev, win1); - rk3036_lcdc_alpha_cfg(lcdc_dev); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - if (0) { - spin_lock_irqsave(&dev_drv->cpl_lock, flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock, flags); - timeout = wait_for_completion_timeout(&dev_drv->frame_done, - msecs_to_jiffies - (dev_drv->cur_screen->ft - + 5)); - if (!timeout && (!dev_drv->frame_done.done)) { - dev_warn(lcdc_dev->dev, - "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } - } - DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id); - return 0; -} -*/ -static void rk3036_lcdc_reg_restore(struct lcdc_device *lcdc_dev) -{ - memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0xe0); -} - -static void rk3036_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv) -{ - u32 mask, val; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - /*spin_lock(&lcdc_dev->reg_lock);*/ - if (likely(lcdc_dev->clk_on)) { - mask = m_MMU_EN | m_AXI_MAX_OUTSTANDING_EN | - m_AXI_OUTSTANDING_MAX_NUM; - val = v_MMU_EN(1) | v_AXI_OUTSTANDING_MAX_NUM(31) | - v_AXI_MAX_OUTSTANDING_EN(1); - lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val); - } - /*spin_unlock(&lcdc_dev->reg_lock);*/ -} - -static int rk3036_lcdc_set_hwc_lut(struct rk_lcdc_driver *dev_drv, - int *hwc_lut, int mode) -{ - int i = 0; - int __iomem *c; - int v; - int len = 256*4; - - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - if (dev_drv->hwc_lut == NULL) - dev_drv->hwc_lut = devm_kzalloc(lcdc_dev->dev, len, GFP_KERNEL); - - spin_lock(&lcdc_dev->reg_lock); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(0)); - lcdc_cfg_done(lcdc_dev); - mdelay(25); - for (i = 0; i < 256; i++) { - if (mode == 1) - dev_drv->hwc_lut[i] = hwc_lut[i]; - v = dev_drv->hwc_lut[i]; - c = lcdc_dev->hwc_lut_addr_base + i; - writel_relaxed(v, c); - } - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(1)); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -#if 0 -static int rk3036_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv) -{ -#ifdef CONFIG_RK_FPGA - return 0; -#endif - int ret, fps; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - - ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock); - if (ret) - dev_err(dev_drv->dev, - "set lcdc%d dclk failed\n", lcdc_dev->id); - lcdc_dev->pixclock = - div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - lcdc_dev->driver.pixclock = lcdc_dev->pixclock; - - fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock); - screen->ft = 1000 / fps; - dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ", - lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps); - return 0; -} -#endif -/********do basic init*********/ -static int rk3036_lcdc_pre_init(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - - if (lcdc_dev->pre_init) - return 0; - lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc"); - lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc"); - lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc"); -/* lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc"); */ - - if (/*IS_ERR(lcdc_dev->pd) ||*/ (IS_ERR(lcdc_dev->aclk)) || - (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) { - dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n", - lcdc_dev->id); - } - - rk_disp_pwr_enable(dev_drv); - rk3036_lcdc_clk_enable(lcdc_dev); - - /*backup reg config at uboot*/ - rk_lcdc_read_reg_defalut_cfg(lcdc_dev); - if (lcdc_readl(lcdc_dev, AXI_BUS_CTRL) & m_TVE_DAC_DCLK_EN) - dev_drv->cur_screen->type = SCREEN_TVOUT; - - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_AUTO_GATING_EN, - v_AUTO_GATING_EN(0)); - lcdc_cfg_done(lcdc_dev); - if (dev_drv->iommu_enabled) - /*disable win0 to workaround iommu pagefault*/ - lcdc_layer_enable(lcdc_dev, 0, 0); - lcdc_dev->pre_init = true; - - return 0; -} - -static int rk3036_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen) -{ - int ret = -EINVAL; - int fps; - u16 face = 0; - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u16 right_margin = screen->mode.right_margin; - u16 left_margin = screen->mode.left_margin; - u16 lower_margin = screen->mode.lower_margin; - u16 upper_margin = screen->mode.upper_margin; - u16 x_res = screen->mode.xres; - u16 y_res = screen->mode.yres; - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - switch (screen->type) { - case SCREEN_HDMI: - mask = m_HDMI_DCLK_EN; - val = v_HDMI_DCLK_EN(1); - if (screen->pixelrepeat) { - mask |= m_CORE_CLK_DIV_EN; - val |= v_CORE_CLK_DIV_EN(1); - } else { - mask |= m_CORE_CLK_DIV_EN; - val |= v_CORE_CLK_DIV_EN(0); - } - lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val); - mask = (1 << 4) | (1 << 5) | (1 << 6); - val = (screen->pin_hsync << 4) | - (screen->pin_vsync << 5) | - (screen->pin_den << 6); - grf_writel(RK3036_GRF_SOC_CON2, (mask << 16) | val); - break; - case SCREEN_TVOUT: - mask = m_TVE_DAC_DCLK_EN; - val = v_TVE_DAC_DCLK_EN(1); - if (screen->pixelrepeat) { - mask |= m_CORE_CLK_DIV_EN; - val |= v_CORE_CLK_DIV_EN(1); - } else { - mask |= m_CORE_CLK_DIV_EN; - val |= v_CORE_CLK_DIV_EN(0); - } - lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val); - if ((x_res == 720) && (y_res == 576)) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, - m_TVE_MODE, v_TVE_MODE(TV_PAL)); - } else if ((x_res == 720) && (y_res == 480)) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, - m_TVE_MODE, v_TVE_MODE(TV_NTSC)); - } else { - dev_err(lcdc_dev->dev, - "unsupported video timing!\n"); - return -1; - } - break; - default: - dev_err(lcdc_dev->dev, "un supported interface!\n"); - break; - } - - mask = m_DSP_OUT_FORMAT | m_HSYNC_POL | m_VSYNC_POL | - m_DEN_POL | m_DCLK_POL; - val = v_DSP_OUT_FORMAT(face) | - v_HSYNC_POL(screen->pin_hsync) | - v_VSYNC_POL(screen->pin_vsync) | - v_DEN_POL(screen->pin_den) | - v_DCLK_POL(screen->pin_dclk); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - - mask = m_BG_COLOR | m_DSP_BG_SWAP | m_DSP_RB_SWAP | - m_DSP_RG_SWAP | m_DSP_DELTA_SWAP | - m_DSP_DUMMY_SWAP | m_BLANK_EN; - - val = v_BG_COLOR(0x000000) | v_DSP_BG_SWAP(screen->swap_gb) | - v_DSP_RB_SWAP(screen->swap_rb) | - v_DSP_RG_SWAP(screen->swap_rg) | - v_DSP_DELTA_SWAP(screen->swap_delta) | - v_DSP_DUMMY_SWAP(screen->swap_dumy) | - v_BLANK_EN(0) | - v_BLACK_EN(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - val = - v_HSYNC(screen->mode.hsync_len) | v_HORPRD(screen->mode. - hsync_len + - left_margin + - x_res + - right_margin); - lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END, val); - val = v_HAEP(screen->mode.hsync_len + left_margin + x_res) | - v_HASP(screen->mode.hsync_len + left_margin); - lcdc_writel(lcdc_dev, DSP_HACT_ST_END, val); - - if (screen->mode.vmode & FB_VMODE_INTERLACED) { - /*First Field Timing*/ - lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, - v_VSYNC(screen->mode.vsync_len) | - v_VERPRD(2 * (screen->mode.vsync_len + - upper_margin + lower_margin) - + y_res + 1)); - lcdc_writel(lcdc_dev, DSP_VACT_ST_END, - v_VAEP(screen->mode.vsync_len + - upper_margin + y_res/2) | - v_VASP(screen->mode.vsync_len + - upper_margin)); - /*Second Field Timing*/ - lcdc_writel(lcdc_dev, DSP_VS_ST_END_F1, - v_VSYNC_ST_F1(screen->mode.vsync_len + - upper_margin + y_res/2 + - lower_margin) | - v_VSYNC_END_F1(2 * screen->mode.vsync_len - + upper_margin + y_res/2 + - lower_margin)); - lcdc_writel(lcdc_dev, DSP_VACT_ST_END_F1, - v_VAEP(2 * (screen->mode.vsync_len + - upper_margin) + y_res + - lower_margin + 1) | - v_VASP(2 * (screen->mode.vsync_len + - upper_margin) + y_res/2 + - lower_margin + 1)); - - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, - m_INTERLACE_DSP_EN | - m_INTERLACE_DSP_POL | - m_WIN1_DIFF_DCLK_EN | - m_WIN0_YRGB_DEFLICK_EN | - m_WIN0_CBR_DEFLICK_EN | - m_WIN0_INTERLACE_EN | - m_WIN1_INTERLACE_EN, - v_INTERLACE_DSP_EN(1) | - v_INTERLACE_DSP_POL(0) | - v_WIN1_DIFF_DCLK_EN(1) | - v_WIN0_YRGB_DEFLICK_EN(1) | - v_WIN0_CBR_DEFLICK_EN(1) | - v_WIN0_INTERLACE_EN(1) | - v_WIN1_INTERLACE_EN(1)); - } else { - val = v_VSYNC(screen->mode.vsync_len) | - v_VERPRD(screen->mode.vsync_len + upper_margin + - y_res + lower_margin); - lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, val); - - val = v_VAEP(screen->mode.vsync_len + - upper_margin + y_res) | - v_VASP(screen->mode.vsync_len + - screen->mode.upper_margin); - lcdc_writel(lcdc_dev, DSP_VACT_ST_END, val); - - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, - m_INTERLACE_DSP_EN | - m_WIN1_DIFF_DCLK_EN | - m_WIN0_YRGB_DEFLICK_EN | - m_WIN0_CBR_DEFLICK_EN | - m_WIN0_INTERLACE_EN | - m_WIN1_INTERLACE_EN, - v_INTERLACE_DSP_EN(0) | - v_WIN1_DIFF_DCLK_EN(0) | - v_WIN0_YRGB_DEFLICK_EN(0) | - v_WIN0_CBR_DEFLICK_EN(0) | - v_WIN0_INTERLACE_EN(1) | - v_WIN1_INTERLACE_EN(1)); - } - } - spin_unlock(&lcdc_dev->reg_lock); - - ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock); - if (ret) - dev_err(dev_drv->dev, - "set lcdc%d dclk failed\n", lcdc_dev->id); - lcdc_dev->pixclock = - div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - lcdc_dev->driver.pixclock = lcdc_dev->pixclock; - - fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock); - screen->ft = 1000 / fps; - dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ", - lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps); - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - if (screen->init) - screen->init(); - - return 0; -} - -static int rk3036_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id, - bool open) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - - /*enable clk,when first layer open */ - if ((open) && (!lcdc_dev->atv_layer_cnt)) { - rk3036_lcdc_pre_init(dev_drv); - rk3036_lcdc_clk_enable(lcdc_dev); - if (dev_drv->iommu_enabled) { - if (!dev_drv->mmu_dev) { - dev_drv->mmu_dev = - rk_fb_get_sysmmu_device_by_compatible( - dev_drv->mmu_dts_name); - if (dev_drv->mmu_dev) { - rk_fb_platform_set_sysmmu(dev_drv->mmu_dev, - dev_drv->dev); - } else { - dev_err(dev_drv->dev, - "failed to get iommu device\n" - ); - return -1; - } - } - } - rk3036_lcdc_reg_restore(lcdc_dev); - /*if (dev_drv->iommu_enabled) - rk3036_lcdc_mmu_en(dev_drv);*/ - if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) { - /*rk3036_lcdc_set_dclk(dev_drv);*/ - rk3036_lcdc_enable_irq(dev_drv); - } else { - rk3036_load_screen(dev_drv, 1); - } - } - - if (win_id < ARRAY_SIZE(lcdc_win)) - lcdc_layer_enable(lcdc_dev, win_id, open); - else - dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id); - - /*when all layer closed,disable clk */ -/* - if ((!open) && (!lcdc_dev->atv_layer_cnt)) { - rk3036_lcdc_disable_irq(lcdc_dev); - rk3036_lcdc_reg_update(dev_drv); - if (dev_drv->iommu_enabled) { - if (dev_drv->mmu_dev) - rockchip_iovmm_deactivate(dev_drv->dev); - } - rk3036_lcdc_clk_disable(lcdc_dev); - } -*/ - return 0; -} - -static int rk3036_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - struct rk_lcdc_win *win = NULL; - char fmt[9] = "NULL"; - - if (!screen) { - dev_err(dev_drv->dev, "screen is null!\n"); - return -ENOENT; - } - - if (win_id == 0) { - win = dev_drv->win[0]; - } else if (win_id == 1) { - win = dev_drv->win[1]; - } else if (win_id == 2) { - win = dev_drv->win[2]; - } else { - dev_err(dev_drv->dev, "un supported win number:%d\n", win_id); - return -EINVAL; - } - - spin_lock(&lcdc_dev->reg_lock); - win->post_cfg.xpos = win->area[0].xpos * (dev_drv->overscan.left + - dev_drv->overscan.right)/200 + screen->mode.xres * - (100 - dev_drv->overscan.left) / 200; - - win->post_cfg.ypos = win->area[0].ypos * (dev_drv->overscan.top + - dev_drv->overscan.bottom)/200 + - screen->mode.yres * - (100 - dev_drv->overscan.top) / 200; - win->post_cfg.xsize = win->area[0].xsize * - (dev_drv->overscan.left + - dev_drv->overscan.right)/200; - win->post_cfg.ysize = win->area[0].ysize * - (dev_drv->overscan.top + - dev_drv->overscan.bottom)/200; - - win->area[0].dsp_stx = win->post_cfg.xpos + screen->mode.left_margin + - screen->mode.hsync_len; - if (screen->mode.vmode & FB_VMODE_INTERLACED) { - win->post_cfg.ysize /= 2; - win->area[0].dsp_sty = win->post_cfg.ypos/2 + - screen->mode.upper_margin + - screen->mode.vsync_len; - } else { - win->area[0].dsp_sty = win->post_cfg.ypos + - screen->mode.upper_margin + - screen->mode.vsync_len; - } - win->scale_yrgb_x = calscale(win->area[0].xact, win->post_cfg.xsize); - win->scale_yrgb_y = calscale(win->area[0].yact, win->post_cfg.ysize); - - switch (win->area[0].format) { - case ARGB888: - win->area[0].fmt_cfg = VOP_FORMAT_ARGB888; - win->area[0].swap_rb = 0; - break; - case XBGR888: - win->area[0].fmt_cfg = VOP_FORMAT_ARGB888; - win->area[0].swap_rb = 1; - break; - case ABGR888: - win->area[0].fmt_cfg = VOP_FORMAT_ARGB888; - win->area[0].swap_rb = 1; - break; - case RGB888: - win->area[0].fmt_cfg = VOP_FORMAT_RGB888; - win->area[0].swap_rb = 0; - break; - case RGB565: - win->area[0].fmt_cfg = VOP_FORMAT_RGB565; - win->area[0].swap_rb = 0; - break; - case YUV444: - if (win_id == 0) { - win->area[0].fmt_cfg = VOP_FORMAT_YCBCR444; - win->scale_cbcr_x = calscale(win->area[0].xact, - win->post_cfg.xsize); - win->scale_cbcr_y = calscale(win->area[0].yact, - win->post_cfg.ysize); - win->area[0].swap_rb = 0; - } else { - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", - __func__); - } - break; - case YUV422: - if (win_id == 0) { - win->area[0].fmt_cfg = VOP_FORMAT_YCBCR422; - win->scale_cbcr_x = calscale((win->area[0].xact / 2), - win->post_cfg.xsize); - win->scale_cbcr_y = calscale(win->area[0].yact, - win->post_cfg.ysize); - win->area[0].swap_rb = 0; - } else { - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", - __func__); - } - break; - case YUV420: - if (win_id == 0) { - win->area[0].fmt_cfg = VOP_FORMAT_YCBCR420; - win->scale_cbcr_x = calscale(win->area[0].xact / 2, - win->post_cfg.xsize); - win->scale_cbcr_y = calscale(win->area[0].yact / 2, - win->post_cfg.ysize); - win->area[0].swap_rb = 0; - } else { - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", - __func__); - } - break; - default: - dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n", - __func__); - break; - } - spin_unlock(&lcdc_dev->reg_lock); - - DBG(2, "lcdc%d>>%s\n" - ">>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n" - ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, - __func__, get_format_string(win->area[0].format, fmt), - win->area[0].xact, win->area[0].yact, win->post_cfg.xsize, - win->post_cfg.ysize, win->area[0].xvir, win->area[0].yvir, - win->post_cfg.xpos, win->post_cfg.ypos); - return 0; -} - -static int rk3036_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct rk_lcdc_win *win = NULL; - struct rk_screen *screen = dev_drv->cur_screen; - - if (!screen) { - dev_err(dev_drv->dev, "screen is null!\n"); - return -ENOENT; - } - - if (win_id == 0) { - win = dev_drv->win[0]; - } else if (win_id == 1) { - win = dev_drv->win[1]; - } else if (win_id == 2) { - win = dev_drv->win[2]; - } else { - dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id); - return -EINVAL; - } - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - win->area[0].y_addr = win->area[0].smem_start + - win->area[0].y_offset; - win->area[0].uv_addr = win->area[0].cbr_start + - win->area[0].c_offset; - if (win->area[0].y_addr) - lcdc_layer_update_regs(lcdc_dev, win); - /*lcdc_cfg_done(lcdc_dev);*/ - } - spin_unlock(&lcdc_dev->reg_lock); - - DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n", - lcdc_dev->id, __func__, win->area[0].y_addr, - win->area[0].uv_addr, win->area[0].y_offset); - /* this is the first frame of the system, - enable frame start interrupt*/ - if ((dev_drv->first_frame)) { - dev_drv->first_frame = 0; - rk3036_lcdc_enable_irq(dev_drv); - } - return 0; -} - -static int rk3036_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd, - unsigned long arg, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - u32 panel_size[2]; - void __user *argp = (void __user *)arg; - struct color_key_cfg clr_key_cfg; - - switch (cmd) { - case RK_FBIOGET_PANEL_SIZE: - panel_size[0] = lcdc_dev->screen->mode.xres; - panel_size[1] = lcdc_dev->screen->mode.yres; - if (copy_to_user(argp, panel_size, 8)) - return -EFAULT; - break; - case RK_FBIOPUT_COLOR_KEY_CFG: - if (copy_from_user(&clr_key_cfg, argp, - sizeof(struct color_key_cfg))) - return -EFAULT; - lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, - clr_key_cfg.win0_color_key_cfg); - lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, - clr_key_cfg.win1_color_key_cfg); - break; - - default: - break; - } - return 0; -} - -static int rk3036_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv, - const char *id) -{ - int win_id = 0; - - mutex_lock(&dev_drv->fb_win_id_mutex); - if (!strcmp(id, "fb0")) - win_id = dev_drv->fb0_win_id; - else if (!strcmp(id, "fb1")) - win_id = dev_drv->fb1_win_id; - else if (!strcmp(id, "fb2")) - win_id = dev_drv->fb2_win_id; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return win_id; -} - -static int rk3036_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, - int win_id, - int area_id) -{ - return dev_drv->win[win_id]->state; -} - -static int rk3036_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, - bool set) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0]; - struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1]; - int ovl, needswap = 0; - - if (!swap) { - if (win0->z_order >= 0 && - win1->z_order >= 0 && - win0->z_order > win1->z_order) - needswap = 1; - else - needswap = 0; - } else { - needswap = swap; - } - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - if (set) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_TOP, - v_WIN0_TOP(needswap)); - ovl = swap; - } else { - ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP); - } - } else { - ovl = -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - - return ovl; -} - -static int rk3036_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - if (dev_drv->suspend_flag) - return 0; - dev_drv->suspend_flag = 1; - flush_kthread_worker(&dev_drv->update_regs_worker); - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable) - dev_drv->trsm_ops->disable(); - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, - v_BLANK_EN(1)); - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR, - v_FS_INT_CLEAR(1)); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO, - v_DSP_OUT_ZERO(1)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY, - v_LCDC_STANDBY(1)); - lcdc_cfg_done(lcdc_dev); - if (dev_drv->iommu_enabled) { - if (dev_drv->mmu_dev) - rockchip_iovmm_deactivate(dev_drv->dev); - } - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - rk3036_lcdc_clk_disable(lcdc_dev); - rk_disp_pwr_disable(dev_drv); - return 0; -} - -static int rk3036_lcdc_early_resume(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if (!dev_drv->suspend_flag) - return 0; - rk_disp_pwr_enable(dev_drv); - dev_drv->suspend_flag = 0; - - if (lcdc_dev->atv_layer_cnt) { - rk3036_lcdc_clk_enable(lcdc_dev); - rk3036_lcdc_reg_restore(lcdc_dev); - /*set hwc lut*/ - rk3036_lcdc_set_hwc_lut(dev_drv, dev_drv->hwc_lut, 0); - - spin_lock(&lcdc_dev->reg_lock); - - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO, - v_DSP_OUT_ZERO(0)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY, - v_LCDC_STANDBY(0)); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, - v_BLANK_EN(0)); - lcdc_cfg_done(lcdc_dev); - if (dev_drv->iommu_enabled) { - if (dev_drv->mmu_dev) - rockchip_iovmm_activate(dev_drv->dev); - } - spin_unlock(&lcdc_dev->reg_lock); - } - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - return 0; -} - - -static int rk3036_lcdc_blank(struct rk_lcdc_driver *dev_drv, - int win_id, int blank_mode) -{ - switch (blank_mode) { - case FB_BLANK_UNBLANK: - rk3036_lcdc_early_resume(dev_drv); - break; - case FB_BLANK_NORMAL: - rk3036_lcdc_early_suspend(dev_drv); - break; - default: - rk3036_lcdc_early_suspend(dev_drv); - break; - } - - dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode); - - return 0; -} - -static int rk3036_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int i; - struct rk_lcdc_win *win = NULL; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - if (dev_drv->iommu_enabled) { - if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) { - lcdc_dev->iommu_status = 1; - if (support_uboot_display() && - lcdc_dev->prop == PRMRY) { - lcdc_msk_reg(lcdc_dev, SYS_CTRL, - m_WIN0_EN, - v_WIN0_EN(0)); - } - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY, - v_LCDC_STANDBY(1)); - lcdc_cfg_done(lcdc_dev); - mdelay(50); - rockchip_iovmm_activate(dev_drv->dev); - rk3036_lcdc_mmu_en(dev_drv); - } - } - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY, - v_LCDC_STANDBY(lcdc_dev->standby)); - for (i = 0; i < ARRAY_SIZE(lcdc_win); i++) { - win = dev_drv->win[i]; - if ((win->state == 0) && (win->last_state == 1)) - lcdc_layer_update_regs(lcdc_dev, win); - win->last_state = win->state; - } - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -/* - a:[-30~0]: - sin_hue = sin(a)*256 +0x100; - cos_hue = cos(a)*256; - a:[0~30] - sin_hue = sin(a)*256; - cos_hue = cos(a)*256; -*/ -static int rk3036_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv, - bcsh_hue_mode mode) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 val; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - val = lcdc_readl(lcdc_dev, BCSH_H); - switch (mode) { - case H_SIN: - val &= m_BCSH_SIN_HUE; - break; - case H_COS: - val &= m_BCSH_COS_HUE; - val >>= 8; - break; - default: - break; - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return val; -} - - -static int rk3036_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv, - int sin_hue, int cos_hue) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE; - val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue); - lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int rk3036_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv, - bcsh_bcs_mode mode, int value) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - switch (mode) { - case BRIGHTNESS: - /*from 0 to 255,typical is 128*/ - if (value < 0x20) - value += 0x20; - else if (value >= 0x20) - value = value - 0x20; - mask = m_BCSH_BRIGHTNESS; - val = v_BCSH_BRIGHTNESS(value); - break; - case CONTRAST: - /*from 0 to 510,typical is 256*/ - mask = m_BCSH_CONTRAST; - val = v_BCSH_CONTRAST(value); - break; - case SAT_CON: - /*from 0 to 1015,typical is 256*/ - mask = m_BCSH_SAT_CON; - val = v_BCSH_SAT_CON(value); - break; - default: - break; - } - lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - return val; -} - -static int rk3036_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv, - bcsh_bcs_mode mode) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 val; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - val = lcdc_readl(lcdc_dev, BCSH_BCS); - switch (mode) { - case BRIGHTNESS: - val &= m_BCSH_BRIGHTNESS; - if (val > 0x20) - val -= 0x20; - else if (val == 0x20) - val = -32; - break; - case CONTRAST: - val &= m_BCSH_CONTRAST; - val >>= 8; - break; - case SAT_CON: - val &= m_BCSH_SAT_CON; - val >>= 16; - break; - default: - break; - } - } - spin_unlock(&lcdc_dev->reg_lock); - return val; -} - - -static int rk3036_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - if (open) { - lcdc_writel(lcdc_dev, BCSH_CTRL, - v_BCSH_EN(1) | v_BCSH_OUT_MODE(3)); - lcdc_writel(lcdc_dev, BCSH_BCS, - v_BCSH_BRIGHTNESS(0x00) | - v_BCSH_CONTRAST(0x80) | - v_BCSH_SAT_CON(0x80)); - lcdc_writel(lcdc_dev, BCSH_H, v_BCSH_COS_HUE(0x80)); - } else { - mask = m_BCSH_EN; - val = v_BCSH_EN(0); - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, mask, val); - } - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk3036_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv, - struct overscan *overscan) -{ - int i; - - dev_drv->overscan = *overscan; - for (i = 0; i < dev_drv->lcdc_win_num; i++) { - if (dev_drv->win[i] && dev_drv->win[i]->state) { - rk3036_lcdc_set_par(dev_drv, i); - rk3036_lcdc_pan_display(dev_drv, i); - } - } - rk3036_lcdc_cfg_done(dev_drv); - return 0; -} - -static int rk3036_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order) -{ - struct rk_lcdc_win_area area; - int fb2_win_id, fb1_win_id, fb0_win_id; - - mutex_lock(&dev_drv->fb_win_id_mutex); - if (order == FB_DEFAULT_ORDER) - order = FB0_WIN0_FB1_WIN1_FB2_WIN2; - - fb2_win_id = order / 100; - fb1_win_id = (order / 10) % 10; - fb0_win_id = order % 10; - - if (fb0_win_id != dev_drv->fb0_win_id) { - area = dev_drv->win[(int)dev_drv->fb0_win_id]->area[0]; - dev_drv->win[(int)dev_drv->fb0_win_id]->area[0] = - dev_drv->win[fb0_win_id]->area[0]; - dev_drv->win[fb0_win_id]->area[0] = area; - dev_drv->fb0_win_id = fb0_win_id; - } - dev_drv->fb1_win_id = fb1_win_id; - dev_drv->fb2_win_id = fb2_win_id; - - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return 0; -} - -static int rk3036_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, - bool set) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u64 ft = 0; - u32 dotclk; - int ret; - u32 pixclock; - u32 x_total, y_total; - - if (set) { - ft = div_u64(1000000000000llu, fps); - x_total = - screen->mode.upper_margin + screen->mode.lower_margin + - screen->mode.yres + screen->mode.vsync_len; - y_total = - screen->mode.left_margin + screen->mode.right_margin + - screen->mode.xres + screen->mode.hsync_len; - dev_drv->pixclock = div_u64(ft, x_total * y_total); - dotclk = div_u64(1000000000000llu, dev_drv->pixclock); - ret = clk_set_rate(lcdc_dev->dclk, dotclk); - } - - pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - lcdc_dev->pixclock = pixclock; - dev_drv->pixclock = pixclock; - fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock); - screen->ft = 1000 / fps; /*one frame time in ms */ - - if (set) - dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__, - clk_get_rate(lcdc_dev->dclk), fps); - - return fps; -} - -static int rk3036_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 int_reg; - int ret; - - if (lcdc_dev->clk_on) { - int_reg = lcdc_readl(lcdc_dev, INT_STATUS); - if (int_reg & m_LF_INT_STA) { - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR, - v_LF_INT_CLEAR(1)); - ret = RK_LF_STATUS_FC; - } else { - ret = RK_LF_STATUS_FR; - } - } else { - ret = RK_LF_STATUS_NC; - } - - return ret; -} - -static int rk3036_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv, - unsigned int dsp_addr[][4]) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if (lcdc_dev->clk_on) { - dsp_addr[0][0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST); - dsp_addr[1][0] = lcdc_readl(lcdc_dev, WIN1_MST); - } - return 0; -} - -static ssize_t rk3036_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv, - char *buf, int win_id) -{ - struct rk_lcdc_win *win = NULL; - char fmt[9] = "NULL"; - u32 size; - - if (win_id < ARRAY_SIZE(lcdc_win)) { - win = dev_drv->win[win_id]; - } else { - dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id); - return 0; - } - - size = snprintf(buf, PAGE_SIZE, "win%d: %s\n", win_id, - get_format_string(win->area[0].format, fmt)); - size += snprintf(buf + size, PAGE_SIZE - size, - " xact %d yact %d xvir %d yvir %d\n", - win->area[0].xact, win->area[0].yact, - win->area[0].xvir, win->area[0].yvir); - size += snprintf(buf + size, PAGE_SIZE - size, - " xpos %d ypos %d xsize %d ysize %d\n", - win->area[0].xpos, win->area[0].ypos, - win->area[0].xsize, win->area[0].ysize); - size += snprintf(buf + size, PAGE_SIZE - size, - " yaddr 0x%x uvaddr 0x%x\n", - win->area[0].y_addr, win->area[0].uv_addr); - return size; -} - -static int rk3036_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, - driver); - int *cbase = (int *)lcdc_dev->regs; - int *regsbak = (int *)lcdc_dev->regsbak; - int i, j; - - dev_info(dev_drv->dev, "back up reg:\n"); - for (i = 0; i <= (0xDC >> 4); i++) { - for (j = 0; j < 4; j++) - dev_info(dev_drv->dev, "%08x ", - *(regsbak + i * 4 + j)); - dev_info(dev_drv->dev, "\n"); - } - - dev_info(dev_drv->dev, "lcdc reg:\n"); - for (i = 0; i <= (0xDC >> 4); i++) { - for (j = 0; j < 4; j++) - dev_info(dev_drv->dev, "%08x ", - readl_relaxed(cbase + i * 4 + j)); - dev_info(dev_drv->dev, "\n"); - } - return 0; -} - -static struct rk_lcdc_drv_ops lcdc_drv_ops = { - .open = rk3036_lcdc_open, - .load_screen = rk3036_load_screen, - .set_par = rk3036_lcdc_set_par, - .pan_display = rk3036_lcdc_pan_display, - .blank = rk3036_lcdc_blank, - .ioctl = rk3036_lcdc_ioctl, - .get_win_state = rk3036_lcdc_get_win_state, - .ovl_mgr = rk3036_lcdc_ovl_mgr, - .get_disp_info = rk3036_lcdc_get_disp_info, - .fps_mgr = rk3036_lcdc_fps_mgr, - .fb_get_win_id = rk3036_lcdc_get_win_id, - .fb_win_remap = rk3036_fb_win_remap, - .poll_vblank = rk3036_lcdc_poll_vblank, - .get_dsp_addr = rk3036_lcdc_get_dsp_addr, - .cfg_done = rk3036_lcdc_cfg_done, - .dump_reg = rk3036_lcdc_reg_dump, - .set_dsp_bcsh_hue = rk3036_lcdc_set_bcsh_hue, - .set_dsp_bcsh_bcs = rk3036_lcdc_set_bcsh_bcs, - .get_dsp_bcsh_hue = rk3036_lcdc_get_bcsh_hue, - .get_dsp_bcsh_bcs = rk3036_lcdc_get_bcsh_bcs, - .open_bcsh = rk3036_lcdc_open_bcsh, - .set_overscan = rk3036_lcdc_set_overscan, - .set_hwc_lut = rk3036_lcdc_set_hwc_lut, -}; - -static int rk3036_lcdc_parse_dt(struct lcdc_device *lcdc_dev) -{ - struct device_node *np = lcdc_dev->dev->of_node; - int val; - - if (of_property_read_u32(np, "rockchip,iommu-enabled", &val)) - lcdc_dev->driver.iommu_enabled = 0; - else - lcdc_dev->driver.iommu_enabled = val; - if (of_property_read_u32(np, "rockchip,fb-win-map", &val)) - lcdc_dev->driver.fb_win_map = FB_DEFAULT_ORDER; - else - lcdc_dev->driver.fb_win_map = val; - - return 0; -} - -static int rk3036_lcdc_probe(struct platform_device *pdev) -{ - struct lcdc_device *lcdc_dev = NULL; - struct rk_lcdc_driver *dev_drv; - struct device *dev = &pdev->dev; - struct resource *res; - int ret; - - lcdc_dev = devm_kzalloc(dev, - sizeof(struct lcdc_device), GFP_KERNEL); - if (!lcdc_dev) { - dev_err(&pdev->dev, "rk3036 lcdc device kmalloc fail!"); - return -ENOMEM; - } - platform_set_drvdata(pdev, lcdc_dev); - lcdc_dev->dev = dev; - rk3036_lcdc_parse_dt(lcdc_dev); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - lcdc_dev->reg_phy_base = res->start; - lcdc_dev->len = resource_size(res); - lcdc_dev->regs = devm_ioremap_resource(dev, res); - if (IS_ERR(lcdc_dev->regs)) - return PTR_ERR(lcdc_dev->regs); - - lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL); - if (IS_ERR(lcdc_dev->regsbak)) - return PTR_ERR(lcdc_dev->regsbak); - - lcdc_dev->hwc_lut_addr_base = (lcdc_dev->regs + HWC_LUT_ADDR); - lcdc_dev->prop = PRMRY; - dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id); - dev_drv = &lcdc_dev->driver; - dev_drv->dev = dev; - dev_drv->prop = PRMRY; - dev_drv->id = lcdc_dev->id; - dev_drv->ops = &lcdc_drv_ops; - dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win); - spin_lock_init(&lcdc_dev->reg_lock); - - lcdc_dev->irq = platform_get_irq(pdev, 0); - if (lcdc_dev->irq < 0) { - dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n", - lcdc_dev->id); - return -ENXIO; - } - - ret = devm_request_irq(dev, lcdc_dev->irq, rk3036_lcdc_isr, - IRQF_DISABLED | IRQF_SHARED, - dev_name(dev), lcdc_dev); - if (ret) { - dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", - lcdc_dev->irq, ret); - return ret; - } - - if (dev_drv->iommu_enabled) - strcpy(dev_drv->mmu_dts_name, VOP_IOMMU_COMPATIBLE_NAME); - - ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id); - if (ret < 0) { - dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id); - return ret; - } - lcdc_dev->screen = dev_drv->screen0; - - dev_info(dev, "lcdc probe ok, iommu %s\n", - dev_drv->iommu_enabled ? "enabled" : "disabled"); - - return 0; -} - -#if defined(CONFIG_PM) -static int rk3036_lcdc_suspend(struct platform_device *pdev, - pm_message_t state) -{ - return 0; -} - -static int rk3036_lcdc_resume(struct platform_device *pdev) -{ - return 0; -} -#else -#define rk3036_lcdc_suspend NULL -#define rk3036_lcdc_resume NULL -#endif - -static int rk3036_lcdc_remove(struct platform_device *pdev) -{ - return 0; -} - -static void rk3036_lcdc_shutdown(struct platform_device *pdev) -{ -} - -#if defined(CONFIG_OF) -static const struct of_device_id rk3036_lcdc_dt_ids[] = { - {.compatible = "rockchip,rk3036-lcdc",}, - {} -}; -#endif - -static struct platform_driver rk3036_lcdc_driver = { - .probe = rk3036_lcdc_probe, - .remove = rk3036_lcdc_remove, - .driver = { - .name = "rk3036-lcdc", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(rk3036_lcdc_dt_ids), - }, - .suspend = rk3036_lcdc_suspend, - .resume = rk3036_lcdc_resume, - .shutdown = rk3036_lcdc_shutdown, -}; - -static int __init rk3036_lcdc_module_init(void) -{ - return platform_driver_register(&rk3036_lcdc_driver); -} - -static void __exit rk3036_lcdc_module_exit(void) -{ - platform_driver_unregister(&rk3036_lcdc_driver); -} - -fs_initcall(rk3036_lcdc_module_init); -module_exit(rk3036_lcdc_module_exit); diff --git a/drivers/video/rockchip/lcdc/rk3036_lcdc.h b/drivers/video/rockchip/lcdc/rk3036_lcdc.h deleted file mode 100644 index 330cb0824d51..000000000000 --- a/drivers/video/rockchip/lcdc/rk3036_lcdc.h +++ /dev/null @@ -1,578 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _RK3036_LCDC_H_ -#define _RK3036_LCDC_H_ - -#include -#include -#include - -/*******************register definition**********************/ - -#define SYS_CTRL (0x00) - #define m_WIN0_EN (1<<0) - #define m_WIN1_EN (1<<1) - #define m_HWC_EN (1<<2) - #define m_WIN0_FORMAT (7<<3) - #define m_WIN1_FORMAT (7<<6) - #define m_HWC_LUT_EN (1<<9) - #define m_HWC_SIZE (1<<10) - #define m_WIN0_RB_SWAP (1<<15) - #define m_WIN0_ALPHA_SWAP (1<<16) - #define m_WIN0_Y8_SWAP (1<<17) - #define m_WIN0_UV_SWAP (1<<18) - #define m_WIN1_RB_SWAP (1<<19) - #define m_WIN1_ALPHA_SWAP (1<<20) - #define m_WIN0_OTSD_DISABLE (1<<22) - #define m_WIN1_OTSD_DISABLE (1<<23) - #define m_DMA_BURST_LENGTH (3<<24) - #define m_HWC_LODAD_EN (1<<26) - #define m_DMA_STOP (1<<29) - #define m_LCDC_STANDBY (1<<30) - #define m_AUTO_GATING_EN (1<<31) - - #define v_WIN0_EN(x) (((x)&1)<<0) - #define v_WIN1_EN(x) (((x)&1)<<1) - #define v_HWC_EN(x) (((x)&1)<<2) - #define v_WIN0_FORMAT(x) (((x)&7)<<3) - #define v_WIN1_FORMAT(x) (((x)&7)<<6) - #define v_HWC_LUT_EN(x) (((x)&1)<<9) - #define v_HWC_SIZE(x) (((x)&1)<<10) - #define v_WIN0_RB_SWAP(x) (((x)&1)<<15) - #define v_WIN0_ALPHA_SWAP(x) (((x)&1)<<16) - #define v_WIN0_Y8_SWAP(x) (((x)&1)<<17) - #define v_WIN0_UV_SWAP(x) (((x)&1)<<18) - #define v_WIN1_RB_SWAP(x) (((x)&1)<<19) - #define v_WIN1_ALPHA_SWAP(x) (((x)&1)<<20) - #define v_WIN0_OTSD_DISABLE(x) (((x)&1)<<22) - #define v_WIN1_OTSD_DISABLE(x) (((x)&1)<<23) - #define v_DMA_BURST_LENGTH(x) (((x)&3)<<24) - #define v_HWC_LODAD_EN(x) (((x)&1)<<26) - #define v_WIN1_LUT_EN(x) (((x)&1)<<27) - #define v_DMA_STOP(x) (((x)&1)<<29) - #define v_LCDC_STANDBY(x) (((x)&1)<<30) - #define v_AUTO_GATING_EN(x) (((x)&1)<<31) - -#define DSP_CTRL0 (0x04) - #define m_DSP_OUT_FORMAT (0x0f<<0) - #define m_HSYNC_POL (1<<4) - #define m_VSYNC_POL (1<<5) - #define m_DEN_POL (1<<6) - #define m_DCLK_POL (1<<7) - #define m_WIN0_TOP (1<<8) - #define m_DITHER_UP_EN (1<<9) - #define m_INTERLACE_DSP_EN (1<<12) - #define m_INTERLACE_DSP_POL (1<<13) - #define m_WIN0_INTERLACE_EN (1<<14) - #define m_WIN1_INTERLACE_EN (1<<15) - #define m_WIN0_YRGB_DEFLICK_EN (1<<16) - #define m_WIN0_CBR_DEFLICK_EN (1<<17) - #define m_WIN0_ALPHA_MODE (1<<18) - #define m_WIN1_ALPHA_MODE (1<<19) - #define m_WIN0_CSC_MODE (3<<20) - #define m_WIN0_YUV_CLIP (1<<23) - #define m_TVE_MODE (1<<25) - #define m_HWC_ALPHA_MODE (1<<28) - #define m_PREMUL_ALPHA_ENABLE (1<<29) - #define m_ALPHA_MODE_SEL1 (1<<30) - #define m_WIN1_DIFF_DCLK_EN (1<<31) - - #define v_DSP_OUT_FORMAT(x) (((x)&0x0f)<<0) - #define v_HSYNC_POL(x) (((x)&1)<<4) - #define v_VSYNC_POL(x) (((x)&1)<<5) - #define v_DEN_POL(x) (((x)&1)<<6) - #define v_DCLK_POL(x) (((x)&1)<<7) - #define v_WIN0_TOP(x) (((x)&1)<<8) - #define v_DITHER_UP_EN(x) (((x)&1)<<9) - #define v_INTERLACE_DSP_EN(x) (((x)&1)<<12) - #define v_INTERLACE_DSP_POL(x) (((x)&1)<<13) - #define v_WIN0_INTERLACE_EN(x) (((x)&1)<<14) - #define v_WIN1_INTERLACE_EN(x) (((x)&1)<<15) - #define v_WIN0_YRGB_DEFLICK_EN(x) (((x)&1)<<16) - #define v_WIN0_CBR_DEFLICK_EN(x) (((x)&1)<<17) - #define v_WIN0_ALPHA_MODE(x) (((x)&1)<<18) - #define v_WIN1_ALPHA_MODE(x) (((x)&1)<<19) - #define v_WIN0_CSC_MODE(x) (((x)&3)<<20) - #define v_WIN0_YUV_CLIP(x) (((x)&1)<<23) - #define v_TVE_MODE(x) (((x)&1)<<25) - #define v_HWC_ALPHA_MODE(x) (((x)&1)<<28) - #define v_PREMUL_ALPHA_ENABLE(x) (((x)&1)<<29) - #define v_ALPHA_MODE_SEL1(x) (((x)&1)<<30) - #define v_WIN1_DIFF_DCLK_EN(x) (((x)&1)<<31) - -#define DSP_CTRL1 (0x08) - #define m_BG_COLOR (0xffffff<<0) - #define m_BG_B (0xff<<0) - #define m_BG_G (0xff<<8) - #define m_BG_R (0xff<<16) - #define m_BLANK_EN (1<<24) - #define m_BLACK_EN (1<<25) - #define m_DSP_BG_SWAP (1<<26) - #define m_DSP_RB_SWAP (1<<27) - #define m_DSP_RG_SWAP (1<<28) - #define m_DSP_DELTA_SWAP (1<<29) - #define m_DSP_DUMMY_SWAP (1<<30) - #define m_DSP_OUT_ZERO (1<<31) - - #define v_BG_COLOR(x) (((x)&0xffffff)<<0) - #define v_BG_B(x) (((x)&0xff)<<0) - #define v_BG_G(x) (((x)&0xff)<<8) - #define v_BG_R(x) (((x)&0xff)<<16) - #define v_BLANK_EN(x) (((x)&1)<<24) - #define v_BLACK_EN(x) (((x)&1)<<25) - #define v_DSP_BG_SWAP(x) (((x)&1)<<26) - #define v_DSP_RB_SWAP(x) (((x)&1)<<27) - #define v_DSP_RG_SWAP(x) (((x)&1)<<28) - #define v_DSP_DELTA_SWAP(x) (((x)&1)<<29) - #define v_DSP_DUMMY_SWAP(x) (((x)&1)<<30) - #define v_DSP_OUT_ZERO(x) (((x)&1)<<31) - -#define INT_STATUS (0x10) - #define m_HS_INT_STA (1<<0) /* status */ - #define m_FS_INT_STA (1<<1) - #define m_LF_INT_STA (1<<2) - #define m_BUS_ERR_INT_STA (1<<3) - #define m_HS_INT_EN (1<<4) /* enable */ - #define m_FS_INT_EN (1<<5) - #define m_LF_INT_EN (1<<6) - #define m_BUS_ERR_INT_EN (1<<7) - #define m_HS_INT_CLEAR (1<<8) /* auto clear*/ - #define m_FS_INT_CLEAR (1<<9) - #define m_LF_INT_CLEAR (1<<10) - #define m_BUS_ERR_INT_CLEAR (1<<11) - #define m_LF_INT_NUM (0xfff<<12) - #define m_WIN0_EMPTY_INT_EN (1<<24) - #define m_WIN1_EMPTY_INT_EN (1<<25) - #define m_WIN0_EMPTY_INT_CLEAR (1<<26) - #define m_WIN1_EMPTY_INT_CLEAR (1<<27) - #define m_WIN0_EMPTY_INT_STA (1<<28) - #define m_WIN1_EMPTY_INT_STA (1<<29) - #define m_FS_RAW_STA (1<<30) - #define m_LF_RAW_STA (1<<31) - - #define v_HS_INT_EN(x) (((x)&1)<<4) - #define v_FS_INT_EN(x) (((x)&1)<<5) - #define v_LF_INT_EN(x) (((x)&1)<<6) - #define v_BUS_ERR_INT_EN(x) (((x)&1)<<7) - #define v_HS_INT_CLEAR(x) (((x)&1)<<8) - #define v_FS_INT_CLEAR(x) (((x)&1)<<9) - #define v_LF_INT_CLEAR(x) (((x)&1)<<10) - #define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11) - #define v_LF_INT_NUM(x) (((x)&0xfff)<<12) - #define v_WIN0_EMPTY_INT_EN(x) (((x)&1)<<24) - #define v_WIN1_EMPTY_INT_EN(x) (((x)&1)<<25) - #define v_WIN0_EMPTY_INT_CLEAR(x) (((x)&1)<<26) - #define v_WIN1_EMPTY_INT_CLEAR(x) (((x)&1)<<27) - - -#define ALPHA_CTRL (0x14) - #define m_WIN0_ALPHA_EN (1<<0) - #define m_WIN1_ALPHA_EN (1<<1) - #define m_HWC_ALPAH_EN (1<<2) - #define m_WIN1_PREMUL_SCALE (1<<3) - #define m_WIN0_ALPHA_VAL (0xff<<4) - #define m_WIN1_ALPHA_VAL (0xff<<12) - #define m_HWC_ALPAH_VAL (0xff<<20) - - #define v_WIN0_ALPHA_EN(x) (((x)&1)<<0) - #define v_WIN1_ALPHA_EN(x) (((x)&1)<<1) - #define v_HWC_ALPAH_EN(x) (((x)&1)<<2) - #define v_WIN1_PREMUL_SCALE(x) (((x)&1)<<3) - #define v_WIN0_ALPHA_VAL(x) (((x)&0xff)<<4) - #define v_WIN1_ALPHA_VAL(x) (((x)&0xff)<<12) - #define v_HWC_ALPAH_VAL(x) (((x)&0xff)<<20) - -#define WIN0_COLOR_KEY (0x18) -#define WIN1_COLOR_KEY (0x1C) - #define m_COLOR_KEY_VAL (0xffffff<<0) - #define m_COLOR_KEY_EN (1<<24) - #define v_COLOR_KEY_VAL(x) (((x)&0xffffff)<<0) - #define v_COLOR_KEY_EN(x) (((x)&1)<<24) - -/* Layer Registers */ -#define WIN0_YRGB_MST (0x20) -#define WIN0_CBR_MST (0x24) -#define WIN1_MST (0xa0) -#define HWC_MST (0x58) - -#define WIN1_VIR (0x28) -#define WIN0_VIR (0x30) - #define m_YRGB_VIR (0x1fff << 0) - #define m_CBBR_VIR (0x1fff << 16) - - #define v_YRGB_VIR(x) ((x & 0x1fff) << 0) - #define v_CBBR_VIR(x) ((x & 0x1fff) << 16) - - #define v_ARGB888_VIRWIDTH(x) (((x) & 0x1fff) << 0) - #define v_RGB888_VIRWIDTH(x) (((((x * 3) >> 2)+(x % 3))&0x1fff)<<0) - #define v_RGB565_VIRWIDTH(x) ((DIV_ROUND_UP(x, 2)&0x1fff)<<0) - #define v_YUV_VIRWIDTH(x) ((DIV_ROUND_UP(x, 4)&0x1fff)<<0) - #define v_CBCR_VIR(x) ((x & 0x1fff) << 16) - -#define WIN0_ACT_INFO (0x34) -#define WIN1_ACT_INFO (0xB4) - #define m_ACT_WIDTH (0x1fff << 0) - #define m_ACT_HEIGHT (0x1fff << 16) - #define v_ACT_WIDTH(x) (((x-1) & 0x1fff)<<0) - #define v_ACT_HEIGHT(x) (((x-1) & 0x1fff)<<16) - -#define WIN0_DSP_INFO (0x38) -#define WIN1_DSP_INFO (0xB8) - #define v_DSP_WIDTH(x) (((x-1)&0x7ff)<<0) - #define v_DSP_HEIGHT(x) (((x-1)&0x7ff)<<16) - -#define WIN0_DSP_ST (0x3C) -#define WIN1_DSP_ST (0xBC) -#define HWC_DSP_ST (0x5C) - #define v_DSP_STX(x) (((x)&0xfff)<<0) - #define v_DSP_STY(x) (((x)&0xfff)<<16) - -#define WIN0_SCL_FACTOR_YRGB (0x40) -#define WIN0_SCL_FACTOR_CBR (0x44) -#define WIN1_SCL_FACTOR_YRGB (0xC0) - #define v_X_SCL_FACTOR(x) (((x)&0xffff)<<0) - #define v_Y_SCL_FACTOR(x) (((x)&0xffff)<<16) - -#define WIN0_SCL_OFFSET (0x48) -#define WIN1_SCL_OFFSET (0xC8) - -/* LUT Registers */ -#define WIN1_LUT_ADDR (0x0400) -#define HWC_LUT_ADDR (0x0800) - -/* Display Infomation Registers */ -#define DSP_HTOTAL_HS_END (0x6C) - /*hsync pulse width*/ - #define v_HSYNC(x) (((x)&0xfff)<<0) - /*horizontal period*/ - #define v_HORPRD(x) (((x)&0xfff)<<16) - -#define DSP_HACT_ST_END (0x70) - /*horizontal active end point*/ - #define v_HAEP(x) (((x)&0xfff)<<0) - /*horizontal active start point*/ - #define v_HASP(x) (((x)&0xfff)<<16) - -#define DSP_VTOTAL_VS_END (0x74) - #define v_VSYNC(x) (((x)&0xfff)<<0) - #define v_VERPRD(x) (((x)&0xfff)<<16) - -#define DSP_VACT_ST_END (0x78) - #define v_VAEP(x) (((x)&0xfff)<<0) - #define v_VASP(x) (((x)&0xfff)<<16) - -#define DSP_VS_ST_END_F1 (0x7C) - #define v_VSYNC_END_F1(x) (((x)&0xfff)<<0) - #define v_VSYNC_ST_F1(x) (((x)&0xfff)<<16) -#define DSP_VACT_ST_END_F1 (0x80) - -/*BCSH Registers*/ -#define BCSH_CTRL (0xD0) - #define m_BCSH_EN (1 << 0) - #define m_BCSH_OUT_MODE (3 << 2) - #define m_BCSH_CSC_MODE (3 << 4) - - #define v_BCSH_EN(x) ((1 & x) << 0) - #define v_BCSH_OUT_MODE(x) ((3 & x) << 2) - #define v_BCSH_CSC_MODE(x) ((3 & x) << 4) - -#define BCSH_COLOR_BAR (0xD4) - #define v_BCSH_COLOR_BAR_Y(x) (((x)&0xf) << 0) - #define v_BCSH_COLOR_BAR_U(x) (((x)&0xf) << 8) - #define v_BCSH_COLOR_BAR_V(x) (((x)&0xf) << 16) - - #define m_BCSH_COLOR_BAR_Y (0xf << 0) - #define m_BCSH_COLOR_BAR_U (0xf << 8) - #define m_BCSH_COLOR_BAR_V (0xf << 16) - -#define BCSH_BCS (0xD8) - #define v_BCSH_BRIGHTNESS(x) (((x)&0x3f) << 0) - #define v_BCSH_CONTRAST(x) (((x)&0xff) << 8) - #define v_BCSH_SAT_CON(x) (((x)&0x1ff) << 16) - - #define m_BCSH_BRIGHTNESS (0x3f << 0) - #define m_BCSH_CONTRAST (0xff << 8) - #define m_BCSH_SAT_CON (0x1ff << 16) - -#define BCSH_H (0xDC) - #define v_BCSH_SIN_HUE(x) (((x)&0xff) << 0) - #define v_BCSH_COS_HUE(x) (((x)&0xff) << 8) - - #define m_BCSH_SIN_HUE (0xff << 0) - #define m_BCSH_COS_HUE (0xff << 8) - -/* Bus Register */ -#define AXI_BUS_CTRL (0x2C) - #define m_IO_PAD_CLK (1 << 31) - #define m_CORE_CLK_DIV_EN (1 << 30) - #define m_HDMI_DCLK_INVERT (1 << 23) - #define m_HDMI_DCLK_EN (1 << 22) - #define m_TVE_DAC_DCLK_INVERT (1 << 21) - #define m_TVE_DAC_DCLK_EN (1 << 20) - #define m_HDMI_DCLK_DIV_EN (1 << 19) - #define m_AXI_OUTSTANDING_MAX_NUM (0x1f << 12) - #define m_AXI_MAX_OUTSTANDING_EN (1 << 11) - #define m_MMU_EN (1 << 10) - #define m_NOC_HURRY_THRESHOLD (0xf << 6) - #define m_NOC_HURRY_VALUE (3 << 4) - #define m_NOC_HURRY_EN (1 << 3) - #define m_NOC_QOS_VALUE (3 << 1) - #define m_NOC_QOS_EN (1 << 0) - - #define v_IO_PAD_CLK(x) ((x&1) << 31) - #define v_CORE_CLK_DIV_EN(x) ((x&1) << 30) - #define v_HDMI_DCLK_INVERT(x) ((x&1) << 23) - #define v_HDMI_DCLK_EN(x) ((x&1) << 22) - #define v_TVE_DAC_DCLK_INVERT(x) ((x&1) << 21) - #define v_TVE_DAC_DCLK_EN(x) ((x&1) << 20) - #define v_HDMI_DCLK_DIV_EN(x) ((x&1) << 19) - #define v_AXI_OUTSTANDING_MAX_NUM(x) ((x&0x1f) << 12) - #define v_AXI_MAX_OUTSTANDING_EN(x) ((x&1) << 11) - #define v_MMU_EN(x) ((x&1) << 10) - #define v_NOC_HURRY_THRESHOLD(x) ((x&0xf) << 6) - #define v_NOC_HURRY_VALUE(x) ((x&3) << 4) - #define v_NOC_HURRY_EN(x) ((x&1) << 3) - #define v_NOC_QOS_VALUE(x) ((x&3) << 1) - #define v_NOC_QOS_EN(x) ((x&1) << 0) - -#define GATHER_TRANSFER (0x84) - #define m_WIN1_AXI_GATHER_NUM (0xf << 12) - #define m_WIN0_CBCR_AXI_GATHER_NUM (0x7 << 8) - #define m_WIN0_YRGB_AXI_GATHER_NUM (0xf << 4) - #define m_WIN1_AXI_GAHTER_EN (1 << 2) - #define m_WIN0_CBCR_AXI_GATHER_EN (1 << 1) - #define m_WIN0_YRGB_AXI_GATHER_EN (1 << 0) - - #define v_WIN1_AXI_GATHER_NUM(x) ((x & 0xf) << 12) - #define v_WIN0_CBCR_AXI_GATHER_NUM(x) ((x & 0x7) << 8) - #define v_WIN0_YRGB_AXI_GATHER_NUM(x) ((x & 0xf) << 4) - #define v_WIN1_AXI_GAHTER_EN(x) ((x & 1) << 2) - #define v_WIN0_CBCR_AXI_GATHER_EN(x) ((x & 1) << 1) - #define v_WIN0_YRGB_AXI_GATHER_EN(x) ((x & 1) << 0) - -#define VERSION_INFO (0x94) - #define m_MAJOR (0xff << 24) - #define m_MINOR (0xff << 16) - #define m_BUILD (0xffff) - -#define REG_CFG_DONE (0x90) - -/* TV Control Registers */ -#define TV_CTRL (0x200) -#define TV_SYNC_TIMING (0x204) -#define TV_ACT_TIMING (0x208) -#define TV_ADJ_TIMING (0x20c) -#define TV_FREQ_SC (0x210) -#define TV_FILTER0 (0x214) -#define TV_FILTER1 (0x218) -#define TV_FILTER2 (0x21C) -#define TV_ACT_ST (0x234) -#define TV_ROUTING (0x238) -#define TV_SYNC_ADJUST (0x250) -#define TV_STATUS (0x254) -#define TV_RESET (0x268) -#define TV_SATURATION (0x278) -#define TV_BW_CTRL (0x28C) -#define TV_BRIGHTNESS_CONTRAST (0x290) - - -/* MMU registers */ -#define MMU_DTE_ADDR (0x0300) - #define v_MMU_DTE_ADDR(x) (((x)&0xffffffff)<<0) - #define m_MMU_DTE_ADDR (0xffffffff<<0) - -#define MMU_STATUS (0x0304) - #define v_PAGING_ENABLED(x) (((x)&1)<<0) - #define v_PAGE_FAULT_ACTIVE(x) (((x)&1)<<1) - #define v_STAIL_ACTIVE(x) (((x)&1)<<2) - #define v_MMU_IDLE(x) (((x)&1)<<3) - #define v_REPLAY_BUFFER_EMPTY(x) (((x)&1)<<4) - #define v_PAGE_FAULT_IS_WRITE(x) (((x)&1)<<5) - #define v_PAGE_FAULT_BUS_ID(x) (((x)&0x1f)<<6) - #define m_PAGING_ENABLED (1<<0) - #define m_PAGE_FAULT_ACTIVE (1<<1) - #define m_STAIL_ACTIVE (1<<2) - #define m_MMU_IDLE (1<<3) - #define m_REPLAY_BUFFER_EMPTY (1<<4) - #define m_PAGE_FAULT_IS_WRITE (1<<5) - #define m_PAGE_FAULT_BUS_ID (0x1f<<6) - -#define MMU_COMMAND (0x0308) - #define v_MMU_CMD(x) (((x)&0x3)<<0) - #define m_MMU_CMD (0x3<<0) - -#define MMU_PAGE_FAULT_ADDR (0x030c) - #define v_PAGE_FAULT_ADDR(x) (((x)&0xffffffff)<<0) - #define m_PAGE_FAULT_ADDR (0xffffffff<<0) - -#define MMU_ZAP_ONE_LINE (0x0310) - #define v_MMU_ZAP_ONE_LINE(x) (((x)&0xffffffff)<<0) - #define m_MMU_ZAP_ONE_LINE (0xffffffff<<0) - -#define MMU_INT_RAWSTAT (0x0314) - #define v_PAGE_FAULT_RAWSTAT(x) (((x)&1)<<0) - #define v_READ_BUS_ERROR_RAWSTAT(x) (((x)&1)<<1) - #define m_PAGE_FAULT_RAWSTAT (1<<0) - #define m_READ_BUS_ERROR_RAWSTAT (1<<1) - -#define MMU_INT_CLEAR (0x0318) - #define v_PAGE_FAULT_CLEAR(x) (((x)&1)<<0) - #define v_READ_BUS_ERROR_CLEAR(x) (((x)&1)<<1) - #define m_PAGE_FAULT_CLEAR (1<<0) - #define m_READ_BUS_ERROR_CLEAR (1<<1) - -#define MMU_INT_MASK (0x031c) - #define v_PAGE_FAULT_MASK(x) (((x)&1)<<0) - #define v_READ_BUS_ERROR_MASK(x) (((x)&1)<<1) - #define m_PAGE_FAULT_MASK (1<<0) - #define m_READ_BUS_ERROR_MASK (1<<1) - -#define MMU_INT_STATUS (0x0320) - #define v_PAGE_FAULT_STATUS(x) (((x)&1)<<0) - #define v_READ_BUS_ERROR_STATUS(x) (((x)&1)<<1) - #define m_PAGE_FAULT_STATUS (1<<0) - #define m_READ_BUS_ERROR_STATUS (1<<1) - -#define MMU_AUTO_GATING (0x0324) - #define v_MMU_AUTO_GATING(x) (((x)&1)<<0) - #define m_MMU_AUTO_GATING (1<<0) - -enum _vop_dma_burst { - DMA_BURST_16 = 0, - DMA_BURST_8, - DMA_BURST_4 -}; - -enum _vop_format_e { - VOP_FORMAT_ARGB888 = 0, - VOP_FORMAT_RGB888, - VOP_FORMAT_RGB565, - VOP_FORMAT_YCBCR420 = 4, - VOP_FORMAT_YCBCR422, - VOP_FORMAT_YCBCR444 -}; - -enum _vop_tv_mode { - TV_NTSC, - TV_PAL, -}; - -enum _vop_csc_mode { - VOP_CSC_BT601 = 0, - VOP_CSC_JPEG, - VOP_CSC_BT709 -}; - -enum _vop_hwc_size { - VOP_HWC_SIZE_32, - VOP_HWC_SIZE_64 -}; - -#define calscale(x, y) ((((u32)(x-1))*0x1000)/(y-1)) - -struct lcdc_device { - int id; - struct rk_lcdc_driver driver; - struct device *dev; - struct rk_screen *screen; - - void __iomem *regs; - void *regsbak; /* back up reg */ - u32 reg_phy_base; /* physical basic address of lcdc register*/ - u32 len; /* physical map length of lcdc register*/ - spinlock_t reg_lock; /* one time only one process allowed to - config the register*/ - - int __iomem *hwc_lut_addr_base; - int __iomem *dsp_lut_addr_base; - - - int prop; /*used for primary or */ - /*extended display device*/ - bool pre_init; - bool pwr18; /*if lcdc use 1.8v power supply*/ - bool clk_on; /*if aclk or hclk is closed, - acess to register is not allowed*/ - u8 atv_layer_cnt; /*active layer counter, when - atv_layer_cnt = 0,disable lcdc*/ - - unsigned int irq; - - struct clk *pd; /*lcdc power domain*/ - struct clk *hclk; /*lcdc AHP clk*/ - struct clk *dclk; /*lcdc dclk*/ - struct clk *aclk; /*lcdc share memory frequency*/ - u32 pixclock; - - u32 standby; /*1:standby,0:work*/ - u32 iommu_status; -}; - -static inline -void lcdc_writel(struct lcdc_device *lcdc_dev, u32 offset, u32 v) -{ - u32 *_pv = (u32 *)lcdc_dev->regsbak; - - _pv += (offset >> 2); - *_pv = v; - writel_relaxed(v, lcdc_dev->regs + offset); -} - -static inline -u32 lcdc_readl(struct lcdc_device *lcdc_dev, u32 offset) -{ - u32 v; - u32 *_pv = (u32 *)lcdc_dev->regsbak; - - _pv += (offset >> 2); - v = readl_relaxed(lcdc_dev->regs + offset); - *_pv = v; - return v; -} - -static inline -u32 lcdc_read_bit(struct lcdc_device *lcdc_dev, u32 offset, u32 msk) -{ - u32 _v = readl_relaxed(lcdc_dev->regs + offset); - - _v &= msk; - return _v ? 1 : 0; -} - -static inline -void lcdc_set_bit(struct lcdc_device *lcdc_dev, u32 offset, u32 msk) -{ - u32 *_pv = (u32 *)lcdc_dev->regsbak; - - _pv += (offset >> 2); - (*_pv) |= msk; - writel_relaxed(*_pv, lcdc_dev->regs + offset); -} - -static inline -void lcdc_clr_bit(struct lcdc_device *lcdc_dev, u32 offset, u32 msk) -{ - u32 *_pv = (u32 *)lcdc_dev->regsbak; - - _pv += (offset >> 2); - (*_pv) &= (~msk); - writel_relaxed(*_pv, lcdc_dev->regs + offset); -} - -static inline -void lcdc_msk_reg(struct lcdc_device *lcdc_dev, u32 offset, u32 msk, u32 v) -{ - u32 *_pv = (u32 *)lcdc_dev->regsbak; - - _pv += (offset >> 2); - (*_pv) &= (~msk); - (*_pv) |= v; - writel_relaxed(*_pv, lcdc_dev->regs + offset); -} - -static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev) -{ - writel_relaxed(0x01, lcdc_dev->regs + REG_CFG_DONE); - dsb(); -} - -#endif /* _RK3036_LCDC_H_ */ diff --git a/drivers/video/rockchip/lcdc/rk3066b_lcdc.c b/drivers/video/rockchip/lcdc/rk3066b_lcdc.c deleted file mode 100755 index 44fc4279a02c..000000000000 --- a/drivers/video/rockchip/lcdc/rk3066b_lcdc.c +++ /dev/null @@ -1,1519 +0,0 @@ -/* - * drivers/video/rockchip/chips/rk3066b_lcdc.c - * - * Copyright (C) 2012 ROCKCHIP, Inc. - *Author:yzq - * yxj - *This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "rk3066b_lcdc.h" -#include "../hdmi/rk_hdmi.h" - - - - -static int dbg_thresd = 0; -module_param(dbg_thresd, int, S_IRUGO|S_IWUSR); -#define DBG(level,x...) do { if(unlikely(dbg_thresd >= level)) printk(KERN_INFO x); } while (0) - - -static int rk3066b_lcdc_clk_enable(struct rk3066b_lcdc_device *lcdc_dev) -{ - if(!lcdc_dev->clk_on) - { - clk_enable(lcdc_dev->hclk); - clk_enable(lcdc_dev->dclk); - clk_enable(lcdc_dev->aclk); - clk_enable(lcdc_dev->pd); - - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 1; - spin_unlock(&lcdc_dev->reg_lock); - } - printk("rk3066b lcdc%d clk enable...\n",lcdc_dev->id); - - return 0; -} - -static int rk3066b_lcdc_clk_disable(struct rk3066b_lcdc_device *lcdc_dev) -{ - if(lcdc_dev->clk_on) - { - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 0; - spin_unlock(&lcdc_dev->reg_lock); - mdelay(25); - clk_disable(lcdc_dev->dclk); - clk_disable(lcdc_dev->hclk); - clk_disable(lcdc_dev->aclk); - clk_disable(lcdc_dev->pd); - } - printk("rk3066b lcdc%d clk disable...\n",lcdc_dev->id); - - return 0; -} - -static int rk3066b_lcdc_reg_resume(struct rk3066b_lcdc_device *lcdc_dev) -{ - memcpy((u8*)lcdc_dev->preg, (u8*)&lcdc_dev->regbak, 0x9C); - return 0; -} - -static int init_rk3066b_lcdc(struct rk_lcdc_device_driver *dev_drv) -{ - int i=0; - int __iomem *c; - int v; - - struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); - - if(lcdc_dev->id == 0) //lcdc0 - { - lcdc_dev->pd = clk_get(NULL,"pd_lcdc0"); - lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0"); - lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0"); - lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0"); - } - else if(lcdc_dev->id == 1) - { - lcdc_dev->pd = clk_get(NULL,"pd_lcdc1"); - lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1"); - lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1"); - lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1"); - } - else - { - printk(KERN_ERR "invalid lcdc device!\n"); - return -EINVAL; - } - if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) - { - printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id); - } - - rk3066b_lcdc_clk_enable(lcdc_dev); - - if(lcdc_dev->id == 0) - { - #if defined(CONFIG_RK3066B_LCDC0_IO_18V) - v = 0x40004000; //bit14: 1,1.8v;0,3.3v - writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4); - #else - v = 0x40000000; - writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4); - #endif - } - - if(lcdc_dev->id == 1) //iomux for lcdc1 - { - #if defined(CONFIG_RK3066B_LCDC1_IO_18V) - v = 0x80008000; //bit14: 1,1.8v;0,3.3v - writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4); - #else - v = 0x80000000; - writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4); - #endif - - iomux_set(LCDC1_DCLK); - iomux_set(LCDC1_DEN); - iomux_set(LCDC1_HSYNC); - iomux_set(LCDC1_VSYNC); - iomux_set(LCDC1_D0); - iomux_set(LCDC1_D1); - iomux_set(LCDC1_D2); - iomux_set(LCDC1_D3); - iomux_set(LCDC1_D4); - iomux_set(LCDC1_D5); - iomux_set(LCDC1_D6); - iomux_set(LCDC1_D7); - iomux_set(LCDC1_D8); - iomux_set(LCDC1_D9); - iomux_set(LCDC1_D10); - iomux_set(LCDC1_D11); - iomux_set(LCDC1_D12); - iomux_set(LCDC1_D13); - iomux_set(LCDC1_D14); - iomux_set(LCDC1_D15); - iomux_set(LCDC1_D16); - iomux_set(LCDC1_D17); - iomux_set(LCDC1_D18); - iomux_set(LCDC1_D19); - iomux_set(LCDC1_D20); - iomux_set(LCDC1_D21); - iomux_set(LCDC1_D22); - iomux_set(LCDC1_D23); - - } - LcdMskReg(lcdc_dev,SYS_CFG, m_LCDC_AXICLK_AUTO_ENABLE | m_W0_AXI_OUTSTANDING2 | - m_W1_AXI_OUTSTANDING2,v_LCDC_AXICLK_AUTO_ENABLE(1) | v_W0_AXI_OUTSTANDING2(1) | - v_W1_AXI_OUTSTANDING2(1));//eanble axi-clk auto gating for low power - LcdWrReg(lcdc_dev,AXI_MS_ID,v_HWC_CHANNEL_ID(5) | v_WIN2_CHANNEL_ID(4) | - v_WIN1_YRGB_CHANNEL_ID(3) | v_WIN0_CBR_CHANNEL_ID(2) | - v_WIN0_YRGB_CHANNEL_ID(1)); - LcdMskReg(lcdc_dev, INT_STATUS,m_HOR_STARTMASK| m_FRM_STARTMASK | - m_SCANNING_MASK, v_HOR_STARTMASK(1) | v_FRM_STARTMASK(1) | - v_SCANNING_MASK(1)); //mask all interrupt in init - LcdMskReg(lcdc_dev,FIFO_WATER_MARK,m_WIN1_FIFO_FULL_LEVEL,v_WIN1_FIFO_FULL_LEVEL(0x1e0)); - //LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective - if(dev_drv->cur_screen->dsp_lut) //resume dsp lut - { - LcdMskReg(lcdc_dev,SYS_CFG,m_DSIP_LUT_CTL,v_DSIP_LUT_CTL(0)); - LCDC_REG_CFG_DONE(); - - mdelay(25); //wait for dsp lut disabled - for(i=0;i<256;i++) - { - v = dev_drv->cur_screen->dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base+i; - writel_relaxed(v,c); - } - LcdMskReg(lcdc_dev,SYS_CFG,m_DSIP_LUT_CTL,v_DSIP_LUT_CTL(1));//enable dsp lut - } - - rk3066b_lcdc_clk_disable(lcdc_dev); - return 0; -} - -static int rk3066b_lcdc_deinit(struct rk3066b_lcdc_device *lcdc_dev) -{ - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_dev->clk_on = 0; - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_STARTCLEAR, v_FRM_STARTCLEAR(1)); - LcdMskReg(lcdc_dev, INT_STATUS,m_HOR_STARTMASK| m_FRM_STARTMASK | - m_SCANNING_MASK, v_HOR_STARTMASK(1) | v_FRM_STARTMASK(1) | - v_SCANNING_MASK(1)); //mask all interrupt in init - LcdSetBit(lcdc_dev,SYS_CFG,m_LCDC_STANDBY); - LCDC_REG_CFG_DONE(); - spin_unlock(&lcdc_dev->reg_lock); - } - else //clk already disabled - { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - mdelay(1); - - return 0; -} - -static int rk3066b_load_screen(struct rk_lcdc_device_driver *dev_drv, bool initscreen) -{ - int ret = -EINVAL; - struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); - rk_screen *screen = dev_drv->cur_screen; - u64 ft; - int fps; - u16 face; - u16 mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend; - u16 right_margin = screen->right_margin; - u16 lower_margin = screen->lower_margin; - u16 x_res = screen->x_res, y_res = screen->y_res; - - // set the rgb or mcu - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(screen->type==SCREEN_MCU) - { - LcdMskReg(lcdc_dev, MCU_CTRL, m_MCU_OUTPUT_SELECT,v_MCU_OUTPUT_SELECT(1)); - // set out format and mcu timing - mcu_total = (screen->mcu_wrperiod*150*1000)/1000000; - if(mcu_total>31) - mcu_total = 31; - if(mcu_total<3) - mcu_total = 3; - mcu_rwstart = (mcu_total+1)/4 - 1; - mcu_rwend = ((mcu_total+1)*3)/4 - 1; - mcu_csstart = (mcu_rwstart>2) ? (mcu_rwstart-3) : (0); - mcu_csend = (mcu_rwend>15) ? (mcu_rwend-1) : (mcu_rwend); - - //DBG(1,">> mcu_total=%d, mcu_rwstart=%d, mcu_csstart=%d, mcu_rwend=%d, mcu_csend=%d \n", - // mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend); - - // set horizontal & vertical out timing - - right_margin = x_res/6; - screen->pixclock = 150000000; //mcu fix to 150 MHz - LcdMskReg(lcdc_dev, MCU_CTRL,m_MCU_CS_ST | m_MCU_CS_END| m_MCU_RW_ST | m_MCU_RW_END | - m_MCU_WRITE_PERIOD | m_MCU_HOLDMODE_SELECT | m_MCU_HOLDMODE_FRAME_ST, - v_MCU_CS_ST(mcu_csstart) | v_MCU_CS_END(mcu_csend) | v_MCU_RW_ST(mcu_rwstart) | - v_MCU_RW_END(mcu_rwend) | v_MCU_WRITE_PERIOD(mcu_total) | - v_MCU_HOLDMODE_SELECT((SCREEN_MCU==screen->type)?(1):(0)) | v_MCU_HOLDMODE_FRAME_ST(0)); - - } - - switch (screen->face) - { - case OUT_P565: - face = OUT_P565; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); - break; - case OUT_P666: - face = OUT_P666; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); - break; - case OUT_D888_P565: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); - break; - case OUT_D888_P666: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); - break; - case OUT_P888: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(1)); - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); - break; - default: - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(0)); - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); - face = screen->face; - break; - } - - //use default overlay,set vsyn hsync den dclk polarity - LcdMskReg(lcdc_dev, DSP_CTRL0,m_DISPLAY_FORMAT | m_HSYNC_POLARITY | m_VSYNC_POLARITY | - m_DEN_POLARITY |m_DCLK_POLARITY,v_DISPLAY_FORMAT(face) | - v_HSYNC_POLARITY(screen->pin_hsync) | v_VSYNC_POLARITY(screen->pin_vsync) | - v_DEN_POLARITY(screen->pin_den) | v_DCLK_POLARITY(screen->pin_dclk)); - - //set background color to black,set swap according to the screen panel,disable blank mode - LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE | m_BLACK_MODE | m_BG_COLOR, v_BLANK_MODE(0) | - v_BLACK_MODE(0) | v_BG_COLOR(0x000000)); - LcdMskReg(lcdc_dev,SWAP_CTRL,m_OUTPUT_RB_SWAP | m_OUTPUT_RG_SWAP | m_DELTA_SWAP | m_DUMMY_SWAP, - v_OUTPUT_RB_SWAP(screen->swap_rb) | v_OUTPUT_RG_SWAP(screen->swap_rg) | - v_DELTA_SWAP(screen->swap_delta) | v_DUMMY_SWAP(screen->swap_dumy)); - LcdWrReg(lcdc_dev, DSP_HTOTAL_HS_END,v_HSYNC(screen->hsync_len) | - v_HORPRD(screen->hsync_len + screen->left_margin + x_res + right_margin)); - LcdWrReg(lcdc_dev, DSP_HACT_ST_END, v_HAEP(screen->hsync_len + screen->left_margin + x_res) | - v_HASP(screen->hsync_len + screen->left_margin)); - - LcdWrReg(lcdc_dev, DSP_VTOTAL_VS_END, v_VSYNC(screen->vsync_len) | - v_VERPRD(screen->vsync_len + screen->upper_margin + y_res + lower_margin)); - LcdWrReg(lcdc_dev, DSP_VACT_ST_END, v_VAEP(screen->vsync_len + screen->upper_margin+y_res)| - v_VASP(screen->vsync_len + screen->upper_margin)); - // let above to take effect - //LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - ret = clk_set_rate(lcdc_dev->dclk, screen->pixclock); - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); - } - lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - - - ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* - (dev_drv->pixclock); // one frame time ,(pico seconds) - fps = div64_u64(1000000000000llu,ft); - screen->ft = 1000/fps; - printk("%s: dclk:%lu>>fps:%d ",lcdc_dev->driver.name,clk_get_rate(lcdc_dev->dclk),fps); - - if(screen->init) - { - screen->init(); - } - printk("%s for lcdc%d ok!\n",__func__,lcdc_dev->id); - return 0; -} - -static int mcu_refresh(struct rk3066b_lcdc_device *lcdc_dev) -{ - - return 0; -} - - - -//enable layer,open:1,enable;0 disable -static int win0_open(struct rk3066b_lcdc_device *lcdc_dev,bool open) -{ - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(open) - { - if(!lcdc_dev->atv_layer_cnt) - { - LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); - } - lcdc_dev->atv_layer_cnt++; - } - else - { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.layer_par[0]->state = open; - - LcdMskReg(lcdc_dev, SYS_CFG, m_W0_EN, v_W0_EN(open)); - if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc - { - LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); - } - //LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - printk(KERN_INFO "lcdc%d win0 %s\n",lcdc_dev->id,open?"open":"closed"); - return 0; -} -static int win1_open(struct rk3066b_lcdc_device *lcdc_dev,bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(open) - { - if(!lcdc_dev->atv_layer_cnt) - { - printk("lcdc%d wakeup from stanby\n",lcdc_dev->id); - LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); - } - lcdc_dev->atv_layer_cnt++; - } - else - { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.layer_par[1]->state = open; - - LcdMskReg(lcdc_dev, SYS_CFG, m_W1_EN, v_W1_EN(open)); - if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc - { - printk(KERN_INFO "no layer of lcdc%d is used,go to standby!",lcdc_dev->id); - LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); - } - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - printk(KERN_INFO "lcdc%d win1 %s\n",lcdc_dev->id,open?"open":"closed"); - return 0; -} - - -static int rk3066b_lcdc_blank(struct rk_lcdc_device_driver*lcdc_drv,int layer_id,int blank_mode) -{ - struct rk3066b_lcdc_device * lcdc_dev = container_of(lcdc_drv,struct rk3066b_lcdc_device ,driver); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - switch(blank_mode) - { - case FB_BLANK_UNBLANK: - LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(0)); - break; - case FB_BLANK_NORMAL: - LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(1)); - break; - default: - LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(1)); - break; - } - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - dev_info(lcdc_drv->dev,"blank mode:%d\n",blank_mode); - - return 0; -} - -static int win0_display(struct rk3066b_lcdc_device *lcdc_dev,struct layer_par *par ) -{ - u32 y_addr; - u32 uv_addr; - y_addr = par->smem_start + par->y_offset; - uv_addr = par->cbr_start + par->c_offset; - DBG(2,KERN_INFO "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN0_YRGB_MST,y_addr); - LcdWrReg(lcdc_dev, WIN0_CBR_MST,uv_addr); - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_display(struct rk3066b_lcdc_device *lcdc_dev,struct layer_par *par ) -{ - u32 y_addr; - u32 uv_addr; - y_addr = par->smem_start + par->y_offset; - uv_addr = par->cbr_start + par->c_offset; - DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN1_YRGB_MST, y_addr); - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win0_set_par(struct rk3066b_lcdc_device *lcdc_dev,rk_screen *screen, - struct layer_par *par ) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u32 ScaleYrgbX = 0x1000; - u32 ScaleYrgbY = 0x1000; - u32 ScaleCbrX = 0x1000; - u32 ScaleCbrY = 0x1000; - u8 fmt_cfg =0 ; //data format register config value - char fmt[9] = "NULL"; - xact = par->xact; //active (origin) picture window width/height - yact = par->yact; - xvir = par->xvir; // virtual resolution - yvir = par->yvir; - xpos = par->xpos+screen->left_margin + screen->hsync_len; - ypos = par->ypos+screen->upper_margin + screen->vsync_len; - - DBG(1,"%s for lcdc%d>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - __func__,lcdc_dev->id,get_format_string(par->format,fmt),xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); - - ScaleYrgbX = CalScale(xact, par->xsize); //both RGB and yuv need this two factor - ScaleYrgbY = CalScale(yact, par->ysize); - switch (par->format) - { - case XBGR888: - case ABGR888: - case ARGB888: - fmt_cfg = 0; - break; - case RGB565: - fmt_cfg = 1; - break; - case YUV422:// yuv422 - fmt_cfg = 2; - ScaleCbrX = CalScale((xact/2), par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - case YUV420: // yuv420 - fmt_cfg = 3; - ScaleCbrX = CalScale(xact/2, par->xsize); - ScaleCbrY = CalScale(yact/2, par->ysize); - break; - case YUV444:// yuv444 - fmt_cfg = 4; - ScaleCbrX = CalScale(xact, par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - default: - printk("%s:un supported format\n",__func__); - break; - } - - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_YRGB, v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY)); - LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX)| v_Y_SCL_FACTOR(ScaleCbrY)); - LcdMskReg(lcdc_dev,SYS_CFG, m_W0_FORMAT, v_W0_FORMAT(fmt_cfg)); //(inf->video_mode==0) - LcdWrReg(lcdc_dev, WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact)); - LcdWrReg(lcdc_dev, WIN0_DSP_ST, v_DSP_STX(xpos) | v_DSP_STY(ypos)); - LcdWrReg(lcdc_dev, WIN0_DSP_INFO, v_DSP_WIDTH(par->xsize)| v_DSP_HEIGHT(par->ysize)); - LcdMskReg(lcdc_dev, WIN0_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR, - v_COLORKEY_EN(0) | v_KEYCOLOR(0)); - LcdWrReg(lcdc_dev,WIN0_VIR,v_VIRWIDTH(xvir)); - //LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_set_par(struct rk3066b_lcdc_device *lcdc_dev,rk_screen *screen, - struct layer_par *par ) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u8 fmt_cfg; - char fmt[9]="NULL"; - xact = par->xact; - yact = par->yact; - xvir = par->xvir; - yvir = par->yvir; - xpos = par->xpos+screen->left_margin + screen->hsync_len; - ypos = par->ypos+screen->upper_margin + screen->vsync_len; - - - DBG(1,"%s for lcdc%d>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - __func__,lcdc_dev->id,get_format_string(par->format,fmt),xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); - - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - switch (par->format) - { - case XBGR888: - case ABGR888: - case ARGB888: - fmt_cfg = 0; - break; - case RGB565: - fmt_cfg = 1; - break; - default: - printk("%s:un supported format\n",__func__); - break; - } - - LcdMskReg(lcdc_dev,SYS_CFG, m_W1_FORMAT, v_W1_FORMAT(fmt_cfg)); - LcdWrReg(lcdc_dev, WIN1_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos)); - LcdWrReg(lcdc_dev, WIN1_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize)); - // enable win1 color key and set the color to black(rgb=0) - LcdMskReg(lcdc_dev,WIN1_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,v_COLORKEY_EN(1) | v_KEYCOLOR(0)); - LcdWrReg(lcdc_dev,WIN1_VIR,v_VIRWIDTH(xvir)); - - //LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk3066b_lcdc_open(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open) -{ - int i=0; - int __iomem *c; - int v; - struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); - - if((open) && (!lcdc_dev->atv_layer_cnt)) //enable clk,when first layer open - { - rk3066b_lcdc_clk_enable(lcdc_dev); - rk3066b_lcdc_reg_resume(lcdc_dev); //resume reg - LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); - rk3066b_load_screen(dev_drv,1); - spin_lock(&lcdc_dev->reg_lock); - if(dev_drv->cur_screen->dsp_lut) //resume dsp lut - { - LcdMskReg(lcdc_dev,SYS_CFG,m_DSIP_LUT_CTL,v_DSIP_LUT_CTL(0)); - LCDC_REG_CFG_DONE(); - - mdelay(25); //wait for dsp lut disabled - for(i=0;i<256;i++) - { - v = dev_drv->cur_screen->dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base+i; - writel_relaxed(v,c); - } - LcdMskReg(lcdc_dev,SYS_CFG,m_DSIP_LUT_CTL,v_DSIP_LUT_CTL(1));//enable dsp lut - } - spin_unlock(&lcdc_dev->reg_lock); - } - if(layer_id == 0) - { - win0_open(lcdc_dev,open); - } - else if(layer_id == 1) - { - win1_open(lcdc_dev,open); - } - - if((!open) && (!lcdc_dev->atv_layer_cnt)) //when all layer closed,disable clk - { - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_STARTCLEAR, v_FRM_STARTCLEAR(1)); - LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); - LCDC_REG_CFG_DONE(); - rk3066b_lcdc_clk_disable(lcdc_dev); - } - return 0; -} - -static int rk3066b_lcdc_set_par(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); - struct layer_par *par = NULL; - rk_screen *screen = dev_drv->cur_screen; - if(!screen) - { - printk(KERN_ERR "screen is null!\n"); - return -ENOENT; - } - if(layer_id==0) - { - par = dev_drv->layer_par[0]; - win0_set_par(lcdc_dev,screen,par); - } - else if(layer_id==1) - { - par = dev_drv->layer_par[1]; - win1_set_par(lcdc_dev,screen,par); - } - - return 0; -} - -int rk3066b_lcdc_pan_display(struct rk_lcdc_device_driver * dev_drv,int layer_id) -{ - struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); - struct layer_par *par = NULL; - rk_screen *screen = dev_drv->cur_screen; - unsigned long flags; - int timeout; - if(!screen) - { - printk(KERN_ERR "screen is null!\n"); - return -ENOENT; - } - if(layer_id==0) - { - par = dev_drv->layer_par[0]; - win0_display(lcdc_dev,par); - } - else if(layer_id==1) - { - par = dev_drv->layer_par[1]; - win1_display(lcdc_dev,par); - } - if((dev_drv->first_frame)) //this is the first frame of the system ,enable frame start interrupt - { - dev_drv->first_frame = 0; - LcdMskReg(lcdc_dev,INT_STATUS,m_HOR_STARTMASK | m_FRM_STARTMASK | m_SCANNING_MASK | - m_HOR_STARTCLEAR | m_FRM_STARTCLEAR |m_SCANNING_CLEAR | m_SCAN_LINE_NUM, - v_HOR_STARTMASK(1) | v_FRM_STARTMASK(0) | v_SCANNING_MASK(0) | - v_HOR_STARTCLEAR(1) | v_FRM_STARTCLEAR(1) | v_SCANNING_CLEAR(1) | - //v_SCANNING_CLEAR(screen->vsync_len + screen->upper_margin+screen->y_res -1)); - v_SCAN_LINE_NUM(screen->vsync_len + screen->upper_margin+screen->y_res -1)); - LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective - - } - -#if 0 - if(dev_drv->num_buf < 3) //3buffer ,no need to wait for sysn - { - spin_lock_irqsave(&dev_drv->cpl_lock,flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock,flags); - timeout = wait_for_completion_timeout(&dev_drv->frame_done,msecs_to_jiffies(dev_drv->cur_screen->ft+5)); - if(!timeout&&(!dev_drv->frame_done.done)) - { - printk(KERN_ERR "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } - } -#endif - - return 0; -} - -int rk3066b_lcdc_ioctl(struct rk_lcdc_device_driver * dev_drv,unsigned int cmd, unsigned long arg,int layer_id) -{ - struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); - u32 panel_size[2]; - void __user *argp = (void __user *)arg; - int ret = 0; - switch(cmd) - { - case RK_FBIOGET_PANEL_SIZE: //get panel size - panel_size[0] = lcdc_dev->screen->x_res; - panel_size[1] = lcdc_dev->screen->y_res; - if(copy_to_user(argp, panel_size, 8)) - return -EFAULT; - break; - default: - break; - } - - return ret; -} -static int rk3066b_lcdc_get_layer_state(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); - struct layer_par *par = dev_drv->layer_par[layer_id]; - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) - { - if(layer_id == 0) - { - par->state = LcdReadBit(lcdc_dev,SYS_CFG,m_W0_EN); - } - else if( layer_id == 1) - { - par->state = LcdReadBit(lcdc_dev,SYS_CFG,m_W1_EN); - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return par->state; - -} - -/*********************************** -overlay manager -swap:1 win0 on the top of win1 - 0 win1 on the top of win0 -set : 1 set overlay - 0 get overlay state -************************************/ -static int rk3066b_lcdc_ovl_mgr(struct rk_lcdc_device_driver *dev_drv,int swap,bool set) -{ - struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); - int ovl; - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) - { - if(set) //set overlay - { - LcdMskReg(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP,v_W0W1_POSITION_SWAP(swap)); - LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); - LCDC_REG_CFG_DONE(); - ovl = swap; - } - else //get overlay - { - ovl = LcdReadBit(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP); - } - } - else - { - ovl = -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - - return ovl; -} - -static ssize_t rk3066b_lcdc_get_disp_info(struct rk_lcdc_device_driver *dev_drv,char *buf,int layer_id) - -{ - struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); - char format_w0[9]= "NULL"; - char format_w1[9]= "NULL"; - char status_w0[9]= "NULL"; - char status_w1[9]= "NULL"; - u32 fmt_id = LcdRdReg(lcdc_dev,SYS_CFG); - u32 act_info,dsp_info,dsp_st,factor; - u16 xvir_w0,x_act_w0,y_act_w0,x_dsp_w0,y_dsp_w0,x_st_w0,y_st_w0; - u16 xvir_w1,x_dsp_w1,y_dsp_w1,x_st_w1,y_st_w1; - u16 x_scale,y_scale; - int ovl = LcdReadBit(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP); - - switch((fmt_id&m_W0_FORMAT)>>3) - { - case 0: - strcpy(format_w0,"ARGB888"); - break; - case 1: - strcpy(format_w0,"RGB565"); - break; - case 2: - strcpy(format_w0,"YCbCr422"); - break; - case 3: - strcpy(format_w0,"YCbCr420"); - break; - case 5: - strcpy(format_w0,"YCbCr444"); - break; - default: - strcpy(format_w0,"invalid\n"); - break; - } - - switch((fmt_id&m_W1_FORMAT)>>2) - { - case 0: - strcpy(format_w1,"ARGB888"); - break; - case 1: - strcpy(format_w1,"RGB565"); - break; - default: - strcpy(format_w1,"invalid\n"); - break; - } - - if((fmt_id&m_W0_EN)>>11) - { - strcpy(status_w0,"enabled"); - } - else - { - strcpy(status_w0,"disabled"); - } - - if((fmt_id&m_W1_EN)>>10) - { - strcpy(status_w1,"enabled"); - } - else - { - strcpy(status_w1,"disabled"); - } - - xvir_w0 = LcdRdReg(lcdc_dev,WIN0_VIR)&0xffff; - act_info = LcdRdReg(lcdc_dev,WIN0_ACT_INFO); - dsp_info = LcdRdReg(lcdc_dev,WIN0_DSP_INFO); - dsp_st = LcdRdReg(lcdc_dev,WIN0_DSP_ST); - factor = LcdRdReg(lcdc_dev,WIN0_SCL_FACTOR_YRGB); - x_act_w0 = (act_info&0xffff); - y_act_w0 = (act_info>>16); - x_dsp_w0 = (dsp_info&0x7ff); - y_dsp_w0 = (dsp_info>>16); - x_scale = 4096*100/(factor&0xffff); - y_scale = 4096*100/(factor>>16); - x_st_w0 = dsp_st&0xffff; - y_st_w0 = dsp_st>>16; - - - xvir_w1 = LcdRdReg(lcdc_dev,WIN1_VIR)&0xffff; - dsp_info = LcdRdReg(lcdc_dev,WIN1_DSP_INFO); - dsp_st = LcdRdReg(lcdc_dev,WIN1_DSP_ST); - x_dsp_w1 = dsp_info&0x7ff; - y_dsp_w1 = dsp_info>>16; - x_st_w1 = dsp_st&0xffff; - y_st_w1 = dsp_st>>16; - - return snprintf(buf,PAGE_SIZE, - "win0:%s\n" - "xvir:%d\n" - "xact:%d\n" - "yact:%d\n" - "xdsp:%d\n" - "ydsp:%d\n" - "x_st:%d\n" - "y_st:%d\n" - "x_scale:%d.%d\n" - "y_scale:%d.%d\n" - "format:%s\n" - "YRGB buffer addr:0x%08x\n" - "CBR buffer addr:0x%08x\n\n" - "win1:%s\n" - "xvir:%d\n" - "xdsp:%d\n" - "ydsp:%d\n" - "x_st:%d\n" - "y_st:%d\n" - "format:%s\n" - "YRGB buffer addr:0x%08x\n" - "overlay:%s\n", - status_w0, - xvir_w0, - x_act_w0, - y_act_w0, - x_dsp_w0, - y_dsp_w0, - x_st_w0, - y_st_w0, - x_scale/100, - x_scale%100, - y_scale/100, - y_scale%100, - format_w0, - LcdRdReg(lcdc_dev,WIN0_YRGB_MST), - LcdRdReg(lcdc_dev,WIN0_CBR_MST), - status_w1, - xvir_w1, - x_dsp_w1, - y_dsp_w1, - x_st_w1, - y_st_w1, - format_w1, - LcdRdReg(lcdc_dev,WIN1_YRGB_MST), - ovl ? "win0 on the top of win1\n":"win1 on the top of win0\n"); - return 0; -} - - -/******************************************* -lcdc fps manager,set or get lcdc fps -set:0 get - 1 set -********************************************/ -static int rk3066b_lcdc_fps_mgr(struct rk_lcdc_device_driver *dev_drv,int fps,bool set) -{ - struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); - rk_screen * screen = dev_drv->cur_screen; - u64 ft = 0; - u32 dotclk; - int ret; - - if(set) - { - ft = div_u64(1000000000000llu,fps); - dev_drv->pixclock = div_u64(ft,(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)); - dotclk = div_u64(1000000000000llu,dev_drv->pixclock); - ret = clk_set_rate(lcdc_dev->dclk, dotclk); - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); - } - dev_drv->pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - - } - - ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* - (dev_drv->pixclock); // one frame time ,(pico seconds) - fps = div64_u64(1000000000000llu,ft); - screen->ft = 1000/fps ; //one frame time in ms - return fps; -} - -static int rk3066b_fb_layer_remap(struct rk_lcdc_device_driver *dev_drv, - enum fb_win_map_order order) -{ - mutex_lock(&dev_drv->fb_win_id_mutex); - if(order == FB_DEFAULT_ORDER) - { - order = FB0_WIN0_FB1_WIN1_FB2_WIN2; - } - dev_drv->fb2_win_id = order/100; - dev_drv->fb1_win_id = (order/10)%10; - dev_drv->fb0_win_id = order%10; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - printk("fb0:win%d\nfb1:win%d\nfb2:win%d\n",dev_drv->fb0_win_id,dev_drv->fb1_win_id, - dev_drv->fb2_win_id); - - return 0; -} - -static int rk3066b_fb_get_layer(struct rk_lcdc_device_driver *dev_drv,const char *id) -{ - int layer_id = 0; - mutex_lock(&dev_drv->fb_win_id_mutex); - if(!strcmp(id,"fb0") || !strcmp(id,"fb2")) - { - layer_id = dev_drv->fb0_win_id; - } - else if(!strcmp(id,"fb1") || !strcmp(id,"fb3")) - { - layer_id = dev_drv->fb1_win_id; - } - else - { - printk(KERN_ERR "%s>>un supported %s\n",__func__,id); - layer_id = -1; - } - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return layer_id; -} - - -static void rk3066b_lcdc_reg_dump(struct rk3066b_lcdc_device *lcdc_dev) -{ - int *cbase = (int *)lcdc_dev->reg_vir_base; - int i,j; - - for(i=0; i<=(0xa0>>4);i++) - { - for(j=0;j<4;j++) - printk("%08x ",readl(cbase+i*4 +j)); - printk("\n"); - } - -} - -int rk3066b_lcdc_early_suspend(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); - - if(dev_drv->screen0->standby) - dev_drv->screen0->standby(1); - if(dev_drv->screen_ctr_info->io_disable) - dev_drv->screen_ctr_info->io_disable(); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_dev->clk_on = 0; - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_STARTCLEAR, v_FRM_STARTCLEAR(1)); - LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); - LCDC_REG_CFG_DONE(); - spin_unlock(&lcdc_dev->reg_lock); - } - else //clk already disabled - { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - - rk3066b_lcdc_clk_disable(lcdc_dev); - - return 0; -} - - -int rk3066b_lcdc_early_resume(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); - int i=0; - int __iomem *c; - int v; - - if(dev_drv->screen_ctr_info->io_enable) //power on - dev_drv->screen_ctr_info->io_enable(); - - if(lcdc_dev->atv_layer_cnt) //only resume the lcdc that need to use - { - - rk3066b_lcdc_clk_enable(lcdc_dev); - mdelay(5); - memcpy((u8*)lcdc_dev->preg, (u8*)&lcdc_dev->regbak, 0x24); //resume reg ,skip INT_STATUS reg - memcpy(((u8*)lcdc_dev->preg) + 0x28,((u8*)&lcdc_dev->regbak) + 0x28, 0x74); - - spin_lock(&lcdc_dev->reg_lock); - - if(dev_drv->cur_screen->dsp_lut) //resume dsp lut - { - LcdMskReg(lcdc_dev,SYS_CFG,m_DSIP_LUT_CTL,v_DSIP_LUT_CTL(0)); - LCDC_REG_CFG_DONE(); - - mdelay(25); //wait for dsp lut disabled - for(i=0;i<256;i++) - { - v = dev_drv->cur_screen->dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base+i; - writel_relaxed(v,c); - } - LcdMskReg(lcdc_dev,SYS_CFG,m_DSIP_LUT_CTL,v_DSIP_LUT_CTL(1));//enable dsp lut - } - LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); - LcdMskReg(lcdc_dev, INT_STATUS, m_SCANNING_CLEAR | m_FRM_STARTCLEAR | m_HOR_STARTCLEAR | - m_SCANNING_MASK | m_HOR_STARTMASK | m_FRM_STARTMASK , - v_SCANNING_CLEAR(1) | v_FRM_STARTCLEAR(1) | v_HOR_STARTCLEAR(1) | - v_SCANNING_MASK(0) | v_FRM_STARTMASK(0) | v_HOR_STARTMASK(1)); - LCDC_REG_CFG_DONE(); - - spin_unlock(&lcdc_dev->reg_lock); - - } - - if(dev_drv->screen0->standby) - dev_drv->screen0->standby(0); //screen wake up - - return 0; -} - -static int no_report(struct rk3066b_lcdc_device *lcdc_dev) -{ - struct rk_lcdc_device_driver *dev = &(lcdc_dev->driver); - static u32 lcdc0_old_addr = 0,cur_addr = 0; - static u32 mode = 0,num = 0; - static u32 cur_state = 0,old_state = 0; - - if(dev->screen_ctr_info->prop == PRMRY){ - cur_addr = LcdRdReg(lcdc_dev,WIN0_YRGB_MST); - if(lcdc0_old_addr != cur_addr){ - if(cur_state++ > 10000) - cur_state = 0; - - lcdc0_old_addr = cur_addr; - } - } - - if(old_state == cur_state){ - if(num++>10 && mode != 0) - mode = 0; - } - else{ - mode = 1; - num = 0; - } - - if(mode == 1 && old_state == cur_state){ - return -1; - } - - old_state = cur_state; - - return 0; -} - -static irqreturn_t rk3066b_lcdc_isr(int irq, void *dev_id) -{ - struct rk3066b_lcdc_device *lcdc_dev = (struct rk3066b_lcdc_device *)dev_id; - - u32 int_reg = LcdRdReg(lcdc_dev,INT_STATUS); - if(int_reg & m_FRM_START){ - ktime_t timestamp = ktime_get(); - - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_STARTCLEAR, v_FRM_STARTCLEAR(1)); - -#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER) - if(hdmi_get_hotplug() == HDMI_HPD_ACTIVED){ - if(no_report(lcdc_dev)){ - return IRQ_HANDLED; - } - } -#endif - //LcdMskReg(lcdc_dev, INT_STATUS, m_LINE_FLAG_INT_CLEAR, v_LINE_FLAG_INT_CLEAR(1)); - -#if 0 - if(lcdc_dev->driver.num_buf < 3) //three buffer ,no need to wait for sync - { - spin_lock(&(lcdc_dev->driver.cpl_lock)); - complete(&(lcdc_dev->driver.frame_done)); - spin_unlock(&(lcdc_dev->driver.cpl_lock)); - } -#endif - - lcdc_dev->driver.vsync_info.timestamp = timestamp; - wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait); - } - else if(int_reg & m_SCANNING_FLAG){ - LcdMskReg(lcdc_dev, INT_STATUS, m_SCANNING_CLEAR, v_SCANNING_CLEAR(1)); - } - return IRQ_HANDLED; -} - - -static int rk3066b_set_dsp_lut(struct rk_lcdc_device_driver *dev_drv,int *lut) -{ - int i=0; - int __iomem *c; - int v; - int ret = 0; - - struct rk3066b_lcdc_device *lcdc_dev = - container_of(dev_drv,struct rk3066b_lcdc_device,driver); - LcdMskReg(lcdc_dev,SYS_CFG,m_DSIP_LUT_CTL,v_DSIP_LUT_CTL(0)); - LCDC_REG_CFG_DONE(); - msleep(25); - if(dev_drv->cur_screen->dsp_lut) - { - for(i=0;i<256;i++) - { - v = dev_drv->cur_screen->dsp_lut[i] = lut[i]; - c = lcdc_dev->dsp_lut_addr_base+i; - writel_relaxed(v,c); - } - } - else - { - dev_err(dev_drv->dev,"no buffer to backup lut data!\n"); - ret = -1; - } - LcdMskReg(lcdc_dev,SYS_CFG,m_DSIP_LUT_CTL,v_DSIP_LUT_CTL(1)); - LCDC_REG_CFG_DONE(); - - return ret; -} - -int rk3066b_lcdc_poll_vblank(struct rk_lcdc_device_driver * dev_drv) -{ - struct rk3066b_lcdc_device *lcdc_dev = - container_of(dev_drv,struct rk3066b_lcdc_device,driver); - u32 int_reg ; - int ret; - //spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) - { - int_reg = LcdRdReg(lcdc_dev,INT_STATUS); - if(int_reg & m_SCANNING_FLAG) - { - LcdMskReg(lcdc_dev, INT_STATUS, m_SCANNING_CLEAR,v_SCANNING_CLEAR(1)); - ret = RK_LF_STATUS_FC; - } - else - ret = RK_LF_STATUS_FR; - } - else - { - ret = RK_LF_STATUS_NC; - } - //spin_unlock(&lcdc_dev->reg_lock); - - - return ret; -} - -static struct layer_par lcdc_layer[] = { - [0] = { - .name = "win0", - .id = 0, - .support_3d = true, - }, - [1] = { - .name = "win1", - .id = 1, - .support_3d = false, - }, -}; - -static struct rk_lcdc_device_driver lcdc_driver = { - .name = "lcdc", - .def_layer_par = lcdc_layer, - .num_layer = ARRAY_SIZE(lcdc_layer), - .open = rk3066b_lcdc_open, - .init_lcdc = init_rk3066b_lcdc, - .ioctl = rk3066b_lcdc_ioctl, - .suspend = rk3066b_lcdc_early_suspend, - .resume = rk3066b_lcdc_early_resume, - .set_par = rk3066b_lcdc_set_par, - .blank = rk3066b_lcdc_blank, - .pan_display = rk3066b_lcdc_pan_display, - .load_screen = rk3066b_load_screen, - .get_layer_state = rk3066b_lcdc_get_layer_state, - .ovl_mgr = rk3066b_lcdc_ovl_mgr, - .get_disp_info = rk3066b_lcdc_get_disp_info, - .fps_mgr = rk3066b_lcdc_fps_mgr, - .fb_get_layer = rk3066b_fb_get_layer, - .fb_layer_remap = rk3066b_fb_layer_remap, - .set_dsp_lut = rk3066b_set_dsp_lut, - .poll_vblank = rk3066b_lcdc_poll_vblank, -}; -#ifdef CONFIG_PM -static int rk3066b_lcdc_suspend(struct platform_device *pdev, pm_message_t state) -{ - return 0; -} - -static int rk3066b_lcdc_resume(struct platform_device *pdev) -{ - return 0; -} - -#else -#define rk3066b_lcdc_suspend NULL -#define rk3066b_lcdc_resume NULL -#endif - -static int __devinit rk3066b_lcdc_probe (struct platform_device *pdev) -{ - struct rk3066b_lcdc_device *lcdc_dev=NULL; - rk_screen *screen; - rk_screen *screen1; - struct rk29fb_info *screen_ctr_info; - struct resource *res = NULL; - struct resource *mem; - int ret = 0; - - /*************Malloc rk3066blcdc_inf and set it to pdev for drvdata**********/ - lcdc_dev = kzalloc(sizeof(struct rk3066b_lcdc_device), GFP_KERNEL); - if(!lcdc_dev) - { - dev_err(&pdev->dev, ">>rk3066b lcdc device kmalloc fail!"); - return -ENOMEM; - } - platform_set_drvdata(pdev, lcdc_dev); - lcdc_dev->id = pdev->id; - screen_ctr_info = (struct rk29fb_info * )pdev->dev.platform_data; - screen = kzalloc(sizeof(rk_screen), GFP_KERNEL); - if(!screen) - { - dev_err(&pdev->dev, ">>rk3066b lcdc screen kmalloc fail!"); - ret = -ENOMEM; - goto err0; - } - else - { - lcdc_dev->screen = screen; - } - screen->lcdc_id = lcdc_dev->id; - screen->screen_id = 0; - -#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& (defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS)) - screen1 = kzalloc(sizeof(rk_screen), GFP_KERNEL); - if(!screen1) - { - dev_err(&pdev->dev, ">>rk3066b lcdc screen1 kmalloc fail!"); - ret = -ENOMEM; - goto err0; - } - screen1->lcdc_id = 1; - screen1->screen_id = 1; - printk("use lcdc%d and rk610 implemention dual display!\n",lcdc_dev->id); - -#endif - /****************get lcdc0 reg *************************/ - res = platform_get_resource(pdev, IORESOURCE_MEM,0); - if (res == NULL) - { - dev_err(&pdev->dev, "failed to get io resource for lcdc%d \n",lcdc_dev->id); - ret = -ENOENT; - goto err1; - } - lcdc_dev->reg_phy_base = res->start; - lcdc_dev->len = resource_size(res); - mem = request_mem_region(lcdc_dev->reg_phy_base, resource_size(res), pdev->name); - if (mem == NULL) - { - dev_err(&pdev->dev, "failed to request mem region for lcdc%d\n",lcdc_dev->id); - ret = -ENOENT; - goto err1; - } - lcdc_dev->reg_vir_base = ioremap(lcdc_dev->reg_phy_base, resource_size(res)); - if (lcdc_dev->reg_vir_base == NULL) - { - dev_err(&pdev->dev, "cannot map IO\n"); - ret = -ENXIO; - goto err2; - } - - lcdc_dev->preg = (LCDC_REG*)lcdc_dev->reg_vir_base; - printk("lcdc%d:reg_phy_base = 0x%08x,reg_vir_base:0x%p\n",pdev->id,lcdc_dev->reg_phy_base, lcdc_dev->preg); - lcdc_dev->dsp_lut_addr_base = (lcdc_dev->reg_vir_base+DSP_LUT_ADDR); - - lcdc_dev->driver.dev=&pdev->dev; - lcdc_dev->driver.screen0 = screen; -#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& (defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS)) - lcdc_dev->driver.screen1 = screen1; -#endif - lcdc_dev->driver.cur_screen = screen; - lcdc_dev->driver.screen_ctr_info = screen_ctr_info; - spin_lock_init(&lcdc_dev->reg_lock); - lcdc_dev->irq = platform_get_irq(pdev, 0); - if(lcdc_dev->irq < 0) - { - dev_err(&pdev->dev, "cannot find IRQ\n"); - goto err3; - } - ret = request_irq(lcdc_dev->irq, rk3066b_lcdc_isr, IRQF_DISABLED,dev_name(&pdev->dev),lcdc_dev); - if (ret) - { - dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", lcdc_dev->irq, ret); - ret = -EBUSY; - goto err3; - } - - if(screen_ctr_info->set_screen_info) - { - screen_ctr_info->set_screen_info(screen,screen_ctr_info->lcd_info); - if(SCREEN_NULL==screen->type) - { - printk(KERN_WARNING "no display device on lcdc%d!?\n",lcdc_dev->id); - ret = -ENODEV; - } - if(screen_ctr_info->io_init) - screen_ctr_info->io_init(NULL); - } - else - { - printk(KERN_WARNING "no display device on lcdc%d!?\n",lcdc_dev->id); - ret = -ENODEV; - goto err4; - } - - ret = rk_fb_register(&(lcdc_dev->driver),&lcdc_driver,lcdc_dev->id); - if(ret < 0) - { - printk(KERN_ERR "register fb for lcdc%d failed!\n",lcdc_dev->id); - goto err4; - } - printk("rk3066b lcdc%d probe ok!\n",lcdc_dev->id); - - return 0; - -err4: - free_irq(lcdc_dev->irq,lcdc_dev); -err3: - iounmap(lcdc_dev->reg_vir_base); -err2: - release_mem_region(lcdc_dev->reg_phy_base,resource_size(res)); -err1: - kfree(screen); -err0: - platform_set_drvdata(pdev, NULL); - kfree(lcdc_dev); - return ret; - -} -static int __devexit rk3066b_lcdc_remove(struct platform_device *pdev) -{ - struct rk3066b_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - rk_fb_unregister(&(lcdc_dev->driver)); - rk3066b_lcdc_deinit(lcdc_dev); - iounmap(lcdc_dev->reg_vir_base); - release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); - kfree(lcdc_dev->screen); - kfree(lcdc_dev); - return 0; -} - -static void rk3066b_lcdc_shutdown(struct platform_device *pdev) -{ - struct rk3066b_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - if(lcdc_dev->driver.cur_screen->standby) //standby the screen if necessary - lcdc_dev->driver.cur_screen->standby(1); - if(lcdc_dev->driver.screen_ctr_info->io_disable) //power off the screen if necessary - lcdc_dev->driver.screen_ctr_info->io_disable(); - if(lcdc_dev->driver.cur_screen->sscreen_set) //turn off lvds if necessary - lcdc_dev->driver.cur_screen->sscreen_set(lcdc_dev->driver.cur_screen , 0); - - rk3066b_lcdc_deinit(lcdc_dev); - //rk_fb_unregister(&(lcdc_dev->driver)); - - /*iounmap(lcdc_dev->reg_vir_base); - release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); - kfree(lcdc_dev->screen); - kfree(lcdc_dev);*/ -} - - -static struct platform_driver rk3066b_lcdc_driver = { - .probe = rk3066b_lcdc_probe, - .remove = __devexit_p(rk3066b_lcdc_remove), - .driver = { - .name = "rk30-lcdc", - .owner = THIS_MODULE, - }, - .suspend = rk3066b_lcdc_suspend, - .resume = rk3066b_lcdc_resume, - .shutdown = rk3066b_lcdc_shutdown, -}; - -static int __init rk3066b_lcdc_init(void) -{ - return platform_driver_register(&rk3066b_lcdc_driver); -} - -static void __exit rk3066b_lcdc_exit(void) -{ - platform_driver_unregister(&rk3066b_lcdc_driver); -} - - - -fs_initcall(rk3066b_lcdc_init); -module_exit(rk3066b_lcdc_exit); - - - diff --git a/drivers/video/rockchip/lcdc/rk3066b_lcdc.h b/drivers/video/rockchip/lcdc/rk3066b_lcdc.h deleted file mode 100755 index 27c92470ad48..000000000000 --- a/drivers/video/rockchip/lcdc/rk3066b_lcdc.h +++ /dev/null @@ -1,558 +0,0 @@ -/* drivers/video/rockchip/chips/rk29_fb.h - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __RK3066B_LCDC_H -#define __RK3066B_LCDC_H - -#include - -#define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk)) -#define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val) -#define LcdRdReg(inf, addr) (inf->preg->addr) -#define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk)) -#define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk)) -#define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk)) -#define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val)) -#define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb() - - -/******************************************************************** -** ºê¶¨Òå * -********************************************************************/ -/* SYS_CONFIG */ -#define m_W2_FORMAT (3<<0) -#define m_W1_FORMAT (1<<2) -#define m_W0_FORMAT (7<<3) -#define m_W0_CBR_DEFLICK_EN (1<<6) -#define m_W0_YRGB_DEFLICK_EN (1<<7) -#define m_INTERIACE_EN (1<<8) -#define m_W2_EN (1<<9) -#define m_W1_EN (1<<10) -#define m_W0_EN (1<<11) -#define m_HWC_EN (1<<12) -#define m_HWC_RELOAD_EN (1<<13) -#define m_W2_INTERLACE_READ (1<<14) -#define m_W1_INTERLACE_READ (1<<15) -#define m_W0_INTERLACE_READ (1<<16) -#define m_LCDC_STANDBY (1<<17) -#define m_HWC_BURST (3<<18) -#define m_W2_BURST (3<<20) -#define m_W1_BURST (3<<22) -#define m_W0_BURST (3<<24) -#define m_W2_LUT_CTL (1<<26) -#define m_DSIP_LUT_CTL (1<<27) -#define m_HWC_REVERSED_COLOR (1<<28) -#define m_W1_AXI_OUTSTANDING2 (1<<29) -#define m_W0_AXI_OUTSTANDING2 (1<<30) -#define m_LCDC_AXICLK_AUTO_ENABLE (1<<31) - -#define v_W2_FORMAT(x) (((x)&3)<<0) -#define v_W1_FORMAT(x) (((x)&1)<<2) -#define v_W0_FORMAT(x) (((x)&7)<<3) -#define v_W0_CBR_DEFLICK_EN(x) (((x)&1)<<6) -#define v_W0_YRGB_DEFLICK_EN(x) (((x)&1)<<7) -#define v_INTERIACE_EN(x) (((x)&1)<<8) -#define v_W2_EN(x) (((x)&)1<<9) -#define v_W1_EN(x) (((x)&1)<<10) -#define v_W0_EN(x) (((x)&1)<<11) -#define v_HWC_EN(x) (((x)&1)<<12) -#define v_HWC_RELOAD_EN(x) (((x)&1)<<13) -#define v_W2_INTERLACE_READ(x) (((x)&1)<<14) -#define v_W1_INTERLACE_READ(x) (((x)&1)<<15) -#define v_W0_INTERLACE_READ(x) (((x)&1)<<16) -#define v_LCDC_STANDBY(x) (((x)&1)<<17) -#define v_HWC_BURST(x) (((x)&3)<<18) -#define v_W2_BURST(x) (((x)&3)<<20) -#define v_W1_BURST(x) (((x)&3)<<22) -#define v_W0_BURST(x) (((x)&3)<<24) -#define v_W2_LUT_CTL(x) (((x)&1)<<26) -#define v_DSIP_LUT_CTL(x) (((x)&1)<<27) -#define v_HWC_REVERSED_COLOR(x) (((x)&1)<<28) -#define v_W1_AXI_OUTSTANDING2(x) (((x)&1)<<29) -#define v_W0_AXI_OUTSTANDING2(x) (((x)&1)<<30) -#define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<31) - -//LCDC_SWAP_CTRL -#define m_W1_565_RB_SWAP (1<<0) -#define m_W0_565_RB_SWAP (1<<1) -#define m_W0_YRGB_M8_SWAP (1<<2) -#define m_W0_YRGB_R_SHIFT_SWAP (1<<3) -#define m_W0_CBR_R_SHIFT_SWAP (1<<4) -#define m_W0_YRGB_16_SWAP (1<<5) -#define m_W0_YRGB_8_SWAP (1<<6) -#define m_W0_CBR_16_SWAP (1<<7) -#define m_W0_CBR_8_SWAP (1<<8) -#define m_W1_16_SWAP (1<<9) -#define m_W1_8_SWAP (1<<10) -#define m_W1_R_SHIFT_SWAP (1<<11) -#define m_OUTPUT_BG_SWAP (1<<12) -#define m_OUTPUT_RB_SWAP (1<<13) -#define m_OUTPUT_RG_SWAP (1<<14) -#define m_DELTA_SWAP (1<<15) -#define m_DUMMY_SWAP (1<<16) -#define m_W2_BYTE_SWAP (1<<17) -#define v_W1_565_RB_SWAP(x) (((x)&1)<<0) -#define v_W0_565_RB_SWAP(x) (((x)&1)<<1) -#define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<2) -#define v_W0_YRGB_R_SHIFT_SWAP(x) (((x)&1)<<3) -#define v_W0_CBR_R_SHIFT_SWAP(x) (((x)&1)<<4) -#define v_W0_YRGB_16_SWAP(x) (((x)&1)<<5) -#define v_W0_YRGB_8_SWAP(x) (((x)&1)<<6) -#define v_W0_CBR_16_SWAP(x) (((x)&1)<<7) -#define v_W0_CBR_8_SWAP(x) (((x)&1)<<8) -#define v_W1_16_SWAP(x) (((x)&1)<<9) -#define v_W1_8_SWAP(x) (((x)&1)<<10) -#define v_W1_R_SHIFT_SWAP(x) (((x)&1)<<11) -#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<12) -#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<13) -#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<14) -#define v_DELTA_SWAP(x) (((x)&1)<<15) -#define v_DUMMY_SWAP(x) (((x)&1)<<16) -#define v_W2_BYTE_SWAP(x) (((x)&1)<<17) - -//LCDC_MCU_TIMING_CTRL -#define m_MCU_WRITE_PERIOD (31<<0) -#define m_MCU_CS_ST (31<<5) -#define m_MCU_CS_END (31<<10) -#define m_MCU_RW_ST (31<<15) -#define m_MCU_RW_END (31<<20) -#define m_MCU_HOLDMODE_SELECT (1<<27) -#define m_MCU_HOLDMODE_FRAME_ST (1<<28) -#define m_MCU_RS_SELECT (1<<29) -#define m_MCU_BYPASSMODE_SELECT (1<<30) -#define m_MCU_OUTPUT_SELECT (1<<31) -#define v_MCU_WRITE_PERIOD(x) (((x)&31)<<0) -#define v_MCU_CS_ST(x) (((x)&31)<<5) -#define v_MCU_CS_END(x) (((x)&31)<<10) -#define v_MCU_RW_ST(x) (((x)&31)<<15) -#define v_MCU_RW_END(x) (((x)&31)<<20) -#define v_MCU_HOLD_STATUS(x) (((x)&1)<<26) -#define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27) -#define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28) -#define v_MCU_RS_SELECT(x) (((x)&1)<<29) -#define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30) -#define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31) - -//LCDC_ BLEND_CTRL -#define m_HWC_BLEND_EN (1<<0) -#define m_W2_BLEND_EN (1<<1) -#define m_W1_BLEND_EN (1<<2) -#define m_W0_BLEND_EN (1<<3) -#define m_HWC_BLEND_FACTOR (15<<4) -#define m_W2_BLEND_FACTOR (0xff<<8) -#define m_W1_BLEND_FACTOR (0xff<<16) -#define m_W0_BLEND_FACTOR (0xff<<24) - -#define v_HWC_BLEND_EN(x) (((x)&1)<<0) -#define v_W2_BLEND_EN(x) (((x)&1)<<1) -#define v_W1_BLEND_EN(x) (((x)&1)<<2) -#define v_W0_BLEND_EN(x) (((x)&1)<<3) -#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4) -#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8) -#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16) -#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24) - - -//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL -#define m_KEYCOLOR (0xffffff<<0) -#define m_KEYCOLOR_B (0xff<<0) -#define m_KEYCOLOR_G (0xff<<8) -#define m_KEYCOLOR_R (0xff<<16) -#define m_COLORKEY_EN (1<<24) -#define v_KEYCOLOR(x) (((x)&0xffffff)<<0) -#define v_KEYCOLOR_B(x) (((x)&0xff)<<0) -#define v_KEYCOLOR_G(x) (((x)&0xff)<<8) -#define v_KEYCOLOR_R(x) (((x)&0xff)<<16) -#define v_COLORKEY_EN(x) (((x)&1)<<24) - -//LCDC_DEFLICKER_SCL_OFFSET -#define m_W0_YRGB_VSD_OFFSET (0xff<<0) -#define m_W0_YRGB_VSP_OFFSET (0xff<<8) -#define m_W1_VSD_OFFSET (0xff<<16) -#define m_W1_VSP_OFFSET (0xff<<24) -#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0) -#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8) -#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16) -#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24) - -//LCDC_DSP_CTRL_REG0 -#define m_DISPLAY_FORMAT (0xf<<0) -#define m_HSYNC_POLARITY (1<<4) -#define m_VSYNC_POLARITY (1<<5) -#define m_DEN_POLARITY (1<<6) -#define m_DCLK_POLARITY (1<<7) -#define m_COLOR_SPACE_CONVERSION (3<<8) -#define m_DITHER_UP_EN (1<<10) -#define m_DITHER_DOWN_MODE (1<<11) -#define m_DITHER_DOWN_EN (1<<12) -#define m_INTERLACE_FIELD_POLARITY (1<<13) -#define m_YUV_CLIP (1<<14) -#define m_W1_TRANSP_FROM (1<<15) -#define m_W0_TRANSP_FROM (1<<16) -#define m_W0W1_POSITION_SWAP (1<<17) -#define m_W1_CLIP_EN (1<<18) -#define m_W0_CLIP_EN (1<<19) -#define m_W0_YCBR_PRIORITY_MODE (1<<20) -#define m_CBR_FILTER_656 (1<<21) -#define m_W2_CHIP_EN (1<<22) - -#define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0) -#define v_HSYNC_POLARITY(x) (((x)&1)<<4) -#define v_VSYNC_POLARITY(x) (((x)&1)<<5) -#define v_DEN_POLARITY(x) (((x)&1)<<6) -#define v_DCLK_POLARITY(x) (((x)&1)<<7) -#define v_COLOR_SPACE_CONVERSION(x) (((x)&3)<<8) -#define v_DITHER_UP_EN(x) (((x)&1)<<10) -#define v_DITHER_DOWN_MODE(x) (((x)&1)<<11) -#define v_DITHER_DOWN_EN(x) (((x)&1)<<12) -#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13) -#define v_YUV_CLIP(x) (((x)&1)<<14) -#define v_W1_TRANSP_FROM(x) (((x)&1)<<15) -#define v_W0_TRANSP_FROM(x) (((x)&1)<<16) -#define v_W0W1_POSITION_SWAP(x) (((x)&1)<<17) -#define v_W1_CLIP_EN(x) (((x)&1)<<18) -#define v_W0_CLIP_EN(x) (((x)&1)<<19) -#define v_W0_YCBR_PRIORITY_MODE(x) (((x)&1)<<20) -#define v_CBR_FILTER_656(x) (((x)&1)<<21) -#define v_W2_CHIP_EN(x) (((x)&1)<<22) - - -//LCDC_DSP_CTRL_REG1 -#define m_BG_COLOR (0xffffff<<0) -#define m_BG_B (0xff<<0) -#define m_BG_G (0xff<<8) -#define m_BG_R (0xff<<16) -#define m_BLANK_MODE (1<<24) -#define m_BLACK_MODE (1<<25) -#define m_DISP_FILTER_FACTOR (3<<26) -#define m_DISP_FILTER_MODE (1<<28) -#define m_DISP_FILTER_EN (1<<29) -#define v_BG_COLOR(x) (((x)&0xffffff)<<0) -#define v_BG_B(x) (((x)&0xff)<<0) -#define v_BG_G(x) (((x)&0xff)<<8) -#define v_BG_R(x) (((x)&0xff)<<16) -#define v_BLANK_MODE(x) (((x)&1)<<24) -#define v_BLACK_MODE(x) (((x)&1)<<25) -#define v_DISP_FILTER_FACTOR(x) (((x)&3)<<26) -#define v_DISP_FILTER_MODE(x) (((x)&1)<<28) -#define v_DISP_FILTER_EN(x) (((x)&1)<<29) - -//LCDC_INT_STATUS -#define m_HOR_START (1<<0) -#define m_FRM_START (1<<1) -#define m_SCANNING_FLAG (1<<2) -#define m_HOR_STARTMASK (1<<3) -#define m_FRM_STARTMASK (1<<4) -#define m_SCANNING_MASK (1<<5) -#define m_HOR_STARTCLEAR (1<<6) -#define m_FRM_STARTCLEAR (1<<7) -#define m_SCANNING_CLEAR (1<<8) -#define m_SCAN_LINE_NUM (0x7ff<<9) -#define v_HOR_START(x) (((x)&1)<<0) -#define v_FRM_START(x) (((x)&1)<<1) -#define v_SCANNING_FLAG(x) (((x)&1)<<2) -#define v_HOR_STARTMASK(x) (((x)&1)<<3) -#define v_FRM_STARTMASK(x) (((x)&1)<<4) -#define v_SCANNING_MASK(x) (((x)&1)<<5) -#define v_HOR_STARTCLEAR(x) (((x)&1)<<6) -#define v_FRM_STARTCLEAR(x) (((x)&1)<<7) -#define v_SCANNING_CLEAR(x) (((x)&1)<<8) -#define v_SCAN_LINE_NUM(x) (((x)&0x7ff)<<9) - -//AXI MS ID -#define m_W0_YRGB_CH_ID (0xF<<0) -#define m_W0_CBR_CH_ID (0xF<<4) -#define m_W1_YRGB_CH_ID (0xF<<8) -#define m_W2_CH_ID (0xF<<12) -#define m_HWC_CH_ID (0xF<<16) -#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0) -#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4) -#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8) -#define v_W2_CH_ID(x) (((x)&0xF)<<12) -#define v_HWC_CH_ID(x) (((x)&0xF)<<16) - - -/* Low Bits Mask */ -#define m_WORDLO (0xffff<<0) -#define m_WORDHI (0xffff<<16) -#define v_WORDLO(x) (((x)&0xffff)<<0) -#define v_WORDHI(x) (((x)&0xffff)<<16) - -#define m_BIT11LO (0x7ff<<0) -#define m_BIT11HI (0x7ff<<16) -#define v_BIT11LO(x) (((x)&0x7ff)<<0) -#define v_BIT11HI(x) (((x)&0x7ff)<<16) - -#define m_BIT12LO (0xfff<<0) -#define m_BIT12HI (0xfff<<16) -#define v_BIT12LO(x) (((x)&0xfff)<<0) -#define v_BIT12HI(x) (((x)&0xfff)<<16) - - -#define m_VIRWIDTH (0xffff<<0) -#define m_VIRHEIGHT (0xffff<<16) -#define v_VIRWIDTH(x) (((x)&0xffff)<<0) -#define v_VIRHEIGHT(x) (((x)&0xffff)<<16) - -#define m_ACTWIDTH (0xffff<<0) -#define m_ACTHEIGHT (0xffff<<16) -#define v_ACTWIDTH(x) (((x)&0xffff)<<0) -#define v_ACTHEIGHT(x) (((x)&0xffff)<<16) - -#define m_VIRST_X (0xffff<<0) -#define m_VIRST_Y (0xffff<<16) -#define v_VIRST_X(x) (((x)&0xffff)<<0) -#define v_VIRST_Y(x) (((x)&0xffff)<<16) - -#define m_PANELST_X (0x3ff<<0) -#define m_PANELST_Y (0x3ff<<16) -#define v_PANELST_X(x) (((x)&0x3ff)<<0) -#define v_PANELST_Y(x) (((x)&0x3ff)<<16) - -#define m_PANELWIDTH (0x3ff<<0) -#define m_PANELHEIGHT (0x3ff<<16) -#define v_PANELWIDTH(x) (((x)&0x3ff)<<0) -#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16) - -#define m_HWC_B (0xff<<0) -#define m_HWC_G (0xff<<8) -#define m_HWC_R (0xff<<16) -#define m_W0_YRGB_HSP_OFFSET (0xff<<24) -#define m_W0_YRGB_HSD_OFFSET (0xff<<24) -#define v_HWC_B(x) (((x)&0xff)<<0) -#define v_HWC_G(x) (((x)&0xff)<<8) -#define v_HWC_R(x) (((x)&0xff)<<16) -#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24) -#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24) - - -//Panel display scanning -#define m_PANEL_HSYNC_WIDTH (0x3ff<<0) -#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16) -#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0) -#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16) - -#define m_PANEL_END (0x3ff<<0) -#define m_PANEL_START (0x3ff<<16) -#define v_PANEL_END(x) (((x)&0x3ff)<<0) -#define v_PANEL_START(x) (((x)&0x3ff)<<16) - -#define m_PANEL_VSYNC_WIDTH (0x3ff<<0) -#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16) -#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0) -#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16) -//----------- - -#define m_HSCALE_FACTOR (0xffff<<0) -#define m_VSCALE_FACTOR (0xffff<<16) -#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0) -#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16) - -#define m_W0_CBR_HSD_OFFSET (0xff<<0) -#define m_W0_CBR_HSP_OFFSET (0xff<<8) -#define m_W0_CBR_VSD_OFFSET (0xff<<16) -#define m_W0_CBR_VSP_OFFSET (0xff<<24) -#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0) -#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8) -#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16) -#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24) - - -#define m_WIN1_FIFO_FULL_LEVEL (0x7f << 0) -#define m_WIN2_FIFO_FULL_LEVEL (0x1f << 7) -#define v_WIN1_FIFO_FULL_LEVEL(x) (((x)&0x7f) << 0) -#define v_WIN2_FIFO_FULL_LEVEL(x) (((x)&0x1f) << 7) - - -#define m_WIN0_YRGB_CHANNEL_ID ((0x0f)<<0) -#define m_WIN0_CBR_CHANNEL_ID ((0x0f)<<4) -#define m_WIN1_YRGB_CHANNEL_ID ((0x0f)<<8) -#define m_WIN2_CHANNEL_ID ((0x0f)<<12) -#define m_HWC_CHANNEL_ID ((0x0f)<<16) -#define v_WIN0_YRGB_CHANNEL_ID(x) (((x)&0x0f)<<0) -#define v_WIN0_CBR_CHANNEL_ID(x) (((x)&0x0f)<<4) -#define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&0x0f)<<8) -#define v_WIN2_CHANNEL_ID(x) (((x)&0x0f)<<12) -#define v_HWC_CHANNEL_ID(x) (((x)&0x0f)<<16) - - -//LCDC_WINx_SCL_FACTOR_Y/CBCR -#define v_X_SCL_FACTOR(x) ((x)<<0) -#define v_Y_SCL_FACTOR(x) ((x)<<16) - -//LCDC_DSP_HTOTAL_HS_END -#define v_HSYNC(x) ((x)<<0) //hsync pulse width -#define v_HORPRD(x) ((x)<<16) //horizontal period - - -//LCDC_DSP_HACT_ST_END -#define v_HAEP(x) ((x)<<0) //horizontal active end point -#define v_HASP(x) ((x)<<16) //horizontal active start point - -//LCDC_DSP_VTOTAL_VS_END -#define v_VSYNC(x) ((x)<<0) -#define v_VERPRD(x) ((x)<<16) - -//LCDC_DSP_VACT_ST_END -#define v_VAEP(x) ((x)<<0) -#define v_VASP(x) ((x)<<16) - -//LCDC_WIN0_ACT_INFO -#define v_ACT_WIDTH(x) ((x)<<0) -#define v_ACT_HEIGHT(x) ((x)<<16) - -//LCDC_WIN0_DSP_INFO -#define v_DSP_WIDTH(x) ((x)<<0) -#define v_DSP_HEIGHT(x) ((x)<<16) - -//LCDC_WIN0_DSP_ST //x,y start point of the panel scanning -#define v_DSP_STX(x) (x<<0) -#define v_DSP_STY(x) (x<<16) - - -/******************************************************************** -** ½á¹¹¶¨Òå * -********************************************************************/ -/* LCDCµÄ¼Ä´æÆ÷½á¹¹ */ - -typedef volatile struct tagLCDC_REG -{ - /* offset 0x00~0xc0 */ - unsigned int SYS_CFG; //0x00 SYSTEM configure register - unsigned int SWAP_CTRL; //0x04 Data SWAP control - unsigned int MCU_CTRL; //0x08 MCU TIMING control register - unsigned int BLEND_CTRL; //0x0c Blending control register - unsigned int WIN0_COLOR_KEY_CTRL; //0x10 Win0 blending control register - unsigned int WIN1_COLOR_KEY_CTRL; //0x14 Win1 blending control register - unsigned int WIN2_VIR; //0x18 WIN2 virtual display width - unsigned int DSP_CTRL0; //0x1c Display control register0 - unsigned int DSP_CTRL1; //0x20 Display control register1 - unsigned int INT_STATUS; //0x24 Interrupt status register - unsigned int WIN0_VIR; //0x28 WIN0 virtual display width/height - unsigned int WIN0_YRGB_MST; //0x2c Win0 active YRGB memory start address - unsigned int WIN0_CBR_MST; //0x30 Win0 active Cbr memory start address - unsigned int WIN0_ACT_INFO; //0x34 Win0 active window width/height - unsigned int WIN0_DSP_ST; //0x38 Win0 display start point on panel - unsigned int WIN0_DSP_INFO; //0x3c Win0 display width/height on panel - unsigned int WIN1_VIR; //0x40 Win1 virtual display width/height - unsigned int WIN1_YRGB_MST; //0x44 Win1 active memory start address - unsigned int WIN1_DSP_INFO; //0x48 Win1 display width/height on panel - unsigned int WIN1_DSP_ST; //0x4c Win1 display start point on panel - unsigned int WIN2_MST; //0X50 Win2 memory start address - unsigned int WIN2_DSP_INFO; //0x54 Win1 display width/height on panel - unsigned int WIN2_DSP_ST; //0x58 Win1 display start point on panel - unsigned int HWC_MST; //0x5C HWC memory start address - unsigned int HWC_DSP_ST; //0x60 HWC display start point on panel - unsigned int HWC_COLOR_LUT0; //0x64 Hardware cursor color 2¡¯b01 look up table 0 - unsigned int HWC_COLOR_LUT1; //0x68 Hardware cursor color 2¡¯b10 look up table 1 - unsigned int HWC_COLOR_LUT2; //0x6c Hardware cursor color 2¡¯b11 look up table 2 - unsigned int DSP_HTOTAL_HS_END; //0x70 Panel scanning horizontal width and hsync pulse end point - unsigned int DSP_HACT_ST_END; //0x74 Panel active horizontal scanning start/end point - unsigned int DSP_VTOTAL_VS_END; //0x78 Panel scanning vertical height and vsync pulse end point - unsigned int DSP_VACT_ST_END; //0x7c Panel active vertical scanning start/end point - unsigned int DSP_VS_ST_END_F1; //0x80 Vertical scanning start point and vsync pulse end point of even filed in interlace mode - unsigned int DSP_VACT_ST_END_F1; //0x84 Vertical scanning active start/end point of even filed in interlace mode - unsigned int WIN0_SCL_FACTOR_YRGB; //0x88 Win0 YRGB scaling down factor setting - unsigned int WIN0_SCL_FACTOR_CBR; //0x8c Win0 YRGB scaling up factor setting - unsigned int WIN0_SCL_OFFSET; //0x90 Win0 Cbr scaling start point offset - unsigned int FIFO_WATER_MARK; //0x94 Fifo water mark - unsigned int AXI_MS_ID; //0x98 Axi master ID - unsigned int reserved0; //0x9c - unsigned int REG_CFG_DONE; //0xa0 REGISTER CONFIG FINISH - unsigned int reserved1[(0x100-0xa4)/4]; - unsigned int MCU_BYPASS_WPORT; //0x100 MCU BYPASS MODE, DATA Write Only Port - unsigned int reserved2[(0x200-0x104)/4]; - unsigned int MCU_BYPASS_RPORT; //0x200 MCU BYPASS MODE, DATA Read Only Port -} LCDC_REG, *pLCDC_REG; - -#define Win2_LUT_ADDR 0x400 -#define DSP_LUT_ADDR 0x800 - -//roate -#define ROTATE_0 0 -#define ROTATE_90 90 -#define ROTATE_180 180 -#define ROTATE_270 270 -#define X_MIRROR (1<<10) -#define Y_MIRROR (1<<11) - - - - -#define CalScale(x, y) (((u32)x*0x1000)/y) -struct rk3066b_lcdc_device{ - int id; - struct rk_lcdc_device_driver driver; - rk_screen *screen; - - LCDC_REG *preg; // LCDC reg base address and backup reg - LCDC_REG regbak; - - void __iomem *reg_vir_base; // virtual basic address of lcdc register - u32 reg_phy_base; // physical basic address of lcdc register - u32 len; // physical map length of lcdc register - spinlock_t reg_lock; //one time only one process allowed to config the register - int __iomem *dsp_lut_addr_base; - bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed - u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc - - unsigned int irq; - - struct clk *pd; //lcdc power domain - struct clk *hclk; //lcdc AHP clk - struct clk *dclk; //lcdc dclk - struct clk *aclk; //lcdc share memory frequency - struct clk *aclk_parent; //lcdc aclk divider frequency source - struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable. - struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable. - struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable. - struct clk *pd_display; // display power domain - u32 pixclock; -}; - -struct lcdc_info{ -/*LCD CLK*/ - struct rk3066b_lcdc_device lcdc0; - struct rk3066b_lcdc_device lcdc1; - -}; - - -struct win_set { - volatile u32 y_offset; - volatile u32 c_offset; -}; - -struct win0_par { - u32 refcount; - u32 pseudo_pal[16]; - u32 y_offset; - u32 c_offset; - u32 xpos; //size in panel - u32 ypos; - u32 xsize; //start point in panel - u32 ysize; - enum data_format format; - - wait_queue_head_t wait; - struct win_set mirror; - struct win_set displ; - struct win_set done; - - u8 par_seted; - u8 addr_seted; -}; - -#endif diff --git a/drivers/video/rockchip/lcdc/rk30_lcdc.c b/drivers/video/rockchip/lcdc/rk30_lcdc.c deleted file mode 100755 index 7b7b79010d8d..000000000000 --- a/drivers/video/rockchip/lcdc/rk30_lcdc.c +++ /dev/null @@ -1,1748 +0,0 @@ -/* - * drivers/video/rockchip/chips/rk30_lcdc.c - * - * Copyright (C) 2012 ROCKCHIP, Inc. - *Author:yzq - * yxj - *This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk30_lcdc.h" - - - -static int dbg_thresd = 0; -module_param(dbg_thresd, int, S_IRUGO|S_IWUSR); -#define DBG(level,x...) do { if(unlikely(dbg_thresd >= level)) printk(KERN_INFO x); } while (0) - - -static int rk30_lcdc_clk_enable(struct rk30_lcdc_device *lcdc_dev) -{ - if(!lcdc_dev->clk_on) - { - clk_enable(lcdc_dev->pd); - clk_enable(lcdc_dev->hclk); - clk_enable(lcdc_dev->dclk); - clk_enable(lcdc_dev->aclk); - - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 1; - spin_unlock(&lcdc_dev->reg_lock); - } - printk("rk30 lcdc%d clk enable...\n",lcdc_dev->id); - - return 0; -} - -static int rk30_lcdc_clk_disable(struct rk30_lcdc_device *lcdc_dev) -{ - if(lcdc_dev->clk_on) - { - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 0; - spin_unlock(&lcdc_dev->reg_lock); - mdelay(30); - clk_disable(lcdc_dev->dclk); - clk_disable(lcdc_dev->hclk); - clk_disable(lcdc_dev->aclk); - clk_disable(lcdc_dev->pd); - } - printk("rk30 lcdc%d clk disable...\n",lcdc_dev->id); - return 0; -} - -static int rk30_lcdc_read_reg_defalut_cfg(struct rk30_lcdc_device *lcdc_dev) -{ - int reg = 0; - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - for(reg=SYS_CTRL0;reg<=DSP_VACT_ST_END_F1; reg +=4) - { - lcdc_readl(lcdc_dev,reg); - } - - spin_unlock(&lcdc_dev->reg_lock); - } - else //clk already disabled - { - spin_unlock(&lcdc_dev->reg_lock); - - } - - return 0; -} -static int rk30_lcdc_init(struct rk_lcdc_device_driver *dev_drv) -{ - int i = 0; - int __iomem *c; - int v; - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - if(lcdc_dev->id == 0) //lcdc0 - { - lcdc_dev->pd = clk_get(NULL,"pd_lcdc0"); - lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0"); - lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0"); - lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0"); - } - else if(lcdc_dev->id == 1) - { - lcdc_dev->pd = clk_get(NULL,"pd_lcdc1"); - lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1"); - lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1"); - lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1"); - } - else - { - printk(KERN_ERR "invalid lcdc device!\n"); - return -EINVAL; - } - if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) - { - printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id); - } - - rk30_lcdc_clk_enable(lcdc_dev); - rk30_lcdc_read_reg_defalut_cfg(lcdc_dev); - lcdc_msk_reg(lcdc_dev,SYS_CTRL0,m_HWC_CHANNEL_ID | m_WIN2_CHANNEL_ID | m_WIN1_CBR_CHANNEL_ID | - m_WIN1_YRGB_CHANNEL_ID | m_WIN0_CBR_CHANNEL1_ID | m_WIN0_YRGB_CHANNEL1_ID | - m_WIN0_CBR_CHANNEL0_ID | m_WIN0_YRGB_CHANNEL0_ID,v_HWC_CHANNEL_ID(7) | - v_WIN2_CHANNEL_ID(6) | v_WIN1_CBR_CHANNEL_ID(5) | v_WIN1_YRGB_CHANNEL_ID(4) | - v_WIN0_CBR_CHANNEL1_ID(3) | v_WIN0_YRGB_CHANNEL1_ID(2) | v_WIN0_CBR_CHANNEL0_ID(1) | - v_WIN0_YRGB_CHANNEL0_ID(0)); //channel id ,just use default value - lcdc_writel(lcdc_dev,WIN0_SCL_FACTOR_YRGB,0x10001000); - lcdc_writel(lcdc_dev,WIN1_SCL_FACTOR_YRGB,0x10001000); - lcdc_set_bit(lcdc_dev,DSP_CTRL0, m_LCDC_AXICLK_AUTO_ENABLE);//eanble axi-clk auto gating for low power - lcdc_msk_reg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR | m_BUS_ERR_INT_CLEAR | m_LINE_FLAG_INT_EN | - m_FRM_START_INT_EN | m_HOR_START_INT_EN,v_FRM_START_INT_CLEAR(1) | v_BUS_ERR_INT_CLEAR(0) | - v_LINE_FLAG_INT_EN(0) | v_FRM_START_INT_EN(0) | v_HOR_START_INT_EN(0)); //enable frame start interrupt for sync - - if(dev_drv->cur_screen->dsp_lut) - { - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(0)); - lcdc_cfg_done(lcdc_dev); - msleep(25); - for(i=0;i<256;i++) - { - v = dev_drv->cur_screen->dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base+i; - writel_relaxed(v,c); - - } - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(1)); - } - - lcdc_cfg_done(lcdc_dev); // write any value to REG_CFG_DONE let config become effective - - rk30_lcdc_clk_disable(lcdc_dev); - - return 0; -} - -static int rk30_lcdc_deinit(struct rk30_lcdc_device *lcdc_dev) -{ - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_dev->clk_on = 0; - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_HOR_START_INT_EN | m_FRM_START_INT_EN | - m_LINE_FLAG_INT_EN | m_BUS_ERR_INT_EN,v_HOR_START_INT_EN(0) | v_FRM_START_INT_EN(0) | - v_LINE_FLAG_INT_EN(0) | v_BUS_ERR_INT_EN(0)); //disable all lcdc interrupt - lcdc_set_bit(lcdc_dev,SYS_CTRL0,m_LCDC_STANDBY); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - } - else //clk already disabled - { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - mdelay(1); - - return 0; -} - -static int rk30_load_screen(struct rk_lcdc_device_driver *dev_drv, bool initscreen) -{ - int ret = -EINVAL; - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - rk_screen *screen = dev_drv->cur_screen; - u64 ft; - int fps; - u16 face; - u16 mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend; - u16 right_margin = screen->right_margin; - u16 lower_margin = screen->lower_margin; - u16 x_res = screen->x_res, y_res = screen->y_res; - - - // set the rgb or mcu - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(screen->type==SCREEN_MCU) - { - lcdc_msk_reg(lcdc_dev, MCU_CTRL, m_MCU_OUTPUT_SELECT,v_MCU_OUTPUT_SELECT(1)); - // set out format and mcu timing - mcu_total = (screen->mcu_wrperiod*150*1000)/1000000; - if(mcu_total>31) - mcu_total = 31; - if(mcu_total<3) - mcu_total = 3; - mcu_rwstart = (mcu_total+1)/4 - 1; - mcu_rwend = ((mcu_total+1)*3)/4 - 1; - mcu_csstart = (mcu_rwstart>2) ? (mcu_rwstart-3) : (0); - mcu_csend = (mcu_rwend>15) ? (mcu_rwend-1) : (mcu_rwend); - - //DBG(1,">> mcu_total=%d, mcu_rwstart=%d, mcu_csstart=%d, mcu_rwend=%d, mcu_csend=%d \n", - // mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend); - - // set horizontal & vertical out timing - - right_margin = x_res/6; - screen->pixclock = 150000000; //mcu fix to 150 MHz - lcdc_msk_reg(lcdc_dev, MCU_CTRL,m_MCU_CS_ST | m_MCU_CS_END| m_MCU_RW_ST | m_MCU_RW_END | - m_MCU_WRITE_PERIOD | m_MCU_HOLDMODE_SELECT | m_MCU_HOLDMODE_FRAME_ST, - v_MCU_CS_ST(mcu_csstart) | v_MCU_CS_END(mcu_csend) | v_MCU_RW_ST(mcu_rwstart) | - v_MCU_RW_END(mcu_rwend) | v_MCU_WRITE_PERIOD(mcu_total) | - v_MCU_HOLDMODE_SELECT((SCREEN_MCU==screen->type)?(1):(0)) | v_MCU_HOLDMODE_FRAME_ST(0)); - - } - - switch (screen->face) - { - case OUT_P565: - face = OUT_P565; - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); - break; - case OUT_P666: - face = OUT_P666; - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); - break; - case OUT_D888_P565: - face = OUT_P888; - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); - break; - case OUT_D888_P666: - face = OUT_P888; - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); - break; - case OUT_P888: - face = OUT_P888; - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(1)); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); - break; - default: - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(0)); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); - face = screen->face; - break; - } - - //use default overlay,set vsyn hsync den dclk polarity - lcdc_msk_reg(lcdc_dev, DSP_CTRL0,m_DISPLAY_FORMAT | m_HSYNC_POLARITY | m_VSYNC_POLARITY | - m_DEN_POLARITY |m_DCLK_POLARITY,v_DISPLAY_FORMAT(face) | - v_HSYNC_POLARITY(screen->pin_hsync) | v_VSYNC_POLARITY(screen->pin_vsync) | - v_DEN_POLARITY(screen->pin_den) | v_DCLK_POLARITY(screen->pin_dclk)); - - //set background color to black,set swap according to the screen panel,disable blank mode - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BG_COLOR | m_OUTPUT_RB_SWAP | m_OUTPUT_RG_SWAP | m_DELTA_SWAP | - m_DUMMY_SWAP | m_BLANK_MODE,v_BG_COLOR(0x000000) | v_OUTPUT_RB_SWAP(screen->swap_rb) | - v_OUTPUT_RG_SWAP(screen->swap_rg) | v_DELTA_SWAP(screen->swap_delta) | v_DUMMY_SWAP(screen->swap_dumy) | - v_BLACK_MODE(0)); - - - lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END,v_HSYNC(screen->hsync_len) | - v_HORPRD(screen->hsync_len + screen->left_margin + x_res + right_margin)); - lcdc_writel(lcdc_dev, DSP_HACT_ST_END, v_HAEP(screen->hsync_len + screen->left_margin + x_res) | - v_HASP(screen->hsync_len + screen->left_margin)); - - lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, v_VSYNC(screen->vsync_len) | - v_VERPRD(screen->vsync_len + screen->upper_margin + y_res + lower_margin)); - lcdc_writel(lcdc_dev, DSP_VACT_ST_END, v_VAEP(screen->vsync_len + screen->upper_margin+y_res)| - v_VASP(screen->vsync_len + screen->upper_margin)); - // let above to take effect - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - ret = clk_set_rate(lcdc_dev->dclk, screen->pixclock); - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); - } - lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - - ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* - (dev_drv->pixclock); // one frame time ,(pico seconds) - fps = div64_u64(1000000000000llu,ft); - screen->ft = 1000/fps; - printk("%s: dclk:%lu>>fps:%d ",lcdc_dev->driver.name,clk_get_rate(lcdc_dev->dclk),fps); - - if(screen->init) - { - screen->init(); - } - - printk("%s for lcdc%d ok!\n",__func__,lcdc_dev->id); - return 0; -} - -static int mcu_refresh(struct rk30_lcdc_device *lcdc_dev) -{ - - return 0; -} - - - -//enable layer,open:1,enable;0 disable -static int win0_open(struct rk30_lcdc_device *lcdc_dev,bool open) -{ - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(open) - { - if(!lcdc_dev->atv_layer_cnt) - { - printk(KERN_INFO "lcdc%d wakeup from standby!\n",lcdc_dev->id); - lcdc_msk_reg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); - } - - lcdc_dev->atv_layer_cnt++; - } - else if((lcdc_dev->atv_layer_cnt > 0) && (!open)) - { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.layer_par[0]->state = open; - - lcdc_msk_reg(lcdc_dev, SYS_CTRL1, m_W0_EN, v_W0_EN(open)); - if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc - { - printk(KERN_INFO "no layer of lcdc%d is used,go to standby!\n",lcdc_dev->id); - lcdc_msk_reg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); - } - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - - return 0; -} -static int win1_open(struct rk30_lcdc_device *lcdc_dev,bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(open) - { - if(!lcdc_dev->atv_layer_cnt) - { - printk(KERN_INFO "lcdc%d wakeup from standby!\n",lcdc_dev->id); - lcdc_msk_reg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); - } - lcdc_dev->atv_layer_cnt++; - } - else if((lcdc_dev->atv_layer_cnt > 0) && (!open)) - { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.layer_par[1]->state = open; - - lcdc_msk_reg(lcdc_dev, SYS_CTRL1, m_W1_EN, v_W1_EN(open)); - if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc - { - printk(KERN_INFO "no layer of lcdc%d is used,go to standby!\n",lcdc_dev->id); - lcdc_msk_reg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); - } - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win2_open(struct rk30_lcdc_device *lcdc_dev,bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(open) - { - if(!lcdc_dev->atv_layer_cnt) - { - printk(KERN_INFO "lcdc%d wakeup from standby!",lcdc_dev->id); - lcdc_msk_reg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); - } - lcdc_dev->atv_layer_cnt++; - } - else if((lcdc_dev->atv_layer_cnt > 0) && (!open)) - { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.layer_par[1]->state = open; - - lcdc_msk_reg(lcdc_dev, SYS_CTRL1, m_W2_EN, v_W2_EN(open)); - - if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc - { - printk(KERN_INFO "no layer of lcdc%d is used,go to standby!",lcdc_dev->id); - lcdc_msk_reg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); - } - - lcdc_writel(lcdc_dev, REG_CFG_DONE, 0x01); - lcdc_dev->driver.layer_par[1]->state = open; - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int rk30_lcdc_blank(struct rk_lcdc_device_driver*lcdc_drv,int layer_id,int blank_mode) -{ - struct rk30_lcdc_device * lcdc_dev = container_of(lcdc_drv,struct rk30_lcdc_device ,driver); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - switch(blank_mode) - { - case FB_BLANK_UNBLANK: - lcdc_msk_reg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(0)); - break; - case FB_BLANK_NORMAL: - lcdc_msk_reg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(1)); - break; - default: - lcdc_msk_reg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(1)); - break; - } - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - dev_info(lcdc_drv->dev,"blank mode:%d\n",blank_mode); - - return 0; -} - -static int win0_display(struct rk30_lcdc_device *lcdc_dev,struct layer_par *par ) -{ - u32 y_addr; - u32 uv_addr; - y_addr = par->smem_start + par->y_offset; - uv_addr = par->cbr_start + par->c_offset; - DBG(2,KERN_INFO "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_writel(lcdc_dev, WIN0_YRGB_MST0, y_addr); - lcdc_writel(lcdc_dev, WIN0_CBR_MST0, uv_addr); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_display(struct rk30_lcdc_device *lcdc_dev,struct layer_par *par ) -{ - u32 y_addr; - u32 uv_addr; - y_addr = par->smem_start + par->y_offset; - uv_addr = par->cbr_start + par->c_offset; - DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_writel(lcdc_dev, WIN1_YRGB_MST, y_addr); - lcdc_writel(lcdc_dev, WIN1_CBR_MST, uv_addr); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win2_display(struct rk30_lcdc_device *lcdc_dev,struct layer_par *par ) -{ - u32 y_addr; - u32 uv_addr; - y_addr = par->smem_start + par->y_offset; - uv_addr = par->cbr_start + par->c_offset; - DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_writel(lcdc_dev, WIN2_MST, y_addr); - lcdc_writel(lcdc_dev, REG_CFG_DONE, 0x01); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win0_set_par(struct rk30_lcdc_device *lcdc_dev,rk_screen *screen, - struct layer_par *par ) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u32 ScaleYrgbX = 0x1000; - u32 ScaleYrgbY = 0x1000; - u32 ScaleCbrX = 0x1000; - u32 ScaleCbrY = 0x1000; - u8 fmt_cfg = 0; - char fmt[9] = "NULL"; - xact = par->xact; //active (origin) picture window width/height - yact = par->yact; - xvir = par->xvir; // virtual resolution - yvir = par->yvir; - xpos = par->xpos+screen->left_margin + screen->hsync_len; - ypos = par->ypos+screen->upper_margin + screen->vsync_len; - - - DBG(1,"%s for lcdc%d>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - __func__,lcdc_dev->id,get_format_string(par->format,fmt),xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); - - if((!xact) || (!yact) || (!par->xsize) || (!par->ysize)) - { - dev_err(lcdc_dev->driver.dev,"invalid parameter for win0-->xact:%d yact:%d xsize:%d ysize:%d\n", - xact,yact,par->xsize,par->ysize); - return -EINVAL; - } - ScaleYrgbX = CalScale(xact, par->xsize); //both RGB and yuv need this two factor - ScaleYrgbY = CalScale(yact, par->ysize); - switch (par->format) - { - case ARGB888: - case XBGR888: - case ABGR888: - fmt_cfg = 0; - break; - case RGB888: - fmt_cfg = 1; - break; - case RGB565: - fmt_cfg = 2; - break; - case YUV422:// yuv422 - fmt_cfg = 5; - ScaleCbrX = CalScale((xact/2), par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - case YUV420: // yuv420 - fmt_cfg = 4; - ScaleCbrX = CalScale(xact/2, par->xsize); - ScaleCbrY = CalScale(yact/2, par->ysize); - break; - case YUV444:// yuv444 - fmt_cfg = 6; - ScaleCbrX = CalScale(xact, par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - default: - printk("%s un supported format\n",__func__); - break; - } - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB,v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY)); - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX)| v_Y_SCL_FACTOR(ScaleCbrY)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL1, m_W0_FORMAT, v_W0_FORMAT(fmt_cfg)); //(inf->video_mode==0) - lcdc_writel(lcdc_dev, WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact)); - lcdc_writel(lcdc_dev, WIN0_DSP_ST, v_DSP_STX(xpos) | v_DSP_STY(ypos)); - lcdc_writel(lcdc_dev, WIN0_DSP_INFO, v_DSP_WIDTH(par->xsize)| v_DSP_HEIGHT(par->ysize)); - //lcdc_msk_reg(lcdc_dev, WIN0_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR, - // v_COLORKEY_EN(1) | v_KEYCOLOR(0)); - switch(par->format) - { - case XBGR888: - lcdc_writel(lcdc_dev, WIN0_VIR,v_ARGB888_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(1)); - break; - case ARGB888: - lcdc_writel(lcdc_dev, WIN0_VIR,v_ARGB888_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(0)); - break; - case ABGR888: - lcdc_writel(lcdc_dev, WIN0_VIR,v_ARGB888_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(1)); - break; - case RGB888: //rgb888 - lcdc_writel(lcdc_dev, WIN0_VIR,v_RGB888_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(0)); - break; - case RGB565: //rgb565 - lcdc_writel(lcdc_dev, WIN0_VIR,v_RGB565_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(0)); - break; - case YUV422: - case YUV420: - lcdc_writel(lcdc_dev, WIN0_VIR,v_YUV_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(0)); - break; - default: - printk("%s:un supported format\n",__func__); - break; - } - - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_set_par(struct rk30_lcdc_device *lcdc_dev,rk_screen *screen, - struct layer_par *par ) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u32 ScaleYrgbX = 0x1000; - u32 ScaleYrgbY = 0x1000; - u32 ScaleCbrX = 0x1000; - u32 ScaleCbrY = 0x1000; - u8 fmt_cfg = 0; - char fmt[9]; - xact = par->xact; - yact = par->yact; - xvir = par->xvir; - yvir = par->yvir; - xpos = par->xpos+screen->left_margin + screen->hsync_len; - ypos = par->ypos+screen->upper_margin + screen->vsync_len; - - ScaleYrgbX = CalScale(xact, par->xsize); - ScaleYrgbY = CalScale(yact, par->ysize); - DBG(1,"%s for lcdc%d>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - __func__,lcdc_dev->id,get_format_string(par->format,fmt),xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); - - if((!xact) || (!yact) || (!par->xsize) || (!par->ysize)) - { - dev_err(lcdc_dev->driver.dev,"invalid parameter for win1-->xact:%d yact:%d xsize:%d ysize:%d\n", - xact,yact,par->xsize,par->ysize); - return -EINVAL; - } - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - switch (par->format) - { - case ARGB888: - case XBGR888: - case ABGR888: - fmt_cfg = 0; - break; - case RGB888: - fmt_cfg = 1; - break; - case RGB565: - fmt_cfg = 2; - break; - case YUV422:// yuv422 - fmt_cfg = 5; - ScaleCbrX = CalScale((xact/2), par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - case YUV420: // yuv420 - fmt_cfg = 4; - ScaleCbrX = CalScale(xact/2, par->xsize); - ScaleCbrY = CalScale(yact/2, par->ysize); - break; - case YUV444:// yuv444 - fmt_cfg = 6; - ScaleCbrX = CalScale(xact, par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - default: - printk("%s:un supported format\n",__func__); - break; - } - - lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_YRGB, v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY)); - lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_CBR, v_X_SCL_FACTOR(ScaleCbrX) | v_Y_SCL_FACTOR(ScaleCbrY)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1, m_W1_FORMAT, v_W1_FORMAT(fmt_cfg)); - lcdc_writel(lcdc_dev, WIN1_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact)); - lcdc_writel(lcdc_dev, WIN1_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos)); - lcdc_writel(lcdc_dev, WIN1_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize)); - // enable win1 color key and set the color to black(rgb=0) - //lcdc_msk_reg(lcdc_dev, WIN1_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,v_COLORKEY_EN(1) | v_KEYCOLOR(0)); - switch(par->format) - { - case XBGR888: - lcdc_writel(lcdc_dev, WIN1_VIR,v_ARGB888_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); - break; - case ARGB888: - lcdc_writel(lcdc_dev, WIN1_VIR,v_ARGB888_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(0)); - break; - case RGB888: //rgb888 - lcdc_writel(lcdc_dev, WIN1_VIR,v_RGB888_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(0)); - break; - case RGB565: //rgb565 - lcdc_writel(lcdc_dev, WIN1_VIR,v_RGB565_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(0)); - break; - case YUV422: - case YUV420: - lcdc_writel(lcdc_dev, WIN1_VIR,v_YUV_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(0)); - break; - default: - printk("%s:un supported formate\n",__func__); - break; - } - - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int win2_set_par(struct rk30_lcdc_device *lcdc_dev,rk_screen *screen, - struct layer_par *par ) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u8 fmt_cfg = 0; - char fmt[9]; - - xact = par->xact; - yact = par->yact; - xvir = par->xvir; - yvir = par->yvir; - xpos = par->xpos+screen->left_margin + screen->hsync_len; - ypos = par->ypos+screen->upper_margin + screen->vsync_len; - - - DBG(1,"%s for lcdc%d>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - __func__,lcdc_dev->id,get_format_string(par->format,fmt),xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); - - if((!xact) || (!yact) || (!par->xsize) || (!par->ysize)) - { - dev_err(lcdc_dev->driver.dev,"invalid parameter for win2-->xact:%d yact:%d xsize:%d ysize:%d\n", - xact,yact,par->xsize,par->ysize); - return -EINVAL; - } - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - - lcdc_writel(lcdc_dev, WIN2_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos)); - lcdc_writel(lcdc_dev, WIN2_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize)); - // enable win1 color key and set the color to black(rgb=0) - //lcdc_msk_reg(lcdc_dev, WIN2_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,v_COLORKEY_EN(1) | v_KEYCOLOR(0)); - switch(par->format) - { - case XBGR888: - fmt_cfg = 0; - lcdc_writel(lcdc_dev, WIN2_VIR,v_ARGB888_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W2_RGB_RB_SWAP,v_W2_RGB_RB_SWAP(1)); - break; - case ARGB888: - fmt_cfg = 0; - lcdc_writel(lcdc_dev, WIN2_VIR,v_ARGB888_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W2_RGB_RB_SWAP,v_W2_RGB_RB_SWAP(0)); - break; - case ABGR888: - fmt_cfg = 0; - lcdc_writel(lcdc_dev, WIN2_VIR,v_ARGB888_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W2_RGB_RB_SWAP,v_W2_RGB_RB_SWAP(1)); - break; - case RGB888: //rgb888 - fmt_cfg = 1; - lcdc_writel(lcdc_dev, WIN2_VIR,v_RGB888_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W2_RGB_RB_SWAP,v_W2_RGB_RB_SWAP(0)); - break; - case RGB565: //rgb565 - fmt_cfg = 2; - lcdc_writel(lcdc_dev, WIN2_VIR,v_RGB565_VIRWIDTH(xvir)); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W2_RGB_RB_SWAP,v_W2_RGB_RB_SWAP(0)); - break; - default: - printk("%s:un supported format\n",__func__); - break; - } - - lcdc_msk_reg(lcdc_dev,SYS_CTRL1, m_W2_FORMAT, v_W2_FORMAT(fmt_cfg)); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk30_lcdc_open(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open) -{ - int i=0; - int __iomem *c; - int v; - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - - //printk("%s>>open:%d>>cnt:%d\n",__func__,open,lcdc_dev->atv_layer_cnt); - if((open) && (!lcdc_dev->atv_layer_cnt)) //enable clk,when first layer open - { - rk30_lcdc_clk_enable(lcdc_dev); - memcpy((u8*)lcdc_dev->regs, (u8*)lcdc_dev->regsbak, 0xc4); //resume reg - rk30_load_screen(dev_drv,1); - spin_lock(&lcdc_dev->reg_lock); - if(dev_drv->cur_screen->dsp_lut) //resume dsp lut - { - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(0)); - lcdc_cfg_done(lcdc_dev); - mdelay(25); - for(i=0;i<256;i++) - { - v = dev_drv->cur_screen->dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base+i; - writel_relaxed(v,c); - - } - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(1)); - } - spin_unlock(&lcdc_dev->reg_lock); - } - - if(layer_id == 0) - { - win0_open(lcdc_dev,open); - } - else if(layer_id == 1) - { - win1_open(lcdc_dev,open); - } - else if(layer_id == 2) - { - win2_open(lcdc_dev,open); - } - - if((!open) && (!lcdc_dev->atv_layer_cnt)) //when all layer closed,disable clk - { - rk30_lcdc_clk_disable(lcdc_dev); - } - - printk(KERN_INFO "lcdc%d win%d %s,atv layer:%d\n", - lcdc_dev->id,layer_id,open?"open":"closed", - lcdc_dev->atv_layer_cnt); - return 0; -} - -static int rk30_lcdc_set_par(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - struct layer_par *par = NULL; - rk_screen *screen = dev_drv->cur_screen; - - if(!screen) - { - printk(KERN_ERR "screen is null!\n"); - return -ENOENT; - } - if(layer_id==0) - { - par = dev_drv->layer_par[0]; - win0_set_par(lcdc_dev,screen,par); - } - else if(layer_id==1) - { - par = dev_drv->layer_par[1]; - win1_set_par(lcdc_dev,screen,par); - } - else if(layer_id == 2) - { - par = dev_drv->layer_par[2]; - win2_set_par(lcdc_dev,screen,par); - } - - return 0; -} - -int rk30_lcdc_pan_display(struct rk_lcdc_device_driver * dev_drv,int layer_id) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - struct layer_par *par = NULL; - rk_screen *screen = dev_drv->cur_screen; - unsigned long flags; - int timeout; - - if(!screen) - { - printk(KERN_ERR "screen is null!\n"); - return -ENOENT; - } - if(layer_id==0) - { - par = dev_drv->layer_par[0]; - win0_display(lcdc_dev,par); - } - else if(layer_id==1) - { - par = dev_drv->layer_par[1]; - win1_display(lcdc_dev,par); - } - else if(layer_id == 2) - { - par = dev_drv->layer_par[2]; - win2_display(lcdc_dev,par); - } - if((dev_drv->first_frame)) //this is the first frame of the system ,enable frame start interrupt - { - dev_drv->first_frame = 0; - lcdc_msk_reg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR |m_FRM_START_INT_EN , - v_FRM_START_INT_CLEAR(1) | v_FRM_START_INT_EN(1)); - lcdc_cfg_done(lcdc_dev); // write any value to REG_CFG_DONE let config become effective - - } - - if(dev_drv->num_buf < 3) //3buffer ,no need to wait for sysn - { - spin_lock_irqsave(&dev_drv->cpl_lock,flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock,flags); - timeout = wait_for_completion_timeout(&dev_drv->frame_done,msecs_to_jiffies(dev_drv->cur_screen->ft+5)); - if(!timeout&&(!dev_drv->frame_done.done)) - { - printk(KERN_ERR "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } - } - - return 0; -} - -int rk30_lcdc_ioctl(struct rk_lcdc_device_driver * dev_drv,unsigned int cmd, unsigned long arg,int layer_id) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - u32 panel_size[2]; - void __user *argp = (void __user *)arg; - int ret = 0; - struct color_key_cfg clr_key_cfg; - switch(cmd) - { - case RK_FBIOGET_PANEL_SIZE: //get panel size - panel_size[0] = dev_drv->screen0->x_res; - panel_size[1] = dev_drv->screen0->y_res; - if(copy_to_user(argp, panel_size, 8)) - return -EFAULT; - break; - case RK_FBIOPUT_COLOR_KEY_CFG: - if(copy_from_user(&clr_key_cfg,argp,sizeof(struct color_key_cfg ))) - return -EFAULT; - lcdc_writel(lcdc_dev,WIN0_COLOR_KEY_CTRL,clr_key_cfg.win0_color_key_cfg); - lcdc_writel(lcdc_dev,WIN1_COLOR_KEY_CTRL,clr_key_cfg.win1_color_key_cfg); - lcdc_writel(lcdc_dev,WIN2_COLOR_KEY_CTRL,clr_key_cfg.win2_color_key_cfg); - break; - default: - break; - } - - return ret; -} -static int rk30_lcdc_get_layer_state(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - struct layer_par *par = dev_drv->layer_par[layer_id]; - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) - { - if(layer_id == 0) - { - par->state = lcdc_read_bit(lcdc_dev,SYS_CTRL1,m_W0_EN); - } - else if( layer_id == 1) - { - par->state = lcdc_read_bit(lcdc_dev,SYS_CTRL1,m_W1_EN); - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return par->state; - -} - -/*********************************** -overlay manager -swap:1 win0 on the top of win1 - 0 win1 on the top of win0 -set : 1 set overlay - 0 get overlay state -************************************/ -static int rk30_lcdc_ovl_mgr(struct rk_lcdc_device_driver *dev_drv,int swap,bool set) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - int ovl; - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) - { - if(set) //set overlay - { - lcdc_msk_reg(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP,v_W0W1_POSITION_SWAP(swap)); - lcdc_writel(lcdc_dev, REG_CFG_DONE, 0x01); - lcdc_cfg_done(lcdc_dev); - ovl = swap; - } - else //get overlay - { - ovl = lcdc_read_bit(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP); - } - } - else - { - ovl = -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - - return ovl; -} - - -static ssize_t rk30_lcdc_get_disp_info(struct rk_lcdc_device_driver *dev_drv,char *buf,int layer_id) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - char format_w0[9]= "NULL"; - char format_w1[9]= "NULL"; - char format_w2[9]= "NULL"; - char status_w0[9]= "NULL"; - char status_w1[9]= "NULL"; - char status_w2[9]= "NULL"; - u32 fmt_id = lcdc_readl(lcdc_dev,SYS_CTRL1); - u32 act_info,dsp_info,dsp_st,factor; - u16 xvir_w0,x_act_w0,y_act_w0,x_dsp_w0,y_dsp_w0,x_st_w0,y_st_w0; - u16 xvir_w1,x_act_w1,y_act_w1,x_dsp_w1,y_dsp_w1,x_st_w1,y_st_w1; - u16 xvir_w2,x_dsp_w2,y_dsp_w2,x_st_w2,y_st_w2; - u16 x_scale_w0,y_scale_w0,x_scale_w1,y_scale_w1; - int ovl = lcdc_read_bit(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP); - - switch((fmt_id&m_W0_FORMAT)>>4) - { - case 0: - strcpy(format_w0,"ARGB888"); - break; - case 1: - strcpy(format_w0,"RGB888"); - break; - case 2: - strcpy(format_w0,"RGB565"); - break; - case 4: - strcpy(format_w0,"YCbCr420"); - break; - case 5: - strcpy(format_w0,"YCbCr422"); - break; - case 6: - strcpy(format_w0,"YCbCr444"); - break; - default: - strcpy(format_w0,"inval\n"); - break; - } - - - switch((fmt_id&m_W1_FORMAT)>>7) - { - case 0: - strcpy(format_w1,"ARGB888"); - break; - case 1: - strcpy(format_w1,"RGB888"); - break; - case 2: - strcpy(format_w1,"RGB565"); - break; - case 4: - strcpy(format_w1,"YCbCr420"); - break; - case 5: - strcpy(format_w1,"YCbCr422"); - break; - case 6: - strcpy(format_w1,"YCbCr444"); - break; - default: - strcpy(format_w1,"inval\n"); - break; - } - - switch((fmt_id&m_W2_FORMAT)>>10) - { - case 0: - strcpy(format_w2,"ARGB888"); - break; - case 1: - strcpy(format_w2,"RGB888"); - break; - case 2: - strcpy(format_w2,"RGB565"); - break; - case 4: - strcpy(format_w2,"8bpp"); - break; - case 5: - strcpy(format_w2,"4bpp"); - break; - case 6: - strcpy(format_w2,"2bpp"); - break; - case 7: - strcpy(format_w2,"1bpp"); - break; - default: - strcpy(format_w2,"inval\n"); - break; - } - - if(fmt_id&m_W0_EN) - { - strcpy(status_w0,"enabled"); - } - else - { - strcpy(status_w0,"disabled"); - } - - if((fmt_id&m_W1_EN)>>1) - { - strcpy(status_w1,"enabled"); - } - else - { - strcpy(status_w1,"disabled"); - } - - - if((fmt_id&m_W2_EN)>>1) - { - strcpy(status_w2,"enabled"); - } - else - { - strcpy(status_w2,"disabled"); - } - - xvir_w0 = lcdc_readl(lcdc_dev,WIN0_VIR)&0xffff; - act_info = lcdc_readl(lcdc_dev,WIN0_ACT_INFO); - dsp_info = lcdc_readl(lcdc_dev,WIN0_DSP_INFO); - dsp_st = lcdc_readl(lcdc_dev,WIN0_DSP_ST); - factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_YRGB); - x_act_w0 = (act_info&0xffff) + 1; - y_act_w0 = (act_info>>16) + 1; - x_dsp_w0 = (dsp_info&0xffff) + 1; - y_dsp_w0 = (dsp_info>>16) + 1; - x_st_w0 = (dsp_st&0xfff); - y_st_w0 = (dsp_st>>16); - x_scale_w0 = 4096*100/(factor&0xffff); - y_scale_w0 = 4096*100/(factor>>16); - - xvir_w1= lcdc_readl(lcdc_dev,WIN1_VIR)&0xffff; - act_info = lcdc_readl(lcdc_dev,WIN1_ACT_INFO); - dsp_info = lcdc_readl(lcdc_dev,WIN1_DSP_INFO); - dsp_st = lcdc_readl(lcdc_dev,WIN1_DSP_ST); - factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_YRGB); - x_act_w1= (act_info&0xffff) + 1; - y_act_w1 = (act_info>>16) + 1; - x_dsp_w1 = (dsp_info&0xffff) + 1; - y_dsp_w1= (dsp_info>>16) + 1; - x_st_w1 = (dsp_st&0xfff); - y_st_w1 = (dsp_st>>16); - x_scale_w1= 4096*100/(factor&0xffff); - y_scale_w1= 4096*100/(factor>>16); - - xvir_w2 = lcdc_readl(lcdc_dev,WIN2_VIR)&0xffff; - dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO); - dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST); - - x_dsp_w2 = dsp_info&0xffff; - y_dsp_w2 = dsp_info>>16; - x_st_w2 = dsp_st&0xfff; - y_st_w2 = dsp_st>>16; - - - return snprintf(buf,PAGE_SIZE, - "win0:%s\n" - "xvir:%d\n" - "xact:%d\n" - "yact:%d\n" - "xdsp:%d\n" - "ydsp:%d\n" - "x_st:%d\n" - "y_st:%d\n" - "x_scale:%d.%d\n" - "y_scale:%d.%d\n" - "format:%s\n" - "YRGB buffer addr:0x%08x\n" - "CBR buffer addr:0x%08x\n\n" - "win1:%s\n" - "xvir:%d\n" - "xact:%d\n" - "yact:%d\n" - "xdsp:%d\n" - "ydsp:%d\n" - "x_st:%d\n" - "y_st:%d\n" - "x_scale:%d.%d\n" - "y_scale:%d.%d\n" - "format:%s\n" - "YRGB buffer addr:0x%08x\n" - "CBR buffer addr:0x%08x\n\n" - "overlay:%s\n\n" - "win2:%s\n" - "xvir:%d\n" - "xdsp:%d\n" - "ydsp:%d\n" - "x_st:%d\n" - "y_st:%d\n" - "format:%s\n" - "YRGB buffer addr:0x%08x\n", - status_w0, - xvir_w0, - x_act_w0, - y_act_w0, - x_dsp_w0, - y_dsp_w0, - x_st_w0, - y_st_w0, - x_scale_w0/100, - x_scale_w0%100, - y_scale_w0/100, - y_scale_w0%100, - format_w0, - lcdc_readl(lcdc_dev,WIN0_YRGB_MST0), - lcdc_readl(lcdc_dev,WIN0_CBR_MST0), - status_w1, - xvir_w1, - x_act_w1, - y_act_w1, - x_dsp_w1, - y_dsp_w1, - x_st_w1, - y_st_w1, - x_scale_w1/100, - x_scale_w1%100, - y_scale_w1/100, - y_scale_w1%100, - format_w1, - lcdc_readl(lcdc_dev,WIN1_YRGB_MST), - lcdc_readl(lcdc_dev,WIN1_CBR_MST), - ovl ? "win0 on the top of win1\n":"win1 on the top of win0\n", - status_w2, - xvir_w2, - x_dsp_w2, - y_dsp_w2, - x_st_w2, - y_st_w2, - format_w2, - lcdc_readl(lcdc_dev,WIN2_MST)); - return 0; -} - -/******************************************* -lcdc fps manager,set or get lcdc fps - - - -set:0 get - 1 set -********************************************/ -static int rk30_lcdc_fps_mgr(struct rk_lcdc_device_driver *dev_drv,int fps,bool set) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - rk_screen * screen = dev_drv->cur_screen; - u64 ft = 0; - u32 dotclk; - int ret; - - if(set) - { - ft = div_u64(1000000000000llu,fps); - dev_drv->pixclock = div_u64(ft,(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)); - dotclk = div_u64(1000000000000llu,dev_drv->pixclock); - ret = clk_set_rate(lcdc_dev->dclk, dotclk); - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); - } - dev_drv->pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - - } - - ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* - (dev_drv->pixclock); // one frame time ,(pico seconds) - fps = div64_u64(1000000000000llu,ft); - screen->ft = 1000/fps ; //one frame time in ms - return fps; -} - -static int rk30_fb_layer_remap(struct rk_lcdc_device_driver *dev_drv, - enum fb_win_map_order order) -{ - mutex_lock(&dev_drv->fb_win_id_mutex); - if(order == FB_DEFAULT_ORDER ) - { - order = FB0_WIN1_FB1_WIN0_FB2_WIN2; - } - dev_drv->fb2_win_id = order/100; - dev_drv->fb1_win_id = (order/10)%10; - dev_drv->fb0_win_id = order%10; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - printk("fb0:win%d\nfb1:win%d\nfb2:win%d\n",dev_drv->fb0_win_id,dev_drv->fb1_win_id, - dev_drv->fb2_win_id); - - return 0; -} - -static int rk30_fb_get_layer(struct rk_lcdc_device_driver *dev_drv,const char *id) -{ - int layer_id = 0; - mutex_lock(&dev_drv->fb_win_id_mutex); - if(!strcmp(id,"fb0")||!strcmp(id,"fb3")) - { - layer_id = dev_drv->fb0_win_id; - } - else if(!strcmp(id,"fb1")||!strcmp(id,"fb4")) - { - layer_id = dev_drv->fb1_win_id; - } - else if(!strcmp(id,"fb2")||!strcmp(id,"fb5")) - { - layer_id = dev_drv->fb2_win_id; - } - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return layer_id; -} - -static int rk30_read_dsp_lut(struct rk_lcdc_device_driver *dev_drv,int *lut) -{ - - return 0; -} - -static int rk30_set_dsp_lut(struct rk_lcdc_device_driver *dev_drv,int *lut) -{ - int i=0; - int __iomem *c; - int v; - int ret = 0; - - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(0)); - lcdc_cfg_done(lcdc_dev); - msleep(25); - if(dev_drv->cur_screen->dsp_lut) - { - for(i=0;i<256;i++) - { - v = dev_drv->cur_screen->dsp_lut[i] = lut[i]; - c = lcdc_dev->dsp_lut_addr_base+i; - writel_relaxed(v,c); - - } - } - else - { - printk(KERN_WARNING "no buffer to backup lut data!\n"); - ret = -1; - } - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(1)); - lcdc_cfg_done(lcdc_dev); - - return ret; -} -int rk30_lcdc_early_suspend(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - - - if(dev_drv->screen0->standby) - dev_drv->screen0->standby(1); - if(dev_drv->screen_ctr_info->io_disable) - dev_drv->screen_ctr_info->io_disable(); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - } - else //clk already disabled - { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - - rk30_lcdc_clk_disable(lcdc_dev); - - return 0; -} - - -int rk30_lcdc_early_resume(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - int i=0; - int __iomem *c; - int v; - - if(dev_drv->screen_ctr_info->io_enable) //power on - dev_drv->screen_ctr_info->io_enable(); - - if(lcdc_dev->atv_layer_cnt) - { - rk30_lcdc_clk_enable(lcdc_dev); - - memcpy((u8*)lcdc_dev->regs, (u8*)lcdc_dev->regsbak, 0xc4); //resume reg - - spin_lock(&lcdc_dev->reg_lock); - if(dev_drv->cur_screen->dsp_lut) //resume dsp lut - { - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(0)); - lcdc_cfg_done(lcdc_dev); - mdelay(25); - for(i=0;i<256;i++) - { - v = dev_drv->cur_screen->dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base+i; - writel_relaxed(v,c); - - } - lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(1)); - } - - lcdc_msk_reg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); - lcdc_cfg_done(lcdc_dev); - - spin_unlock(&lcdc_dev->reg_lock); - - } - - if(dev_drv->screen0->standby) - dev_drv->screen0->standby(0); //screen wake up - - return 0; -} - - -static irqreturn_t rk30_lcdc_isr(int irq, void *dev_id) -{ - struct rk30_lcdc_device *lcdc_dev = (struct rk30_lcdc_device *)dev_id; - ktime_t timestamp = ktime_get(); - - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); - //lcdc_cfg_done(lcdc_dev); - //lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LINE_FLAG_INT_CLEAR, v_LINE_FLAG_INT_CLEAR(1)); - - if(lcdc_dev->driver.num_buf < 3) //three buffer ,no need to wait for sync - { - spin_lock(&(lcdc_dev->driver.cpl_lock)); - complete(&(lcdc_dev->driver.frame_done)); - spin_unlock(&(lcdc_dev->driver.cpl_lock)); - } - - lcdc_dev->driver.vsync_info.timestamp = timestamp; - wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait); - - return IRQ_HANDLED; -} - -static struct layer_par lcdc_layer[] = { - [0] = { - .name = "win0", - .id = 0, - .support_3d = true, - }, - [1] = { - .name = "win1", - .id = 1, - .support_3d = false, - }, - [2] = { - .name = "win2", - .id = 2, - .support_3d = false, - }, -}; - -static struct rk_lcdc_device_driver lcdc_driver = { - .name = "lcdc", - .def_layer_par = lcdc_layer, - .num_layer = ARRAY_SIZE(lcdc_layer), - .open = rk30_lcdc_open, - .init_lcdc = rk30_lcdc_init, - .ioctl = rk30_lcdc_ioctl, - .suspend = rk30_lcdc_early_suspend, - .resume = rk30_lcdc_early_resume, - .set_par = rk30_lcdc_set_par, - .blank = rk30_lcdc_blank, - .pan_display = rk30_lcdc_pan_display, - .load_screen = rk30_load_screen, - .get_layer_state = rk30_lcdc_get_layer_state, - .ovl_mgr = rk30_lcdc_ovl_mgr, - .get_disp_info = rk30_lcdc_get_disp_info, - .fps_mgr = rk30_lcdc_fps_mgr, - .fb_get_layer = rk30_fb_get_layer, - .fb_layer_remap = rk30_fb_layer_remap, - .set_dsp_lut = rk30_set_dsp_lut, - .read_dsp_lut = rk30_read_dsp_lut, -}; -#ifdef CONFIG_PM -static int rk30_lcdc_suspend(struct platform_device *pdev, pm_message_t state) -{ - return 0; -} - -static int rk30_lcdc_resume(struct platform_device *pdev) -{ - return 0; -} - -#else -#define rk30_lcdc_suspend NULL -#define rk30_lcdc_resume NULL -#endif - -static int __devinit rk30_lcdc_probe (struct platform_device *pdev) -{ - struct rk30_lcdc_device *lcdc_dev=NULL; - rk_screen *screen; -#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) - rk_screen *screen1; -#endif - struct rk29fb_info *screen_ctr_info; - struct resource *res = NULL; - struct resource *mem; - int ret = 0; - - /*************Malloc rk30lcdc_inf and set it to pdev for drvdata**********/ - lcdc_dev = kzalloc(sizeof(struct rk30_lcdc_device), GFP_KERNEL); - if(!lcdc_dev) - { - dev_err(&pdev->dev, ">>rk30 lcdc device kmalloc fail!"); - return -ENOMEM; - } - platform_set_drvdata(pdev, lcdc_dev); - lcdc_dev->id = pdev->id; - screen_ctr_info = (struct rk29fb_info * )pdev->dev.platform_data; - screen = kzalloc(sizeof(rk_screen), GFP_KERNEL); - if(!screen) - { - dev_err(&pdev->dev, ">>rk30 lcdc screen kmalloc fail!"); - ret = -ENOMEM; - goto err0; - } - else - { - lcdc_dev->screen = screen; - screen->lcdc_id = lcdc_dev->id; - screen->screen_id = 0; - } -#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& (defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS)) - screen1 = kzalloc(sizeof(rk_screen), GFP_KERNEL); - if(!screen1) - { - dev_err(&pdev->dev, ">>rk30 lcdc screen1 kmalloc fail!"); - ret = -ENOMEM; - goto err0; - } - screen1->lcdc_id = 1; - screen1->screen_id = 1; - printk("use lcdc%d and jetta implemention dual display!\n",lcdc_dev->id); - -#endif - /****************get lcdc0 reg *************************/ - res = platform_get_resource(pdev, IORESOURCE_MEM,0); - if (res == NULL) - { - dev_err(&pdev->dev, "failed to get io resource for lcdc%d \n",lcdc_dev->id); - ret = -ENOENT; - goto err1; - } - lcdc_dev->reg_phy_base = res->start; - lcdc_dev->len = resource_size(res); - mem = request_mem_region(lcdc_dev->reg_phy_base, resource_size(res), pdev->name); - if (mem == NULL) - { - dev_err(&pdev->dev, "failed to request mem region for lcdc%d\n",lcdc_dev->id); - ret = -ENOENT; - goto err1; - } - lcdc_dev->reg_vir_base = ioremap(lcdc_dev->reg_phy_base, resource_size(res)); - if (lcdc_dev->reg_vir_base == NULL) - { - dev_err(&pdev->dev, "cannot map IO\n"); - ret = -ENXIO; - goto err2; - } - - //lcdc_dev->preg = (LCDC_REG*)lcdc_dev->reg_vir_base; - lcdc_dev->regs = lcdc_dev->reg_vir_base; - lcdc_dev->regsbak = kzalloc(lcdc_dev->len,GFP_KERNEL); - if(!lcdc_dev->regsbak) - { - dev_err(&pdev->dev, "failed to map memory for reg backup!\n"); - } - //lcdc_dev->dsp_lut_addr_base = &lcdc_dev->preg->DSP_LUT_ADDR; - lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + DSP_LUT_ADDR); - printk("lcdc%d:reg_phy_base = 0x%08x,reg_vir_base:0x%p\n",pdev->id,lcdc_dev->reg_phy_base, lcdc_dev->regs); - lcdc_dev->driver.dev=&pdev->dev; - lcdc_dev->driver.screen0 = screen; -#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& (defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS)) - lcdc_dev->driver.screen1 = screen1; -#endif - lcdc_dev->driver.cur_screen = screen; - lcdc_dev->driver.screen_ctr_info = screen_ctr_info; - - spin_lock_init(&lcdc_dev->reg_lock); - lcdc_dev->irq = platform_get_irq(pdev, 0); - if(lcdc_dev->irq < 0) - { - dev_err(&pdev->dev, "cannot find IRQ\n"); - goto err3; - } - ret = request_irq(lcdc_dev->irq, rk30_lcdc_isr, IRQF_DISABLED,dev_name(&pdev->dev),lcdc_dev); - if (ret) - { - dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", lcdc_dev->irq, ret); - ret = -EBUSY; - goto err3; - } - - if(screen_ctr_info->set_screen_info) - { - screen_ctr_info->set_screen_info(screen,screen_ctr_info->lcd_info); - if(SCREEN_NULL==screen->type) - { - printk(KERN_WARNING "no display device on lcdc%d!?\n",lcdc_dev->id); - ret = -ENODEV; - } - if(screen_ctr_info->io_init) - screen_ctr_info->io_init(NULL); - } - else - { - printk(KERN_WARNING "no display device on lcdc%d!?\n",lcdc_dev->id); - ret = -ENODEV; - goto err4; - } - - ret = rk_fb_register(&(lcdc_dev->driver),&lcdc_driver,lcdc_dev->id); - if(ret < 0) - { - printk(KERN_ERR "register fb for lcdc%d failed!\n",lcdc_dev->id); - goto err4; - } - printk("rk30 lcdc%d probe ok!\n",lcdc_dev->id); - - return 0; - -err4: - free_irq(lcdc_dev->irq,lcdc_dev); -err3: - iounmap(lcdc_dev->reg_vir_base); -err2: - release_mem_region(lcdc_dev->reg_phy_base,resource_size(res)); -err1: - kfree(screen); -err0: - platform_set_drvdata(pdev, NULL); - kfree(lcdc_dev); - return ret; - -} -static int __devexit rk30_lcdc_remove(struct platform_device *pdev) -{ - struct rk30_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - rk_fb_unregister(&(lcdc_dev->driver)); - rk30_lcdc_deinit(lcdc_dev); - iounmap(lcdc_dev->reg_vir_base); - release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); - kfree(lcdc_dev->screen); - kfree(lcdc_dev); - return 0; -} - -static void rk30_lcdc_shutdown(struct platform_device *pdev) -{ - struct rk30_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - if(lcdc_dev->driver.cur_screen->standby) //standby the screen if necessary - lcdc_dev->driver.cur_screen->standby(1); - if(lcdc_dev->driver.screen_ctr_info->io_disable) //power off the screen if necessary - lcdc_dev->driver.screen_ctr_info->io_disable(); - if(lcdc_dev->driver.cur_screen->sscreen_set) //turn off lvds if necessary - lcdc_dev->driver.cur_screen->sscreen_set(lcdc_dev->driver.cur_screen , 0); - rk30_lcdc_deinit(lcdc_dev); - //rk_fb_unregister(&(lcdc_dev->driver)); - - /*iounmap(lcdc_dev->reg_vir_base); - release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); - kfree(lcdc_dev->screen); - kfree(lcdc_dev);*/ -} - - -static struct platform_driver rk30lcdc_driver = { - .probe = rk30_lcdc_probe, - .remove = __devexit_p(rk30_lcdc_remove), - .driver = { - .name = "rk30-lcdc", - .owner = THIS_MODULE, - }, - .suspend = rk30_lcdc_suspend, - .resume = rk30_lcdc_resume, - .shutdown = rk30_lcdc_shutdown, -}; - -static int __init rk30_lcdc_module_init(void) -{ - return platform_driver_register(&rk30lcdc_driver); -} - -static void __exit rk30_lcdc_module_exit(void) -{ - platform_driver_unregister(&rk30lcdc_driver); -} - - - -fs_initcall(rk30_lcdc_module_init); -module_exit(rk30_lcdc_module_exit); - - - diff --git a/drivers/video/rockchip/lcdc/rk30_lcdc.h b/drivers/video/rockchip/lcdc/rk30_lcdc.h deleted file mode 100644 index 9d754971afa5..000000000000 --- a/drivers/video/rockchip/lcdc/rk30_lcdc.h +++ /dev/null @@ -1,700 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef RK30_LCDC_H_ -#define RK30_LCDC_H_ - -#include - - -#if 0 -#define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk)) -#define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val) -#define LcdRdReg(inf, addr) (inf->preg->addr) -#define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk)) -#define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk)) -#define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk)) -#define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val)) -#define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb() - -/******************************************************************** -** ½á¹¹¶¨Òå * -********************************************************************/ -/* LCDCµÄ¼Ä´æÆ÷½á¹¹ */ - -typedef volatile struct tagLCDC_REG -{ - /* offset 0x00~0xc0 */ - unsigned int SYS_CTRL0; //0x00 system control register 0 - unsigned int SYS_CTRL1; //0x04 system control register 1 - unsigned int DSP_CTRL0; //0x08 display control register 0 - unsigned int DSP_CTRL1; //0x0c display control register 1 - unsigned int INT_STATUS; //0x10 Interrupt status register - unsigned int MCU_CTRL ; //0x14 MCU mode contol register - unsigned int BLEND_CTRL; //0x18 Blending control register - unsigned int WIN0_COLOR_KEY_CTRL; //0x1c Win0 blending control register - unsigned int WIN1_COLOR_KEY_CTRL; //0x20 Win1 blending control register - unsigned int WIN2_COLOR_KEY_CTRL; //0x24 Win2 blending control register - unsigned int WIN0_YRGB_MST0; //0x28 Win0 active YRGB memory start address0 - unsigned int WIN0_CBR_MST0; //0x2c Win0 active Cbr memory start address0 - unsigned int WIN0_YRGB_MST1; //0x30 Win0 active YRGB memory start address1 - unsigned int WIN0_CBR_MST1; //0x34 Win0 active Cbr memory start address1 - unsigned int WIN0_VIR; //0x38 WIN0 virtual display width/height - unsigned int WIN0_ACT_INFO; //0x3C Win0 active window width/height - unsigned int WIN0_DSP_INFO; //0x40 Win0 display width/height on panel - unsigned int WIN0_DSP_ST; //0x44 Win0 display start point on panel - unsigned int WIN0_SCL_FACTOR_YRGB; //0x48Win0 YRGB scaling factor setting - unsigned int WIN0_SCL_FACTOR_CBR; //0x4c Win0 YRGB scaling factor setting - unsigned int WIN0_SCL_OFFSET; //0x50 Win0 Cbr scaling start point offset - unsigned int WIN1_YRGB_MST; //0x54 Win1 active YRGB memory start address - unsigned int WIN1_CBR_MST; //0x58 Win1 active Cbr memory start address - unsigned int WIN1_VIR; //0x5c WIN1 virtual display width/height - unsigned int WIN1_ACT_INFO; //0x60 Win1 active window width/height - unsigned int WIN1_DSP_INFO; //0x64 Win1 display width/height on panel - unsigned int WIN1_DSP_ST; //0x68 Win1 display start point on panel - unsigned int WIN1_SCL_FACTOR_YRGB; //0x6c Win1 YRGB scaling factor setting - unsigned int WIN1_SCL_FACTOR_CBR; //0x70 Win1 YRGB scaling factor setting - unsigned int WIN1_SCL_OFFSET; //0x74 Win1 Cbr scaling start point offset - unsigned int WIN2_MST; //0x78 win2 memort start address - unsigned int WIN2_VIR; //0x7c win2 virtual stride - unsigned int WIN2_DSP_INFO; //0x80 Win2 display width/height on panel - unsigned int WIN2_DSP_ST; //0x84 Win2 display start point on panel - unsigned int HWC_MST; //0x88 HWC memory start address - unsigned int HWC_DSP_ST; //0x8C HWC display start point on panel - unsigned int HWC_COLOR_LUT0; //0x90 Hardware cursor color 2¡¯b01 look up table 0 - unsigned int HWC_COLOR_LUT1; //0x94 Hardware cursor color 2¡¯b10 look up table 1 - unsigned int HWC_COLOR_LUT2; //0x98 Hardware cursor color 2¡¯b11 look up table 2 - unsigned int DSP_HTOTAL_HS_END; //0x9c Panel scanning horizontal width and hsync pulse end point - unsigned int DSP_HACT_ST_END; //0xa0 Panel active horizontal scanning start/end point - unsigned int DSP_VTOTAL_VS_END; //0xa4 Panel scanning vertical height and vsync pulse end point - unsigned int DSP_VACT_ST_END; //0xa8 Panel active vertical scanning start/end point - unsigned int DSP_VS_ST_END_F1; //0xac Vertical scanning start point and vsync pulse end point of even filed in interlace mode - unsigned int DSP_VACT_ST_END_F1; //0xb0 Vertical scanning active start/end point of even filed in interlace mode - unsigned int reserved0[(0xc0-0xb4)/4]; - unsigned int REG_CFG_DONE; //0xc0 REGISTER CONFIG FINISH - unsigned int reserved1[(0x100-0xc4)/4]; - unsigned int MCU_BYPASS_WPORT; //0x100 MCU BYPASS MODE, DATA Write Only Port - unsigned int reserved2[(0x200-0x104)/4]; - unsigned int MCU_BYPASS_RPORT; //0x200 MCU BYPASS MODE, DATA Read Only Port - unsigned int reserved3[(0x400-0x204)/4]; - unsigned int WIN2_LUT_ADDR; - unsigned int reserved4[(0x800-0x404)/4]; - unsigned int DSP_LUT_ADDR; - -} LCDC_REG, *pLCDC_REG; - -#else - -#define SYS_CTRL0 0x00 //0x00 system control register 0 -#define SYS_CTRL1 0x04 //0x04 system control register 1 -#define DSP_CTRL0 0x08 //0x08 display control register 0 -#define DSP_CTRL1 0x0c //0x0c display control register 1 -#define INT_STATUS 0x10 //0x10 Interrupt status register -#define MCU_CTRL 0x14 //0x14 MCU mode contol register -#define BLEND_CTRL 0x18 //0x18 Blending control register -#define WIN0_COLOR_KEY_CTRL 0x1c //0x1c Win0 blending control register -#define WIN1_COLOR_KEY_CTRL 0x20 //0x20 Win1 blending control register -#define WIN2_COLOR_KEY_CTRL 0x24 //0x24 Win2 blending control register -#define WIN0_YRGB_MST0 0x28 //0x28 Win0 active YRGB memory start address0 -#define WIN0_CBR_MST0 0x2c //0x2c Win0 active Cbr memory start address0 -#define WIN0_YRGB_MST1 0x30 //0x30 Win0 active YRGB memory start address1 -#define WIN0_CBR_MST1 0x34 //0x34 Win0 active Cbr memory start address1 -#define WIN0_VIR 0x38 //0x38 WIN0 virtual display width/height -#define WIN0_ACT_INFO 0x3c //0x3C Win0 active window width/height -#define WIN0_DSP_INFO 0x40 //0x40 Win0 display width/height on panel -#define WIN0_DSP_ST 0x44 //0x44 Win0 display start point on panel -#define WIN0_SCL_FACTOR_YRGB 0x48 //0x48Win0 YRGB scaling factor setting -#define WIN0_SCL_FACTOR_CBR 0x4c //0x4c Win0 YRGB scaling factor setting -#define WIN0_SCL_OFFSET 0x50 //0x50 Win0 Cbr scaling start point offset -#define WIN1_YRGB_MST 0x54 //0x54 Win1 active YRGB memory start address -#define WIN1_CBR_MST 0x58 //0x58 Win1 active Cbr memory start address -#define WIN1_VIR 0x5c //0x5c WIN1 virtual display width/height -#define WIN1_ACT_INFO 0x60 //0x60 Win1 active window width/height -#define WIN1_DSP_INFO 0x64 //0x64 Win1 display width/height on panel -#define WIN1_DSP_ST 0x68 //0x68 Win1 display start point on panel -#define WIN1_SCL_FACTOR_YRGB 0x6c //0x6c Win1 YRGB scaling factor setting -#define WIN1_SCL_FACTOR_CBR 0x70 //0x70 Win1 YRGB scaling factor setting -#define WIN1_SCL_OFFSET 0x74 //0x74 Win1 Cbr scaling start point offset -#define WIN2_MST 0x78 //0x78 win2 memort start address -#define WIN2_VIR 0x7c //0x7c win2 virtual stride -#define WIN2_DSP_INFO 0x80 //0x80 Win2 display width/height on panel -#define WIN2_DSP_ST 0x84 //0x84 Win2 display start point on panel -#define HWC_MST 0x88 //0x88 HWC memory start address -#define HWC_DSP_ST 0x8c //0x8C HWC display start point on panel -#define HWC_COLOR_LUT0 0x90 //0x90 Hardware cursor color 2¡¯b01 look up table 0 -#define HWC_COLOR_LUT1 0x94 //0x94 Hardware cursor color 2¡¯b10 look up table 1 -#define HWC_COLOR_LUT2 0x98 //0x98 Hardware cursor color 2¡¯b11 look up table 2 -#define DSP_HTOTAL_HS_END 0x9c //0x9c Panel scanning horizontal width and hsync pulse end point -#define DSP_HACT_ST_END 0xa0 //0xa0 Panel active horizontal scanning start/end point -#define DSP_VTOTAL_VS_END 0xa4 //0xa4 Panel scanning vertical height and vsync pulse end point -#define DSP_VACT_ST_END 0xa8 //0xa8 Panel active vertical scanning start/end point -#define DSP_VS_ST_END_F1 0xac //0xac Vertical scanning start point and vsync pulse end point of even filed in interlace mode -#define DSP_VACT_ST_END_F1 0xb0 //0xb0 Vertical scanning active start/end point of even filed in interlace mode -#define REG_CFG_DONE 0xc0 //0xc0 REGISTER CONFIG FINISH -#define MCU_BYPASS_WPORT 0x100 //0x100 MCU BYPASS MODE, DATA Write Only Port -#define MCU_BYPASS_RPORT 0x200 //0x200 MCU BYPASS MODE, DATA Read Only Port -#define WIN2_LUT_ADDR 0x400 -#define DSP_LUT_ADDR 0x800 - -#if 0 -#define lcdc_writel(lcdc_dev,offset,v) do { \ - u32 *_pv = (u32*)lcdc_dev->regsbak; \ - _pv += (offset >> 2); \ - writel_relaxed(v,lcdc_dev->regs+offset);\ - *_pv = v; \ -} while(0) - -#define lcdc_readl(lcdc_dev,offset) \ - readl_relaxed(lcdc_dev->regs+offset) - -#define lcdc_read_bit(lcdc_dev,offset,msk) ( { \ - u32 _v = readl_relaxed(lcdc_dev->regs+offset); \ - _v &= msk;_v; } ) - -#define lcdc_set_bit(lcdc_dev,offset,msk) do { \ - u32* _pv = (u32*)lcdc_dev->regsbak; \ - _pv += (offset >> 2); \ - (*_pv) |= msk; \ - writel_relaxed(*_pv,lcdc_dev->regs + offset); \ -} while(0) - -#define lcdc_clr_bit(lcdc_dev,offset,msk) do{ \ - u32* _pv = (u32*)lcdc_dev->regsbak; \ - _pv += (offset >> 2); \ - (*_pv) &= ~msk; \ - writel_relaxed(*_pv,lcdc_dev->regs + offset); \ -} while (0) - -#define lcdc_msk_reg(lcdc_dev,offset,msk,v) do { \ - u32 *_pv = (u32*)lcdc_dev->regsbak; \ - _pv += (offset >> 2); \ - (*_pv) &= (~msk); \ - (*_pv) |= v; \ - writel_relaxed(*_pv,lcdc_dev->regs+offset); \ -} while(0) - -#define lcdc_cfg_done(lcdc_dev) do{ \ - writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE); \ - dsb(); \ -} while(0) -#endif -#endif - -/* SYS_CONFIG */ - -#define m_LCDC_DMA_STOP (1<<0) -#define m_LCDC_STANDBY (1<<1) -#define m_HWC_RELOAD_EN (1<<2) -#define m_W0_AXI_OUTSTANDING_DISABLE (1<<3) -#define m_W1_AXI_OUTSTANDING_DISABLE (1<<4) -#define m_W2_AXI_OUTSTANDING_DISABLE (1<<5) -#define m_DMA_BURST_LENGTH (3<<6) -#define m_WIN0_YRGB_CHANNEL0_ID ((0x07)<<8) -#define m_WIN0_CBR_CHANNEL0_ID ((0x07)<<11) -#define m_WIN0_YRGB_CHANNEL1_ID ((0x07)<<14) -#define m_WIN0_CBR_CHANNEL1_ID ((0x07)<<17) -#define m_WIN1_YRGB_CHANNEL_ID ((0x07)<<20) -#define m_WIN1_CBR_CHANNEL_ID ((0x07)<<23) -#define m_WIN2_CHANNEL_ID ((0x07)<<26) -#define m_HWC_CHANNEL_ID ((0x07)<<29) - - - - - -#define v_LCDC_DMA_STOP(x) (((x)&1)<<0) -#define v_LCDC_STANDBY(x) (((x)&1)<<1) -#define v_HWC_RELOAD_EN(x) (((x)&1)<<2) -#define v_W0_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<3) -#define v_W1_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<4) -#define v_W2_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<5) -#define v_DMA_BURST_LENGTH(x) (((x)&3)<<6) -#define v_WIN0_YRGB_CHANNEL0_ID(x) (((x)&7)<<8) -#define v_WIN0_CBR_CHANNEL0_ID(x) (((x)&7)<<11) -#define v_WIN0_YRGB_CHANNEL1_ID(x) (((x)&7)<<14) -#define v_WIN0_CBR_CHANNEL1_ID(x) (((x)&7)<<17) -#define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&7)<<20) -#define v_WIN1_CBR_CHANNEL_ID(x) (((x)&7)<<23) -#define v_WIN2_CHANNEL_ID(x) (((x)&7)<<26) -#define v_HWC_CHANNEL_ID(x) (((x)&7)<<29) - - - -//LCDC_SYS_CTRL1 -#define m_W0_EN (1<<0) -#define m_W1_EN (1<<1) -#define m_W2_EN (1<<2) -#define m_HWC_EN (1<<3) -#define m_W0_FORMAT (7<<4) -#define m_W1_FORMAT (7<<7) -#define m_W2_FORMAT (7<<10) -#define m_HWC_COLOR_MODE (1<<13) -#define m_HWC_SIZE_SELET (1<<14) -#define m_W0_3D_MODE_EN (1<<15) -#define m_W0_3D_MODE_SELET (7<<16) -#define m_W0_RGB_RB_SWAP (1<<19) -#define m_W0_RGB_ALPHA_SWAP (1<<20) -#define m_W0_YRGB_M8_SWAP (1<<21) -#define m_W0_CBCR_SWAP (1<<22) -#define m_W1_RGB_RB_SWAP (1<<23) -#define m_W1_RGB_ALPHA_SWAP (1<<24) -#define m_W1_YRGB_M8_SWAP (1<<25) -#define m_W1_CBCR_SWAP (1<<26) -#define m_W2_RGB_RB_SWAP (1<<27) -#define m_W2_RGB_ALPHA_SWAP (1<<28) -#define m_W2_8pp_PALETTE_ENDIAN_SELECT (1<<29) -#define m_W2_LUT_RAM_EN (1<<30) -#define m_DSP_LUT_RAM_EN (1<<31) - -#define v_W0_EN(x) (((x)&1)<<0) -#define v_W1_EN(x) (((x)&1)<<1) -#define v_W2_EN(x) (((x)&1)<<2) -#define v_HWC_EN(x) (((x)&1)<<3) -#define v_W0_FORMAT(x) (((x)&7)<<4) -#define v_W1_FORMAT(x) (((x)&7)<<7) -#define v_W2_FORMAT(x) (((x)&7)<<10) -#define v_HWC_COLOR_MODE(x) (((x)&1)<<13) -#define v_HWC_SIZE_SELET(x) (((x)&1)<<14) -#define v_W0_3D_MODE_EN(x) (((x)&1)<<15) -#define v_W0_3D_MODE_SELET(x) (((x)&3)<<16) -#define v_W0_RGB_RB_SWAP(x) (((x)&1)<<19) -#define v_W0_RGB_ALPHA_SWAP(x) (((x)&1)<<20) -#define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<21) -#define v_W0_CBCR_SWAP(x) (((x)&1)<<22) -#define v_W1_RGB_RB_SWAP(x) (((x)&1)<<23) -#define v_W1_RGB_ALPHA_SWAP(x) (((x)&1)<<24) -#define v_W1_YRGB_M8_SWAP(x) (((x)&1)<<25) -#define v_W1_CBCR_SWAP(x) (((x)&1)<<26) -#define v_W2_RGB_RB_SWAP(x) (((x)&1)<<27) -#define v_W2_RGB_ALPHA_SWAP(x) (((x)&1)<<28) -#define v_W2_8pp_PALETTE_ENDIAN_SELECT (((x)&1)<<29) -#define v_W2_LUT_RAM_EN(x) (((x)&1)<<30) -#define v_DSP_LUT_RAM_EN(x) (((x)&1)<<31) - -//LCDC_DSP_CTRL_REG0 -#define m_DISPLAY_FORMAT (0x0f<<0) -#define m_HSYNC_POLARITY (1<<4) -#define m_VSYNC_POLARITY (1<<5) -#define m_DEN_POLARITY (1<<6) -#define m_DCLK_POLARITY (1<<7) -#define m_W0W1_POSITION_SWAP (1<<8) -#define m_DITHER_UP_EN (1<<9) -#define m_DITHER_DOWN_MODE (1<<10) -#define m_DITHER_DOWN_EN (1<<11) -#define m_INTERLACE_DSP_EN (1<<12) -#define m_INTERLACE_FIELD_POLARITY (1<<13) -#define m_W0_INTERLACE_READ_MODE (1<<14) -#define m_W1_INTERLACE_READ_MODE (1<<15) -#define m_W2_INTERLACE_READ_MODE (1<<16) -#define m_W0_YRGB_DEFLICK_MODE (1<<17) -#define m_W0_CBR_DEFLICK_MODE (1<<18) -#define m_W1_YRGB_DEFLICK_MODE (1<<19) -#define m_W1_CBR_DEFLICK_MODE (1<<20) -#define m_W0_ALPHA_MODE (1<<21) -#define m_W1_ALPHA_MODE (1<<22) -#define m_W2_ALPHA_MODE (1<<23) -#define m_W0_COLOR_SPACE_CONVERSION (3<<24) -#define m_W1_COLOR_SPACE_CONVERSION (3<<26) -#define m_W2_COLOR_SPACE_CONVERSION (1<<28) -#define m_YCRCB_CLIP_EN (1<<29) -#define m_CBR_FILTER_656 (1<<30) -#define m_LCDC_AXICLK_AUTO_ENABLE (1<<31) //eanble for low power - -#define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0) -#define v_HSYNC_POLARITY(x) (((x)&1)<<4) -#define v_VSYNC_POLARITY(x) (((x)&1)<<5) -#define v_DEN_POLARITY(x) (((x)&1)<<6) -#define v_DCLK_POLARITY(x) (((x)&1)<<7) -#define v_W0W1_POSITION_SWAP(x) (((x)&1)<<8) -#define v_DITHER_UP_EN(x) (((x)&1)<<9) -#define v_DITHER_DOWN_MODE(x) (((x)&1)<<10) -#define v_DITHER_DOWN_EN(x) (((x)&1)<<11) -#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12) -#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13) -#define v_W0_INTERLACE_READ_MODE(x) (((x)&1)<<14) -#define v_W1_INTERLACE_READ_MODE(x) (((x)&1)<<15) -#define v_W2_INTERLACE_READ_MODE(x) (((x)&1)<<16) -#define v_W0_YRGB_DEFLICK_MODE(x) (((x)&1)<<17) -#define v_W0_CBR_DEFLICK_MODE(x) (((x)&1)<<18) -#define v_W1_YRGB_DEFLICK_MODE(x) (((x)&1)<<19) -#define v_W1_CBR_DEFLICK_MODE(x) (((x)&1)<<20) -#define v_W0_ALPHA_MODE(x) (((x)&1)<<21) -#define v_W1_ALPHA_MODE(x) (((x)&1)<<22) -#define v_W2_ALPHA_MODE(x) (((x)&1)<<23) -#define v_W0_COLOR_SPACE_CONVERSION(x) (((x)&3)<<24) -#define v_W1_COLOR_SPACE_CONVERSION(x) (((x)&3)<<26) -#define v_W2_COLOR_SPACE_CONVERSION(x) (((x)&1)<<28) -#define v_YCRCB_CLIP_EN(x) (((x)&1)<<29) -#define v_CBR_FILTER_656(x) (((x)&1)<<30) -#define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<31) //eanble for low power - -//LCDC_DSP_CTRL_REG1 -#define m_BG_COLOR (0xffffff<<0) -#define m_BG_B (0xff<<0) -#define m_BG_G (0xff<<8) -#define m_BG_R (0xff<<16) -#define m_BLANK_MODE (1<<24) -#define m_BLACK_MODE (1<<25) -#define m_OUTPUT_BG_SWAP (1<<26) -#define m_OUTPUT_RB_SWAP (1<<27) -#define m_OUTPUT_RG_SWAP (1<<28) -#define m_DELTA_SWAP (1<<29) -#define m_DUMMY_SWAP (1<<30) - -#define v_BG_COLOR(x) (((x)&0xffffff)<<0) -#define v_BG_B(x) (((x)&0xff)<<0) -#define v_BG_G(x) (((x)&0xff)<<8) -#define v_BG_R(x) (((x)&0xff)<<16) -#define v_BLANK_MODE(x) (((x)&1)<<24) -#define v_BLACK_MODE(x) (((x)&1)<<25) -#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<26) -#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<27) -#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<28) -#define v_DELTA_SWAP(x) (((x)&1)<<29) -#define v_DUMMY_SWAP(x) (((x)&1)<<30) - - -//LCDC_INT_STATUS -#define v_HOR_START_INT_STA (1<<0) //status -#define v_FRM_START_INT_STA (1<<1) -#define v_LINE_FLAG_INT_STA (1<<2) -#define v_BUS_ERR_INT_STA (1<<3) -#define m_HOR_START_INT_EN (1<<4) //enable -#define m_FRM_START_INT_EN (1<<5) -#define m_LINE_FLAG_INT_EN (1<<6) -#define m_BUS_ERR_INT_EN (1<<7) -#define m_HOR_START_INT_CLEAR (1<<8) //auto clear -#define m_FRM_START_INT_CLEAR (1<<9) -#define m_LINE_FLAG_INT_CLEAR (1<<10) -#define m_BUS_ERR_INT_CLEAR (1<<11) -#define m_LINE_FLAG_NUM (0xfff<<12) -#define v_HOR_START_INT_EN(x) (((x)&1)<<4) -#define v_FRM_START_INT_EN(x) (((x)&1)<<5) -#define v_LINE_FLAG_INT_EN(x) (((x)&1)<<6) -#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7) -#define v_HOR_START_INT_CLEAR(x) (((x)&1)<<8) -#define v_FRM_START_INT_CLEAR(x) (((x)&1)<<9) -#define v_LINE_FLAG_INT_CLEAR(x) (((x)&1)<<10) -#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11) -#define v_LINE_FLAG_NUM(x) (((x)&0xfff)<<12) - - - -//LCDC_MCU_TIMING_CTRL -#define m_MCU_WRITE_PERIOD (0x3f<<0) -#define m_MCU_CS_ST (0xf<<6) -#define m_MCU_CS_END (0x3f<<10) -#define m_MCU_RW_ST (0xf<<16) -#define m_MCU_RW_END (0x3f<<20) -#define m_MCU_BPS_CLK_SEL (1<<26) -#define m_MCU_HOLDMODE_SELECT (1<<27) -#define m_MCU_HOLDMODE_FRAME_ST (1<<28) -#define m_MCU_RS_SELECT (1<<29) -#define m_MCU_BYPASSMODE_SELECT (1<<30) -#define m_MCU_OUTPUT_SELECT (1<<31) -#define v_MCU_WRITE_PERIOD(x) (((x)&0x3f)<<0) -#define v_MCU_CS_ST(x) (((x)&0xf)<<6) -#define v_MCU_CS_END(x) (((x)&0x3f)<<10) -#define v_MCU_RW_ST(x) (((x)&0xf)<<16) -#define v_MCU_RW_END(x) (((x)&0x3f)<<20) -#define v_MCU_BPS_CLK_SEL (((x)&1)<<26) -#define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27) -#define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28) -#define v_MCU_RS_SELECT(x) (((x)&1)<<29) -#define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30) -#define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31) - -//LCDC_ BLEND_CTRL -#define m_W0_BLEND_EN (1<<0) -#define m_W1_BLEND_EN (1<<1) -#define m_W2_BLEND_EN (1<<2) -#define m_HWC_BLEND_EN (1<<3) -#define m_W0_BLEND_FACTOR (15<<4) -#define m_W1_BLEND_FACTOR (0xff<<8) -#define m_W2_BLEND_FACTOR (0xff<<16) -#define m_HWC_BLEND_FACTOR (0xff<<24) - -#define v_W0_BLEND_EN(x) (((x)&1)<<0) -#define v_W1_BLEND_EN(x) (((x)&1)<<1) -#define v_W2_BLEND_EN(x) (((x)&1)<<2) -#define v_HWC_BLEND_EN(x) (((x)&1)<<3) -#define v_W0_BLEND_FACTOR(x) (((x)&15)<<4) -#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<8) -#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<16) -#define v_HWC_BLEND_FACTOR(x) (((x)&0xff)<<24) - - -//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL -#define m_KEYCOLOR (0xffffff<<0) -#define m_KEYCOLOR_B (0xff<<0) -#define m_KEYCOLOR_G (0xff<<8) -#define m_KEYCOLOR_R (0xff<<16) -#define m_COLORKEY_EN (1<<24) -#define v_KEYCOLOR(x) (((x)&0xffffff)<<0) -#define v_KEYCOLOR_B(x) (((x)&0xff)<<0) -#define v_KEYCOLOR_G(x) (((x)&0xff)<<8) -#define v_KEYCOLOR_R(x) (((x)&0xff)<<16) -#define v_COLORKEY_EN(x) (((x)&1)<<24) - -//LCDC_DEFLICKER_SCL_OFFSET -#define m_W0_YRGB_VSD_OFFSET (0xff<<0) -#define m_W0_YRGB_VSP_OFFSET (0xff<<8) -#define m_W1_VSD_OFFSET (0xff<<16) -#define m_W1_VSP_OFFSET (0xff<<24) -#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0) -#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8) -#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16) -#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24) - - - - - -//AXI MS ID -#define m_W0_YRGB_CH_ID (0xF<<0) -#define m_W0_CBR_CH_ID (0xF<<4) -#define m_W1_YRGB_CH_ID (0xF<<8) -#define m_W2_CH_ID (0xF<<12) -#define m_HWC_CH_ID (0xF<<16) -#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0) -#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4) -#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8) -#define v_W2_CH_ID(x) (((x)&0xF)<<12) -#define v_HWC_CH_ID(x) (((x)&0xF)<<16) - - -/* Low Bits Mask */ -#define m_WORDLO (0xffff<<0) -#define m_WORDHI (0xffff<<16) -#define v_WORDLO(x) (((x)&0xffff)<<0) -#define v_WORDHI(x) (((x)&0xffff)<<16) - - -//LCDC_WINx_SCL_FACTOR_Y/CBCR -#define v_X_SCL_FACTOR(x) ((x)<<0) -#define v_Y_SCL_FACTOR(x) ((x)<<16) - -//LCDC_DSP_HTOTAL_HS_END -#define v_HSYNC(x) ((x)<<0) //hsync pulse width -#define v_HORPRD(x) ((x)<<16) //horizontal period - - -//LCDC_DSP_HACT_ST_END -#define v_HAEP(x) ((x)<<0) //horizontal active end point -#define v_HASP(x) ((x)<<16) //horizontal active start point - -//LCDC_DSP_VTOTAL_VS_END -#define v_VSYNC(x) ((x)<<0) -#define v_VERPRD(x) ((x)<<16) - -//LCDC_DSP_VACT_ST_END -#define v_VAEP(x) ((x)<<0) -#define v_VASP(x) ((x)<<16) - - -//LCDC_WINx_VIR ,x is number of words of win0 virtual width -#define v_ARGB888_VIRWIDTH(x) (x) -#define v_RGB888_VIRWIDTH(x) (((x*3)>>2)+((x)%3)) -#define v_RGB565_VIRWIDTH(x) (((x)>>1) + ((x%2)?1:0)) -#define v_YUV_VIRWIDTH(x) (((x)>>2) +((x%4)?1:0)) - -#define m_ACTWIDTH (0xffff<<0) -#define m_ACTHEIGHT (0xffff<<16) -#define v_ACTWIDTH(x) (((x)&0xffff)<<0) -#define v_ACTHEIGHT(x) (((x)&0xffff)<<16) - -#define m_VIRST_X (0xffff<<0) -#define m_VIRST_Y (0xffff<<16) -#define v_VIRST_X(x) (((x)&0xffff)<<0) -#define v_VIRST_Y(x) (((x)&0xffff)<<16) - -#define m_PANELST_X (0x3ff<<0) -#define m_PANELST_Y (0x3ff<<16) -#define v_PANELST_X(x) (((x)&0x3ff)<<0) -#define v_PANELST_Y(x) (((x)&0x3ff)<<16) - -#define m_PANELWIDTH (0x3ff<<0) -#define m_PANELHEIGHT (0x3ff<<16) -#define v_PANELWIDTH(x) (((x)&0x3ff)<<0) -#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16) - -#define m_HWC_B (0xff<<0) -#define m_HWC_G (0xff<<8) -#define m_HWC_R (0xff<<16) -#define m_W0_YRGB_HSP_OFFSET (0xff<<24) -#define m_W0_YRGB_HSD_OFFSET (0xff<<24) -#define v_HWC_B(x) (((x)&0xff)<<0) -#define v_HWC_G(x) (((x)&0xff)<<8) -#define v_HWC_R(x) (((x)&0xff)<<16) -#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24) -#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24) - -//LCDC_WIN0_ACT_INFO -#define v_ACT_WIDTH(x) ((x-1)<<0) -#define v_ACT_HEIGHT(x) ((x-1)<<16) - -//LCDC_WIN0_DSP_INFO -#define v_DSP_WIDTH(x) ((x-1)<<0) -#define v_DSP_HEIGHT(x) ((x-1)<<16) - -//LCDC_WIN0_DSP_ST //x,y start point of the panel scanning -#define v_DSP_STX(x) (x<<0) -#define v_DSP_STY(x) (x<<16) - -//Panel display scanning -#define m_PANEL_HSYNC_WIDTH (0x3ff<<0) -#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16) -#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0) -#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16) - -#define m_PANEL_END (0x3ff<<0) -#define m_PANEL_START (0x3ff<<16) -#define v_PANEL_END(x) (((x)&0x3ff)<<0) -#define v_PANEL_START(x) (((x)&0x3ff)<<16) - -#define m_PANEL_VSYNC_WIDTH (0x3ff<<0) -#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16) -#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0) -#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16) -//----------- - -#define m_HSCALE_FACTOR (0xffff<<0) -#define m_VSCALE_FACTOR (0xffff<<16) -#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0) -#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16) - -#define m_W0_CBR_HSD_OFFSET (0xff<<0) -#define m_W0_CBR_HSP_OFFSET (0xff<<8) -#define m_W0_CBR_VSD_OFFSET (0xff<<16) -#define m_W0_CBR_VSP_OFFSET (0xff<<24) -#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0) -#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8) -#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16) -#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24) - - - -#define CalScale(x, y) (((u32)x*0x1000)/y) -struct rk30_lcdc_device{ - int id; - struct rk_lcdc_device_driver driver; - rk_screen *screen; - - //LCDC_REG *preg; // LCDC reg base address and backup reg - //LCDC_REG regbak; - void __iomem *regs; - void *regsbak; //back up reg - int __iomem *dsp_lut_addr_base; - - void __iomem *reg_vir_base; // virtual basic address of lcdc register - u32 reg_phy_base; // physical basic address of lcdc register - u32 len; // physical map length of lcdc register - spinlock_t reg_lock; //one time only one process allowed to config the register - bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed - u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc - - unsigned int irq; - - struct clk *pd; //lcdc power domain - struct clk *hclk; //lcdc AHP clk - struct clk *dclk; //lcdc dclk - struct clk *aclk; //lcdc share memory frequency - struct clk *aclk_parent; //lcdc aclk divider frequency source - struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable. - struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable. - struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable. - struct clk *pd_display; // display power domain - u32 pixclock; -}; - -struct lcdc_info{ -/*LCD CLK*/ - struct rk30_lcdc_device lcdc0; - struct rk30_lcdc_device lcdc1; - -}; - - -struct win_set { - volatile u32 y_offset; - volatile u32 c_offset; -}; - -struct win0_par { - u32 refcount; - u32 pseudo_pal[16]; - u32 y_offset; - u32 c_offset; - u32 xpos; //size in panel - u32 ypos; - u32 xsize; //start point in panel - u32 ysize; - enum data_format format; - - wait_queue_head_t wait; - struct win_set mirror; - struct win_set displ; - struct win_set done; - - u8 par_seted; - u8 addr_seted; -}; - - -static inline void lcdc_writel(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 v) -{ - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - *_pv = v; - writel_relaxed(v,lcdc_dev->regs+offset); -} - -static inline u32 lcdc_readl(struct rk30_lcdc_device *lcdc_dev,u32 offset) -{ - u32 v; - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - v = readl_relaxed(lcdc_dev->regs+offset); - *_pv = v; - return v; -} - -static inline u32 lcdc_read_bit(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 msk) -{ - u32 _v = readl_relaxed(lcdc_dev->regs+offset); - _v &= msk; - return (_v >> msk); -} - -static inline void lcdc_set_bit(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 msk) -{ - u32* _pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) |= msk; - writel_relaxed(*_pv,lcdc_dev->regs + offset); -} - -static inline void lcdc_clr_bit(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 msk) -{ - u32* _pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) &= (~msk); - writel_relaxed(*_pv,lcdc_dev->regs + offset); -} - -static inline void lcdc_msk_reg(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 msk,u32 v) -{ - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) &= (~msk); - (*_pv) |= v; - writel_relaxed(*_pv,lcdc_dev->regs+offset); -} - -static inline void lcdc_cfg_done(struct rk30_lcdc_device *lcdc_dev) -{ - writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE); - dsb(); -} - -#endif - - diff --git a/drivers/video/rockchip/lcdc/rk312x_lcdc.c b/drivers/video/rockchip/lcdc/rk312x_lcdc.c deleted file mode 100755 index 2de0ef9fbf57..000000000000 --- a/drivers/video/rockchip/lcdc/rk312x_lcdc.c +++ /dev/null @@ -1,2781 +0,0 @@ -/* - * drivers/video/rockchip/lcdc/rk312x_lcdc.c - * - * Copyright (C) 2014 ROCKCHIP, Inc. - * Author: zhuangwenlong - * zhengyang - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk312x_lcdc.h" -#include - -static int dbg_thresd; -module_param(dbg_thresd, int, S_IRUGO | S_IWUSR); - -#define DBG(level, x...) do { \ - if (unlikely(dbg_thresd >= level)) \ - pr_info(KERN_INFO x); \ - } while (0) - -#define grf_writel(offset, v) do { \ - writel_relaxed(v, RK_GRF_VIRT + offset); \ - dsb(); \ - } while (0) - -static struct rk_lcdc_win lcdc_win[] = { - [0] = { - .name = "win0", - .id = 0, - .support_3d = false, - }, - [1] = { - .name = "win1", - .id = 1, - .support_3d = false, - }, - [2] = { - .name = "hwc", - .id = 2, - .support_3d = false, - }, -}; - -static irqreturn_t rk312x_lcdc_isr(int irq, void *dev_id) -{ - struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id; - ktime_t timestamp = ktime_get(); - u32 int_reg = lcdc_readl(lcdc_dev, INT_STATUS); - u32 irq_active = 0; - - irq_active = int_reg & INT_STA_MSK; - if (irq_active) - lcdc_writel(lcdc_dev, INT_STATUS, - int_reg | (irq_active << INT_CLR_SHIFT)); - - if (int_reg & m_FS_INT_STA) { - timestamp = ktime_get(); - - /*if (lcdc_dev->driver.wait_fs) {*/ - if (0) { - spin_lock(&(lcdc_dev->driver.cpl_lock)); - complete(&(lcdc_dev->driver.frame_done)); - spin_unlock(&(lcdc_dev->driver.cpl_lock)); - } - lcdc_dev->driver.vsync_info.timestamp = timestamp; - wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait); - } - - if (int_reg & m_LF_INT_STA) { - lcdc_dev->driver.frame_time.last_framedone_t = - lcdc_dev->driver.frame_time.framedone_t; - lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0); - } - - if (int_reg & m_HS_INT_STA) { - spin_lock(&lcdc_dev->driver.cpl_lock); - complete(&lcdc_dev->driver.frame_done); - spin_unlock(&lcdc_dev->driver.cpl_lock); - } - -#ifdef LCDC_IRQ_EMPTY_DEBUG - if (int_reg & m_WIN0_EMPTY_INT_STA) { - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_WIN0_EMPTY_INT_CLEAR, - v_WIN0_EMPTY_INT_CLEAR(1)); - dev_info(lcdc_dev->dev, "win0 empty irq\n"); - } else if (int_reg & m_WIN1_EMPTY_INT_STA) { - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_WIN1_EMPTY_INT_CLEAR, - v_WIN1_EMPTY_INT_CLEAR(1)); - dev_info(lcdc_dev->dev, "win1 empty irq\n"); - } -#endif - - return IRQ_HANDLED; -} - -static int rk312x_lcdc_clk_enable(struct lcdc_device *lcdc_dev) -{ -#ifdef CONFIG_RK_FPGA - lcdc_dev->clk_on = 1; - return 0; -#endif - if (!lcdc_dev->clk_on) { - clk_prepare_enable(lcdc_dev->hclk); - clk_prepare_enable(lcdc_dev->dclk); - clk_prepare_enable(lcdc_dev->aclk); - clk_prepare_enable(lcdc_dev->pd); - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 1; - spin_unlock(&lcdc_dev->reg_lock); - } - - return 0; -} - -static int rk312x_lcdc_clk_disable(struct lcdc_device *lcdc_dev) -{ -#ifdef CONFIG_RK_FPGA - lcdc_dev->clk_on = 0; - return 0; -#endif - if (lcdc_dev->clk_on) { - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 0; - spin_unlock(&lcdc_dev->reg_lock); - mdelay(25); - clk_disable_unprepare(lcdc_dev->dclk); - clk_disable_unprepare(lcdc_dev->hclk); - clk_disable_unprepare(lcdc_dev->aclk); - clk_disable_unprepare(lcdc_dev->pd); - } - - return 0; -} - -static int rk312x_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv) -{ - u32 mask, val; - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - /*struct rk_screen *screen = dev_drv->cur_screen;*/ - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - mask = m_FS_INT_CLEAR | m_FS_INT_EN | - m_LF_INT_CLEAR | m_LF_INT_EN | - m_HS_INT_CLEAR | m_HS_INT_EN | - m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN; - val = v_FS_INT_CLEAR(1) | v_FS_INT_EN(1) | - v_LF_INT_CLEAR(1) | v_LF_INT_EN(1) | - v_HS_INT_CLEAR(1) | v_HS_INT_EN(1) | - v_BUS_ERR_INT_CLEAR(1) | v_BUS_ERR_INT_EN(0); - #if 0 - mask |= m_LF_INT_NUM; - val |= v_LF_INT_NUM(screen->mode.vsync_len + - screen->mode.upper_margin + - screen->mode.yres) - #endif -#ifdef LCDC_IRQ_EMPTY_DEBUG - mask |= m_WIN0_EMPTY_INT_EN | m_WIN1_EMPTY_INT_EN; - val |= v_WIN0_EMPTY_INT_EN(1) | v_WIN1_EMPTY_INT_EN(1); -#endif - - lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val); - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - } - - return 0; -} - -static int rk312x_lcdc_disable_irq(struct lcdc_device *lcdc_dev) -{ - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - mask = m_FS_INT_CLEAR | m_FS_INT_EN | - m_LF_INT_CLEAR | m_LF_INT_EN | - m_HS_INT_CLEAR | m_HS_INT_EN | - m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN; - val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0) | - v_LF_INT_CLEAR(0) | v_LF_INT_EN(0) | - v_HS_INT_CLEAR(0) | v_HS_INT_EN(0) | - v_BUS_ERR_INT_CLEAR(0) | v_BUS_ERR_INT_EN(0); -#ifdef LCDC_IRQ_EMPTY_DEBUG - mask |= m_WIN0_EMPTY_INT_EN | m_WIN1_EMPTY_INT_EN; - val |= v_WIN0_EMPTY_INT_EN(0) | v_WIN1_EMPTY_INT_EN(0); -#endif - - lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val); - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - } - mdelay(1); - return 0; -} - - -static int win0_set_addr(struct lcdc_device *lcdc_dev, u32 addr) -{ - spin_lock(&lcdc_dev->reg_lock); - lcdc_writel(lcdc_dev, WIN0_YRGB_MST, addr); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN, v_WIN0_EN(1)); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win1_set_addr(struct lcdc_device *lcdc_dev, u32 addr) -{ - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->soc_type == VOP_RK3036) - lcdc_writel(lcdc_dev, WIN1_MST, addr); - else - lcdc_writel(lcdc_dev, WIN1_MST_RK312X, addr); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN1_EN, v_WIN1_EN(1)); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -int rk312x_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv, - int win_id, u32 addr) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - if (win_id == 0) - win0_set_addr(lcdc_dev, addr); - else - win1_set_addr(lcdc_dev, addr); - - return 0; -} - -static void rk_lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev) -{ - int reg = 0; - u32 val = 0; - struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0]; - struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1]; - - spin_lock(&lcdc_dev->reg_lock); - for (reg = 0; reg < 0xe0; reg += 4) { - val = lcdc_readl_backup(lcdc_dev, reg); - if (reg == WIN0_ACT_INFO) { - win0->area[0].xact = (val & m_ACT_WIDTH)+1; - win0->area[0].yact = ((val & m_ACT_HEIGHT)>>16)+1; - } - - if (lcdc_dev->soc_type == VOP_RK312X) { - if (reg == WIN1_DSP_INFO_RK312X) { - win1->area[0].xact = (val & m_DSP_WIDTH) + 1; - win1->area[0].yact = - ((val & m_DSP_HEIGHT) >> 16) + 1; - } - } else { - if (reg == WIN1_ACT_INFO) { - win1->area[0].xact = (val & m_ACT_WIDTH) + 1; - win1->area[0].yact = - ((val & m_ACT_HEIGHT) >> 16) + 1; - } - } - } - spin_unlock(&lcdc_dev->reg_lock); -} - -static int rk312x_lcdc_alpha_cfg(struct lcdc_device *lcdc_dev) -{ - int win0_top = 0; - u32 mask, val; - enum data_format win0_format = lcdc_dev->driver.win[0]->area[0].format; - enum data_format win1_format = lcdc_dev->driver.win[1]->area[0].format; - - int win0_alpha_en = ((win0_format == ARGB888) || - (win0_format == ABGR888)) ? 1 : 0; - int win1_alpha_en = ((win1_format == ARGB888) || - (win1_format == ABGR888)) ? 1 : 0; - int atv_layer_cnt = lcdc_dev->driver.win[0]->state + - lcdc_dev->driver.win[1]->state; - u32 *_pv = (u32 *)lcdc_dev->regsbak; - - _pv += (DSP_CTRL0 >> 2); - win0_top = ((*_pv) & (m_WIN0_TOP)) >> 8; - if (win0_top && (atv_layer_cnt >= 2) && (win0_alpha_en)) { - mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN; - val = v_WIN0_ALPHA_EN(1) | v_WIN1_ALPHA_EN(0); - lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val); - - mask = m_WIN0_ALPHA_MODE | - m_ALPHA_MODE_SEL0 | m_ALPHA_MODE_SEL1; - val = v_WIN0_ALPHA_MODE(1) | - v_ALPHA_MODE_SEL0(1) | v_ALPHA_MODE_SEL1(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - /*this vop bg layer not support yuv domain overlay,so bg val - have to set 0x800a80 equeal to 0x000000 at rgb domian,after - android start we recover to 0x00000*/ - mask = m_BG_COLOR; - val = v_BG_COLOR(0x000000); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - } else if ((!win0_top) && (atv_layer_cnt >= 2) && - (win1_alpha_en)) { - mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN; - val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(1); - lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val); - - mask = m_WIN1_ALPHA_MODE | - m_ALPHA_MODE_SEL0 | m_ALPHA_MODE_SEL1; - if (lcdc_dev->driver.overlay_mode == VOP_YUV_DOMAIN) - val = v_WIN0_ALPHA_MODE(1) | - v_ALPHA_MODE_SEL0(0) | - v_ALPHA_MODE_SEL1(0); - else - val = v_WIN1_ALPHA_MODE(1) | - v_ALPHA_MODE_SEL0(1) | - v_ALPHA_MODE_SEL1(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - /*this vop bg layer not support yuv domain overlay,so bg val - have to set 0x800a80 equeal to 0x000000 at rgb domian,after - android start we recover to 0x00000*/ - mask = m_BG_COLOR; - val = v_BG_COLOR(0x000000); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - } else { - mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN; - val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(0); - lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val); - } - - if (lcdc_dev->driver.win[2]->state == 1) { - mask = m_HWC_ALPAH_EN; - val = v_HWC_ALPAH_EN(1); - lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val); - - mask = m_HWC_ALPHA_MODE; - val = v_HWC_ALPHA_MODE(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - } else { - mask = m_HWC_ALPAH_EN; - val = v_HWC_ALPAH_EN(0); - lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val); - } - - return 0; -} - -static void lcdc_layer_csc_mode(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver; - struct rk_screen *screen = dev_drv->cur_screen; - - if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) { - switch (win->area[0].fmt_cfg) { - case VOP_FORMAT_ARGB888: - case VOP_FORMAT_RGB888: - case VOP_FORMAT_RGB565: - if ((screen->mode.xres < 1280) && - (screen->mode.yres < 720)) { - win->csc_mode = VOP_R2Y_CSC_BT601; - } else { - win->csc_mode = VOP_R2Y_CSC_BT709; - } - break; - default: - break; - } - if (win->id == 0) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_CSC_MODE, - v_WIN0_CSC_MODE(win->csc_mode)); - } else if (win->id == 1) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN1_CSC_MODE, - v_WIN1_CSC_MODE(win->csc_mode)); - } - } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) { - switch (win->area[0].fmt_cfg) { - case VOP_FORMAT_YCBCR420: - if (win->id == 0) { - win->csc_mode = VOP_Y2R_CSC_MPEG; - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, - m_WIN0_CSC_MODE, - v_WIN0_CSC_MODE(win->csc_mode)); - } - break; - default: - break; - } - } -} - - -static void lcdc_layer_update_regs(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 mask, val; - int hwc_size; - - if (win->state == 1) { - if (lcdc_dev->soc_type == VOP_RK312X) - lcdc_layer_csc_mode(lcdc_dev, win); - - if (win->id == 0) { - mask = m_WIN0_EN | m_WIN0_FORMAT | m_WIN0_RB_SWAP | - m_WIN0_UV_SWAP; - val = v_WIN0_EN(win->state) | - v_WIN0_FORMAT(win->area[0].fmt_cfg) | - v_WIN0_RB_SWAP(win->area[0].swap_rb) | - v_WIN0_UV_SWAP(win->area[0].swap_uv); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB, - v_X_SCL_FACTOR(win->scale_yrgb_x) | - v_Y_SCL_FACTOR(win->scale_yrgb_y)); - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR, - v_X_SCL_FACTOR(win->scale_cbcr_x) | - v_Y_SCL_FACTOR(win->scale_cbcr_y)); - - lcdc_msk_reg(lcdc_dev, WIN0_VIR, - m_YRGB_VIR | m_CBBR_VIR, - v_YRGB_VIR(win->area[0].y_vir_stride) | - v_CBCR_VIR(win->area[0].uv_vir_stride)); - lcdc_writel(lcdc_dev, WIN0_ACT_INFO, - v_ACT_WIDTH(win->area[0].xact) | - v_ACT_HEIGHT(win->area[0].yact)); - lcdc_writel(lcdc_dev, WIN0_DSP_ST, - v_DSP_STX(win->area[0].dsp_stx) | - v_DSP_STY(win->area[0].dsp_sty)); - lcdc_writel(lcdc_dev, WIN0_DSP_INFO, - v_DSP_WIDTH(win->area[0].xsize) | - v_DSP_HEIGHT(win->area[0].ysize)); - - lcdc_writel(lcdc_dev, WIN0_YRGB_MST, - win->area[0].y_addr); - lcdc_writel(lcdc_dev, WIN0_CBR_MST, - win->area[0].uv_addr); - } else if (win->id == 1) { - mask = m_WIN1_EN | m_WIN1_FORMAT | m_WIN1_RB_SWAP; - val = v_WIN1_EN(win->state) | - v_WIN1_FORMAT(win->area[0].fmt_cfg) | - v_WIN1_RB_SWAP(win->area[0].swap_rb); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - /* rk312x unsupport win1 scale */ - if (lcdc_dev->soc_type == VOP_RK3036) { - lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_YRGB, - v_X_SCL_FACTOR(win->scale_yrgb_x) | - v_Y_SCL_FACTOR(win->scale_yrgb_y)); - lcdc_writel(lcdc_dev, WIN1_ACT_INFO, - v_ACT_WIDTH(win->area[0].xact) | - v_ACT_HEIGHT(win->area[0].yact)); - lcdc_writel(lcdc_dev, WIN1_DSP_INFO, - v_DSP_WIDTH(win->area[0].xsize) | - v_DSP_HEIGHT(win->area[0].ysize)); - lcdc_writel(lcdc_dev, WIN1_DSP_ST, - v_DSP_STX(win->area[0].dsp_stx) | - v_DSP_STY(win->area[0].dsp_sty)); - lcdc_writel(lcdc_dev, - WIN1_MST, win->area[0].y_addr); - } else { - lcdc_writel(lcdc_dev, WIN1_DSP_INFO_RK312X, - v_DSP_WIDTH(win->area[0].xsize) | - v_DSP_HEIGHT(win->area[0].ysize)); - lcdc_writel(lcdc_dev, WIN1_DSP_ST_RK312X, - v_DSP_STX(win->area[0].dsp_stx) | - v_DSP_STY(win->area[0].dsp_sty)); - - lcdc_writel(lcdc_dev, - WIN1_MST_RK312X, - win->area[0].y_addr); - } - - lcdc_msk_reg(lcdc_dev, WIN1_VIR, m_YRGB_VIR, - v_YRGB_VIR(win->area[0].y_vir_stride)); - - - } else if (win->id == 2) { - mask = m_HWC_EN | m_HWC_LODAD_EN; - val = v_HWC_EN(win->state) | v_HWC_LODAD_EN(1); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - if ((win->area[0].xsize == 32) && - (win->area[0].ysize == 32)) - hwc_size = 0; - else if ((win->area[0].xsize == 64) && - (win->area[0].ysize == 64)) - hwc_size = 1; - else - dev_err(lcdc_dev->dev, "unsupport hwc size:x=%d,y=%d\n", - win->area[0].xsize, win->area[0].ysize); - lcdc_writel(lcdc_dev, HWC_DSP_ST, - v_DSP_STX(win->area[0].dsp_stx) | - v_DSP_STY(win->area[0].dsp_sty)); - - lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr); - } - } else { - win->area[0].y_addr = 0; - win->area[0].uv_addr = 0; - if (win->id == 0) { - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN, - v_WIN0_EN(0)); - lcdc_writel(lcdc_dev, WIN0_YRGB_MST, - win->area[0].y_addr); - lcdc_writel(lcdc_dev, WIN0_CBR_MST, - win->area[0].uv_addr); - } else if (win->id == 1) { - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN1_EN, - v_WIN1_EN(0)); - lcdc_writel(lcdc_dev, WIN1_MST, win->area[0].y_addr); - } else if (win->id == 2) { - lcdc_msk_reg(lcdc_dev, - SYS_CTRL, m_HWC_EN | m_HWC_LODAD_EN, - v_HWC_EN(0) | v_HWC_LODAD_EN(0)); - lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr); - } - } - rk312x_lcdc_alpha_cfg(lcdc_dev); -} - -static void lcdc_layer_enable(struct lcdc_device *lcdc_dev, unsigned int win_id, - bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on) && - lcdc_dev->driver.win[win_id]->state != open) { - if (open) { - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, - "wakeup from standby!\n"); - lcdc_dev->standby = 0; - } - lcdc_dev->atv_layer_cnt |= (1 << win_id); - } else if ((lcdc_dev->atv_layer_cnt & (1 << win_id)) && (!open)) { - lcdc_dev->atv_layer_cnt &= ~(1 << win_id); - } - lcdc_dev->driver.win[win_id]->state = open; - if (!open) { - lcdc_layer_update_regs(lcdc_dev, - lcdc_dev->driver.win[win_id]); - lcdc_cfg_done(lcdc_dev); - } - /*if no layer used,disable lcdc */ - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, - "no layer is used,go to standby!\n"); - lcdc_dev->standby = 1; - } - } - spin_unlock(&lcdc_dev->reg_lock); -} -/* -static int rk312x_lcdc_reg_update(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0]; - struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1]; - int timeout; - unsigned long flags; - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY, - v_LCDC_STANDBY(lcdc_dev->standby)); - lcdc_layer_update_regs(lcdc_dev, win0); - lcdc_layer_update_regs(lcdc_dev, win1); - rk312x_lcdc_alpha_cfg(lcdc_dev); - lcdc_cfg_done(lcdc_dev); - - } - spin_unlock(&lcdc_dev->reg_lock); - //if (dev_drv->wait_fs) { - if (0) { - spin_lock_irqsave(&dev_drv->cpl_lock, flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock, flags); - timeout = wait_for_completion_timeout(&dev_drv->frame_done, - msecs_to_jiffies - (dev_drv->cur_screen->ft + - 5)); - if (!timeout && (!dev_drv->frame_done.done)) { - dev_warn(lcdc_dev->dev, - "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } - } - DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id); - return 0; - -}*/ - -static void rk312x_lcdc_reg_restore(struct lcdc_device *lcdc_dev) -{ - memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0xe0); -} - -static int rk312x_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv) -{ - u32 mask, val; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - /*spin_lock(&lcdc_dev->reg_lock);*/ - if (likely(lcdc_dev->clk_on)) { - mask = m_MMU_EN | m_AXI_MAX_OUTSTANDING_EN | - m_AXI_OUTSTANDING_MAX_NUM; - val = v_MMU_EN(1) | v_AXI_OUTSTANDING_MAX_NUM(31) | - v_AXI_MAX_OUTSTANDING_EN(1); - lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val); - } - /*spin_unlock(&lcdc_dev->reg_lock);*/ - if (dev_drv->iommu_enabled) { - if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) { - lcdc_dev->iommu_status = 1; - rockchip_iovmm_activate(dev_drv->dev); - } - } - - return 0; -} - -static int rk312x_lcdc_set_hwc_lut(struct rk_lcdc_driver *dev_drv, - int *hwc_lut, int mode) -{ - int i = 0; - int __iomem *c; - int v; - int len = 256*4; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - if (dev_drv->hwc_lut == NULL) - dev_drv->hwc_lut = devm_kzalloc(lcdc_dev->dev, len, GFP_KERNEL); - - spin_lock(&lcdc_dev->reg_lock); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(0)); - lcdc_cfg_done(lcdc_dev); - mdelay(25); - for (i = 0; i < 256; i++) { - if (mode == 1) - dev_drv->hwc_lut[i] = hwc_lut[i]; - v = dev_drv->hwc_lut[i]; - c = lcdc_dev->hwc_lut_addr_base + i; - writel_relaxed(v, c); - } - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(1)); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int rk312x_lcdc_set_lut(struct rk_lcdc_driver *dev_drv, - int *dsp_lut) -{ - int i = 0; - int __iomem *c; - int v; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if (!dsp_lut) - return 0; - - spin_lock(&lcdc_dev->reg_lock); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(0)); - lcdc_cfg_done(lcdc_dev); - mdelay(25); - for (i = 0; i < 256; i++) { - v = dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base + i; - writel_relaxed(v, c); - } - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(1)); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk312x_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv, - int reset_rate) -{ -#ifdef CONFIG_RK_FPGA - return 0; -#endif - int ret, fps; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - - if (reset_rate) - ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock); - if (ret) - dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id); - lcdc_dev->pixclock = - div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - lcdc_dev->driver.pixclock = lcdc_dev->pixclock; - - fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock); - screen->ft = 1000 / fps; - dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ", - lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps); - return 0; -} - -static int rk312x_lcdc_standby(struct rk_lcdc_driver *dev_drv, bool enable) -{ - struct lcdc_device *vop_dev = - container_of(dev_drv, struct lcdc_device, driver); - int timeout; - unsigned long flags; - - if (unlikely(!vop_dev->clk_on)) - return 0; - - if (dev_drv->standby && !enable) { - dev_drv->standby = 0; - lcdc_msk_reg(vop_dev, SYS_CTRL, m_LCDC_STANDBY, - v_LCDC_STANDBY(0)); - return 0; - } else if (!dev_drv->standby && enable) { - spin_lock_irqsave(&dev_drv->cpl_lock, flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock, flags); - - lcdc_msk_reg(vop_dev, SYS_CTRL, m_LCDC_STANDBY, - v_LCDC_STANDBY(1)); - /* wait for standby hold valid */ - timeout = wait_for_completion_timeout(&dev_drv->frame_done, - msecs_to_jiffies(25)); - - if (!timeout && (!dev_drv->frame_done.done)) { - dev_info(dev_drv->dev, - "wait for standy hold valid start time out!\n"); - return -ETIMEDOUT; - } - - dev_drv->standby = 1; - } - - return 0; -} - -/********do basic init*********/ -static int rk312x_lcdc_pre_init(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - if (lcdc_dev->pre_init) - return 0; - - lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc"); - lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc"); - lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc"); - lcdc_dev->sclk = devm_clk_get(lcdc_dev->dev, "sclk_lcdc"); - lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc"); - lcdc_dev->pll_sclk = devm_clk_get(lcdc_dev->dev, "sclk_pll"); - - if (/*IS_ERR(lcdc_dev->pd) || */ (IS_ERR(lcdc_dev->aclk)) || - (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) { - dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n", - lcdc_dev->id); - } - - rk_disp_pwr_enable(dev_drv); - rk312x_lcdc_clk_enable(lcdc_dev); - - /* backup reg config at uboot */ - rk_lcdc_read_reg_defalut_cfg(lcdc_dev); - - /* config for the FRC mode of dither down */ - lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821); - lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412); - lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0x55aaaa55); - lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x55aaaa55); - lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb); - lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de); - - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_AUTO_GATING_EN, v_AUTO_GATING_EN(0)); - lcdc_cfg_done(lcdc_dev); - /*if (dev_drv->iommu_enabled) - {// disable all wins to workaround iommu pagefault - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN | m_WIN1_EN, - v_WIN0_EN(0) | v_WIN1_EN(0)); - lcdc_cfg_done(lcdc_dev); - while(lcdc_readl(lcdc_dev, SYS_CTRL) & (m_WIN0_EN | m_WIN1_EN)); - }*/ - if ((dev_drv->ops->open_bcsh) && (dev_drv->output_color == COLOR_YCBCR)) { - if (support_uboot_display()) - dev_drv->bcsh_init_status = 1; - else - dev_drv->ops->open_bcsh(dev_drv, 1); - } - lcdc_dev->pre_init = true; - - return 0; -} - -static void rk312x_lcdc_deinit(struct lcdc_device *lcdc_dev) -{ - rk312x_lcdc_disable_irq(lcdc_dev); -} - -static u32 calc_sclk_freq(struct rk_screen *src_screen, - struct rk_screen *dst_screen) -{ - u32 dsp_vtotal; - u64 dsp_htotal; - u32 dsp_in_vtotal; - u64 dsp_in_htotal; - u64 sclk_freq; - - if (!src_screen || !dst_screen) - return 0; - - dsp_vtotal = dst_screen->mode.yres; - dsp_htotal = dst_screen->mode.left_margin + dst_screen->mode.hsync_len + - dst_screen->mode.xres + dst_screen->mode.right_margin; - dsp_in_vtotal = src_screen->mode.yres; - dsp_in_htotal = src_screen->mode.left_margin + - src_screen->mode.hsync_len + - src_screen->mode.xres + src_screen->mode.right_margin; - sclk_freq = dsp_vtotal * dsp_htotal * src_screen->mode.pixclock; - do_div(sclk_freq, dsp_in_vtotal * dsp_in_htotal); - - return (u32)sclk_freq; -} - -#define SCLK_PLL_LIMIT 594000000 -#define GPU_FREQ_MAX_LIMIT 297000000 -#define GPU_FREQ_NEED 400000000 - -static u32 calc_sclk_pll_freq(u32 sclk_freq) -{ - u32 multi_num; - - if (sclk_freq < (SCLK_PLL_LIMIT / 10)) { - return (sclk_freq * 10); - } else { - multi_num = GPU_FREQ_NEED / sclk_freq; - return (sclk_freq * multi_num); - } -} - -static int calc_dsp_frm_vst_hst(struct rk_screen *src, - struct rk_screen *dst, u32 sclk_freq) -{ - u32 BP_in, BP_out; - u32 v_scale_ratio; - long long T_frm_st; - u64 T_BP_in, T_BP_out, T_Delta, Tin; - u32 src_pixclock, dst_pixclock; - u64 temp; - u32 dsp_htotal, dsp_vtotal, src_htotal, src_vtotal; - - if (unlikely(!src) || unlikely(!dst)) - return -1; - - src_pixclock = div_u64(1000000000000llu, src->mode.pixclock); - dst_pixclock = div_u64(1000000000000llu, sclk_freq); - dsp_htotal = dst->mode.left_margin + dst->mode.hsync_len + - dst->mode.xres + dst->mode.right_margin; - dsp_vtotal = dst->mode.upper_margin + dst->mode.vsync_len + - dst->mode.yres + dst->mode.lower_margin; - src_htotal = src->mode.left_margin + src->mode.hsync_len + - src->mode.xres + src->mode.right_margin; - src_vtotal = src->mode.upper_margin + src->mode.vsync_len + - src->mode.yres + src->mode.lower_margin; - BP_in = (src->mode.upper_margin + src->mode.vsync_len) * src_htotal + - src->mode.hsync_len + src->mode.left_margin; - BP_out = (dst->mode.upper_margin + dst->mode.vsync_len) * dsp_htotal + - dst->mode.hsync_len + dst->mode.left_margin; - - T_BP_in = BP_in * src_pixclock; - T_BP_out = BP_out * dst_pixclock; - Tin = src_vtotal * src_htotal * src_pixclock; - - v_scale_ratio = src->mode.yres / dst->mode.yres; - if (v_scale_ratio <= 2) - T_Delta = 5 * src_htotal * src_pixclock; - else - T_Delta = 12 * src_htotal * src_pixclock; - - if (T_BP_in + T_Delta > T_BP_out) - T_frm_st = (T_BP_in + T_Delta - T_BP_out); - else - T_frm_st = Tin - (T_BP_out - (T_BP_in + T_Delta)); - - /* (T_frm_st = scl_vst * src_htotal * src_pixclock + - scl_hst * src_pixclock) */ - temp = do_div(T_frm_st, src_pixclock); - temp = do_div(T_frm_st, src_htotal); - dst->scl_hst = temp - 1; - dst->scl_vst = T_frm_st; - - return 0; -} - -static int rk312x_lcdc_set_scaler(struct rk_lcdc_driver *dev_drv, - struct rk_screen *dst_screen, bool enable) -{ - u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end; - u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end; - u32 dsp_hbor_end, dsp_hbor_st, dsp_vbor_end, dsp_vbor_st; - u32 scl_v_factor, scl_h_factor; - u32 dst_frame_hst, dst_frame_vst; - u32 src_w, src_h, dst_w, dst_h; - u16 bor_right = 0; - u16 bor_left = 0; - u16 bor_up = 0; - u16 bor_down = 0; - u32 pll_freq = 0; - struct rk_screen *src; - struct rk_screen *dst; - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct dvfs_node *gpu_clk = clk_get_dvfs_node("clk_gpu"); - - if (unlikely(!lcdc_dev->clk_on)) - return 0; - - if (!enable) { - spin_lock(&lcdc_dev->reg_lock); - lcdc_msk_reg(lcdc_dev, SCALER_CTRL, - m_SCALER_EN | m_SCALER_OUT_ZERO | - m_SCALER_OUT_EN, - v_SCALER_EN(0) | v_SCALER_OUT_ZERO(1) | - v_SCALER_OUT_EN(0)); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - if (lcdc_dev->sclk_on) { - clk_disable_unprepare(lcdc_dev->sclk); - lcdc_dev->sclk_on = false; - } - - /* switch pll freq as default when sclk is no used */ - if (clk_get_rate(lcdc_dev->pll_sclk) != GPU_FREQ_NEED) { - dvfs_clk_enable_limit(gpu_clk, GPU_FREQ_MAX_LIMIT, - GPU_FREQ_MAX_LIMIT); - clk_set_rate(lcdc_dev->pll_sclk, GPU_FREQ_NEED); - dvfs_clk_enable_limit(gpu_clk, 0, -1); - } - dev_dbg(lcdc_dev->dev, "%s: disable\n", __func__); - return 0; - } - - /* - * rk312x used one lcdc to apply dual disp - * hdmi screen is used for scaler src - * prmry screen is used for scaler dst - */ - dst = dst_screen; - src = dev_drv->cur_screen; - if (!dst || !src) { - dev_err(lcdc_dev->dev, "%s: dst screen is null!\n", __func__); - return -EINVAL; - } - - if (!lcdc_dev->sclk_on) { - clk_prepare_enable(lcdc_dev->sclk); - lcdc_dev->s_pixclock = calc_sclk_freq(src, dst); - pll_freq = calc_sclk_pll_freq(lcdc_dev->s_pixclock); - - /* limit gpu freq */ - dvfs_clk_enable_limit(gpu_clk, - GPU_FREQ_MAX_LIMIT, - GPU_FREQ_MAX_LIMIT); - /* set pll freq */ - clk_set_rate(lcdc_dev->pll_sclk, pll_freq); - /* cancel limit gpu freq */ - dvfs_clk_enable_limit(gpu_clk, 0, -1); - - clk_set_rate(lcdc_dev->sclk, lcdc_dev->s_pixclock); - lcdc_dev->sclk_on = true; - dev_info(lcdc_dev->dev, "%s:sclk=%d\n", __func__, - lcdc_dev->s_pixclock); - } - - /* config scale timing */ - calc_dsp_frm_vst_hst(src, dst, lcdc_dev->s_pixclock); - dst_frame_vst = dst->scl_vst; - dst_frame_hst = dst->scl_hst; - - dsp_htotal = dst->mode.hsync_len + dst->mode.left_margin + - dst->mode.xres + dst->mode.right_margin; - dsp_hs_end = dst->mode.hsync_len; - - dsp_vtotal = dst->mode.vsync_len + dst->mode.upper_margin + - dst->mode.yres + dst->mode.lower_margin; - dsp_vs_end = dst->mode.vsync_len; - - dsp_hbor_end = dst->mode.hsync_len + dst->mode.left_margin + - dst->mode.xres; - dsp_hbor_st = dst->mode.hsync_len + dst->mode.left_margin; - dsp_vbor_end = dst->mode.vsync_len + dst->mode.upper_margin + - dst->mode.yres; - dsp_vbor_st = dst->mode.vsync_len + dst->mode.upper_margin; - - dsp_hact_st = dsp_hbor_st + bor_left; - dsp_hact_end = dsp_hbor_end - bor_right; - dsp_vact_st = dsp_vbor_st + bor_up; - dsp_vact_end = dsp_vbor_end - bor_down; - - src_w = src->mode.xres; - src_h = src->mode.yres; - dst_w = dsp_hact_end - dsp_hact_st; - dst_h = dsp_vact_end - dsp_vact_st; - - /* calc scale factor */ - scl_h_factor = ((src_w - 1) << 12) / (dst_w - 1); - scl_v_factor = ((src_h - 1) << 12) / (dst_h - 1); - - spin_lock(&lcdc_dev->reg_lock); - if (dst->color_mode != src->color_mode) { - /*dev_drv->output_color = dst->color_mode; - if (dev_drv->output_color == COLOR_YCBCR) - dev_drv->overlay_mode = VOP_YUV_DOMAIN; - else - dev_drv->overlay_mode = VOP_RGB_DOMAIN; - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_SW_OVERLAY_MODE, - v_SW_OVERLAY_MODE(dev_drv->overlay_mode));*/ - } - - lcdc_writel(lcdc_dev, SCALER_FACTOR, - v_SCALER_H_FACTOR(scl_h_factor) | - v_SCALER_V_FACTOR(scl_v_factor)); - - lcdc_writel(lcdc_dev, SCALER_FRAME_ST, - v_SCALER_FRAME_HST(dst_frame_hst) | - v_SCALER_FRAME_VST(dst_frame_vst)); - lcdc_writel(lcdc_dev, SCALER_DSP_HOR_TIMING, - v_SCALER_HS_END(dsp_hs_end) | - v_SCALER_HTOTAL(dsp_htotal)); - lcdc_writel(lcdc_dev, SCALER_DSP_HACT_ST_END, - v_SCALER_HAEP(dsp_hact_end) | - v_SCALER_HASP(dsp_hact_st)); - lcdc_writel(lcdc_dev, SCALER_DSP_VER_TIMING, - v_SCALER_VS_END(dsp_vs_end) | - v_SCALER_VTOTAL(dsp_vtotal)); - lcdc_writel(lcdc_dev, SCALER_DSP_VACT_ST_END, - v_SCALER_VAEP(dsp_vact_end) | - v_SCALER_VASP(dsp_vact_st)); - lcdc_writel(lcdc_dev, SCALER_DSP_HBOR_TIMING, - v_SCALER_HBOR_END(dsp_hbor_end) | - v_SCALER_HBOR_ST(dsp_hbor_st)); - lcdc_writel(lcdc_dev, SCALER_DSP_VBOR_TIMING, - v_SCALER_VBOR_END(dsp_vbor_end) | - v_SCALER_VBOR_ST(dsp_vbor_st)); - lcdc_msk_reg(lcdc_dev, SCALER_CTRL, - m_SCALER_VSYNC_VST | m_SCALER_VSYNC_MODE, - v_SCALER_VSYNC_VST(4) | v_SCALER_VSYNC_MODE(2)); - lcdc_msk_reg(lcdc_dev, SCALER_CTRL, - m_SCALER_EN | m_SCALER_OUT_ZERO | - m_SCALER_OUT_EN, - v_SCALER_EN(1) | v_SCALER_OUT_ZERO(0) | - v_SCALER_OUT_EN(1)); - - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static void rk312x_lcdc_select_bcsh(struct rk_lcdc_driver *dev_drv, - struct lcdc_device *lcdc_dev) -{ - u32 bcsh_ctrl; - if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) { - if (IS_YUV_COLOR(dev_drv->output_color))/* bypass */ - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, - m_BCSH_Y2R_EN | m_BCSH_R2Y_EN, - v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0)); - else /* YUV2RGB */ - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, - m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE | - m_BCSH_R2Y_EN, - v_BCSH_Y2R_EN(1) | - v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) | - v_BCSH_R2Y_EN(0)); - } else { /* overlay_mode=VOP_RGB_DOMAIN */ - if (dev_drv->output_color == COLOR_RGB) { - /* bypass */ - bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL); - if (((bcsh_ctrl&m_BCSH_EN) == 1) || - (dev_drv->bcsh.enable == 1))/*bcsh enabled*/ - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, - m_BCSH_R2Y_EN | m_BCSH_Y2R_EN, - v_BCSH_R2Y_EN(1) | v_BCSH_Y2R_EN(1)); - else/*bcsh disabled*/ - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, - m_BCSH_R2Y_EN | m_BCSH_Y2R_EN, - v_BCSH_R2Y_EN(0) | v_BCSH_Y2R_EN(0)); - } else /* RGB2YUV */ - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, - m_BCSH_R2Y_EN | - m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN, - v_BCSH_R2Y_EN(1) | - v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) | - v_BCSH_Y2R_EN(0)); - } -} - -static int rk312x_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact, - u16 *yact, int *format, u32 *dsp_addr, - int *ymirror) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - u32 val; - - spin_lock(&lcdc_dev->reg_lock); - - val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO); - *xact = (val & m_ACT_WIDTH)+1; - *yact = ((val & m_ACT_HEIGHT)>>16)+1; - - val = lcdc_readl(lcdc_dev, SYS_CTRL); - - *format = (val & m_WIN0_FORMAT) >> 3; - *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST); - - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int rk312x_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst, - int format, u16 xact, u16 yact, u16 xvir, - int ymirror) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct rk_lcdc_win *win = dev_drv->win[0]; - u32 val, mask; - - mask = m_WIN0_FORMAT; - val = v_WIN0_FORMAT(format); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - - lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_YRGB_VIR, - v_YRGB_VIR(xvir)); - lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_ACT_WIDTH(xact) | - v_ACT_HEIGHT(yact)); - - lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst); - - lcdc_cfg_done(lcdc_dev); - win->state = 1; - win->last_state = 1; - - return 0; -} - -static int rk312x_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen) -{ - u16 face = 0; - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u16 right_margin = screen->mode.right_margin; - u16 left_margin = screen->mode.left_margin; - u16 lower_margin = screen->mode.lower_margin; - u16 upper_margin = screen->mode.upper_margin; - u16 x_res = screen->mode.xres; - u16 y_res = screen->mode.yres; - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - /* Select output color domain */ - dev_drv->output_color = screen->color_mode; - /*if (lcdc_dev->soc_type == VOP_RK312X) { - if (dev_drv->output_color == COLOR_YCBCR) - dev_drv->overlay_mode = VOP_YUV_DOMAIN; - else - dev_drv->overlay_mode = VOP_RGB_DOMAIN; - } else { - dev_drv->output_color = COLOR_RGB; - dev_drv->overlay_mode = VOP_RGB_DOMAIN; - }*/ - dev_drv->overlay_mode = VOP_RGB_DOMAIN; - /*something wrong at yuv domain*/ - - switch (screen->type) { - case SCREEN_RGB: - if (lcdc_dev->soc_type == VOP_RK312X) { - mask = m_RGB_DCLK_EN | m_RGB_DCLK_INVERT; - val = v_RGB_DCLK_EN(1) | v_RGB_DCLK_INVERT(0); - lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val); - } - break; - case SCREEN_LVDS: - if (lcdc_dev->soc_type == VOP_RK312X) { - mask = m_LVDS_DCLK_EN | m_LVDS_DCLK_INVERT; - val = v_LVDS_DCLK_EN(1) | v_LVDS_DCLK_INVERT(1); - lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val); - } - break; - case SCREEN_MIPI: - if (lcdc_dev->soc_type == VOP_RK312X) { - mask = m_MIPI_DCLK_EN | m_MIPI_DCLK_INVERT; - val = v_MIPI_DCLK_EN(1) | v_MIPI_DCLK_INVERT(0); - lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val); - } - break; - case SCREEN_HDMI: - mask = m_HDMI_DCLK_EN; - val = v_HDMI_DCLK_EN(1); - if (screen->pixelrepeat) { - mask |= m_CORE_CLK_DIV_EN; - val |= v_CORE_CLK_DIV_EN(1); - } else { - mask |= m_CORE_CLK_DIV_EN; - val |= v_CORE_CLK_DIV_EN(0); - } - lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val); - if (lcdc_dev->soc_type == VOP_RK312X) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, - m_SW_UV_OFFSET_EN, - v_SW_UV_OFFSET_EN(0)); - mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL | - m_HDMI_DEN_POL; - val = v_HDMI_HSYNC_POL(screen->pin_hsync) | - v_HDMI_VSYNC_POL(screen->pin_vsync) | - v_HDMI_DEN_POL(screen->pin_den); - lcdc_msk_reg(lcdc_dev, INT_SCALER, mask, val); - } else { - mask = (1 << 4) | (1 << 5) | (1 << 6); - val = (screen->pin_hsync << 4) | - (screen->pin_vsync << 5) | - (screen->pin_den << 6); - grf_writel(RK3036_GRF_SOC_CON2, - (mask << 16) | val); - } - rk312x_lcdc_select_bcsh(dev_drv, lcdc_dev); - break; - case SCREEN_TVOUT: - case SCREEN_TVOUT_TEST: - mask = m_TVE_DAC_DCLK_EN; - val = v_TVE_DAC_DCLK_EN(1); - if (screen->pixelrepeat) { - mask |= m_CORE_CLK_DIV_EN; - val |= v_CORE_CLK_DIV_EN(1); - } - lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val); - if (x_res == 720 && y_res == 576) - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_TVE_MODE, - v_TVE_MODE(TV_PAL)); - else if (x_res == 720 && y_res == 480) - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_TVE_MODE, - v_TVE_MODE(TV_NTSC)); - else { - dev_err(lcdc_dev->dev, - "unsupported video timing!\n"); - return -1; - } - if (lcdc_dev->soc_type == VOP_RK312X) { - if (screen->type == SCREEN_TVOUT_TEST) - /*for TVE index test,vop must ovarlay at yuv domain*/ - dev_drv->overlay_mode = VOP_YUV_DOMAIN; - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, - m_SW_UV_OFFSET_EN, - v_SW_UV_OFFSET_EN(1)); - - rk312x_lcdc_select_bcsh(dev_drv, lcdc_dev); - } - break; - default: - dev_err(lcdc_dev->dev, "un supported interface!\n"); - break; - } - if (lcdc_dev->soc_type == VOP_RK312X) { - switch (dev_drv->screen0->face) { - case OUT_P565: - face = OUT_P565; - mask = m_DITHER_DOWN_EN | - m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | - v_DITHER_DOWN_MODE(0) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - break; - case OUT_P666: - face = OUT_P666; - mask = m_DITHER_DOWN_EN | - m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | - v_DITHER_DOWN_MODE(1) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - break; - case OUT_D888_P565: - face = OUT_P888; - mask = m_DITHER_DOWN_EN | - m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | - v_DITHER_DOWN_MODE(0) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - break; - case OUT_D888_P666: - face = OUT_P888; - mask = m_DITHER_DOWN_EN | - m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | - v_DITHER_DOWN_MODE(1) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - break; - case OUT_P888: - face = OUT_P888; - mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN; - val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - break; - default: - dev_err(lcdc_dev->dev, "un supported interface!\n"); - break; - } - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_SW_OVERLAY_MODE, - v_SW_OVERLAY_MODE(dev_drv->overlay_mode)); - } - - mask = m_HSYNC_POL | m_VSYNC_POL | - m_DEN_POL | m_DCLK_POL; - val = v_HSYNC_POL(screen->pin_hsync) | - v_VSYNC_POL(screen->pin_vsync) | - v_DEN_POL(screen->pin_den) | - v_DCLK_POL(screen->pin_dclk); - - if (screen->type != SCREEN_HDMI) { - mask |= m_DSP_OUT_FORMAT; - val |= v_DSP_OUT_FORMAT(face); - } - - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - - mask = m_BG_COLOR | m_DSP_BG_SWAP | m_DSP_RB_SWAP | - m_DSP_RG_SWAP | m_DSP_DELTA_SWAP | - m_DSP_DUMMY_SWAP | m_BLANK_EN | m_BLACK_EN; - - val = v_BG_COLOR(0x000000) | v_DSP_BG_SWAP(screen->swap_gb) | - v_DSP_RB_SWAP(screen->swap_rb) | - v_DSP_RG_SWAP(screen->swap_rg) | - v_DSP_DELTA_SWAP(screen->swap_delta) | - v_DSP_DUMMY_SWAP(screen->swap_dumy) | - v_BLANK_EN(0) | v_BLACK_EN(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - - /* config timing */ - val = v_HSYNC(screen->mode.hsync_len) | - v_HORPRD(screen->mode.hsync_len + left_margin + x_res + - right_margin); - lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END, val); - val = v_HAEP(screen->mode.hsync_len + left_margin + x_res) | - v_HASP(screen->mode.hsync_len + left_margin); - lcdc_writel(lcdc_dev, DSP_HACT_ST_END, val); - - if (screen->mode.vmode & FB_VMODE_INTERLACED) { - /* First Field Timing */ - lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, - v_VSYNC(screen->mode.vsync_len) | - v_VERPRD(2 * (screen->mode.vsync_len + - upper_margin + - lower_margin) + y_res + 1)); - lcdc_writel(lcdc_dev, DSP_VACT_ST_END, - v_VAEP(screen->mode.vsync_len + - upper_margin + y_res / 2) | - v_VASP(screen->mode.vsync_len + - upper_margin)); - /* Second Field Timing */ - lcdc_writel(lcdc_dev, DSP_VS_ST_END_F1, - v_VSYNC_ST_F1(screen->mode.vsync_len + - upper_margin + y_res / 2 + - lower_margin) | - v_VSYNC_END_F1(2 * screen->mode.vsync_len + - upper_margin + y_res / 2 + - lower_margin)); - lcdc_writel(lcdc_dev, DSP_VACT_ST_END_F1, - v_VAEP(2 * (screen->mode.vsync_len + - upper_margin) + - y_res + lower_margin + 1) | - v_VASP(2 * (screen->mode.vsync_len + - upper_margin) + - y_res / 2 + lower_margin + 1)); - - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, - m_INTERLACE_DSP_EN | - m_WIN0_YRGB_DEFLICK_EN | - m_WIN0_CBR_DEFLICK_EN | - m_INTERLACE_FIELD_POL | - m_WIN0_INTERLACE_EN | - m_WIN1_INTERLACE_EN, - v_INTERLACE_DSP_EN(1) | - v_WIN0_YRGB_DEFLICK_EN(1) | - v_WIN0_CBR_DEFLICK_EN(1) | - v_INTERLACE_FIELD_POL(0) | - v_WIN0_INTERLACE_EN(1) | - v_WIN1_INTERLACE_EN(1)); - mask = m_LF_INT_NUM; - val = v_LF_INT_NUM(screen->mode.vsync_len + - screen->mode.upper_margin + - screen->mode.yres/2); - lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val); - } else { - val = v_VSYNC(screen->mode.vsync_len) | - v_VERPRD(screen->mode.vsync_len + upper_margin + - y_res + lower_margin); - lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, val); - - val = v_VAEP(screen->mode.vsync_len + - upper_margin + y_res) | - v_VASP(screen->mode.vsync_len + upper_margin); - lcdc_writel(lcdc_dev, DSP_VACT_ST_END, val); - - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, - m_INTERLACE_DSP_EN | - m_WIN0_YRGB_DEFLICK_EN | - m_WIN0_CBR_DEFLICK_EN | - m_INTERLACE_FIELD_POL | - m_WIN0_INTERLACE_EN | - m_WIN1_INTERLACE_EN, - v_INTERLACE_DSP_EN(0) | - v_WIN0_YRGB_DEFLICK_EN(0) | - v_WIN0_CBR_DEFLICK_EN(0) | - v_INTERLACE_FIELD_POL(0) | - v_WIN0_INTERLACE_EN(0) | - v_WIN1_INTERLACE_EN(0)); - mask = m_LF_INT_NUM; - val = v_LF_INT_NUM(screen->mode.vsync_len + - screen->mode.upper_margin + - screen->mode.yres); - lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val); - } - } - spin_unlock(&lcdc_dev->reg_lock); - - rk312x_lcdc_set_dclk(dev_drv, 1); - lcdc_cfg_done(lcdc_dev); - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - if (screen->init) - screen->init(); - - return 0; -} - -static int rk312x_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id, - bool open) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - - /* enable clk,when first layer open */ - if ((open) && (!lcdc_dev->atv_layer_cnt)) { - rockchip_set_system_status(SYS_STATUS_LCDC0); - rk312x_lcdc_pre_init(dev_drv); - rk312x_lcdc_clk_enable(lcdc_dev); - if (dev_drv->iommu_enabled) { - if (!dev_drv->mmu_dev) { - dev_drv->mmu_dev = - rk_fb_get_sysmmu_device_by_compatible(dev_drv->mmu_dts_name); - if (dev_drv->mmu_dev) { - rk_fb_platform_set_sysmmu(dev_drv->mmu_dev, - dev_drv->dev); - } else { - dev_err(dev_drv->dev, - "failed to get rockchip iommu device\n"); - return -1; - } - } - /*if (dev_drv->mmu_dev) - rockchip_iovmm_activate(dev_drv->dev);*/ - } - rk312x_lcdc_reg_restore(lcdc_dev); - /*if (dev_drv->iommu_enabled) - rk312x_lcdc_mmu_en(dev_drv);*/ - if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) { - rk312x_lcdc_set_dclk(dev_drv, 0); - rk312x_lcdc_enable_irq(dev_drv); - } else { - dev_drv->standby = 1; - rk312x_load_screen(dev_drv, 1); - rk312x_lcdc_standby(dev_drv, false); - } - - /* set screen lut */ - if (dev_drv->cur_screen->dsp_lut) - rk312x_lcdc_set_lut(dev_drv, - dev_drv->cur_screen->dsp_lut); - } - - if (win_id < ARRAY_SIZE(lcdc_win)) - lcdc_layer_enable(lcdc_dev, win_id, open); - else - dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id); - - /* when all layer closed,disable clk */ -/* if ((!open) && (!lcdc_dev->atv_layer_cnt)) { - rk312x_lcdc_disable_irq(lcdc_dev); - rk312x_lcdc_reg_update(dev_drv); - if (dev_drv->iommu_enabled) { - if (dev_drv->mmu_dev) - rockchip_iovmm_deactivate(dev_drv->dev); - } - rk312x_lcdc_clk_disable(lcdc_dev); - rockchip_clear_system_status(SYS_STATUS_LCDC0); - }*/ - return 0; -} - -static int rk312x_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - struct rk_lcdc_win *win = NULL; - char fmt[9] = "NULL"; - - if (!screen) { - dev_err(dev_drv->dev, "screen is null!\n"); - return -ENOENT; - } - - if (win_id == 0) { - win = dev_drv->win[0]; - } else if (win_id == 1) { - win = dev_drv->win[1]; - } else if (win_id == 2) { - win = dev_drv->win[2]; - } else { - dev_err(dev_drv->dev, "un supported win number:%d\n", win_id); - return -EINVAL; - } - - spin_lock(&lcdc_dev->reg_lock); - win->area[0].dsp_stx = win->area[0].xpos + screen->mode.left_margin + - screen->mode.hsync_len; - if (win_id == 1) { - if ((win->area[0].xact != win->area[0].xsize) || - (win->area[0].yact != win->area[0].ysize)) { - pr_err("win[1],not support scale\n"); - pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n", - win->area[0].xact,win->area[0].yact, - win->area[0].xsize,win->area[0].ysize); - win->area[0].xsize = win->area[0].xact; - win->area[0].ysize = win->area[0].yact; - } - } - if (screen->mode.vmode & FB_VMODE_INTERLACED) { - win->area[0].ysize /= 2; - win->area[0].dsp_sty = win->area[0].ypos / 2 + - screen->mode.upper_margin + - screen->mode.vsync_len; - } else { - win->area[0].dsp_sty = win->area[0].ypos + - screen->mode.upper_margin + - screen->mode.vsync_len; - } - win->scale_yrgb_x = CalScale(win->area[0].xact, win->area[0].xsize); - win->scale_yrgb_y = CalScale(win->area[0].yact, win->area[0].ysize); - - switch (win->area[0].format) { - case ARGB888: - win->area[0].fmt_cfg = VOP_FORMAT_ARGB888; - win->area[0].swap_rb = 0; - win->area[0].swap_uv = 0; - break; - case XBGR888: - win->area[0].fmt_cfg = VOP_FORMAT_ARGB888; - win->area[0].swap_rb = 1; - win->area[0].swap_uv = 0; - break; - case ABGR888: - win->area[0].fmt_cfg = VOP_FORMAT_ARGB888; - win->area[0].swap_rb = 1; - win->area[0].swap_uv = 0; - break; - case RGB888: - win->area[0].fmt_cfg = VOP_FORMAT_RGB888; - win->area[0].swap_rb = 0; - win->area[0].swap_uv = 0; - break; - case RGB565: - win->area[0].fmt_cfg = VOP_FORMAT_RGB565; - win->area[0].swap_rb = 0; - break; - case YUV444: - if (win_id == 0) { - win->area[0].fmt_cfg = VOP_FORMAT_YCBCR444; - win->scale_cbcr_x = - CalScale(win->area[0].xact, win->area[0].xsize); - win->scale_cbcr_y = - CalScale(win->area[0].yact, win->area[0].ysize); - win->area[0].swap_rb = 0; - win->area[0].swap_uv = 0; - } else { - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", __func__); - } - break; - case YUV422: - if (win_id == 0) { - win->area[0].fmt_cfg = VOP_FORMAT_YCBCR422; - win->scale_cbcr_x = CalScale((win->area[0].xact / 2), - win->area[0].xsize); - win->scale_cbcr_y = - CalScale(win->area[0].yact, win->area[0].ysize); - win->area[0].swap_rb = 0; - win->area[0].swap_uv = 0; - } else { - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", __func__); - } - break; - case YUV420: - if (win_id == 0) { - win->area[0].fmt_cfg = VOP_FORMAT_YCBCR420; - win->scale_cbcr_x = - CalScale(win->area[0].xact / 2, win->area[0].xsize); - win->scale_cbcr_y = - CalScale(win->area[0].yact / 2, win->area[0].ysize); - win->area[0].swap_rb = 0; - win->area[0].swap_uv = 0; - } else { - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", __func__); - } - break; - case YUV420_NV21: - if (win_id == 0) { - win->area[0].fmt_cfg = VOP_FORMAT_YCBCR420; - win->scale_cbcr_x = - CalScale(win->area[0].xact / 2, win->area[0].xsize); - win->scale_cbcr_y = - CalScale(win->area[0].yact / 2, win->area[0].ysize); - win->area[0].swap_rb = 0; - win->area[0].swap_uv = 1; - } else { - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", __func__); - } - break; - default: - dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n", - __func__); - break; - } - spin_unlock(&lcdc_dev->reg_lock); - - DBG(1, - "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n" - ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, __func__, - get_format_string(win->area[0].format, fmt), win->area[0].xact, - win->area[0].yact, win->area[0].xsize, win->area[0].ysize, - win->area[0].xvir, win->area[0].yvir, win->area[0].xpos, - win->area[0].ypos); - return 0; -} - -static int rk312x_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct rk_lcdc_win *win = NULL; - struct rk_screen *screen = dev_drv->cur_screen; - - if (!screen) { - dev_err(dev_drv->dev, "screen is null!\n"); - return -ENOENT; - } - - if (win_id == 0) { - win = dev_drv->win[0]; - } else if (win_id == 1) { - win = dev_drv->win[1]; - } else if (win_id == 2) { - win = dev_drv->win[2]; - } else { - dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id); - return -EINVAL; - } - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - win->area[0].y_addr = - win->area[0].smem_start + win->area[0].y_offset; - win->area[0].uv_addr = - win->area[0].cbr_start + win->area[0].c_offset; - if (win->area[0].y_addr) - lcdc_layer_update_regs(lcdc_dev, win); - /* lcdc_cfg_done(lcdc_dev); */ - } - spin_unlock(&lcdc_dev->reg_lock); - - DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n", - lcdc_dev->id, __func__, win->area[0].y_addr, win->area[0].uv_addr, - win->area[0].y_offset); - /* this is the first frame of the system,enable frame start interrupt */ - if ((dev_drv->first_frame)) { - dev_drv->first_frame = 0; - rk312x_lcdc_enable_irq(dev_drv); - } - - return 0; -} - -static int rk312x_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd, - unsigned long arg, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - u32 panel_size[2]; - void __user *argp = (void __user *)arg; - struct color_key_cfg clr_key_cfg; - - switch (cmd) { - case RK_FBIOGET_PANEL_SIZE: - panel_size[0] = lcdc_dev->screen->mode.xres; - panel_size[1] = lcdc_dev->screen->mode.yres; - if (copy_to_user(argp, panel_size, 8)) - return -EFAULT; - break; - case RK_FBIOPUT_COLOR_KEY_CFG: - if (copy_from_user(&clr_key_cfg, argp, - sizeof(struct color_key_cfg))) - return -EFAULT; - lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, - clr_key_cfg.win0_color_key_cfg); - lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, - clr_key_cfg.win1_color_key_cfg); - break; - - default: - break; - } - return 0; -} - -static int rk312x_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv, - const char *id) -{ - int win_id = 0; - - mutex_lock(&dev_drv->fb_win_id_mutex); - if (!strcmp(id, "fb0")) - win_id = dev_drv->fb0_win_id; - else if (!strcmp(id, "fb1")) - win_id = dev_drv->fb1_win_id; - else if (!strcmp(id, "fb2")) - win_id = dev_drv->fb2_win_id; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return win_id; -} - -static int rk312x_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, - int win_id, - int area_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int win_status = 0; - - if (win_id == 0) - win_status = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_WIN0_EN); - else if (win_id == 1) - win_status = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_WIN1_EN); - else if (win_id == 2) - win_status = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_HWC_EN); - else - pr_err("!!!%s,win_id :%d,unsupport!!!\n",__func__,win_id); - - return win_status; -} - -static int rk312x_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, - bool set) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int ovl; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - if (set) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_TOP, - v_WIN0_TOP(swap)); - ovl = swap; - } else { - ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP); - } - } else { - ovl = -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - - return ovl; -} - -static int rk312x_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct device_node *backlight; - - if (lcdc_dev->backlight) - return 0; - - backlight = of_parse_phandle(lcdc_dev->dev->of_node, - "backlight", 0); - if (backlight) { - lcdc_dev->backlight = of_find_backlight_by_node(backlight); - if (!lcdc_dev->backlight) - dev_info(lcdc_dev->dev, "No find backlight device\n"); - } else { - dev_info(lcdc_dev->dev, "No find backlight device node\n"); - } - - return 0; -} - -static int rk312x_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - if (dev_drv->suspend_flag) - return 0; - - /* close the backlight */ - rk312x_lcdc_get_backlight_device(dev_drv); - if (lcdc_dev->backlight) { - lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN; - backlight_update_status(lcdc_dev->backlight); - } - - dev_drv->suspend_flag = 1; - flush_kthread_worker(&dev_drv->update_regs_worker); - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable) - dev_drv->trsm_ops->disable(); - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, v_BLANK_EN(1)); - lcdc_msk_reg(lcdc_dev, INT_STATUS, - m_FS_INT_CLEAR | m_LF_INT_CLEAR, - v_FS_INT_CLEAR(1) | v_LF_INT_CLEAR(1)); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO, - v_DSP_OUT_ZERO(1)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY, - v_LCDC_STANDBY(1)); - lcdc_cfg_done(lcdc_dev); - - if (dev_drv->iommu_enabled) { - if (dev_drv->mmu_dev) - rockchip_iovmm_deactivate(dev_drv->dev); - } - - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - rk312x_lcdc_clk_disable(lcdc_dev); - rk_disp_pwr_disable(dev_drv); - return 0; -} - -static int rk312x_lcdc_early_resume(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if (!dev_drv->suspend_flag) - return 0; - rk_disp_pwr_enable(dev_drv); - - rk312x_lcdc_clk_enable(lcdc_dev); - rk312x_lcdc_reg_restore(lcdc_dev); - - /* config for the FRC mode of dither down */ - if (dev_drv->cur_screen && - dev_drv->cur_screen->face != OUT_P888) { - lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821); - lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412); - lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0x55aaaa55); - lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x55aaaa55); - lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb); - lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de); - } - - /* set screen lut */ - if (dev_drv->cur_screen && dev_drv->cur_screen->dsp_lut) - rk312x_lcdc_set_lut(dev_drv, - dev_drv->cur_screen->dsp_lut); - /*set hwc lut*/ - rk312x_lcdc_set_hwc_lut(dev_drv, dev_drv->hwc_lut, 0); - - spin_lock(&lcdc_dev->reg_lock); - - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO, - v_DSP_OUT_ZERO(0)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY, - v_LCDC_STANDBY(0)); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, v_BLANK_EN(0)); - lcdc_cfg_done(lcdc_dev); - - if (dev_drv->iommu_enabled) { - if (dev_drv->mmu_dev) { - /* - * At here, maybe win is enabled and buffer address - * is not a vaild iommu mapped addr, incase crash, - * delay 30ms to ensure H/W switch done. - */ - mdelay(30); - rockchip_iovmm_activate(dev_drv->dev); - } - } - - spin_unlock(&lcdc_dev->reg_lock); - dev_drv->suspend_flag = 0; - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - mdelay(100); - - return 0; -} - -static int rk312x_lcdc_blank(struct rk_lcdc_driver *dev_drv, - int win_id, int blank_mode) -{ - switch (blank_mode) { - case FB_BLANK_UNBLANK: - rk312x_lcdc_early_resume(dev_drv); - break; - case FB_BLANK_NORMAL: - rk312x_lcdc_early_suspend(dev_drv); - break; - default: - rk312x_lcdc_early_suspend(dev_drv); - break; - } - - dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode); - - return 0; -} - -static int rk312x_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - int i; - struct rk_lcdc_win *win = NULL; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - for (i = 0; i < ARRAY_SIZE(lcdc_win); i++) { - win = dev_drv->win[i]; - if ((win->state == 0) && (win->last_state == 1)) - lcdc_layer_update_regs(lcdc_dev, win); - win->last_state = win->state; - } - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -/* - a:[-30~0]: - sin_hue = sin(a)*256 +0x100; - cos_hue = cos(a)*256; - a:[0~30] - sin_hue = sin(a)*256; - cos_hue = cos(a)*256; -*/ -static int rk312x_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv, - bcsh_hue_mode mode) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 val; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - val = lcdc_readl(lcdc_dev, BCSH_H); - switch (mode) { - case H_SIN: - val &= m_BCSH_SIN_HUE; - break; - case H_COS: - val &= m_BCSH_COS_HUE; - val >>= 16; - break; - default: - break; - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return val; -} - -static int rk312x_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv, int sin_hue, - int cos_hue) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE; - val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue); - lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int rk312x_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv, - bcsh_bcs_mode mode, int value) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - switch (mode) { - case BRIGHTNESS: - /* from 0 to 255,typical is 128 */ - if (value < 0x80) - value += 0x80; - else if (value >= 0x80) - value = value - 0x80; - mask = m_BCSH_BRIGHTNESS; - val = v_BCSH_BRIGHTNESS(value); - break; - case CONTRAST: - /* from 0 to 510,typical is 256 */ - mask = m_BCSH_CONTRAST; - val = v_BCSH_CONTRAST(value); - break; - case SAT_CON: - /* from 0 to 1015,typical is 256 */ - mask = m_BCSH_SAT_CON; - val = v_BCSH_SAT_CON(value); - break; - default: - break; - } - lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - return val; -} - -static int rk312x_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv, - bcsh_bcs_mode mode) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 val; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - val = lcdc_readl(lcdc_dev, BCSH_BCS); - switch (mode) { - case BRIGHTNESS: - val &= m_BCSH_BRIGHTNESS; - if (val > 0x80) - val -= 0x80; - else - val += 0x80; - break; - case CONTRAST: - val &= m_BCSH_CONTRAST; - val >>= 8; - break; - case SAT_CON: - val &= m_BCSH_SAT_CON; - val >>= 20; - break; - default: - break; - } - } - spin_unlock(&lcdc_dev->reg_lock); - return val; -} - -static int rk312x_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask, val; - if (dev_drv->bcsh_init_status && open) { - dev_drv->bcsh_init_status = 0; - return 0; - } - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - if (open) { - lcdc_msk_reg(lcdc_dev, - BCSH_CTRL, m_BCSH_EN | m_BCSH_OUT_MODE, - v_BCSH_EN(1) | v_BCSH_OUT_MODE(3)); - lcdc_writel(lcdc_dev, BCSH_BCS, - v_BCSH_BRIGHTNESS(0x00) | - v_BCSH_CONTRAST(0x80) | - v_BCSH_SAT_CON(0x80)); - lcdc_writel(lcdc_dev, BCSH_H, v_BCSH_COS_HUE(0x80)); - dev_drv->bcsh.enable = 1; - } else { - mask = m_BCSH_EN; - val = v_BCSH_EN(0); - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, mask, val); - dev_drv->bcsh.enable = 0; - } - rk312x_lcdc_select_bcsh(dev_drv, lcdc_dev); - lcdc_cfg_done(lcdc_dev); - } - - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk312x_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order) -{ - struct rk_lcdc_win_area area; - int fb2_win_id, fb1_win_id, fb0_win_id; - - mutex_lock(&dev_drv->fb_win_id_mutex); - if (order == FB_DEFAULT_ORDER) - order = FB0_WIN0_FB1_WIN1_FB2_WIN2; - - fb2_win_id = order / 100; - fb1_win_id = (order / 10) % 10; - fb0_win_id = order % 10; - - if (fb0_win_id != dev_drv->fb0_win_id) { - area = dev_drv->win[(int)dev_drv->fb0_win_id]->area[0]; - dev_drv->win[(int)dev_drv->fb0_win_id]->area[0] = - dev_drv->win[fb0_win_id]->area[0]; - dev_drv->win[fb0_win_id]->area[0] = area; - dev_drv->fb0_win_id = fb0_win_id; - } - dev_drv->fb1_win_id = fb1_win_id; - dev_drv->fb2_win_id = fb2_win_id; - - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return 0; -} - -static int rk312x_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, - bool set) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u64 ft = 0; - u32 dotclk; - int ret; - u32 pixclock; - u32 x_total, y_total; - - if (set) { - ft = div_u64(1000000000000llu, fps); - x_total = - screen->mode.upper_margin + screen->mode.lower_margin + - screen->mode.yres + screen->mode.vsync_len; - y_total = - screen->mode.left_margin + screen->mode.right_margin + - screen->mode.xres + screen->mode.hsync_len; - dev_drv->pixclock = div_u64(ft, x_total * y_total); - dotclk = div_u64(1000000000000llu, dev_drv->pixclock); - ret = clk_set_rate(lcdc_dev->dclk, dotclk); - } - - pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - dev_drv->pixclock = lcdc_dev->pixclock = pixclock; - fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock); - screen->ft = 1000 / fps; /*one frame time in ms */ - - if (set) - dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__, - clk_get_rate(lcdc_dev->dclk), fps); - - return fps; -} - -static int rk312x_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv, - int enable) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, - struct lcdc_device, driver); - if (enable) - enable_irq(lcdc_dev->irq); - else - disable_irq(lcdc_dev->irq); - return 0; -} - -static int rk312x_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 int_reg; - int ret; - - if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) { - int_reg = lcdc_readl(lcdc_dev, INT_STATUS); - if (int_reg & m_LF_INT_STA) { - dev_drv->frame_time.last_framedone_t = - dev_drv->frame_time.framedone_t; - dev_drv->frame_time.framedone_t = cpu_clock(0); - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR, - v_LF_INT_CLEAR(1)); - ret = RK_LF_STATUS_FC; - } else { - ret = RK_LF_STATUS_FR; - } - } else { - ret = RK_LF_STATUS_NC; - } - - return ret; -} - -static int rk312x_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv, - unsigned int dsp_addr[][4]) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if (lcdc_dev->clk_on) { - dsp_addr[0][0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST); - if (lcdc_dev->soc_type == VOP_RK3036) - dsp_addr[1][0] = lcdc_readl(lcdc_dev, WIN1_MST); - else if (lcdc_dev->soc_type == VOP_RK312X) - dsp_addr[1][0] = lcdc_readl(lcdc_dev, WIN1_MST_RK312X); - } - return 0; -} - -static ssize_t rk312x_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv, - char *buf, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device, - driver); - char format_w0[9] = "NULL"; - char format_w1[9] = "NULL"; - char status_w0[9] = "NULL"; - char status_w1[9] = "NULL"; - u32 fmt_id, act_info, dsp_info, dsp_st, factor; - u16 xvir_w0, x_act_w0, y_act_w0, x_dsp_w0, y_dsp_w0, x_st_w0, y_st_w0; - u16 xvir_w1, x_act_w1, y_act_w1, x_dsp_w1, y_dsp_w1, x_st_w1, y_st_w1; - u16 x_factor, y_factor, x_scale, y_scale; - u16 ovl; - u32 win1_dsp_yaddr = 0; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - /* data format */ - fmt_id = lcdc_readl(lcdc_dev, SYS_CTRL); - get_format_string((fmt_id & m_WIN0_FORMAT) >> 3, format_w0); - get_format_string((fmt_id & m_WIN1_FORMAT) >> 6, format_w1); - - /* win status */ - if (fmt_id & m_WIN0_EN) - strcpy(status_w0, "enabled"); - else - strcpy(status_w0, "disabled"); - - if ((fmt_id & m_WIN1_EN) >> 1) - strcpy(status_w1, "enabled"); - else - strcpy(status_w1, "disabled"); - - /* ovl */ - ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP); - - /* xvir */ - xvir_w0 = lcdc_readl(lcdc_dev, WIN0_VIR) & m_YRGB_VIR; - xvir_w1 = lcdc_readl(lcdc_dev, WIN1_VIR) & m_YRGB_VIR; - - /* xact/yact */ - act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO); - x_act_w0 = (act_info & m_ACT_WIDTH) + 1; - y_act_w0 = ((act_info & m_ACT_HEIGHT) >> 16) + 1; - - if (lcdc_dev->soc_type == VOP_RK3036) { - act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO); - x_act_w1 = (act_info & m_ACT_WIDTH) + 1; - y_act_w1 = ((act_info & m_ACT_HEIGHT) >> 16) + 1; - } else if (lcdc_dev->soc_type == VOP_RK312X) { - /* rk312x unsupport win1 scaler,so have no act info */ - x_act_w1 = 0; - y_act_w1 = 0; - } - - /* xsize/ysize */ - dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO); - x_dsp_w0 = (dsp_info & m_DSP_WIDTH) + 1; - y_dsp_w0 = ((dsp_info & m_DSP_HEIGHT) >> 16) + 1; - - if (lcdc_dev->soc_type == VOP_RK3036) - dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO); - else if (lcdc_dev->soc_type == VOP_RK312X) - dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO_RK312X); - x_dsp_w1 = (dsp_info & m_DSP_WIDTH) + 1; - y_dsp_w1 = ((dsp_info & m_DSP_HEIGHT) >> 16) + 1; - - /* xpos/ypos */ - dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST); - x_st_w0 = dsp_st & m_DSP_STX; - y_st_w0 = (dsp_st & m_DSP_STY) >> 16; - - if (lcdc_dev->soc_type == VOP_RK3036) - dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST); - else if (lcdc_dev->soc_type == VOP_RK312X) - dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST_RK312X); - - x_st_w1 = dsp_st & m_DSP_STX; - y_st_w1 = (dsp_st & m_DSP_STY) >> 16; - - /* scale factor */ - factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB); - x_factor = factor & m_X_SCL_FACTOR; - y_factor = (factor & m_Y_SCL_FACTOR) >> 16; - x_scale = 4096 * 100 / x_factor; - y_scale = 4096 * 100 / y_factor; - - /* dsp addr */ - if (lcdc_dev->soc_type == VOP_RK3036) - win1_dsp_yaddr = lcdc_readl(lcdc_dev, WIN1_MST); - else if (lcdc_dev->soc_type == VOP_RK312X) - win1_dsp_yaddr = lcdc_readl(lcdc_dev, WIN1_MST_RK312X); - } else { - spin_unlock(&lcdc_dev->reg_lock); - return -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - return snprintf(buf, PAGE_SIZE, - "win0:%s\n" - "xvir:%d\n" - "xact:%d\n" - "yact:%d\n" - "xdsp:%d\n" - "ydsp:%d\n" - "x_st:%d\n" - "y_st:%d\n" - "x_scale:%d.%d\n" - "y_scale:%d.%d\n" - "format:%s\n" - "YRGB buffer addr:0x%08x\n" - "CBR buffer addr:0x%08x\n\n" - "win1:%s\n" - "xvir:%d\n" - "xact:%d\n" - "yact:%d\n" - "xdsp:%d\n" - "ydsp:%d\n" - "x_st:%d\n" - "y_st:%d\n" - "format:%s\n" - "YRGB buffer addr:0x%08x\n" - "overlay:%s\n", - status_w0, - xvir_w0, - x_act_w0, - y_act_w0, - x_dsp_w0, - y_dsp_w0, - x_st_w0, - y_st_w0, - x_scale / 100, - x_scale % 100, - y_scale / 100, - y_scale % 100, - format_w0, - lcdc_readl(lcdc_dev, WIN0_YRGB_MST), - lcdc_readl(lcdc_dev, WIN0_CBR_MST), - status_w1, - xvir_w1, - x_act_w1, - y_act_w1, - x_dsp_w1, - y_dsp_w1, - x_st_w1, - y_st_w1, - format_w1, - win1_dsp_yaddr, - ovl ? "win0 on the top of win1\n" : - "win1 on the top of win0\n"); -} - -static int rk312x_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, - driver); - int *cbase = (int *)lcdc_dev->regs; - int *regsbak = (int *)lcdc_dev->regsbak; - int i, j; - - pr_info("back up reg:\n"); - for (i = 0; i <= (0xDC >> 4); i++) { - for (j = 0; j < 4; j++) - pr_info("%08x ", *(regsbak + i * 4 + j)); - pr_info("\n"); - } - - pr_info("lcdc reg:\n"); - for (i = 0; i <= (0xDC >> 4); i++) { - for (j = 0; j < 4; j++) - pr_info("%08x ", readl_relaxed(cbase + i * 4 + j)); - pr_info("\n"); - } - return 0; -} - -static int rk312x_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - if (lcdc_dev->soc_type == VOP_RK312X) { - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN, - v_DIRECT_PATH_EN(open)); - lcdc_cfg_done(lcdc_dev); - } - return 0; -} - -static int rk312x_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - - if (lcdc_dev->soc_type == VOP_RK312X) { - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_LAYER, - v_DIRECT_PATH_LAYER(win_id)); - lcdc_cfg_done(lcdc_dev); - } - return 0; -} - -static int rk312x_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - int ovl = 0; - - if (lcdc_dev->soc_type == VOP_RK312X) - ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN); - - return ovl; -} - -static int rk312x_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - - rk312x_lcdc_get_backlight_device(dev_drv); - - if (enable) { - /* close the backlight */ - if (lcdc_dev->backlight) { - lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN; - backlight_update_status(lcdc_dev->backlight); - } - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLACK_EN, - v_BLACK_EN(1)); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - rk312x_lcdc_standby(dev_drv, true); - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable) - dev_drv->trsm_ops->disable(); - } else { - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLACK_EN, - v_BLACK_EN(0)); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - - rk312x_lcdc_standby(dev_drv, false); - - msleep(100); - /* open the backlight */ - if (lcdc_dev->backlight) { - lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK; - backlight_update_status(lcdc_dev->backlight); - } - } - - return 0; -} - - -static struct rk_lcdc_drv_ops lcdc_drv_ops = { - .open = rk312x_lcdc_open, - .load_screen = rk312x_load_screen, - .get_dspbuf_info = rk312x_get_dspbuf_info, - .post_dspbuf = rk312x_post_dspbuf, - .set_par = rk312x_lcdc_set_par, - .pan_display = rk312x_lcdc_pan_display, - .direct_set_addr = rk312x_lcdc_direct_set_win_addr, - .blank = rk312x_lcdc_blank, - .ioctl = rk312x_lcdc_ioctl, - .get_win_state = rk312x_lcdc_get_win_state, - .ovl_mgr = rk312x_lcdc_ovl_mgr, - .get_disp_info = rk312x_lcdc_get_disp_info, - .fps_mgr = rk312x_lcdc_fps_mgr, - .fb_get_win_id = rk312x_lcdc_get_win_id, - .fb_win_remap = rk312x_fb_win_remap, - .poll_vblank = rk312x_lcdc_poll_vblank, - .get_dsp_addr = rk312x_lcdc_get_dsp_addr, - .cfg_done = rk312x_lcdc_cfg_done, - .dump_reg = rk312x_lcdc_reg_dump, - .dpi_open = rk312x_lcdc_dpi_open, - .dpi_win_sel = rk312x_lcdc_dpi_win_sel, - .dpi_status = rk312x_lcdc_dpi_status, - .set_dsp_bcsh_hue = rk312x_lcdc_set_bcsh_hue, - .set_dsp_bcsh_bcs = rk312x_lcdc_set_bcsh_bcs, - .get_dsp_bcsh_hue = rk312x_lcdc_get_bcsh_hue, - .get_dsp_bcsh_bcs = rk312x_lcdc_get_bcsh_bcs, - .open_bcsh = rk312x_lcdc_open_bcsh, - .set_screen_scaler = rk312x_lcdc_set_scaler, - .set_dsp_lut = rk312x_lcdc_set_lut, - .set_hwc_lut = rk312x_lcdc_set_hwc_lut, - .set_irq_to_cpu = rk312x_lcdc_set_irq_to_cpu, - .dsp_black = rk312x_lcdc_dsp_black, - .mmu_en = rk312x_lcdc_mmu_en, -}; -#if 0 -static const struct rk_lcdc_drvdata rk3036_lcdc_drvdata = { - .soc_type = VOP_RK3036, -}; -#endif -static const struct rk_lcdc_drvdata rk312x_lcdc_drvdata = { - .soc_type = VOP_RK312X, -}; - -#if defined(CONFIG_OF) -static const struct of_device_id rk312x_lcdc_dt_ids[] = { -#if 0 - { - .compatible = "rockchip,rk3036-lcdc", - .data = (void *)&rk3036_lcdc_drvdata, - }, -#endif - { - .compatible = "rockchip,rk312x-lcdc", - .data = (void *)&rk312x_lcdc_drvdata, - }, -}; -#endif - -static int rk312x_lcdc_parse_dt(struct lcdc_device *lcdc_dev) -{ - struct device_node *np = lcdc_dev->dev->of_node; - const struct of_device_id *match; - const struct rk_lcdc_drvdata *lcdc_drvdata; - int val; - - if (of_property_read_u32(np, "rockchip,iommu-enabled", &val)) - lcdc_dev->driver.iommu_enabled = 0; - else - lcdc_dev->driver.iommu_enabled = val; - - if (of_property_read_u32(np, "rockchip,fb-win-map", &val)) - lcdc_dev->driver.fb_win_map = FB_DEFAULT_ORDER; - else - lcdc_dev->driver.fb_win_map = val; - - match = of_match_node(rk312x_lcdc_dt_ids, np); - if (match) { - lcdc_drvdata = (const struct rk_lcdc_drvdata *)match->data; - lcdc_dev->soc_type = lcdc_drvdata->soc_type; - } else { - return PTR_ERR(match); - } - - return 0; -} - -static int rk312x_lcdc_probe(struct platform_device *pdev) -{ - struct lcdc_device *lcdc_dev = NULL; - struct rk_lcdc_driver *dev_drv; - struct device *dev = &pdev->dev; - struct resource *res; - int ret; - - lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL); - if (!lcdc_dev) { - dev_err(&pdev->dev, "rk312x lcdc device kzalloc fail!\n"); - return -ENOMEM; - } - platform_set_drvdata(pdev, lcdc_dev); - lcdc_dev->dev = dev; - if (rk312x_lcdc_parse_dt(lcdc_dev)) { - dev_err(lcdc_dev->dev, "rk312x lcdc parse dt failed!\n"); - goto err_parse_dt; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - lcdc_dev->reg_phy_base = res->start; - lcdc_dev->len = resource_size(res); - lcdc_dev->regs = devm_ioremap_resource(dev, res); - if (IS_ERR(lcdc_dev->regs)) { - ret = PTR_ERR(lcdc_dev->regs); - goto err_remap_reg; - } - - lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL); - if (IS_ERR(lcdc_dev->regsbak)) { - dev_err(&pdev->dev, "rk312x lcdc device kmalloc fail!\n"); - ret = PTR_ERR(lcdc_dev->regsbak); - goto err_remap_reg; - } - lcdc_dev->hwc_lut_addr_base = (lcdc_dev->regs + HWC_LUT_ADDR); - lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + DSP_LUT_ADDR); - lcdc_dev->prop = PRMRY; - dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id); - dev_drv = &lcdc_dev->driver; - dev_drv->dev = dev; - dev_drv->prop = lcdc_dev->prop; - dev_drv->id = lcdc_dev->id; - dev_drv->ops = &lcdc_drv_ops; - dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win); - spin_lock_init(&lcdc_dev->reg_lock); - - lcdc_dev->irq = platform_get_irq(pdev, 0); - if (lcdc_dev->irq < 0) { - dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n", - lcdc_dev->id); - ret = -ENXIO; - goto err_request_irq; - } - - ret = devm_request_irq(dev, lcdc_dev->irq, rk312x_lcdc_isr, - IRQF_DISABLED | IRQF_SHARED, - dev_name(dev), lcdc_dev); - if (ret) { - dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", - lcdc_dev->irq, ret); - goto err_request_irq; - } - - if (dev_drv->iommu_enabled) - strcpy(dev_drv->mmu_dts_name, VOP_IOMMU_COMPATIBLE_NAME); - - ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id); - if (ret < 0) { - dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id); - goto err_register_fb; - } - lcdc_dev->screen = dev_drv->screen0; - - dev_info(dev, "lcdc%d probe ok, iommu %s\n", - lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled"); - - return 0; -err_register_fb: -err_request_irq: - devm_kfree(lcdc_dev->dev, lcdc_dev->regsbak); -err_remap_reg: -err_parse_dt: - devm_kfree(&pdev->dev, lcdc_dev); - return ret; -} - -#if defined(CONFIG_PM) -static int rk312x_lcdc_suspend(struct platform_device *pdev, pm_message_t state) -{ - return 0; -} - -static int rk312x_lcdc_resume(struct platform_device *pdev) -{ - return 0; -} -#else -#define rk312x_lcdc_suspend NULL -#define rk312x_lcdc_resume NULL -#endif - -static int rk312x_lcdc_remove(struct platform_device *pdev) -{ - return 0; -} - -static void rk312x_lcdc_shutdown(struct platform_device *pdev) -{ - struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - struct rk_lcdc_driver *dev_drv=&lcdc_dev->driver; - - flush_kthread_worker(&dev_drv->update_regs_worker); - kthread_stop(dev_drv->update_regs_thread); - - rk312x_lcdc_standby(dev_drv, true); - rk312x_lcdc_deinit(lcdc_dev); - rk312x_lcdc_clk_disable(lcdc_dev); - rk_disp_pwr_disable(&lcdc_dev->driver); -} - -static struct platform_driver rk312x_lcdc_driver = { - .probe = rk312x_lcdc_probe, - .remove = rk312x_lcdc_remove, - .driver = { - .name = "rk312x-lcdc", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(rk312x_lcdc_dt_ids), - }, - .suspend = rk312x_lcdc_suspend, - .resume = rk312x_lcdc_resume, - .shutdown = rk312x_lcdc_shutdown, -}; - -static int __init rk312x_lcdc_module_init(void) -{ - return platform_driver_register(&rk312x_lcdc_driver); -} - -static void __exit rk312x_lcdc_module_exit(void) -{ - platform_driver_unregister(&rk312x_lcdc_driver); -} - -fs_initcall(rk312x_lcdc_module_init); -module_exit(rk312x_lcdc_module_exit); diff --git a/drivers/video/rockchip/lcdc/rk312x_lcdc.h b/drivers/video/rockchip/lcdc/rk312x_lcdc.h deleted file mode 100644 index 431bd0f97747..000000000000 --- a/drivers/video/rockchip/lcdc/rk312x_lcdc.h +++ /dev/null @@ -1,768 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _RK312X_LCDC_H_ -#define _RK312X_LCDC_H_ - -#include -#include -#include - -enum _VOP_SOC_TYPE { - VOP_RK3036 = 0, - VOP_RK312X, -}; - - -#define BITS(x, bit) ((x) << (bit)) -#define BITS_MASK(x, mask, bit) BITS((x) & (mask), bit) - -/*******************register definition**********************/ - -#define SYS_CTRL (0x00) - #define m_WIN0_EN BITS(1, 0) - #define m_WIN1_EN BITS(1, 1) - #define m_HWC_EN BITS(1, 2) - #define m_WIN0_FORMAT BITS(7, 3) - #define m_WIN1_FORMAT BITS(7, 6) - #define m_HWC_LUT_EN BITS(1, 9) - #define m_HWC_SIZE BITS(1, 10) - #define m_DIRECT_PATH_EN BITS(1, 11) /* rk312x */ - #define m_DIRECT_PATH_LAYER BITS(1, 12) /* rk312x */ - #define m_TVE_MODE_SEL BITS(1, 13) /* rk312x */ - #define m_TVE_DAC_EN BITS(1, 14) /* rk312x */ - #define m_WIN0_RB_SWAP BITS(1, 15) - #define m_WIN0_ALPHA_SWAP BITS(1, 16) - #define m_WIN0_Y8_SWAP BITS(1, 17) - #define m_WIN0_UV_SWAP BITS(1, 18) - #define m_WIN1_RB_SWAP BITS(1, 19) - #define m_WIN1_ALPHA_SWAP BITS(1, 20) - #define m_WIN1_ENDIAN_SWAP BITS(1, 21) /* rk312x */ - #define m_WIN0_OTSD_DISABLE BITS(1, 22) - #define m_WIN1_OTSD_DISABLE BITS(1, 23) - #define m_DMA_BURST_LENGTH BITS(3, 24) - #define m_HWC_LODAD_EN BITS(1, 26) - #define m_WIN1_LUT_EN BITS(1, 27) /* rk312x */ - #define m_DSP_LUT_EN BITS(1, 28) /* rk312x */ - #define m_DMA_STOP BITS(1, 29) - #define m_LCDC_STANDBY BITS(1, 30) - #define m_AUTO_GATING_EN BITS(1, 31) - - #define v_WIN0_EN(x) BITS_MASK(x, 1, 0) - #define v_WIN1_EN(x) BITS_MASK(x, 1, 1) - #define v_HWC_EN(x) BITS_MASK(x, 1, 2) - #define v_WIN0_FORMAT(x) BITS_MASK(x, 7, 3) - #define v_WIN1_FORMAT(x) BITS_MASK(x, 7, 6) - #define v_HWC_LUT_EN(x) BITS_MASK(x, 1, 9) - #define v_HWC_SIZE(x) BITS_MASK(x, 1, 10) - #define v_DIRECT_PATH_EN(x) BITS_MASK(x, 1, 11) - #define v_DIRECT_PATH_LAYER(x) BITS_MASK(x, 1, 12) - #define v_TVE_MODE_SEL(x) BITS_MASK(x, 1, 13) - #define v_TVE_DAC_EN(x) BITS_MASK(x, 1, 14) - #define v_WIN0_RB_SWAP(x) BITS_MASK(x, 1, 15) - #define v_WIN0_ALPHA_SWAP(x) BITS_MASK(x, 1, 16) - #define v_WIN0_Y8_SWAP(x) BITS_MASK(x, 1, 17) - #define v_WIN0_UV_SWAP(x) BITS_MASK(x, 1, 18) - #define v_WIN1_RB_SWAP(x) BITS_MASK(x, 1, 19) - #define v_WIN1_ALPHA_SWAP(x) BITS_MASK(x, 1, 20) - #define v_WIN1_ENDIAN_SWAP(x) BITS_MASK(x, 1, 21) - #define v_WIN0_OTSD_DISABLE(x) BITS_MASK(x, 1, 22) - #define v_WIN1_OTSD_DISABLE(x) BITS_MASK(x, 1, 23) - #define v_DMA_BURST_LENGTH(x) BITS_MASK(x, 3, 24) - #define v_HWC_LODAD_EN(x) BITS_MASK(x, 1, 26) - #define v_WIN1_LUT_EN(x) BITS_MASK(x, 1, 27) - #define v_DSP_LUT_EN(x) BITS_MASK(x, 1, 28) - #define v_DMA_STOP(x) BITS_MASK(x, 1, 29) - #define v_LCDC_STANDBY(x) BITS_MASK(x, 1, 30) - #define v_AUTO_GATING_EN(x) BITS_MASK(x, 1, 31) - -#define DSP_CTRL0 (0x04) - #define m_DSP_OUT_FORMAT BITS(0x0f, 0) - #define m_HSYNC_POL BITS(1, 4) - #define m_VSYNC_POL BITS(1, 5) - #define m_DEN_POL BITS(1, 6) - #define m_DCLK_POL BITS(1, 7) - #define m_WIN0_TOP BITS(1, 8) - #define m_DITHER_UP_EN BITS(1, 9) - #define m_DITHER_DOWN_MODE BITS(1, 10) /* use for rk312x */ - #define m_DITHER_DOWN_EN BITS(1, 11) /* use for rk312x */ - #define m_INTERLACE_DSP_EN BITS(1, 12) - #define m_INTERLACE_FIELD_POL BITS(1, 13) /* use for rk312x */ - #define m_WIN0_INTERLACE_EN BITS(1, 14) /* use for rk312x */ - #define m_WIN1_INTERLACE_EN BITS(1, 15) - #define m_WIN0_YRGB_DEFLICK_EN BITS(1, 16) - #define m_WIN0_CBR_DEFLICK_EN BITS(1, 17) - #define m_WIN0_ALPHA_MODE BITS(1, 18) - #define m_WIN1_ALPHA_MODE BITS(1, 19) - #define m_WIN0_CSC_MODE BITS(3, 20) - #define m_WIN1_CSC_MODE BITS(1, 22) - #define m_WIN0_YUV_CLIP BITS(1, 23) - #define m_TVE_MODE BITS(1, 25) - #define m_SW_UV_OFFSET_EN BITS(1, 26) /* use for rk312x */ - #define m_DITHER_DOWN_SEL BITS(1, 27) /* use for rk312x */ - #define m_HWC_ALPHA_MODE BITS(1, 28) - #define m_ALPHA_MODE_SEL0 BITS(1, 29) - #define m_ALPHA_MODE_SEL1 BITS(1, 30) - #define m_WIN1_DIFF_DCLK_EN BITS(1, 31) /* use for rk3036 */ - #define m_SW_OVERLAY_MODE BITS(1, 31) /* use for rk312x */ - - #define v_DSP_OUT_FORMAT(x) BITS_MASK(x, 0x0f, 0) - #define v_HSYNC_POL(x) BITS_MASK(x, 1, 4) - #define v_VSYNC_POL(x) BITS_MASK(x, 1, 5) - #define v_DEN_POL(x) BITS_MASK(x, 1, 6) - #define v_DCLK_POL(x) BITS_MASK(x, 1, 7) - #define v_WIN0_TOP(x) BITS_MASK(x, 1, 8) - #define v_DITHER_UP_EN(x) BITS_MASK(x, 1, 9) - #define v_DITHER_DOWN_MODE(x) BITS_MASK(x, 1, 10) /* rk312x */ - #define v_DITHER_DOWN_EN(x) BITS_MASK(x, 1, 11) /* rk312x */ - #define v_INTERLACE_DSP_EN(x) BITS_MASK(x, 1, 12) - #define v_INTERLACE_FIELD_POL(x) BITS_MASK(x, 1, 13) /* rk312x */ - #define v_WIN0_INTERLACE_EN(x) BITS_MASK(x, 1, 14) /* rk312x */ - #define v_WIN1_INTERLACE_EN(x) BITS_MASK(x, 1, 15) - #define v_WIN0_YRGB_DEFLICK_EN(x) BITS_MASK(x, 1, 16) - #define v_WIN0_CBR_DEFLICK_EN(x) BITS_MASK(x, 1, 17) - #define v_WIN0_ALPHA_MODE(x) BITS_MASK(x, 1, 18) - #define v_WIN1_ALPHA_MODE(x) BITS_MASK(x, 1, 19) - #define v_WIN0_CSC_MODE(x) BITS_MASK(x, 3, 20) - #define v_WIN1_CSC_MODE(x) BITS_MASK(x, 1, 22) - #define v_WIN0_YUV_CLIP(x) BITS_MASK(x, 1, 23) - #define v_TVE_MODE(x) BITS_MASK(x, 1, 25) - #define v_SW_UV_OFFSET_EN(x) BITS_MASK(x, 1, 26) /* rk312x */ - #define v_DITHER_DOWN_SEL(x) BITS_MASK(x, 1, 27) /* rk312x */ - #define v_HWC_ALPHA_MODE(x) BITS_MASK(x, 1, 28) - #define v_ALPHA_MODE_SEL0(x) BITS_MASK(x, 1, 29) - #define v_ALPHA_MODE_SEL1(x) BITS_MASK(x, 1, 30) - #define v_WIN1_DIFF_DCLK_EN(x) BITS_MASK(x, 1, 31) /* rk3036 */ - #define v_SW_OVERLAY_MODE(x) BITS_MASK(x, 1, 31) /* rk312x */ - -#define DSP_CTRL1 (0x08) - #define m_BG_COLOR BITS(0xffffff, 0) - #define m_BG_B BITS(0xff, 0) - #define m_BG_G BITS(0xff, 8) - #define m_BG_R BITS(0xff, 16) - #define m_BLANK_EN BITS(1, 24) - #define m_BLACK_EN BITS(1, 25) - #define m_DSP_BG_SWAP BITS(1, 26) - #define m_DSP_RB_SWAP BITS(1, 27) - #define m_DSP_RG_SWAP BITS(1, 28) - #define m_DSP_DELTA_SWAP BITS(1, 29) /* rk3036 */ - #define m_DSP_DUMMY_SWAP BITS(1, 30) /* rk3036 */ - #define m_DSP_OUT_ZERO BITS(1, 31) - - #define v_BG_COLOR(x) BITS_MASK(x, 0xffffff, 0) - #define v_BG_B(x) BITS_MASK(x, 0xff, 0) - #define v_BG_G(x) BITS_MASK(x, 0xff, 8) - #define v_BG_R(x) BITS_MASK(x, 0xff, 16) - #define v_BLANK_EN(x) BITS_MASK(x, 1, 24) - #define v_BLACK_EN(x) BITS_MASK(x, 1, 25) - #define v_DSP_BG_SWAP(x) BITS_MASK(x, 1, 26) - #define v_DSP_RB_SWAP(x) BITS_MASK(x, 1, 27) - #define v_DSP_RG_SWAP(x) BITS_MASK(x, 1, 28) - #define v_DSP_DELTA_SWAP(x) BITS_MASK(x, 1, 29) /* rk3036 */ - #define v_DSP_DUMMY_SWAP(x) BITS_MASK(x, 1, 30) /* rk3036 */ - #define v_DSP_OUT_ZERO(x) BITS_MASK(x, 1, 31) - -#define INT_SCALER (0x0c) /* only use for rk312x */ - #define m_SCALER_EMPTY_INTR_EN BITS(1, 0) - #define m_SCLAER_EMPTY_INTR_CLR BITS(1, 1) - #define m_SCLAER_EMPTY_INTR_STA BITS(1, 2) - #define m_FS_MASK_EN BITS(1, 3) - #define m_HDMI_HSYNC_POL BITS(1, 4) - #define m_HDMI_VSYNC_POL BITS(1, 5) - #define m_HDMI_DEN_POL BITS(1, 6) - - #define v_SCALER_EMPTY_INTR_EN(x) BITS_MASK(x, 1, 0) - #define v_SCLAER_EMPTY_INTR_CLR(x) BITS_MASK(x, 1, 1) - #define v_SCLAER_EMPTY_INTR_STA(x) BITS_MASK(x, 1, 2) - #define v_FS_MASK_EN(x) BITS_MASK(x, 1, 3) - #define v_HDMI_HSYNC_POL(x) BITS_MASK(x, 1, 4) - #define v_HDMI_VSYNC_POL(x) BITS_MASK(x, 1, 5) - #define v_HDMI_DEN_POL(x) BITS_MASK(x, 1, 6) - -#define INT_STATUS (0x10) - #define m_HS_INT_STA BITS(1, 0) - #define m_FS_INT_STA BITS(1, 1) - #define m_LF_INT_STA BITS(1, 2) - #define m_BUS_ERR_INT_STA BITS(1, 3) - #define m_HS_INT_EN BITS(1, 4) - #define m_FS_INT_EN BITS(1, 5) - #define m_LF_INT_EN BITS(1, 6) - #define m_BUS_ERR_INT_EN BITS(1, 7) - #define m_HS_INT_CLEAR BITS(1, 8) - #define m_FS_INT_CLEAR BITS(1, 9) - #define m_LF_INT_CLEAR BITS(1, 10) - #define m_BUS_ERR_INT_CLEAR BITS(1, 11) - #define m_LF_INT_NUM BITS(0xfff, 12) - #define m_WIN0_EMPTY_INT_EN BITS(1, 24) - #define m_WIN1_EMPTY_INT_EN BITS(1, 25) - #define m_WIN0_EMPTY_INT_CLEAR BITS(1, 26) - #define m_WIN1_EMPTY_INT_CLEAR BITS(1, 27) - #define m_WIN0_EMPTY_INT_STA BITS(1, 28) - #define m_WIN1_EMPTY_INT_STA BITS(1, 29) - #define m_FS_RAW_STA BITS(1, 30) - #define m_LF_RAW_STA BITS(1, 31) - - #define v_HS_INT_EN(x) BITS_MASK(x, 1, 4) - #define v_FS_INT_EN(x) BITS_MASK(x, 1, 5) - #define v_LF_INT_EN(x) BITS_MASK(x, 1, 6) - #define v_BUS_ERR_INT_EN(x) BITS_MASK(x, 1, 7) - #define v_HS_INT_CLEAR(x) BITS_MASK(x, 1, 8) - #define v_FS_INT_CLEAR(x) BITS_MASK(x, 1, 9) - #define v_LF_INT_CLEAR(x) BITS_MASK(x, 1, 10) - #define v_BUS_ERR_INT_CLEAR(x) BITS_MASK(x, 1, 11) - #define v_LF_INT_NUM(x) BITS_MASK(x, 0xfff, 12) - #define v_WIN0_EMPTY_INT_EN(x) BITS_MASK(x, 1, 24) - #define v_WIN1_EMPTY_INT_EN(x) BITS_MASK(x, 1, 25) - #define v_WIN0_EMPTY_INT_CLEAR(x) BITS_MASK(x, 1, 26) - #define v_WIN1_EMPTY_INT_CLEAR(x) BITS_MASK(x, 1, 27) - -#define ALPHA_CTRL (0x14) - #define m_WIN0_ALPHA_EN BITS(1, 0) - #define m_WIN1_ALPHA_EN BITS(1, 1) - #define m_HWC_ALPAH_EN BITS(1, 2) - #define m_WIN1_PREMUL_SCALE BITS(1, 3) /* rk3036 */ - #define m_WIN0_ALPHA_VAL BITS(0xff, 4) - #define m_WIN1_ALPHA_VAL BITS(0xff, 12) - #define m_HWC_ALPAH_VAL BITS(0xff, 20) - - #define v_WIN0_ALPHA_EN(x) BITS_MASK(x, 1, 0) - #define v_WIN1_ALPHA_EN(x) BITS_MASK(x, 1, 1) - #define v_HWC_ALPAH_EN(x) BITS_MASK(x, 1, 2) - #define v_WIN1_PREMUL_SCALE(x) BITS_MASK(x, 1, 3) /* rk3036 */ - #define v_WIN0_ALPHA_VAL(x) BITS_MASK(x, 0xff, 4) - #define v_WIN1_ALPHA_VAL(x) BITS_MASK(x, 0xff, 12) - #define v_HWC_ALPAH_VAL(x) BITS_MASK(x, 0xff, 20) - -#define WIN0_COLOR_KEY (0x18) -#define WIN1_COLOR_KEY (0x1c) - #define m_COLOR_KEY_VAL BITS(0xffffff, 0) - #define m_COLOR_KEY_EN BITS(1, 24) - - #define v_COLOR_KEY_VAL(x) BITS_MASK(x, 0xffffff, 0) - #define v_COLOR_KEY_EN(x) BITS_MASK(x, 1, 24) - -/* Layer Registers */ -#define WIN0_YRGB_MST (0x20) -#define WIN0_CBR_MST (0x24) -#define WIN1_MST (0xa0) /* rk3036 */ -#define WIN1_MST_RK312X (0x4c) /* rk312x */ -#define HWC_MST (0x58) - -#define WIN1_VIR (0x28) -#define WIN0_VIR (0x30) - #define m_YRGB_VIR BITS(0x1fff, 0) - #define m_CBBR_VIR BITS(0x1fff, 16) - - #define v_YRGB_VIR(x) BITS_MASK(x, 0x1fff, 0) - #define v_CBBR_VIR(x) BITS_MASK(x, 0x1fff, 16) - - #define v_ARGB888_VIRWIDTH(x) BITS_MASK(x, 0x1fff, 0) - #define v_RGB888_VIRWIDTH(x) BITS_MASK(((x*3)>>2)+((x)%3), 0x1fff, 0) - #define v_RGB565_VIRWIDTH(x) BITS_MASK(DIV_ROUND_UP(x, 2), 0x1fff, 0) - #define v_YUV_VIRWIDTH(x) BITS_MASK(DIV_ROUND_UP(x, 4), 0x1fff, 0) - #define v_CBCR_VIR(x) BITS_MASK(x, 0x1fff, 16) - -#define WIN0_ACT_INFO (0x34) -#define WIN1_ACT_INFO (0xb4) /* rk3036 */ - #define m_ACT_WIDTH BITS(0x1fff, 0) - #define m_ACT_HEIGHT BITS(0x1fff, 16) - - #define v_ACT_WIDTH(x) BITS_MASK(x - 1, 0x1fff, 0) - #define v_ACT_HEIGHT(x) BITS_MASK(x - 1, 0x1fff, 16) - -#define WIN0_DSP_INFO (0x38) -#define WIN1_DSP_INFO (0xb8) /* rk3036 */ -#define WIN1_DSP_INFO_RK312X (0x50) /* rk312x */ - #define m_DSP_WIDTH BITS(0x7ff, 0) - #define m_DSP_HEIGHT BITS(0x7ff, 16) - - #define v_DSP_WIDTH(x) BITS_MASK(x - 1, 0x7ff, 0) - #define v_DSP_HEIGHT(x) BITS_MASK(x - 1, 0x7ff, 16) - -#define WIN0_DSP_ST (0x3c) -#define WIN1_DSP_ST (0xbc) /* rk3036 */ -#define WIN1_DSP_ST_RK312X (0x54) /* rk312x */ -#define HWC_DSP_ST (0x5c) - #define m_DSP_STX BITS(0xfff, 0) - #define m_DSP_STY BITS(0xfff, 16) - - #define v_DSP_STX(x) BITS_MASK(x, 0xfff, 0) - #define v_DSP_STY(x) BITS_MASK(x, 0xfff, 16) - -#define WIN0_SCL_FACTOR_YRGB (0x40) -#define WIN0_SCL_FACTOR_CBR (0x44) -#define WIN1_SCL_FACTOR_YRGB (0xc0) /* rk3036 */ - #define m_X_SCL_FACTOR BITS(0xffff, 0) - #define m_Y_SCL_FACTOR BITS(0xffff, 16) - - #define v_X_SCL_FACTOR(x) BITS_MASK(x, 0xffff, 0) - #define v_Y_SCL_FACTOR(x) BITS_MASK(x, 0xffff, 16) - -#define WIN0_SCL_OFFSET (0x48) -#define WIN1_SCL_OFFSET (0xc8) /* rk3036 */ - -/* LUT Registers */ -#define WIN1_LUT_ADDR (0x0400) /* rk3036 */ -#define HWC_LUT_ADDR (0x0800) -#define DSP_LUT_ADDR (0x0c00) /* rk312x */ - -/* Display Infomation Registers */ -#define DSP_HTOTAL_HS_END (0x6c) - #define v_HSYNC(x) BITS_MASK(x, 0xfff, 0) /* hsync pulse width */ - #define v_HORPRD(x) BITS_MASK(x, 0xfff, 16) /* horizontal period */ - -#define DSP_HACT_ST_END (0x70) - #define v_HAEP(x) BITS_MASK(x, 0xfff, 0) /* horizontal active end point */ - #define v_HASP(x) BITS_MASK(x, 0xfff, 16) /* horizontal active start point */ - -#define DSP_VTOTAL_VS_END (0x74) - #define v_VSYNC(x) BITS_MASK(x, 0xfff, 0) - #define v_VERPRD(x) BITS_MASK(x, 0xfff, 16) - -#define DSP_VACT_ST_END (0x78) - #define v_VAEP(x) BITS_MASK(x, 0xfff, 0) - #define v_VASP(x) BITS_MASK(x, 0xfff, 16) - -#define DSP_VS_ST_END_F1 (0x7c) - #define v_VSYNC_END_F1(x) BITS_MASK(x, 0xfff, 0) - #define v_VSYNC_ST_F1(x) BITS_MASK(x, 0xfff, 16) -#define DSP_VACT_ST_END_F1 (0x80) - #define v_VAEP_F1(x) BITS_MASK(x, 0xfff, 0) - #define v_VASP_F1(x) BITS_MASK(x, 0xfff, 16) - -/* Scaler Registers - * Only used for rk312x - */ -#define SCALER_CTRL (0xa0) - #define m_SCALER_EN BITS(1, 0) - #define m_SCALER_SYNC_INVERT BITS(1, 2) - #define m_SCALER_DEN_INVERT BITS(1, 3) - #define m_SCALER_OUT_ZERO BITS(1, 4) - #define m_SCALER_OUT_EN BITS(1, 5) - #define m_SCALER_VSYNC_MODE BITS(3, 6) - #define m_SCALER_VSYNC_VST BITS(0xff, 8) - - #define v_SCALER_EN(x) BITS_MASK(x, 1, 0) - #define v_SCALER_SYNC_INVERT(x) BITS_MASK(x, 1, 2) - #define v_SCALER_DEN_INVERT(x) BITS_MASK(x, 1, 3) - #define v_SCALER_OUT_ZERO(x) BITS_MASK(x, 1, 4) - #define v_SCALER_OUT_EN(x) BITS_MASK(x, 1, 5) - #define v_SCALER_VSYNC_MODE(x) BITS_MASK(x, 3, 6) - #define v_SCALER_VSYNC_VST(x) BITS_MASK(x, 0xff, 8) - -#define SCALER_FACTOR (0xa4) - #define m_SCALER_H_FACTOR BITS(0x3fff, 0) - #define m_SCALER_V_FACTOR BITS(0x3fff, 16) - - #define v_SCALER_H_FACTOR(x) BITS_MASK(x, 0x3fff, 0) - #define v_SCALER_V_FACTOR(x) BITS_MASK(x, 0x3fff, 16) - -#define SCALER_FRAME_ST (0xa8) - #define m_SCALER_FRAME_HST BITS(0xfff, 0) - #define m_SCALER_FRAME_VST BITS(0xfff, 16) - - #define v_SCALER_FRAME_HST(x) BITS_MASK(x, 0xfff, 0) - #define v_SCALER_FRAME_VST(x) BITS_MASK(x, 0xfff, 16) - -#define SCALER_DSP_HOR_TIMING (0xac) - #define m_SCALER_HTOTAL BITS(0xfff, 0) - #define m_SCALER_HS_END BITS(0xff, 16) - - #define v_SCALER_HTOTAL(x) BITS_MASK(x, 0xfff, 0) - #define v_SCALER_HS_END(x) BITS_MASK(x, 0xff, 16) - -#define SCALER_DSP_HACT_ST_END (0xb0) - #define m_SCALER_HAEP BITS(0xfff, 0) - #define m_SCALER_HASP BITS(0x3ff, 16) - - #define v_SCALER_HAEP(x) BITS_MASK(x, 0xfff, 0) - #define v_SCALER_HASP(x) BITS_MASK(x, 0x3ff, 16) - -#define SCALER_DSP_VER_TIMING (0xb4) - #define m_SCALER_VTOTAL BITS(0xfff, 0) - #define m_SCALER_VS_END BITS(0xff, 16) - - #define v_SCALER_VTOTAL(x) BITS_MASK(x, 0xfff, 0) - #define v_SCALER_VS_END(x) BITS_MASK(x, 0xff, 16) - -#define SCALER_DSP_VACT_ST_END (0xb8) - #define m_SCALER_VAEP BITS(0xfff, 0) - #define m_SCALER_VASP BITS(0xff, 16) - - #define v_SCALER_VAEP(x) BITS_MASK(x, 0xfff, 0) - #define v_SCALER_VASP(x) BITS_MASK(x, 0xff, 16) - -#define SCALER_DSP_HBOR_TIMING (0xbc) - #define m_SCALER_HBOR_END BITS(0xfff, 0) - #define m_SCALER_HBOR_ST BITS(0x3ff, 16) - - #define v_SCALER_HBOR_END(x) BITS_MASK(x, 0xfff, 0) - #define v_SCALER_HBOR_ST(x) BITS_MASK(x, 0x3ff, 16) - -#define SCALER_DSP_VBOR_TIMING (0xc0) - #define m_SCALER_VBOR_END BITS(0xfff, 0) - #define m_SCALER_VBOR_ST BITS(0xff, 16) - - #define v_SCALER_VBOR_END(x) BITS_MASK(x, 0xfff, 0) - #define v_SCALER_VBOR_ST(x) BITS_MASK(x, 0xff, 16) - -/* BCSH Registers */ -#define BCSH_CTRL (0xd0) - #define m_BCSH_EN BITS(1, 0) - #define m_BCSH_R2Y_CSC_MODE BITS(1, 1) /* rk312x */ - #define m_BCSH_OUT_MODE BITS(3, 2) - #define m_BCSH_Y2R_CSC_MODE BITS(3, 4) - #define m_BCSH_Y2R_EN BITS(1, 6) /* rk312x */ - #define m_BCSH_R2Y_EN BITS(1, 7) /* rk312x */ - - #define v_BCSH_EN(x) BITS_MASK(x, 1, 0) - #define v_BCSH_R2Y_CSC_MODE(x) BITS_MASK(x, 1, 1) /* rk312x */ - #define v_BCSH_OUT_MODE(x) BITS_MASK(x, 3, 2) - #define v_BCSH_Y2R_CSC_MODE(x) BITS_MASK(x, 3, 4) - #define v_BCSH_Y2R_EN(x) BITS_MASK(x, 1, 6) /* rk312x */ - #define v_BCSH_R2Y_EN(x) BITS_MASK(x, 1, 7) /* rk312x */ - -#define BCSH_COLOR_BAR (0xd4) - #define m_BCSH_COLOR_BAR_Y BITS(0xff, 0) - #define m_BCSH_COLOR_BAR_U BITS(0xff, 8) - #define m_BCSH_COLOR_BAR_V BITS(0xff, 16) - - #define v_BCSH_COLOR_BAR_Y(x) BITS_MASK(x, 0xff, 0) - #define v_BCSH_COLOR_BAR_U(x) BITS_MASK(x, 0xff, 8) - #define v_BCSH_COLOR_BAR_V(x) BITS_MASK(x, 0xff, 16) - -#define BCSH_BCS (0xd8) - #define m_BCSH_BRIGHTNESS BITS(0x1f, 0) - #define m_BCSH_CONTRAST BITS(0xff, 8) - #define m_BCSH_SAT_CON BITS(0x1ff, 16) - - #define v_BCSH_BRIGHTNESS(x) BITS_MASK(x, 0x1f, 0) - #define v_BCSH_CONTRAST(x) BITS_MASK(x, 0xff, 8) - #define v_BCSH_SAT_CON(x) BITS_MASK(x, 0x1ff, 16) - -#define BCSH_H (0xdc) - #define m_BCSH_SIN_HUE BITS(0xff, 0) - #define m_BCSH_COS_HUE BITS(0xff, 8) - - #define v_BCSH_SIN_HUE(x) BITS_MASK(x, 0xff, 0) - #define v_BCSH_COS_HUE(x) BITS_MASK(x, 0xff, 8) - -#define FRC_LOWER01_0 (0xe0) -#define FRC_LOWER01_1 (0xe4) -#define FRC_LOWER10_0 (0xe8) -#define FRC_LOWER10_1 (0xec) -#define FRC_LOWER11_0 (0xf0) -#define FRC_LOWER11_1 (0xf4) - -/* Bus Register */ -#define AXI_BUS_CTRL (0x2c) - #define m_IO_PAD_CLK BITS(1, 31) - #define m_CORE_CLK_DIV_EN BITS(1, 30) - #define m_MIPI_DCLK_INVERT BITS(1, 29) /* rk312x */ - #define m_MIPI_DCLK_EN BITS(1, 28) /* rk312x */ - #define m_LVDS_DCLK_INVERT BITS(1, 27) /* rk312x */ - #define m_LVDS_DCLK_EN BITS(1, 26) /* rk312x */ - #define m_RGB_DCLK_INVERT BITS(1, 25) /* rk312x */ - #define m_RGB_DCLK_EN BITS(1, 24) /* rk312x */ - #define m_HDMI_DCLK_INVERT BITS(1, 23) - #define m_HDMI_DCLK_EN BITS(1, 22) - #define m_TVE_DAC_DCLK_INVERT BITS(1, 21) - #define m_TVE_DAC_DCLK_EN BITS(1, 20) - #define m_HDMI_DCLK_DIV_EN BITS(1, 19) - #define m_AXI_OUTSTANDING_MAX_NUM BITS(0x1f, 12) - #define m_AXI_MAX_OUTSTANDING_EN BITS(1, 11) - #define m_MMU_EN BITS(1, 10) - #define m_NOC_HURRY_THRESHOLD BITS(0xf, 6) - #define m_NOC_HURRY_VALUE BITS(3, 4) - #define m_NOC_HURRY_EN BITS(1, 3) - #define m_NOC_QOS_VALUE BITS(3, 1) - #define m_NOC_QOS_EN BITS(1, 0) - - #define v_IO_PAD_CLK(x) BITS_MASK(x, 1, 31) - #define v_CORE_CLK_DIV_EN(x) BITS_MASK(x, 1, 30) - #define v_MIPI_DCLK_INVERT(x) BITS_MASK(x, 1, 29) - #define v_MIPI_DCLK_EN(x) BITS_MASK(x, 1, 28) - #define v_LVDS_DCLK_INVERT(x) BITS_MASK(x, 1, 27) - #define v_LVDS_DCLK_EN(x) BITS_MASK(x, 1, 26) - #define v_RGB_DCLK_INVERT(x) BITS_MASK(x, 1, 25) - #define v_RGB_DCLK_EN(x) BITS_MASK(x, 1, 24) - #define v_HDMI_DCLK_INVERT(x) BITS_MASK(x, 1, 23) - #define v_HDMI_DCLK_EN(x) BITS_MASK(x, 1, 22) - #define v_TVE_DAC_DCLK_INVERT(x) BITS_MASK(x, 1, 21) - #define v_TVE_DAC_DCLK_EN(x) BITS_MASK(x, 1, 20) - #define v_HDMI_DCLK_DIV_EN(x) BITS_MASK(x, 1, 19) - #define v_AXI_OUTSTANDING_MAX_NUM(x) BITS_MASK(x, 0x1f, 12) - #define v_AXI_MAX_OUTSTANDING_EN(x) BITS_MASK(x, 1, 11) - #define v_MMU_EN(x) BITS_MASK(x, 1, 10) - #define v_NOC_HURRY_THRESHOLD(x) BITS_MASK(x, 0xf, 6) - #define v_NOC_HURRY_VALUE(x) BITS_MASK(x, 3, 4) - #define v_NOC_HURRY_EN(x) BITS_MASK(x, 1, 3) - #define v_NOC_QOS_VALUE(x) BITS_MASK(x, 3, 1) - #define v_NOC_QOS_EN(x) BITS_MASK(x, 1, 0) - -#define GATHER_TRANSFER (0x84) - #define m_WIN1_AXI_GATHER_NUM BITS(0xf, 12) - #define m_WIN0_CBCR_AXI_GATHER_NUM BITS(0x7, 8) - #define m_WIN0_YRGB_AXI_GATHER_NUM BITS(0xf, 4) - #define m_WIN1_AXI_GAHTER_EN BITS(1, 2) - #define m_WIN0_CBCR_AXI_GATHER_EN BITS(1, 1) - #define m_WIN0_YRGB_AXI_GATHER_EN BITS(1, 0) - - #define v_WIN1_AXI_GATHER_NUM(x) BITS_MASK(x, 0xf, 12) - #define v_WIN0_CBCR_AXI_GATHER_NUM(x) BITS_MASK(x, 0x7, 8) - #define v_WIN0_YRGB_AXI_GATHER_NUM(x) BITS_MASK(x, 0xf, 4) - #define v_WIN1_AXI_GAHTER_EN(x) BITS_MASK(x, 1, 2) - #define v_WIN0_CBCR_AXI_GATHER_EN(x) BITS_MASK(x, 1, 1) - #define v_WIN0_YRGB_AXI_GATHER_EN(x) BITS_MASK(x, 1, 0) - -#define VERSION_INFO (0x94) - #define m_MAJOR BITS(0xff, 24) - #define m_MINOR BITS(0xff, 16) - #define m_BUILD BITS(0xffff) - -#define REG_CFG_DONE (0x90) - -/* TV Control Registers */ -#define TV_CTRL (0x200) -#define TV_SYNC_TIMING (0x204) -#define TV_ACT_TIMING (0x208) -#define TV_ADJ_TIMING (0x20c) -#define TV_FREQ_SC (0x210) -#define TV_FILTER0 (0x214) -#define TV_FILTER1 (0x218) -#define TV_FILTER2 (0x21C) -#define TV_ACT_ST (0x234) -#define TV_ROUTING (0x238) -#define TV_SYNC_ADJUST (0x250) -#define TV_STATUS (0x254) -#define TV_RESET (0x268) -#define TV_SATURATION (0x278) -#define TV_BW_CTRL (0x28C) -#define TV_BRIGHTNESS_CONTRAST (0x290) - - -/* MMU registers */ -#define MMU_DTE_ADDR (0x0300) - #define m_MMU_DTE_ADDR BITS(0xffffffff, 0) - #define v_MMU_DTE_ADDR(x) BITS_MASK(x, 0xffffffff, 0) - -#define MMU_STATUS (0x0304) - #define m_PAGING_ENABLED BITS(1, 0) - #define m_PAGE_FAULT_ACTIVE BITS(1, 1) - #define m_STAIL_ACTIVE BITS(1, 2) - #define m_MMU_IDLE BITS(1, 3) - #define m_REPLAY_BUFFER_EMPTY BITS(1, 4) - #define m_PAGE_FAULT_IS_WRITE BITS(1, 5) - #define m_PAGE_FAULT_BUS_ID BITS(0x1f, 6) - - #define v_PAGING_ENABLED(x) BITS_MASK(x, 1, 0) - #define v_PAGE_FAULT_ACTIVE(x) BITS_MASK(x, 1, 1) - #define v_STAIL_ACTIVE(x) BITS_MASK(x, 1, 2) - #define v_MMU_IDLE(x) BITS_MASK(x, 1, 3) - #define v_REPLAY_BUFFER_EMPTY(x) BITS_MASK(x, 1, 4) - #define v_PAGE_FAULT_IS_WRITE(x) BITS_MASK(x, 1, 5) - #define v_PAGE_FAULT_BUS_ID(x) BITS_MASK(x, 0x1f, 6) - -#define MMU_COMMAND (0x0308) - #define m_MMU_CMD BITS(0x7, 0) - #define v_MMU_CMD(x) BITS_MASK(x, 0x7, 0) - -#define MMU_PAGE_FAULT_ADDR (0x030c) - #define m_PAGE_FAULT_ADDR BITS(0xffffffff, 0) - #define v_PAGE_FAULT_ADDR(x) BITS_MASK(x, 0xffffffff, 0) - -#define MMU_ZAP_ONE_LINE (0x0310) - #define m_MMU_ZAP_ONE_LINE BITS(0xffffffff, 0) - #define v_MMU_ZAP_ONE_LINE(x) BITS_MASK(x, 0xffffffff, 0) - -#define MMU_INT_RAWSTAT (0x0314) - #define m_PAGE_FAULT_RAWSTAT BITS(1, 0) - #define m_READ_BUS_ERROR_RAWSTAT BITS(1, 1) - - #define v_PAGE_FAULT_RAWSTAT(x) BITS(x, 1, 0) - #define v_READ_BUS_ERROR_RAWSTAT(x) BITS(x, 1, 1) - -#define MMU_INT_CLEAR (0x0318) - #define m_PAGE_FAULT_CLEAR BITS(1, 0) - #define m_READ_BUS_ERROR_CLEAR BITS(1, 1) - - #define v_PAGE_FAULT_CLEAR(x) BITS(x, 1, 0) - #define v_READ_BUS_ERROR_CLEAR(x) BITS(x, 1, 1) - -#define MMU_INT_MASK (0x031c) - #define m_PAGE_FAULT_MASK BITS(1, 0) - #define m_READ_BUS_ERROR_MASK BITS(1, 1) - - #define v_PAGE_FAULT_MASK(x) BITS(x, 1, 0) - #define v_READ_BUS_ERROR_MASK(x) BITS(x, 1, 1) - -#define MMU_INT_STATUS (0x0320) - #define m_PAGE_FAULT_STATUS BITS(1, 0) - #define m_READ_BUS_ERROR_STATUS BITS(1, 1) - - #define v_PAGE_FAULT_STATUS(x) BITS(x, 1, 0) - #define v_READ_BUS_ERROR_STATUS(x) BITS(x, 1, 1) - -#define MMU_AUTO_GATING (0x0324) - #define m_MMU_AUTO_GATING BITS(1, 0) - #define v_MMU_AUTO_GATING(x) BITS(x, 1, 0) - - -enum _vop_dma_burst { - DMA_BURST_16 = 0, - DMA_BURST_8, - DMA_BURST_4 -}; - -enum _vop_format_e { - VOP_FORMAT_ARGB888 = 0, - VOP_FORMAT_RGB888, - VOP_FORMAT_RGB565, - VOP_FORMAT_YCBCR420 = 4, - VOP_FORMAT_YCBCR422, - VOP_FORMAT_YCBCR444 -}; - -enum _vop_tv_mode { - TV_NTSC, - TV_PAL, -}; - -enum _vop_r2y_csc_mode { - VOP_R2Y_CSC_BT601 = 0, - VOP_R2Y_CSC_BT709 -}; - -enum _vop_y2r_csc_mode { - VOP_Y2R_CSC_MPEG = 0, - VOP_Y2R_CSC_JPEG, - VOP_Y2R_CSC_HD, - VOP_Y2R_CSC_BYPASS -}; - -enum _vop_hwc_size { - VOP_HWC_SIZE_32, - VOP_HWC_SIZE_64 -}; - -enum _vop_overlay_mode { - VOP_RGB_DOMAIN, - VOP_YUV_DOMAIN -}; - - -#define CalScale(x, y) ((((u32)(x - 1)) * 0x1000) / (y - 1)) -#define INT_STA_MSK (m_HS_INT_STA | m_FS_INT_STA | \ - m_LF_INT_STA | m_BUS_ERR_INT_STA) -#define INT_CLR_SHIFT 8 - -struct rk_lcdc_drvdata { - u8 soc_type; - u32 reserve; -}; - -struct lcdc_device { - int id; - u8 soc_type; - struct rk_lcdc_driver driver; - struct device *dev; - struct rk_screen *screen; - - void __iomem *regs; - void *regsbak; /* back up reg */ - u32 reg_phy_base; /* physical basic address of lcdc register */ - u32 len; /* physical map length of lcdc register */ - spinlock_t reg_lock; /* one time only one process allowed to config the register */ - - int __iomem *hwc_lut_addr_base; - int __iomem *dsp_lut_addr_base; - - int prop; /* used for primary or extended display device */ - bool pre_init; - bool pwr18; /* if lcdc use 1.8v power supply */ - bool clk_on; /* if aclk or hclk is closed ,acess to register is not allowed */ - bool sclk_on; /* if sclk is open or closed */ - u8 atv_layer_cnt; /* active layer counter,when atv_layer_cnt = 0,lcdc is disable*/ - - unsigned int irq; - - struct clk *pd; /* lcdc power domain */ - struct clk *hclk; /* lcdc AHP clk */ - struct clk *dclk; /* lcdc dclk */ - struct clk *aclk; /* lcdc share memory frequency */ - struct clk *sclk; /* scaler clk */ - struct clk *pll_sclk; - u32 pixclock; - u32 s_pixclock; - - u32 standby; /* 1:standby,0:work */ - struct backlight_device *backlight; - u32 iommu_status; -}; - -static inline void lcdc_writel(struct lcdc_device *lcdc_dev, u32 offset, u32 v) -{ - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - *_pv = v; - writel_relaxed(v, lcdc_dev->regs + offset); -} - -static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev, u32 offset) -{ - u32 v; - v = readl_relaxed(lcdc_dev->regs + offset); - return v; -} - -static inline u32 lcdc_readl_backup(struct lcdc_device *lcdc_dev, u32 offset) -{ - u32 v; - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - v = readl_relaxed(lcdc_dev->regs + offset); - *_pv = v; - return v; -} - -static inline u32 lcdc_read_bit(struct lcdc_device *lcdc_dev, u32 offset, - u32 msk) -{ - u32 _v = readl_relaxed(lcdc_dev->regs + offset); - _v &= msk; - return (_v? 1 : 0); -} - -static inline void lcdc_set_bit(struct lcdc_device *lcdc_dev, u32 offset, - u32 msk) -{ - u32* _pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) |= msk; - writel_relaxed(*_pv, lcdc_dev->regs + offset); -} - -static inline void lcdc_clr_bit(struct lcdc_device *lcdc_dev, u32 offset, - u32 msk) -{ - u32* _pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) &= (~msk); - writel_relaxed(*_pv, lcdc_dev->regs + offset); -} - -static inline void lcdc_msk_reg(struct lcdc_device *lcdc_dev, u32 offset, - u32 msk, u32 v) -{ - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) &= (~msk); - (*_pv) |= v; - writel_relaxed(*_pv, lcdc_dev->regs + offset); -} - -static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev) -{ - writel_relaxed(0x01, lcdc_dev->regs + REG_CFG_DONE); - dsb(); -} - -#endif /* _RK312X_LCDC_H_ */ diff --git a/drivers/video/rockchip/lcdc/rk3188_lcdc.c b/drivers/video/rockchip/lcdc/rk3188_lcdc.c deleted file mode 100755 index b689e9c33752..000000000000 --- a/drivers/video/rockchip/lcdc/rk3188_lcdc.c +++ /dev/null @@ -1,1666 +0,0 @@ -/* - * drivers/video/rockchip/lcdc/rk3188_lcdc.c - * - * Copyright (C) 2013 ROCKCHIP, Inc. - *Author:yxj - *This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "rk3188_lcdc.h" - - -static int dbg_thresd; -module_param(dbg_thresd, int, S_IRUGO | S_IWUSR); - -#define DBG(level, x...) do { \ - if (unlikely(dbg_thresd >= level)) \ - printk(KERN_INFO x); } while (0) - -//#define WAIT_FOR_SYNC 1 - -static int rk3188_lcdc_get_id(u32 phy_base) -{ - if (cpu_is_rk319x()) { - if (phy_base == 0xffc40000) - return 0; - else if (phy_base == 0xffc50000) - return 1; - else - return -EINVAL; - } else if (cpu_is_rk3188()) { - if (phy_base == 0x1010c000) - return 0; - else if (phy_base == 0x1010e000) - return 1; - else - return -EINVAL; - } else if (cpu_is_rk3026()) { - if (phy_base == 0x1010e000) - return 0; - else if (phy_base == 0x01110000) - return 1; - else - return -EINVAL; - } else { - pr_err("un supported platform \n"); - return -EINVAL; - } - -} - -static int rk3188_lcdc_set_lut(struct rk_lcdc_driver *dev_drv) -{ - int i = 0; - int __iomem *c; - int v; - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct - lcdc_device, - driver); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(0)); - lcdc_cfg_done(lcdc_dev); - mdelay(25); - for (i = 0; i < 256; i++) { - v = dev_drv->cur_screen->dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base + i; - writel_relaxed(v, c); - - } - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(1)); - - return 0; - -} - -static int rk3188_lcdc_clk_enable(struct lcdc_device *lcdc_dev) -{ - - if (!lcdc_dev->clk_on) { - clk_prepare_enable(lcdc_dev->hclk); - clk_prepare_enable(lcdc_dev->dclk); - clk_prepare_enable(lcdc_dev->aclk); - //clk_enable(lcdc_dev->pd); - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 1; - spin_unlock(&lcdc_dev->reg_lock); - } - return 0; -} - -static int rk3188_lcdc_clk_disable(struct lcdc_device *lcdc_dev) -{ - if (lcdc_dev->clk_on) { - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 0; - spin_unlock(&lcdc_dev->reg_lock); - mdelay(25); - clk_disable_unprepare(lcdc_dev->dclk); - clk_disable_unprepare(lcdc_dev->hclk); - clk_disable_unprepare(lcdc_dev->aclk); - //clk_disable(lcdc_dev->pd); - } - return 0; -} - -static int rk3188_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, - driver); - int *cbase = (int *)lcdc_dev->regs; - int *regsbak = (int *)lcdc_dev->regsbak; - int i, j; - - printk("back up reg:\n"); - for (i = 0; i <= (0x90 >> 4); i++) { - for (j = 0; j < 4; j++) - printk("%08x ", *(regsbak + i * 4 + j)); - printk("\n"); - } - - printk("lcdc reg:\n"); - for (i = 0; i <= (0x90 >> 4); i++) { - for (j = 0; j < 4; j++) - printk("%08x ", readl_relaxed(cbase + i * 4 + j)); - printk("\n"); - } - return 0; -} - -static void rk3188_lcdc_read_reg_defalut_cfg(struct lcdc_device - *lcdc_dev) -{ - int reg = 0; - u32 value = 0; - struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0]; - struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1]; - - spin_lock(&lcdc_dev->reg_lock); - for (reg = 0; reg < REG_CFG_DONE; reg += 4) { - value = lcdc_readl(lcdc_dev, reg); - switch (reg) { - case SYS_CTRL: - lcdc_dev->standby = (value & m_LCDC_STANDBY) >> 17; - win0->state = (value & m_WIN0_EN) >> 0; - win1->state = (value & m_WIN1_EN) >> 1; - if (lcdc_dev->id == 0) - lcdc_dev->atv_layer_cnt = win0->state; - else - lcdc_dev->atv_layer_cnt = win1->state; - win0->area[0].swap_rb = (value & m_WIN0_RB_SWAP) >> 15; - win1->area[0].swap_rb = (value & m_WIN1_RB_SWAP) >> 19; - win0->area[0].fmt_cfg = (value & m_WIN0_FORMAT) >> 3; - win1->area[0].fmt_cfg = (value & m_WIN1_FORMAT) >> 6; - break; - case WIN0_SCL_FACTOR_YRGB: - win0->scale_yrgb_x = (value >> 0) & 0xffff; - win0->scale_yrgb_y = (value >> 16) & 0xffff; - break; - case WIN0_SCL_FACTOR_CBR: - win0->scale_cbcr_x = (value >> 0) & 0xffff; - win0->scale_cbcr_y = (value >> 16) & 0xffff; - break; - case WIN0_ACT_INFO: - win0->area[0].xact = (((value >> 0) & 0x1fff) + 1); - win0->area[0].yact = (((value >> 16) & 0x1fff) + 1); - break; - case WIN0_DSP_ST: - win0->area[0].dsp_stx = (value >> 0) & 0xfff; - win0->area[0].dsp_sty = (value >> 16) & 0xfff; - break; - case WIN0_DSP_INFO: - win0->area[0].xsize = (((value >> 0) & 0x7ff) + 1); - win0->area[0].ysize = (((value >> 16) & 0x7ff) + 1); - break; - case WIN_VIR: - win0->area[0].y_vir_stride = (value >> 0) & 0x1fff; - win1->area[0].y_vir_stride = (value) & 0x1fff0000; - break; - case WIN0_YRGB_MST0: - win0->area[0].y_addr = value >> 0; - break; - case WIN0_CBR_MST0: - win0->area[0].uv_addr = value >> 0; - break; - case WIN1_DSP_INFO: - win1->area[0].xsize = (((value >> 0) & 0x7ff) + 1); - win1->area[0].ysize = (((value >> 16) & 0x7ff) + 1); - break; - case WIN1_DSP_ST: - win1->area[0].dsp_stx = (value >> 0) & 0xfff; - win1->area[0].dsp_sty = (value >> 16) & 0xfff; - break; - case WIN1_MST: - win1->area[0].y_addr = value >> 0; - break; - default: - DBG(2, "%s:uncare reg\n", __func__); - break; - } - } - spin_unlock(&lcdc_dev->reg_lock); -} - -/********do basic init*********/ -static int rk3188_lcdc_pre_init(struct rk_lcdc_driver *dev_drv) -{ - int v; - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct - lcdc_device, - driver); - - if (lcdc_dev->pre_init) - return 0; - - if (lcdc_dev->id == 0) { - //lcdc_dev->pd = clk_get(NULL,"pd_lcdc0"); - lcdc_dev->hclk = clk_get(NULL, "g_h_lcdc0"); - lcdc_dev->aclk = clk_get(NULL, "aclk_lcdc0"); - lcdc_dev->dclk = clk_get(NULL, "dclk_lcdc0"); - } else if (lcdc_dev->id == 1) { - //lcdc_dev->pd = clk_get(NULL,"pd_lcdc1"); - lcdc_dev->hclk = clk_get(NULL, "g_h_lcdc1"); - lcdc_dev->aclk = clk_get(NULL, "aclk_lcdc1"); - lcdc_dev->dclk = clk_get(NULL, "dclk_lcdc1"); - } else { - dev_err(lcdc_dev->dev, "invalid lcdc device!\n"); - return -EINVAL; - } - if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) || - (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) { - dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n", - lcdc_dev->id); - } - - /*uboot display has enabled lcdc in boot */ - if (!support_uboot_display()) { - rk_disp_pwr_enable(dev_drv); - rk3188_lcdc_clk_enable(lcdc_dev); - } else { - lcdc_dev->clk_on = 1; - } - - rk3188_lcdc_read_reg_defalut_cfg(lcdc_dev); - - if (lcdc_dev->id == 0) { - if (lcdc_dev->pwr18 == true) { - v = 0x40004000; /*bit14: 1,1.8v;0,3.3v*/ - writel_relaxed(v, RK_GRF_VIRT + RK3188_GRF_IO_CON4); - } else { - v = 0x40000000; - writel_relaxed(v, RK_GRF_VIRT + RK3188_GRF_IO_CON4); - } - } - - if (lcdc_dev->id == 1) { - if (lcdc_dev->pwr18 == true) { - v = 0x80008000; /*bit14: 1,1.8v;0,3.3v*/ - writel_relaxed(v, RK_GRF_VIRT + RK3188_GRF_IO_CON4); - } else { - v = 0x80000000; - writel_relaxed(v, RK_GRF_VIRT + RK3188_GRF_IO_CON4); - } - pinctrl_select_state(lcdc_dev->dev->pins->p, - lcdc_dev->dev->pins->default_state); - } - - lcdc_set_bit(lcdc_dev, SYS_CTRL, m_AUTO_GATING_EN); - lcdc_cfg_done(lcdc_dev); - lcdc_dev->pre_init = true; - - return 0; -} - -static void rk3188_lcdc_deint(struct lcdc_device *lcdc_dev) -{ - u32 mask, val; - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_dev->clk_on = 0; - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR, - v_FS_INT_CLEAR(1)); - mask = m_HS_INT_EN | m_FS_INT_EN | m_LF_INT_EN | - m_BUS_ERR_INT_EN; - val = v_HS_INT_EN(0) | v_FS_INT_EN(0) | - v_LF_INT_EN(0) | v_BUS_ERR_INT_EN(0); - lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val); - lcdc_set_bit(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - } - mdelay(1); - -} - -static int rk3188_lcdc_alpha_cfg(struct lcdc_device *lcdc_dev) -{ - int win0_top = 0; - u32 mask, val; - enum data_format win0_format = lcdc_dev->driver.win[0]->area[0].format; - enum data_format win1_format = lcdc_dev->driver.win[1]->area[0].format; - - int win0_alpha_en = ((win0_format == ARGB888) - || (win0_format == ABGR888)) ? 1 : 0; - int win1_alpha_en = ((win1_format == ARGB888) - || (win1_format == ABGR888)) ? 1 : 0; - u32 *_pv = (u32 *) lcdc_dev->regsbak; - _pv += (DSP_CTRL0 >> 2); - win0_top = ((*_pv) & (m_WIN0_TOP)) >> 8; - if (win0_top && (lcdc_dev->atv_layer_cnt >= 2) && (win0_alpha_en)) { - lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, m_WIN0_ALPHA_EN | - m_WIN1_ALPHA_EN, v_WIN0_ALPHA_EN(1) | - v_WIN1_ALPHA_EN(0)); - mask = m_WIN0_ALPHA_MODE | m_ALPHA_MODE_SEL0 | m_ALPHA_MODE_SEL1; - val = v_WIN0_ALPHA_MODE(1) | v_ALPHA_MODE_SEL0(1) | v_ALPHA_MODE_SEL1(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - } else if ((!win0_top) && (lcdc_dev->atv_layer_cnt >= 2) - && (win1_alpha_en)) { - mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN; - val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(1); - lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val); - - mask = m_WIN1_ALPHA_MODE | m_ALPHA_MODE_SEL0 | m_ALPHA_MODE_SEL1; - val = v_WIN1_ALPHA_MODE(1) | v_ALPHA_MODE_SEL0(1) | v_ALPHA_MODE_SEL1(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - } else { - mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN; - val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(0); - lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val); - } - - return 0; -} - -static int rk3188_lcdc_reg_update(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0]; - struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1]; - int timeout; - unsigned long flags; - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY, - v_LCDC_STANDBY(lcdc_dev->standby)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, - m_WIN0_EN | m_WIN1_EN | m_WIN0_RB_SWAP | - m_WIN1_RB_SWAP, - v_WIN0_EN(win0->state) | v_WIN1_EN(win1->state) | - v_WIN0_RB_SWAP(win0->area[0].swap_rb) | - v_WIN1_RB_SWAP(win1->area[0].swap_rb)); - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB, - v_X_SCL_FACTOR(win0->scale_yrgb_x) | - v_Y_SCL_FACTOR(win0->scale_yrgb_y)); - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR, - v_X_SCL_FACTOR(win0->scale_cbcr_x) | - v_Y_SCL_FACTOR(win0->scale_cbcr_y)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_FORMAT, - v_WIN0_FORMAT(win0->area[0].fmt_cfg)); - lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_ACT_WIDTH(win0->area[0].xact) | - v_ACT_HEIGHT(win0->area[0].yact)); - lcdc_writel(lcdc_dev, WIN0_DSP_ST, v_DSP_STX(win0->area[0].dsp_stx) | - v_DSP_STY(win0->area[0].dsp_sty)); - lcdc_writel(lcdc_dev, WIN0_DSP_INFO, v_DSP_WIDTH(win0->area[0].xsize) | - v_DSP_HEIGHT(win0->area[0].ysize)); - lcdc_msk_reg(lcdc_dev, WIN_VIR, m_WIN0_VIR, - v_WIN0_VIR_VAL(win0->area[0].y_vir_stride)); - lcdc_writel(lcdc_dev, WIN0_YRGB_MST0, win0->area[0].y_addr); - lcdc_writel(lcdc_dev, WIN0_CBR_MST0, win0->area[0].uv_addr); - lcdc_writel(lcdc_dev, WIN1_DSP_INFO, v_DSP_WIDTH(win1->area[0].xsize) | - v_DSP_HEIGHT(win1->area[0].ysize)); - lcdc_writel(lcdc_dev, WIN1_DSP_ST, v_DSP_STX(win1->area[0].dsp_stx) | - v_DSP_STY(win1->area[0].dsp_sty)); - lcdc_msk_reg(lcdc_dev, WIN_VIR, m_WIN1_VIR, - ((win1->area[0].y_vir_stride)&0x1fff)<<16); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN1_FORMAT, - v_WIN1_FORMAT(win1->area[0].fmt_cfg)); - lcdc_writel(lcdc_dev, WIN1_MST, win1->area[0].y_addr); - rk3188_lcdc_alpha_cfg(lcdc_dev); - lcdc_cfg_done(lcdc_dev); - - } - spin_unlock(&lcdc_dev->reg_lock); - //if (dev_drv->wait_fs) { - if (0) { - spin_lock_irqsave(&dev_drv->cpl_lock, flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock, flags); - timeout = wait_for_completion_timeout(&dev_drv->frame_done, - msecs_to_jiffies - (dev_drv->cur_screen->ft + - 5)); - if (!timeout && (!dev_drv->frame_done.done)) { - dev_warn(lcdc_dev->dev, "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } - } - DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id); - return 0; - -} - -static int rk3188_lcdc_reg_restore(struct lcdc_device *lcdc_dev) -{ - memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0x84); - return 0; -} - - -static int rk3188_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen) -{ - int ret = -EINVAL; - int fps; - u16 face = 0; - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u16 right_margin = screen->mode.right_margin; - u16 left_margin = screen->mode.left_margin; - u16 lower_margin = screen->mode.lower_margin; - u16 upper_margin = screen->mode.upper_margin; - u16 x_res = screen->mode.xres; - u16 y_res = screen->mode.yres; - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - switch (screen->face) { - case OUT_P565: - face = OUT_P565; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - break; - case OUT_P666: - face = OUT_P666; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - break; - case OUT_D888_P565: - face = OUT_P888; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - break; - case OUT_D888_P666: - face = OUT_P888; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - break; - case OUT_P888: - face = OUT_P888; - mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN; - val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - break; - default: - dev_err(lcdc_dev->dev, "un supported interface!\n"); - break; - } - - mask = m_DSP_OUT_FORMAT | m_HSYNC_POL | m_VSYNC_POL | - m_DEN_POL | m_DCLK_POL; - val = v_DSP_OUT_FORMAT(face) | v_HSYNC_POL(screen->pin_hsync) | - v_VSYNC_POL(screen->pin_vsync) | v_DEN_POL(screen->pin_den) | - v_DCLK_POL(screen->pin_dclk); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - - mask = m_BG_COLOR | m_DSP_BG_SWAP | m_DSP_RB_SWAP | - m_DSP_RG_SWAP | m_DSP_DELTA_SWAP | - m_DSP_DUMMY_SWAP | m_BLANK_EN; - val = v_BG_COLOR(0x000000) | v_DSP_BG_SWAP(screen->swap_gb) | - v_DSP_RB_SWAP(screen->swap_rb) | v_DSP_RG_SWAP(screen-> - swap_rg) | - v_DSP_DELTA_SWAP(screen-> - swap_delta) | v_DSP_DUMMY_SWAP(screen-> - swap_dumy) | - v_BLANK_EN(0) | v_BLACK_EN(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - val = - v_HSYNC(screen->mode.hsync_len) | v_HORPRD(screen->mode. - hsync_len + - left_margin + - x_res + - right_margin); - lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END, val); - val = v_HAEP(screen->mode.hsync_len + left_margin + x_res) | - v_HASP(screen->mode.hsync_len + left_margin); - lcdc_writel(lcdc_dev, DSP_HACT_ST_END, val); - - val = - v_VSYNC(screen->mode.vsync_len) | v_VERPRD(screen->mode. - vsync_len + - upper_margin + - y_res + - lower_margin); - lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, val); - - val = v_VAEP(screen->mode.vsync_len + upper_margin + y_res) | - v_VASP(screen->mode.vsync_len + screen->mode.upper_margin); - lcdc_writel(lcdc_dev, DSP_VACT_ST_END, val); - } - spin_unlock(&lcdc_dev->reg_lock); - - ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock); - if (ret) - dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id); - lcdc_dev->pixclock = - div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - lcdc_dev->driver.pixclock = lcdc_dev->pixclock; - - fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock); - screen->ft = 1000 / fps; - dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ", - lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps); - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - if (screen->init) - screen->init(); - - return 0; -} - -/*enable layer,open:1,enable;0 disable*/ -static int win0_open(struct lcdc_device *lcdc_dev, bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - if (open) { - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "wakeup from standby!\n"); - lcdc_dev->standby = 0; - } - lcdc_dev->atv_layer_cnt++; - } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.win[0]->state = open; - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n"); - lcdc_dev->standby = 1; - } - } - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN, v_WIN0_EN(open)); - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win1_open(struct lcdc_device *lcdc_dev, bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - if (open) { - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "wakeup from standby!\n"); - lcdc_dev->standby = 0; - } - lcdc_dev->atv_layer_cnt++; - } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.win[1]->state = open; - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN1_EN, v_WIN1_EN(open)); - /*if no layer used,disable lcdc*/ - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n"); - lcdc_dev->standby = 1; - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int rk3188_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id, - bool open) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - - /*enable clk,when first layer open */ - if ((open) && (!lcdc_dev->atv_layer_cnt)) { - rk3188_lcdc_pre_init(dev_drv); - rk3188_lcdc_clk_enable(lcdc_dev); - rk3188_lcdc_reg_restore(lcdc_dev); - rk3188_load_screen(dev_drv, 1); - spin_lock(&lcdc_dev->reg_lock); - if (dev_drv->cur_screen->dsp_lut) - rk3188_lcdc_set_lut(dev_drv); - spin_unlock(&lcdc_dev->reg_lock); - } - - if (win_id == 0) - win0_open(lcdc_dev, open); - else if (win_id == 1) - win1_open(lcdc_dev, open); - else - dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id); - - /*when all layer closed,disable clk */ - if ((!open) && (!lcdc_dev->atv_layer_cnt)) { - lcdc_msk_reg(lcdc_dev, INT_STATUS, - m_FS_INT_CLEAR, v_FS_INT_CLEAR(1)); - rk3188_lcdc_reg_update(dev_drv); - rk3188_lcdc_clk_disable(lcdc_dev); - } - - return 0; -} - -static int win0_display(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 y_addr; - u32 uv_addr; - y_addr = win->area[0].smem_start+win->area[0].y_offset; - uv_addr = win->area[0].cbr_start + win->area[0].c_offset; - DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n", - lcdc_dev->id, __func__, y_addr, uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_writel(lcdc_dev, WIN0_YRGB_MST0, y_addr); - lcdc_writel(lcdc_dev, WIN0_CBR_MST0, uv_addr); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_display(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 y_addr; - u32 uv_addr; - y_addr = win->area[0].smem_start + win->area[0].y_offset; - uv_addr = win->area[0].cbr_start + win->area[0].c_offset; - DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n", - lcdc_dev->id, __func__, y_addr, uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) - lcdc_writel(lcdc_dev,WIN1_MST,y_addr); - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - - -static int rk3188_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct rk_lcdc_win *win = NULL; - struct rk_screen *screen = dev_drv->cur_screen; - u32 msk, val; -#if defined(WAIT_FOR_SYNC) - int timeout; - unsigned long flags; -#endif - - if (!screen) { - dev_err(dev_drv->dev,"screen is null!\n"); - return -ENOENT; - } - - if (win_id == 0) { - win = dev_drv->win[0]; - win0_display(lcdc_dev, win); - } else if(win_id==1) { - win = dev_drv->win[1]; - win1_display(lcdc_dev, win); - } else { - dev_err(dev_drv->dev,"invalid win number:%d!\n", win_id); - return -EINVAL; - } - - /*this is the first frame of the system ,enable frame start interrupt*/ - if ((dev_drv->first_frame)) { - dev_drv->first_frame = 0; - msk = m_FS_INT_CLEAR |m_FS_INT_EN; - val = v_FS_INT_CLEAR(1) | v_FS_INT_EN(1); - lcdc_msk_reg(lcdc_dev, INT_STATUS, msk, val); - - } - -#if defined(WAIT_FOR_SYNC) - spin_lock_irqsave(&dev_drv->cpl_lock, flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock, flags); - timeout = wait_for_completion_timeout(&dev_drv->frame_done, - msecs_to_jiffies(dev_drv->cur_screen->ft +5)); - if (!timeout && (!dev_drv->frame_done.done)) { - dev_info(dev_drv->dev, "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } -#endif - - return 0; -} - - -static int win0_set_par(struct lcdc_device *lcdc_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u32 ScaleYrgbX = 0x1000; - u32 ScaleYrgbY = 0x1000; - u32 ScaleCbrX = 0x1000; - u32 ScaleCbrY = 0x1000; - u8 fmt_cfg = 0; - char fmt[9] = "NULL"; - xact = win->area[0].xact; - yact = win->area[0].yact; - xvir = win->area[0].xvir; - yvir = win->area[0].yvir; - xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len; - ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len; - - ScaleYrgbX = CalScale(xact, win->area[0].xsize); - ScaleYrgbY = CalScale(yact, win->area[0].ysize); - switch (win->area[0].format) { - case ARGB888: - case XBGR888: - case ABGR888: - fmt_cfg = 0; - break; - case RGB888: - fmt_cfg = 1; - break; - case RGB565: - fmt_cfg = 2; - break; - case YUV422: - fmt_cfg = 5; - ScaleCbrX = CalScale((xact / 2), win->area[0].xsize); - ScaleCbrY = CalScale(yact, win->area[0].ysize); - break; - case YUV420: - fmt_cfg = 4; - ScaleCbrX = CalScale(xact / 2, win->area[0].xsize); - ScaleCbrY = CalScale(yact / 2, win->area[0].ysize); - break; - case YUV444: - fmt_cfg = 6; - ScaleCbrX = CalScale(xact, win->area[0].xsize); - ScaleCbrY = CalScale(yact, win->area[0].ysize); - break; - default: - dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n", - __func__); - break; - } - - DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n" - ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, - __func__, get_format_string(win->area[0].format, fmt), xact, - yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos); - - spin_lock(&lcdc_dev->reg_lock); - - win->scale_yrgb_x = ScaleYrgbX; - win->scale_yrgb_y = ScaleYrgbY; - win->scale_cbcr_x = ScaleCbrX; - win->scale_cbcr_y = ScaleCbrY; - win->area[0].fmt_cfg = fmt_cfg; - win->area[0].dsp_stx = xpos; - win->area[0].dsp_sty = ypos; - - switch (win->area[0].format) { - case XBGR888: - case ABGR888: - win->area[0].swap_rb = 1; - break; - case ARGB888: - win->area[0].swap_rb = 0; - break; - case RGB888: - win->area[0].swap_rb = 0; - break; - case RGB565: - win->area[0].swap_rb = 0; - break; - case YUV422: - case YUV420: - case YUV444: - win->area[0].swap_rb = 0; - break; - default: - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", __func__); - break; - } - - - if (likely(lcdc_dev->clk_on)) { - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB,v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY)); - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX) | v_Y_SCL_FACTOR(ScaleCbrY)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL,m_WIN0_FORMAT,v_WIN0_FORMAT(fmt_cfg)); - lcdc_writel(lcdc_dev, WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact)); - lcdc_writel(lcdc_dev, WIN0_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos)); - lcdc_writel(lcdc_dev, WIN0_DSP_INFO,v_DSP_WIDTH(win->area[0].xsize) | - v_DSP_HEIGHT(win->area[0].ysize)); - lcdc_msk_reg(lcdc_dev, WIN_VIR, m_WIN0_VIR, v_WIN0_VIR_VAL(win->area[0].y_vir_stride)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN | m_WIN0_RB_SWAP, - v_WIN0_EN(win->state) | - v_WIN0_RB_SWAP(win->area[0].swap_rb)); - lcdc_msk_reg(lcdc_dev, WIN0_COLOR_KEY, m_COLOR_KEY_EN, v_COLOR_KEY_EN(0)); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_set_par(struct lcdc_device *lcdc_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u8 fmt_cfg; - char fmt[9] = "NULL"; - xact = win->area[0].xact; - yact = win->area[0].yact; - xvir = win->area[0].xvir; - yvir = win->area[0].yvir; - xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len; - ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len; - - DBG(1, "lcdc%d>>%s>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n" - ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, - __func__, get_format_string(win->area[0].format, fmt), - xact, yact, win->area[0].xsize, win->area[0].ysize, - xvir, yvir, xpos, ypos); - - spin_lock(&lcdc_dev->reg_lock); - win->area[0].dsp_stx = xpos; - win->area[0].dsp_sty = ypos; - switch (win->area[0].format) { - case XBGR888: - case ABGR888: - fmt_cfg = 0; - win->area[0].swap_rb = 1; - break; - case ARGB888: - fmt_cfg = 0; - win->area[0].swap_rb = 0; - - break; - case RGB888: - fmt_cfg = 1; - win->area[0].swap_rb = 0; - break; - case RGB565: - fmt_cfg = 2; - win->area[0].swap_rb = 0; - break; - default: - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", __func__); - break; - } - win->area[0].fmt_cfg = fmt_cfg; - if (likely(lcdc_dev->clk_on)) { - lcdc_writel(lcdc_dev, WIN1_DSP_INFO,v_DSP_WIDTH(win->area[0].xsize) | - v_DSP_HEIGHT(win->area[0].ysize)); - lcdc_writel(lcdc_dev, WIN1_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN1_EN | m_WIN1_RB_SWAP, - v_WIN1_EN(win->state) | - v_WIN1_RB_SWAP(win->area[0].swap_rb)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL,m_WIN1_FORMAT, v_WIN1_FORMAT(fmt_cfg)); - lcdc_msk_reg(lcdc_dev, WIN_VIR, m_WIN1_VIR, - ((win->area[0].y_vir_stride)&0x1fff)<<16); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int rk3188_lcdc_set_par(struct rk_lcdc_driver *dev_drv,int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct rk_lcdc_win *win = NULL; - struct rk_screen *screen = dev_drv->cur_screen; - - if (!screen) { - dev_err(dev_drv->dev, "screen is null!\n"); - return -ENOENT; - } - - if (win_id == 0) { - win = dev_drv->win[0]; - win0_set_par(lcdc_dev, screen, win); - } else if (win_id == 1) { - win = dev_drv->win[1]; - win1_set_par(lcdc_dev, screen, win); - } else { - dev_err(dev_drv->dev, "un supported win number:%d\n", win_id); - return -EINVAL; - } - - if (lcdc_dev->clk_on) { - rk3188_lcdc_alpha_cfg(lcdc_dev); - } - - return 0; -} - - - -static int rk3188_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd, - unsigned long arg, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - u32 panel_size[2]; - void __user *argp = (void __user *)arg; - struct color_key_cfg clr_key_cfg; - - switch (cmd) { - case RK_FBIOGET_PANEL_SIZE: - panel_size[0] = lcdc_dev->screen->mode.xres; - panel_size[1] = lcdc_dev->screen->mode.yres; - if (copy_to_user(argp, panel_size, 8)) - return -EFAULT; - break; - case RK_FBIOPUT_COLOR_KEY_CFG: - if (copy_from_user(&clr_key_cfg, argp, - sizeof(struct color_key_cfg))) - return -EFAULT; - lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, - clr_key_cfg.win0_color_key_cfg); - lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, - clr_key_cfg.win1_color_key_cfg); - break; - - default: - break; - } - return 0; -} - -static int rk3188_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv) -{ - - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - if (dev_drv->suspend_flag) - return 0; - dev_drv->suspend_flag = 1; - flush_kthread_worker(&dev_drv->update_regs_worker); - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable) - dev_drv->trsm_ops->disable(); - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, - v_BLANK_EN(1)); - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR, - v_FS_INT_CLEAR(1)); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO, - v_DSP_OUT_ZERO(1)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY, - v_LCDC_STANDBY(1)); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - rk3188_lcdc_clk_disable(lcdc_dev); - rk_disp_pwr_disable(dev_drv); - return 0; -} - -static int rk3188_lcdc_early_resume(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int i = 0; - int __iomem *c; - int v; - - if (!dev_drv->suspend_flag) - return 0; - rk_disp_pwr_enable(dev_drv); - dev_drv->suspend_flag = 0; - - if (lcdc_dev->atv_layer_cnt) { - rk3188_lcdc_clk_enable(lcdc_dev); - rk3188_lcdc_reg_restore(lcdc_dev); - - spin_lock(&lcdc_dev->reg_lock); - if (dev_drv->cur_screen->dsp_lut) { - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, - v_DSP_LUT_EN(0)); - lcdc_cfg_done(lcdc_dev); - mdelay(25); - for (i = 0; i < 256; i++) { - v = dev_drv->cur_screen->dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base + i; - writel_relaxed(v, c); - } - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, - v_DSP_LUT_EN(1)); - } - - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO, - v_DSP_OUT_ZERO(0)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY, - v_LCDC_STANDBY(0)); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, - v_BLANK_EN(0)); - lcdc_cfg_done(lcdc_dev); - - spin_unlock(&lcdc_dev->reg_lock); - } - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - return 0; -} - - -static int rk3188_lcdc_blank(struct rk_lcdc_driver *dev_drv, - int win_id, int blank_mode) -{ - switch (blank_mode) { - case FB_BLANK_UNBLANK: - rk3188_lcdc_early_resume(dev_drv); - break; - case FB_BLANK_NORMAL: - rk3188_lcdc_early_suspend(dev_drv); - break; - default: - rk3188_lcdc_early_suspend(dev_drv); - break; - } - - dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode); - - return 0; -} - -static int rk3188_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, - int win_id, - int area_id) -{ - return 0; -} - -static int rk3188_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, - bool set) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int ovl; - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - if (set) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_TOP, - v_WIN0_TOP(swap)); - ovl = swap; - } else { - ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP); - } - } else { - ovl = -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - - return ovl; -} - -static ssize_t rk3188_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv, - char *buf, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct - lcdc_device, - driver); - - char format_w0[9] = "NULL"; - char format_w1[9] = "NULL"; - char status_w0[9] = "NULL"; - char status_w1[9] = "NULL"; - u32 fmt_id, act_info, dsp_info, dsp_st, factor; - u16 xvir_w0, x_act_w0, y_act_w0, x_dsp_w0, y_dsp_w0; - u16 x_st_w0, y_st_w0, x_factor, y_factor; - u16 xvir_w1, x_dsp_w1, y_dsp_w1, x_st_w1, y_st_w1; - u16 x_scale, y_scale, ovl; - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - fmt_id = lcdc_readl(lcdc_dev, SYS_CTRL); - ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP); - switch ((fmt_id & m_WIN0_FORMAT) >> 3) { - case 0: - strcpy(format_w0, "ARGB888"); - break; - case 1: - strcpy(format_w0, "RGB888"); - break; - case 2: - strcpy(format_w0, "RGB565"); - break; - case 4: - strcpy(format_w0, "YCbCr420"); - break; - case 5: - strcpy(format_w0, "YCbCr422"); - break; - case 6: - strcpy(format_w0, "YCbCr444"); - break; - default: - strcpy(format_w0, "invalid\n"); - break; - } - - switch ((fmt_id & m_WIN1_FORMAT) >> 6) { - case 0: - strcpy(format_w1, "ARGB888"); - break; - case 1: - strcpy(format_w1, "RGB888"); - break; - case 2: - strcpy(format_w1, "RGB565"); - break; - case 4: - strcpy(format_w1, "8bpp"); - break; - case 5: - strcpy(format_w1, "4bpp"); - break; - case 6: - strcpy(format_w1, "2bpp"); - break; - case 7: - strcpy(format_w1, "1bpp"); - break; - default: - strcpy(format_w1, "invalid\n"); - break; - } - - if (fmt_id & m_WIN0_EN) - strcpy(status_w0, "enabled"); - else - strcpy(status_w0, "disabled"); - - if ((fmt_id & m_WIN1_EN) >> 1) - strcpy(status_w1, "enabled"); - else - strcpy(status_w1, "disabled"); - - xvir_w0 = lcdc_readl(lcdc_dev, WIN_VIR) & 0x1fff; - act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO); - dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO); - dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST); - factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB); - x_act_w0 = (act_info & 0x1fff) + 1; - y_act_w0 = ((act_info >> 16) & 0x1fff) + 1; - x_dsp_w0 = (dsp_info & 0x7ff) + 1; - y_dsp_w0 = ((dsp_info >> 16) & 0x7ff) + 1; - x_st_w0 = dsp_st & 0xffff; - y_st_w0 = dsp_st >> 16; - x_factor = factor & 0xffff; - y_factor = factor >> 16; - x_scale = 4096 * 100 / x_factor; - y_scale = 4096 * 100 / y_factor; - xvir_w1 = (lcdc_readl(lcdc_dev, WIN_VIR) >> 16) & 0x1fff; - dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO); - dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST); - x_dsp_w1 = (dsp_info & 0x7ff) + 1; - y_dsp_w1 = ((dsp_info >> 16) & 0x7ff) + 1; - x_st_w1 = dsp_st & 0xffff; - y_st_w1 = dsp_st >> 16; - } else { - spin_unlock(&lcdc_dev->reg_lock); - return -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - return snprintf(buf, PAGE_SIZE, - "win0:%s\n" - "xvir:%d\n" - "xact:%d\n" - "yact:%d\n" - "xdsp:%d\n" - "ydsp:%d\n" - "x_st:%d\n" - "y_st:%d\n" - "x_scale:%d.%d\n" - "y_scale:%d.%d\n" - "format:%s\n" - "YRGB buffer addr:0x%08x\n" - "CBR buffer addr:0x%08x\n\n" - "win1:%s\n" - "xvir:%d\n" - "xdsp:%d\n" - "ydsp:%d\n" - "x_st:%d\n" - "y_st:%d\n" - "format:%s\n" - "YRGB buffer addr:0x%08x\n" - "overlay:%s\n", - status_w0, - xvir_w0, - x_act_w0, - y_act_w0, - x_dsp_w0, - y_dsp_w0, - x_st_w0, - y_st_w0, - x_scale / 100, - x_scale % 100, - y_scale / 100, - y_scale % 100, - format_w0, - lcdc_readl(lcdc_dev, WIN0_YRGB_MST0), - lcdc_readl(lcdc_dev, WIN0_CBR_MST0), - status_w1, - xvir_w1, - x_dsp_w1, - y_dsp_w1, - x_st_w1, - y_st_w1, - format_w1, - lcdc_readl(lcdc_dev, WIN1_MST), - ovl ? "win0 on the top of win1\n" : - "win1 on the top of win0\n"); -} - -static int rk3188_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, - bool set) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u64 ft = 0; - u32 dotclk; - int ret; - u32 pixclock; - u32 x_total, y_total; - if (set) { - ft = div_u64(1000000000000llu, fps); - x_total = - screen->mode.upper_margin + screen->mode.lower_margin + - screen->mode.yres + screen->mode.vsync_len; - y_total = - screen->mode.left_margin + screen->mode.right_margin + - screen->mode.xres + screen->mode.hsync_len; - dev_drv->pixclock = div_u64(ft, x_total * y_total); - dotclk = div_u64(1000000000000llu, dev_drv->pixclock); - ret = clk_set_rate(lcdc_dev->dclk, dotclk); - } - - pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - dev_drv->pixclock = lcdc_dev->pixclock = pixclock; - fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock); - screen->ft = 1000 / fps; /*one frame time in ms */ - - if (set) - dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__, - clk_get_rate(lcdc_dev->dclk), fps); - - return fps; -} - -static int rk3188_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order) -{ - mutex_lock(&dev_drv->fb_win_id_mutex); - if (order == FB_DEFAULT_ORDER) - order = FB0_WIN0_FB1_WIN1_FB2_WIN2; - dev_drv->fb2_win_id = order / 100; - dev_drv->fb1_win_id = (order / 10) % 10; - dev_drv->fb0_win_id = order % 10; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return 0; -} - -static int rk3188_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv, - const char *id) -{ - int win_id = 0; - mutex_lock(&dev_drv->fb_win_id_mutex); - if (!strcmp(id, "fb0") || !strcmp(id, "fb2")) - win_id = dev_drv->fb0_win_id; - else if (!strcmp(id, "fb1") || !strcmp(id, "fb3")) - win_id = dev_drv->fb1_win_id; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return win_id; -} - -static int rk3188_set_dsp_lut(struct rk_lcdc_driver *dev_drv, int *lut) -{ - int i = 0; - int __iomem *c; - int v; - int ret = 0; - - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(0)); - lcdc_cfg_done(lcdc_dev); - msleep(25); - if (dev_drv->cur_screen->dsp_lut) { - for (i = 0; i < 256; i++) { - v = dev_drv->cur_screen->dsp_lut[i] = lut[i]; - c = lcdc_dev->dsp_lut_addr_base + i; - writel_relaxed(v, c); - - } - } else { - dev_err(dev_drv->dev, "no buffer to backup lut data!\n"); - ret = -1; - } - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(1)); - lcdc_cfg_done(lcdc_dev); - - return ret; -} - -static int rk3188_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_EN, - v_DIRECT_PATCH_EN(open)); - lcdc_cfg_done(lcdc_dev); - return 0; -} - -static int rk3188_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_LAY_SEL, - v_DIRECT_PATH_LAY_SEL(win_id)); - lcdc_cfg_done(lcdc_dev); - return 0; - -} - -static int rk3188_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_EN); - return ovl; -} - -int rk3188_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 int_reg; - int ret; - - if (lcdc_dev->clk_on) { - int_reg = lcdc_readl(lcdc_dev, INT_STATUS); - if (int_reg & m_LF_INT_STA) { - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR, - v_LF_INT_CLEAR(1)); - ret = RK_LF_STATUS_FC; - } else - ret = RK_LF_STATUS_FR; - } else { - ret = RK_LF_STATUS_NC; - } - - return ret; -} - - -static int rk3188_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,unsigned int dsp_addr[][4]) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if(lcdc_dev->clk_on){ - dsp_addr[0][0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST0); - dsp_addr[1][0] = lcdc_readl(lcdc_dev, WIN1_MST); - } - return 0; -} - -static int rk3188_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - - -static struct rk_lcdc_win lcdc_win[] = { - [0] = { - .name = "win0", - .id = 0, - .support_3d = true, - }, - [1] = { - .name = "win1", - .id = 1, - .support_3d = false, - }, -}; - -static struct rk_lcdc_drv_ops lcdc_drv_ops = { - .open = rk3188_lcdc_open, - .load_screen = rk3188_load_screen, - .set_par = rk3188_lcdc_set_par, - .pan_display = rk3188_lcdc_pan_display, - .blank = rk3188_lcdc_blank, - .ioctl = rk3188_lcdc_ioctl, - .get_win_state = rk3188_lcdc_get_win_state, - .ovl_mgr = rk3188_lcdc_ovl_mgr, - .get_disp_info = rk3188_lcdc_get_disp_info, - .fps_mgr = rk3188_lcdc_fps_mgr, - .fb_get_win_id = rk3188_lcdc_get_win_id, - .fb_win_remap = rk3188_fb_win_remap, - .set_dsp_lut = rk3188_set_dsp_lut, - .poll_vblank = rk3188_lcdc_poll_vblank, - .dpi_open = rk3188_lcdc_dpi_open, - .dpi_win_sel = rk3188_lcdc_dpi_win_sel, - .dpi_status = rk3188_lcdc_dpi_status, - .get_dsp_addr = rk3188_lcdc_get_dsp_addr, - .cfg_done = rk3188_lcdc_cfg_done, - .dump_reg = rk3188_lcdc_reg_dump, -}; - -static irqreturn_t rk3188_lcdc_isr(int irq, void *dev_id) -{ - struct lcdc_device *lcdc_dev = - (struct lcdc_device *)dev_id; - ktime_t timestamp = ktime_get(); - u32 int_reg = lcdc_readl(lcdc_dev, INT_STATUS); - - if (int_reg & m_FS_INT_STA) { - timestamp = ktime_get(); - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR, - v_FS_INT_CLEAR(1)); - //if (lcdc_dev->driver.wait_fs) { - if (0) { - spin_lock(&(lcdc_dev->driver.cpl_lock)); - complete(&(lcdc_dev->driver.frame_done)); - spin_unlock(&(lcdc_dev->driver.cpl_lock)); - } - lcdc_dev->driver.vsync_info.timestamp = timestamp; - wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait); - - } else if (int_reg & m_LF_INT_STA) { - lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR, - v_LF_INT_CLEAR(1)); - } - return IRQ_HANDLED; -} - -#if defined(CONFIG_PM) -static int rk3188_lcdc_suspend(struct platform_device *pdev, pm_message_t state) -{ - return 0; -} - -static int rk3188_lcdc_resume(struct platform_device *pdev) -{ - return 0; -} -#else -#define rk3188_lcdc_suspend NULL -#define rk3188_lcdc_resume NULL -#endif - -static int rk3188_lcdc_parse_dt(struct lcdc_device *lcdc_dev) -{ - struct device_node *np = lcdc_dev->dev->of_node; - int val; - if (of_property_read_u32(np, "rockchip,prop", &val)) - lcdc_dev->prop = PRMRY; /*default set it as primary */ - else - lcdc_dev->prop = val; - - if (of_property_read_u32(np, "rockchip,pwr18", &val)) - lcdc_dev->pwr18 = false; /*default set it as 3.xv power supply */ - else - lcdc_dev->pwr18 = (val ? true : false); - - if (of_property_read_u32(np, "rockchip,fb-win-map", &val)) - lcdc_dev->driver.fb_win_map = FB_DEFAULT_ORDER; - else - lcdc_dev->driver.fb_win_map = val; - - return 0; -} - -static int rk3188_lcdc_probe(struct platform_device *pdev) -{ - struct lcdc_device *lcdc_dev = NULL; - struct rk_lcdc_driver *dev_drv; - struct device *dev = &pdev->dev; - struct resource *res; - struct device_node *np = pdev->dev.of_node; - int prop; - int ret = 0; - - /*if the primary lcdc has not registered ,the extend - lcdc register later */ - of_property_read_u32(np, "rockchip,prop", &prop); - if (prop == EXTEND) { - if (!is_prmry_rk_lcdc_registered()) - return -EPROBE_DEFER; - } - lcdc_dev = devm_kzalloc(dev, - sizeof(struct lcdc_device), GFP_KERNEL); - if (!lcdc_dev) { - dev_err(&pdev->dev, "rk3188 lcdc device kmalloc fail!"); - return -ENOMEM; - } - platform_set_drvdata(pdev, lcdc_dev); - lcdc_dev->dev = dev; - rk3188_lcdc_parse_dt(lcdc_dev); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - lcdc_dev->reg_phy_base = res->start; - lcdc_dev->len = resource_size(res); - lcdc_dev->regs = devm_ioremap_resource(dev, res); - if (IS_ERR(lcdc_dev->regs)) - return PTR_ERR(lcdc_dev->regs); - - lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL); - if (IS_ERR(lcdc_dev->regsbak)) - return PTR_ERR(lcdc_dev->regsbak); - lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + DSP_LUT_ADDR); - lcdc_dev->id = rk3188_lcdc_get_id(lcdc_dev->reg_phy_base); - if (lcdc_dev->id < 0) { - dev_err(&pdev->dev, "no such lcdc device!\n"); - return -ENXIO; - } - dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id); - dev_drv = &lcdc_dev->driver; - dev_drv->dev = dev; - dev_drv->prop = prop; - dev_drv->id = lcdc_dev->id; - dev_drv->ops = &lcdc_drv_ops; - dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win); - spin_lock_init(&lcdc_dev->reg_lock); - - lcdc_dev->irq = platform_get_irq(pdev, 0); - if (lcdc_dev->irq < 0) { - dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n", - lcdc_dev->id); - return -ENXIO; - } - - ret = devm_request_irq(dev, lcdc_dev->irq, rk3188_lcdc_isr, - IRQF_DISABLED, dev_name(dev), lcdc_dev); - if (ret) { - dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", - lcdc_dev->irq, ret); - return ret; - } - - ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id); - if (ret < 0) { - dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id); - return ret; - } - lcdc_dev->screen = dev_drv->screen0; - - dev_info(dev, "lcdc%d probe ok\n", lcdc_dev->id); - - return 0; -} - -static int rk3188_lcdc_remove(struct platform_device *pdev) -{ - - return 0; -} - -static void rk3188_lcdc_shutdown(struct platform_device *pdev) -{ - struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - - rk3188_lcdc_deint(lcdc_dev); - rk_disp_pwr_disable(&lcdc_dev->driver); -} - -#if defined(CONFIG_OF) -static const struct of_device_id rk3188_lcdc_dt_ids[] = { - {.compatible = "rockchip,rk3188-lcdc",}, - {} -}; -#endif - -static struct platform_driver rk3188_lcdc_driver = { - .probe = rk3188_lcdc_probe, - .remove = rk3188_lcdc_remove, - .driver = { - .name = "rk3188-lcdc", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(rk3188_lcdc_dt_ids), - }, - .suspend = rk3188_lcdc_suspend, - .resume = rk3188_lcdc_resume, - .shutdown = rk3188_lcdc_shutdown, -}; - -static int __init rk3188_lcdc_module_init(void) -{ - return platform_driver_register(&rk3188_lcdc_driver); -} - -static void __exit rk3188_lcdc_module_exit(void) -{ - platform_driver_unregister(&rk3188_lcdc_driver); -} - -fs_initcall(rk3188_lcdc_module_init); -module_exit(rk3188_lcdc_module_exit); diff --git a/drivers/video/rockchip/lcdc/rk3188_lcdc.h b/drivers/video/rockchip/lcdc/rk3188_lcdc.h deleted file mode 100644 index 3e199e5f71ce..000000000000 --- a/drivers/video/rockchip/lcdc/rk3188_lcdc.h +++ /dev/null @@ -1,413 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef RK3188_LCDC_H_ -#define RK3188_LCDC_H_ - -#include -#include -#include - - -/*******************register definition**********************/ - -#define SYS_CTRL (0x00) -#define m_WIN0_EN (1<<0) -#define m_WIN1_EN (1<<1) -#define m_HWC_EN (1<<2) -#define m_WIN0_FORMAT (7<<3) -#define m_WIN1_FORMAT (7<<6) -#define m_HWC_COLOR_MODE (1<<9) -#define m_HWC_SIZE (1<<10) -#define m_WIN0_3D_EN (1<<11) -#define m_WIN0_3D_MODE (7<<12) -#define m_WIN0_RB_SWAP (1<<15) -#define m_WIN0_ALPHA_SWAP (1<<16) -#define m_WIN0_Y8_SWAP (1<<17) -#define m_WIN0_UV_SWAP (1<<18) -#define m_WIN1_RB_SWAP (1<<19) -#define m_WIN1_ALPHA_SWAP (1<<20) -#define m_WIN1_BL_SWAP (1<<21) -#define m_WIN0_OTSD_DISABLE (1<<22) -#define m_WIN1_OTSD_DISABLE (1<<23) -#define m_DMA_BURST_LENGTH (3<<24) -#define m_HWC_LODAD_EN (1<<26) -#define m_WIN1_LUT_EN (1<<27) -#define m_DSP_LUT_EN (1<<28) -#define m_DMA_STOP (1<<29) -#define m_LCDC_STANDBY (1<<30) -#define m_AUTO_GATING_EN (1<<31) -#define v_WIN0_EN(x) (((x)&1)<<0) -#define v_WIN1_EN(x) (((x)&1)<<1) -#define v_HWC_EN(x) (((x)&1)<<2) -#define v_WIN0_FORMAT(x) (((x)&7)<<3) -#define v_WIN1_FORMAT(x) (((x)&7)<<6) -#define v_HWC_COLOR_MODE(x) (((x)&1)<<9) -#define v_HWC_SIZE(x) (((x)&1)<<10) -#define v_WIN0_3D_EN(x) (((x)&1)<<11) -#define v_WIN0_3D_MODE(x) (((x)&7)<<12) -#define v_WIN0_RB_SWAP(x) (((x)&1)<<15) -#define v_WIN0_ALPHA_SWAP(x) (((x)&1)<<16) -#define v_WIN0_Y8_SWAP(x) (((x)&1)<<17) -#define v_WIN0_UV_SWAP(x) (((x)&1)<<18) -#define v_WIN1_RB_SWAP(x) (((x)&1)<<19) -#define v_WIN1_ALPHA_SWAP(x) (((x)&1)<<20) -#define v_WIN1_BL_SWAP(x) (((x)&1)<<21) -#define v_WIN0_OTSD_DISABLE(x) (((x)&1)<<22) -#define v_WIN1_OTSD_DISABLE(x) (((x)&1)<<23) -#define v_DMA_BURST_LENGTH(x) (((x)&3)<<24) -#define v_HWC_LODAD_EN(x) (((x)&1)<<26) -#define v_WIN1_LUT_EN(x) (((x)&1)<<27) -#define v_DSP_LUT_EN(x) (((x)&1)<<28) -#define v_DMA_STOP(x) (((x)&1)<<29) -#define v_LCDC_STANDBY(x) (((x)&1)<<30) -#define v_AUTO_GATING_EN(x) (((x)&1)<<31) - - -#define DSP_CTRL0 (0x04) -#define m_DSP_OUT_FORMAT (0x0f<<0) -#define m_HSYNC_POL (1<<4) -#define m_VSYNC_POL (1<<5) -#define m_DEN_POL (1<<6) -#define m_DCLK_POL (1<<7) -#define m_WIN0_TOP (1<<8) -#define m_DITHER_UP_EN (1<<9) -#define m_DITHER_DOWN_MODE (1<<10) -#define m_DITHER_DOWN_EN (1<<11) -#define m_INTERLACE_DSP_EN (1<<12) -#define m_INTERLACE_POL (1<<13) -#define m_WIN0_INTERLACE_EN (1<<14) -#define m_WIN1_INTERLACE_EN (1<<15) -#define m_WIN0_YRGB_DEFLICK_EN (1<<16) -#define m_WIN0_CBR_DEFLICK_EN (1<<17) -#define m_WIN0_ALPHA_MODE (1<<18) -#define m_WIN1_ALPHA_MODE (1<<19) -#define m_WIN0_CSC_MODE (3<<20) -#define m_WIN1_CSC_MODE (1<<22) -#define m_WIN0_YUV_CLIP (1<<23) -#define m_DSP_CCIR656_AVG (1<<24) -#define m_DCLK_OUTPUT_MODE (1<<25) -#define m_DCLK_PHASE_LOCK (1<<26) -#define m_DITHER_DOWN_SEL (3<<27) -#define m_ALPHA_MODE_SEL0 (1<<29) -#define m_ALPHA_MODE_SEL1 (1<<30) -#define m_DIFF_DCLK_EN (1<<31) -#define v_DSP_OUT_FORMAT(x) (((x)&0x0f)<<0) -#define v_HSYNC_POL(x) (((x)&1)<<4) -#define v_VSYNC_POL(x) (((x)&1)<<5) -#define v_DEN_POL(x) (((x)&1)<<6) -#define v_DCLK_POL(x) (((x)&1)<<7) -#define v_WIN0_TOP(x) (((x)&1)<<8) -#define v_DITHER_UP_EN(x) (((x)&1)<<9) -#define v_DITHER_DOWN_MODE(x) (((x)&1)<<10) -#define v_DITHER_DOWN_EN(x) (((x)&1)<<11) -#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12) -#define v_INTERLACE_POL(x) (((x)&1)<<13) -#define v_WIN0_INTERLACE_EN(x) (((x)&1)<<14) -#define v_WIN1_INTERLACE_EN(x) (((x)&1)<<15) -#define v_WIN0_YRGB_DEFLICK_EN(x) (((x)&1)<<16) -#define v_WIN0_CBR_DEFLICK_EN(x) (((x)&1)<<17) -#define v_WIN0_ALPHA_MODE(x) (((x)&1)<<18) -#define v_WIN1_ALPHA_MODE(x) (((x)&1)<<19) -#define v_WIN0_CSC_MODE(x) (((x)&3)<<20) -#define v_WIN1_CSC_MODE(x) (((x)&1)<<22) -#define v_WIN0_YUV_CLIP(x) (((x)&1)<<23) -#define v_DSP_CCIR656_AVG(x) (((x)&1)<<24) -#define v_DCLK_OUTPUT_MODE(x) (((x)&1)<<25) -#define v_DCLK_PHASE_LOCK(x) (((x)&1)<<26) -#define v_DITHER_DOWN_SEL(x) (((x)&1)<<27) -#define v_ALPHA_MODE_SEL0(x) (((x)&1)<<29) -#define v_ALPHA_MODE_SEL1(x) (((x)&1)<<30) -#define v_DIFF_DCLK_EN(x) (((x)&1)<<31) - - -#define DSP_CTRL1 (0x08) -#define m_BG_COLOR (0xffffff<<0) -#define m_BG_B (0xff<<0) -#define m_BG_G (0xff<<8) -#define m_BG_R (0xff<<16) -#define m_BLANK_EN (1<<24) -#define m_BLACK_EN (1<<25) -#define m_DSP_BG_SWAP (1<<26) -#define m_DSP_RB_SWAP (1<<27) -#define m_DSP_RG_SWAP (1<<28) -#define m_DSP_DELTA_SWAP (1<<29) -#define m_DSP_DUMMY_SWAP (1<<30) -#define m_DSP_OUT_ZERO (1<<31) -#define v_BG_COLOR(x) (((x)&0xffffff)<<0) -#define v_BG_B(x) (((x)&0xff)<<0) -#define v_BG_G(x) (((x)&0xff)<<8) -#define v_BG_R(x) (((x)&0xff)<<16) -#define v_BLANK_EN(x) (((x)&1)<<24) -#define v_BLACK_EN(x) (((x)&1)<<25) -#define v_DSP_BG_SWAP(x) (((x)&1)<<26) -#define v_DSP_RB_SWAP(x) (((x)&1)<<27) -#define v_DSP_RG_SWAP(x) (((x)&1)<<28) -#define v_DSP_DELTA_SWAP(x) (((x)&1)<<29) -#define v_DSP_DUMMY_SWAP(x) (((x)&1)<<30) -#define v_DSP_OUT_ZERO(x) (((x)&1)<<31) - - -#define MCU_CTRL (0x0c) -#define m_MCU_PIX_TOTAL (0x3f<<0) -#define m_MCU_CS_ST (0x0f<<6) -#define m_MCU_CS_END (0x3f<<10) -#define m_MCU_RW_ST (0x0f<<16) -#define m_MCU_RW_END (0x3f<<20) -#define m_MCU_CLK_SEL (1<<26) -#define m_MCU_HOLD_MODE (1<<27) -#define m_MCU_FS_HOLD_STA (1<<28) -#define m_MCU_RS_SELECT (1<<29) -#define m_MCU_BYPASS (1<<30) -#define m_MCU_TYPE (1<<31) - -#define v_MCU_PIX_TOTAL(x) (((x)&0x3f)<<0) -#define v_MCU_CS_ST(x) (((x)&0x0f)<<6) -#define v_MCU_CS_END(x) (((x)&0x3f)<<10) -#define v_MCU_RW_ST(x) (((x)&0x0f)<<16) -#define v_MCU_RW_END(x) (((x)&0x3f)<<20) -#define v_MCU_CLK_SEL(x) (((x)&1)<<26) -#define v_MCU_HOLD_MODE(x) (((x)&1)<<27) -#define v_MCU_FS_HOLD_STA(x) (((x)&1)<<28) -#define v_MCU_RS_SELECT(x) (((x)&1)<<29) -#define v_MCU_BYPASS(x) (((x)&1)<<30) -#define v_MCU_TYPE(x) (((x)&1)<<31) - -#define INT_STATUS (0x10) -#define m_HS_INT_STA (1<<0) //status -#define m_FS_INT_STA (1<<1) -#define m_LF_INT_STA (1<<2) -#define m_BUS_ERR_INT_STA (1<<3) -#define m_HS_INT_EN (1<<4) //enable -#define m_FS_INT_EN (1<<5) -#define m_LF_INT_EN (1<<6) -#define m_BUS_ERR_INT_EN (1<<7) -#define m_HS_INT_CLEAR (1<<8) //auto clear -#define m_FS_INT_CLEAR (1<<9) -#define m_LF_INT_CLEAR (1<<10) -#define m_BUS_ERR_INT_CLEAR (1<<11) -#define m_LF_INT_NUM (0xfff<<12) -#define v_HS_INT_EN(x) (((x)&1)<<4) -#define v_FS_INT_EN(x) (((x)&1)<<5) -#define v_LF_INT_EN(x) (((x)&1)<<6) -#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7) -#define v_HS_INT_CLEAR(x) (((x)&1)<<8) -#define v_FS_INT_CLEAR(x) (((x)&1)<<9) -#define v_LF_INT_CLEAR(x) (((x)&1)<<10) -#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11) -#define v_LF_INT_NUM(x) (((x)&0xfff)<<12) - - -#define ALPHA_CTRL (0x14) -#define m_WIN0_ALPHA_EN (1<<0) -#define m_WIN1_ALPHA_EN (1<<1) -#define m_HWC_ALPAH_EN (1<<2) -#define m_WIN0_ALPHA_VAL (0xff<<4) -#define m_WIN1_ALPHA_VAL (0xff<<12) -#define m_HWC_ALPAH_VAL (0x0f<<20) -#define v_WIN0_ALPHA_EN(x) (((x)&1)<<0) -#define v_WIN1_ALPHA_EN(x) (((x)&1)<<1) -#define v_HWC_ALPAH_EN(x) (((x)&1)<<2) -#define v_WIN0_ALPHA_VAL(x) (((x)&0xff)<<4) -#define v_WIN1_ALPHA_VAL(x) (((x)&0xff)<<12) -#define v_HWC_ALPAH_VAL(x) (((x)&0x0f)<<20) - -#define WIN0_COLOR_KEY (0x18) -#define m_COLOR_KEY_VAL (0xffffff<<0) -#define m_COLOR_KEY_EN (1<<24) -#define v_COLOR_KEY_VAL(x) (((x)&0xffffff)<<0) -#define v_COLOR_KEY_EN(x) (((x)&1)<<24) - -#define WIN1_COLOR_KEY (0x1C) - - -#define WIN0_YRGB_MST0 (0x20) -#define WIN0_CBR_MST0 (0x24) -#define WIN0_YRGB_MST1 (0x28) -#define WIN0_CBR_MST1 (0x2C) -#define WIN_VIR (0x30) -#define m_WIN0_VIR (0x1fff << 0) -#define m_WIN1_VIR (0x1fff << 16) -#define v_WIN0_VIR_VAL(x) ((x)<<0) -#define v_WIN1_VIR_VAL(x) ((x)<<16) -#define v_ARGB888_VIRWIDTH(x) (((x)&0x1fff)<<0) -#define v_RGB888_VIRWIDTH(x) (((((x*3)>>2)+((x)%3))&0x1fff)<<0) -#define v_RGB565_VIRWIDTH(x) ((DIV_ROUND_UP(x,2)&0x1fff)<<0) -#define v_YUV_VIRWIDTH(x) ((DIV_ROUND_UP(x,4)&0x1fff)<<0) -#define v_WIN1_ARGB888_VIRWIDTH(x) (((x)&0x1fff)<<16) -#define v_WIN1_RGB888_VIRWIDTH(x) (((((x*3)>>2)+((x)%3))&0x1fff)<<16) -#define v_WIN1_RGB565_VIRWIDTH(x) ((DIV_ROUND_UP(x,2)&0x1fff)<<16) - - - -#define WIN0_ACT_INFO (0x34) -#define m_ACT_WIDTH (0x1fff<<0) -#define m_ACT_HEIGHT (0x1fff<<16) -#define v_ACT_WIDTH(x) (((x-1)&0x1fff)<<0) -#define v_ACT_HEIGHT(x) (((x-1)&0x1fff)<<16) - -#define WIN0_DSP_INFO (0x38) -#define v_DSP_WIDTH(x) (((x-1)&0x7ff)<<0) -#define v_DSP_HEIGHT(x) (((x-1)&0x7ff)<<16) - -#define WIN0_DSP_ST (0x3C) -#define v_DSP_STX(x) (((x)&0xfff)<<0) -#define v_DSP_STY(x) (((x)&0xfff)<<16) - -#define WIN0_SCL_FACTOR_YRGB (0x40) -#define v_X_SCL_FACTOR(x) (((x)&0xffff)<<0) -#define v_Y_SCL_FACTOR(x) (((x)&0xffff)<<16) - -#define WIN0_SCL_FACTOR_CBR (0x44) -#define WIN0_SCL_OFFSET (0x48) -#define WIN1_MST (0x4C) -#define WIN1_DSP_INFO (0x50) -#define WIN1_DSP_ST (0x54) -#define HWC_MST (0x58) -#define HWC_DSP_ST (0x5C) -#define HWC_COLOR_LUT0 (0x60) -#define HWC_COLOR_LUT1 (0x64) -#define HWC_COLOR_LUT2 (0x68) -#define DSP_HTOTAL_HS_END (0x6C) -#define v_HSYNC(x) (((x)&0xfff)<<0) //hsync pulse width -#define v_HORPRD(x) (((x)&0xfff)<<16) //horizontal period - -#define DSP_HACT_ST_END (0x70) -#define v_HAEP(x) (((x)&0xfff)<<0) //horizontal active end point -#define v_HASP(x) (((x)&0xfff)<<16) //horizontal active start point - -#define DSP_VTOTAL_VS_END (0x74) -#define v_VSYNC(x) (((x)&0xfff)<<0) -#define v_VERPRD(x) (((x)&0xfff)<<16) -#define DSP_VACT_ST_END (0x78) -#define v_VAEP(x) (((x)&0xfff)<<0) -#define v_VASP(x) (((x)&0xfff)<<16) - -#define DSP_VS_ST_END_F1 (0x7C) -#define DSP_VACT_ST_END_F1 (0x80) -#define REG_CFG_DONE (0x90) -#define MCU_BYPASS_WPORT (0x100) -#define MCU_BYPASS_RPORT (0x200) -#define WIN1_LUT_ADDR (0x400) -#define DSP_LUT_ADDR (0x800) - -/* - RK3026/RK3028A max output resolution 1920x1080 - support IEP instead of 3d -*/ -//#ifdef CONFIG_ARCH_RK3026 -//SYS_CTRL 0x00 -#define m_DIRECT_PATCH_EN (1<<11) -#define m_DIRECT_PATH_LAY_SEL (1<<12) - -#define v_DIRECT_PATCH_EN(x) (((x)&1)<<11) -#define v_DIRECT_PATH_LAY_SEL(x) (((x)&1)<<12) - -//INT_STATUS 0x10 -#define m_WIN0_EMPTY_INTR_EN (1<<24) -#define m_WIN1_EMPTY_INTR_EN (1<<25) -#define m_WIN0_EMPTY_INTR_CLR (1<<26) -#define m_WIN1_EMPTY_INTR_CLR (1<<27) -#define m_WIN0_EMPTY_INTR_STA (1<<28) -#define m_WIN1_EMPTY_INTR_STA (1<<29) - -#define v_WIN0_EMPTY_INTR_EN(x) (((x)&1)<<24) -#define v_WIN1_EMPTY_INTR_EN(x) (((x)&1)<<25) -#define v_WIN0_EMPTY_INTR_CLR(x) (((x)&1)<<26) -#define v_WIN1_EMPTY_INTR_CLR(x) (((x)&1)<<27) -#define v_WIN0_EMPTY_INTR_STA(x) (((x)&1)<<28) -#define v_WIN1_EMPTY_INTR_STA(x) (((x)&1)<<29) -//#endif - - -#define CalScale(x, y) ((((u32)(x-1))*0x1000)/(y-1)) - -struct lcdc_device{ - int id; - struct rk_lcdc_driver driver; - struct device *dev; - struct rk_screen *screen; - - void __iomem *regs; - void *regsbak; //back up reg - u32 reg_phy_base; // physical basic address of lcdc register - u32 len; // physical map length of lcdc register - spinlock_t reg_lock; //one time only one process allowed to config the register - - int __iomem *dsp_lut_addr_base; - - int prop; /*used for primary or extended display device*/ - bool pre_init; - bool pwr18; /*if lcdc use 1.8v power supply*/ - bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed - u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc - - - unsigned int irq; - - struct clk *pd; //lcdc power domain - struct clk *hclk; //lcdc AHP clk - struct clk *dclk; //lcdc dclk - struct clk *aclk; //lcdc share memory frequency - u32 pixclock; - - u32 standby; //1:standby,0:wrok -}; - - - -static inline void lcdc_writel(struct lcdc_device *lcdc_dev,u32 offset,u32 v) -{ - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - *_pv = v; - writel_relaxed(v,lcdc_dev->regs+offset); -} - -static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev,u32 offset) -{ - u32 v; - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - v = readl_relaxed(lcdc_dev->regs+offset); - *_pv = v; - return v; -} - -static inline u32 lcdc_read_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk) -{ - u32 _v = readl_relaxed(lcdc_dev->regs+offset); - _v &= msk; - return (_v?1:0); -} - -static inline void lcdc_set_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk) -{ - u32* _pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) |= msk; - writel_relaxed(*_pv,lcdc_dev->regs + offset); -} - -static inline void lcdc_clr_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk) -{ - u32* _pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) &= (~msk); - writel_relaxed(*_pv,lcdc_dev->regs + offset); -} - -static inline void lcdc_msk_reg(struct lcdc_device *lcdc_dev,u32 offset,u32 msk,u32 v) -{ - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) &= (~msk); - (*_pv) |= v; - writel_relaxed(*_pv,lcdc_dev->regs+offset); -} - -static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev) -{ - writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE); - dsb(); -} - -#endif diff --git a/drivers/video/rockchip/lcdc/rk322x_lcdc.c b/drivers/video/rockchip/lcdc/rk322x_lcdc.c deleted file mode 100644 index 7e52f5b799f5..000000000000 --- a/drivers/video/rockchip/lcdc/rk322x_lcdc.c +++ /dev/null @@ -1,5334 +0,0 @@ -/* - * drivers/video/rockchip/lcdc/rk322x_lcdc.c - * - * Copyright (C) 2015 ROCKCHIP, Inc. - * Author: Mark Yao - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "rk322x_lcdc.h" - -/*#define CONFIG_RK_FPGA 1*/ -#define VOP_CHIP(dev) (dev->data->chip_type) - -static int dbg_thresd; -module_param(dbg_thresd, int, S_IRUGO | S_IWUSR); - -#define DBG(level, x...) do { \ - if (unlikely(dbg_thresd >= level)) \ - pr_info(x);\ - } while (0) - -static struct rk_lcdc_win rk322x_vop_win[] = { - { .name = "win0", - .id = VOP_WIN0, - .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST | - SUPPORT_SCALE | SUPPORT_YUV | - SUPPORT_YUV10BIT, - .property.max_input_x = 4096, - .property.max_input_y = 2304}, - { .name = "win1", - .id = VOP_WIN1, - .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST | - SUPPORT_SCALE | SUPPORT_YUV | - SUPPORT_YUV10BIT, - .property.max_input_x = 4096, - .property.max_input_y = 2304}, - { - .name = "hwc", - .id = VOP_HWC, - .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST | - SUPPORT_HWC_LAYER, - .property.max_input_x = 128, - .property.max_input_y = 128 - } -}; - -static struct rk_lcdc_win rk3399_vop_win[] = { - { .name = "win0", - .id = VOP_WIN0, - .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST | - SUPPORT_SCALE | SUPPORT_YUV | - SUPPORT_YUV10BIT, - .property.max_input_x = 4096, - .property.max_input_y = 2304}, - { .name = "win1", - .id = VOP_WIN1, - .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST | - SUPPORT_SCALE | SUPPORT_YUV | - SUPPORT_YUV10BIT, - .property.max_input_x = 4096, - .property.max_input_y = 2304}, - { .name = "win2", - .id = VOP_WIN2, - .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST | - SUPPORT_MULTI_AREA, - .property.max_input_x = 4096, - .property.max_input_y = 2304}, - { .name = "win3", - .id = VOP_WIN3, - .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST | - SUPPORT_MULTI_AREA, - .property.max_input_x = 4096, - .property.max_input_y = 2304}, - { - .name = "hwc", - .id = VOP_HWC, - .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST | - SUPPORT_HWC_LAYER, - .property.max_input_x = 128, - .property.max_input_y = 128 - } -}; - -static const struct vop_data rk322x_data = { - .chip_type = VOP_RK322X, - .win = rk322x_vop_win, - .n_wins = ARRAY_SIZE(rk322x_vop_win), -}; - -static const struct vop_data rk3399_data = { - .chip_type = VOP_RK3399, - .win = rk3399_vop_win, - .n_wins = ARRAY_SIZE(rk3399_vop_win), -}; - -#if defined(CONFIG_OF) -static const struct of_device_id vop_dt_ids[] = { - {.compatible = "rockchip,rk322x-lcdc", - .data = &rk322x_data, }, - {.compatible = "rockchip,rk3399-lcdc", - .data = &rk3399_data, }, - {} -}; -#endif - -static const u32 csc_y2r_bt601_limit[12] = { - 0x04a8, 0, 0x0662, 0xfffc8654, - 0x04a8, 0xfe6f, 0xfcbf, 0x00022056, - 0x04a8, 0x0812, 0, 0xfffbaeac, -}; - -static const u32 csc_y2r_bt709_full[12] = { - 0x04a8, 0, 0x072c, 0xfffc219e, - 0x04a8, 0xff26, 0xfdde, 0x0001357b, - 0x04a8, 0x0873, 0, 0xfffb7dee, -}; - -static const u32 csc_y2r_bt601_full[12] = { - 0x0400, 0, 0x059c, 0xfffd342d, - 0x0400, 0xfea0, 0xfd25, 0x00021fcc, - 0x0400, 0x0717, 0, 0xfffc76bc, -}; - -static const u32 csc_y2r_bt601_limit_10[12] = { - 0x04a8, 0, 0x0662, 0xfff2134e, - 0x04a8, 0xfe6f, 0xfcbf, 0x00087b58, - 0x04a8, 0x0812, 0, 0xffeeb4b0, -}; - -static const u32 csc_y2r_bt709_full_10[12] = { - 0x04a8, 0, 0x072c, 0xfff08077, - 0x04a8, 0xff26, 0xfdde, 0x0004cfed, - 0x04a8, 0x0873, 0, 0xffedf1b8, -}; - -static const u32 csc_y2r_bt601_full_10[12] = { - 0x0400, 0, 0x059c, 0xfff4cab4, - 0x0400, 0xfea0, 0xfd25, 0x00087932, - 0x0400, 0x0717, 0, 0xfff1d4f2, -}; - -static const u32 csc_y2r_bt2020[12] = { - 0x04a8, 0, 0x06b6, 0xfff16bfc, - 0x04a8, 0xff40, 0xfd66, 0x58ae9, - 0x04a8, 0x0890, 0, 0xffedb828, -}; - -static const u32 csc_r2y_bt601_limit[12] = { - 0x0107, 0x0204, 0x0064, 0x04200, - 0xff68, 0xfed6, 0x01c2, 0x20200, - 0x01c2, 0xfe87, 0xffb7, 0x20200, -}; - -static const u32 csc_r2y_bt709_full[12] = { - 0x00bb, 0x0275, 0x003f, 0x04200, - 0xff99, 0xfea5, 0x01c2, 0x20200, - 0x01c2, 0xfe68, 0xffd7, 0x20200, -}; - -static const u32 csc_r2y_bt601_full[12] = { - 0x0132, 0x0259, 0x0075, 0x200, - 0xff53, 0xfead, 0x0200, 0x20200, - 0x0200, 0xfe53, 0xffad, 0x20200, -}; - -static const u32 csc_r2y_bt601_limit_10[12] = { - 0x0107, 0x0204, 0x0064, 0x10200, - 0xff68, 0xfed6, 0x01c2, 0x80200, - 0x01c2, 0xfe87, 0xffb7, 0x80200, -}; - -static const u32 csc_r2y_bt709_full_10[12] = { - 0x00bb, 0x0275, 0x003f, 0x10200, - 0xff99, 0xfea5, 0x01c2, 0x80200, - 0x01c2, 0xfe68, 0xffd7, 0x80200, -}; - -static const u32 csc_r2y_bt601_full_10[12] = { - 0x0132, 0x0259, 0x0075, 0x200, - 0xff53, 0xfead, 0x0200, 0x80200, - 0x0200, 0xfe53, 0xffad, 0x80200, -}; - -static const u32 csc_r2y_bt2020[12] = { - 0x00e6, 0x0253, 0x0034, 0x10200, - 0xff83, 0xfebd, 0x01c1, 0x80200, - 0x01c1, 0xfe64, 0xffdc, 0x80200, -}; - -static const u32 csc_r2r_bt2020to709[12] = { - 0x06a4, 0xfda6, 0xffb5, 0x200, - 0xff80, 0x0488, 0xfff8, 0x200, - 0xffed, 0xff99, 0x047a, 0x200, -}; - -static const u32 csc_r2r_bt709to2020[12] = { - 0x282, 0x151, 0x02c, 0x200, - 0x047, 0x3ae, 0x00c, 0x200, - 0x011, 0x05a, 0x395, 0x200, -}; - -static int vop_get_id(struct vop_device *vop_dev, u32 phy_base) -{ - if (VOP_CHIP(vop_dev) == VOP_RK3399) { - if (phy_base == 0xff900000) /* vop big */ - return 0; - else if (phy_base == 0xff8f0000) /* vop lit */ - return 1; - else - return -EINVAL; - } else { - return 0; - } -} - -static void vop_load_csc_table(struct vop_device *vop_dev, u32 offset, - const u32 *table) -{ - u32 csc_val; - - csc_val = table[1] << 16 | table[0]; - vop_writel(vop_dev, offset, csc_val); - csc_val = table[4] << 16 | table[2]; - vop_writel(vop_dev, offset + 4, csc_val); - csc_val = table[6] << 16 | table[5]; - vop_writel(vop_dev, offset + 8, csc_val); - csc_val = table[9] << 16 | table[8]; - vop_writel(vop_dev, offset + 0xc, csc_val); - csc_val = table[10]; - vop_writel(vop_dev, offset + 0x10, csc_val); - csc_val = table[3]; - vop_writel(vop_dev, offset + 0x14, csc_val); - csc_val = table[7]; - vop_writel(vop_dev, offset + 0x18, csc_val); - csc_val = table[11]; - vop_writel(vop_dev, offset + 0x1c, csc_val); -} - -#define LOAD_CSC(dev, mode, table, win_id) \ - vop_load_csc_table(dev, \ - WIN0_YUV2YUV_##mode + 0x60 * win_id, \ - table) - -static int vop_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable); - -static int vop_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - int i, j; - - if (!vop_dev->dsp_lut_addr_base) { - dev_warn(vop_dev->dev, "not support dsp lut config\n"); - return 0; - } - - if (!dsp_lut) { - dev_err(vop_dev->dev, "dsp lut table is null\n"); - return -EINVAL; - } - - spin_lock(&vop_dev->reg_lock); - for (i = 0; i < 256; i++) { - u32 v, r, g, b; - int __iomem *c; - - v = dsp_lut[i]; - if (dev_drv->id == 0) { - c = vop_dev->dsp_lut_addr_base + (i << 2); - b = (v & 0xff) << 2; - g = (v & 0xff00) << 4; - r = (v & 0xff0000) << 6; - v = r + g + b; - for (j = 0; j < 4; j++) { - writel_relaxed(v, c); - v += (1 + (1 << 10) + (1 << 20)); - c++; - } - } else { - c = vop_dev->dsp_lut_addr_base + i; - writel_relaxed(v, c); - } - } - vop_msk_reg(vop_dev, DSP_CTRL1, V_DSP_LUT_EN(1)); - /* - * update_gamma value auto clean to 0 by HW, should not - * bakeup it. - */ - vop_msk_reg_nobak(vop_dev, DSP_CTRL1, V_UPDATE_GAMMA_LUT(1)); - - vop_cfg_done(vop_dev); - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_set_cabc(struct rk_lcdc_driver *dev_drv, int *cabc_lut) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - int i; - - if (!vop_dev->cabc_lut_addr_base) { - dev_warn(vop_dev->dev, "not support cabc config\n"); - return 0; - } - - if (!cabc_lut) { - dev_err(vop_dev->dev, "cabc lut table is null\n"); - return -EINVAL; - } - spin_lock(&vop_dev->reg_lock); - vop_msk_reg(vop_dev, CABC_CTRL1, V_CABC_LUT_EN(0)); - vop_cfg_done(vop_dev); - spin_unlock(&vop_dev->reg_lock); - - mdelay(25); - - spin_lock(&vop_dev->reg_lock); - for (i = 0; i < 128; i++) { - u32 v; - - v = cabc_lut[i]; - - writel_relaxed(v, vop_dev->cabc_lut_addr_base + i); - } - vop_msk_reg(vop_dev, CABC_CTRL1, V_CABC_LUT_EN(1)); - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_clk_enable(struct vop_device *vop_dev) -{ - if (!vop_dev->clk_on) { - clk_prepare_enable(vop_dev->hclk); - clk_prepare_enable(vop_dev->dclk); - clk_prepare_enable(vop_dev->aclk); - if (vop_dev->hclk_noc) - clk_prepare_enable(vop_dev->hclk_noc); - if (vop_dev->aclk_noc) - clk_prepare_enable(vop_dev->aclk_noc); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) - pm_runtime_get_sync(vop_dev->dev); -#endif - spin_lock(&vop_dev->reg_lock); - vop_dev->clk_on = 1; - spin_unlock(&vop_dev->reg_lock); - } - - return 0; -} - -static int vop_clk_disable(struct vop_device *vop_dev) -{ - if (vop_dev->clk_on) { - spin_lock(&vop_dev->reg_lock); - vop_dev->clk_on = 0; - spin_unlock(&vop_dev->reg_lock); - mdelay(25); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) - pm_runtime_put_sync(vop_dev->dev); -#endif - clk_disable_unprepare(vop_dev->dclk); - clk_disable_unprepare(vop_dev->hclk); - clk_disable_unprepare(vop_dev->aclk); - if (vop_dev->hclk_noc) - clk_disable_unprepare(vop_dev->hclk_noc); - if (vop_dev->aclk_noc) - clk_disable_unprepare(vop_dev->aclk_noc); - } - - return 0; -} - -static int __maybe_unused vop_disable_irq(struct vop_device *vop_dev) -{ - if (likely(vop_dev->clk_on)) { - spin_lock(&vop_dev->reg_lock); - vop_writel(vop_dev, INTR_EN0, 0xffff0000); - vop_writel(vop_dev, INTR_EN1, 0xffff0000); - vop_writel(vop_dev, INTR_CLEAR0, 0xffffffff); - vop_writel(vop_dev, INTR_CLEAR1, 0xffffffff); - vop_cfg_done(vop_dev); - spin_unlock(&vop_dev->reg_lock); - }; - - return 0; -} - -static int vop_reg_dump(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - int *cbase = (int *)vop_dev->regs; - int *regsbak = (int *)vop_dev->regsbak; - int i, j, val; - char dbg_message[30]; - char buf[10]; - - pr_info("lcd back up reg:\n"); - memset(dbg_message, 0, sizeof(dbg_message)); - memset(buf, 0, sizeof(buf)); - for (i = 0; i <= (0x200 >> 4); i++) { - val = sprintf(dbg_message, "0x%04x: ", i * 16); - for (j = 0; j < 4; j++) { - val = sprintf(buf, "%08x ", *(regsbak + i * 4 + j)); - strcat(dbg_message, buf); - } - pr_info("%s\n", dbg_message); - memset(dbg_message, 0, sizeof(dbg_message)); - memset(buf, 0, sizeof(buf)); - } - - pr_info("lcdc reg:\n"); - for (i = 0; i <= (0x200 >> 4); i++) { - val = sprintf(dbg_message, "0x%04x: ", i * 16); - for (j = 0; j < 4; j++) { - sprintf(buf, "%08x ", - readl_relaxed(cbase + i * 4 + j)); - strcat(dbg_message, buf); - } - pr_info("%s\n", dbg_message); - memset(dbg_message, 0, sizeof(dbg_message)); - memset(buf, 0, sizeof(buf)); - } - - return 0; -} - -#define WIN_EN(id) \ -static int win##id##_enable(struct vop_device *vop_dev, int en) \ -{ \ - spin_lock(&vop_dev->reg_lock); \ - vop_msk_reg(vop_dev, WIN##id##_CTRL0, V_WIN##id##_EN((u64)en)); \ - vop_cfg_done(vop_dev); \ - spin_unlock(&vop_dev->reg_lock); \ - return 0; \ -} - -WIN_EN(0); -WIN_EN(1); -WIN_EN(2); -WIN_EN(3); - -/*enable/disable win directly*/ -static int vop_win_direct_en(struct rk_lcdc_driver *drv, - int win_id, int en) -{ - struct vop_device *vop_dev = - container_of(drv, struct vop_device, driver); - - drv->win[win_id]->state = en; - if (win_id == 0) - win0_enable(vop_dev, en); - else if (win_id == 1) - win1_enable(vop_dev, en); - else if (win_id == 2) - win2_enable(vop_dev, en); - else if (win_id == 3) - win3_enable(vop_dev, en); - else - dev_err(vop_dev->dev, "invalid win number:%d\n", win_id); - return 0; -} - -#define SET_WIN_ADDR(id) \ -static int set_win##id##_addr(struct vop_device *vop_dev, u32 addr) \ -{ \ - spin_lock(&vop_dev->reg_lock); \ - vop_writel(vop_dev, WIN##id##_YRGB_MST, addr); \ - vop_msk_reg(vop_dev, WIN##id##_CTRL0, V_WIN##id##_EN(1)); \ - vop_cfg_done(vop_dev); \ - spin_unlock(&vop_dev->reg_lock); \ - return 0; \ -} - -SET_WIN_ADDR(0); -SET_WIN_ADDR(1); -int vop_direct_set_win_addr(struct rk_lcdc_driver *dev_drv, - int win_id, u32 addr) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - if (win_id == 0) - set_win0_addr(vop_dev, addr); - else - set_win1_addr(vop_dev, addr); - - return 0; -} - -static void lcdc_read_reg_defalut_cfg(struct vop_device *vop_dev) -{ - int reg = 0; - u32 val = 0; - struct rk_screen *screen = vop_dev->driver.cur_screen; - u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin; - u32 V_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin; - u32 st_x, st_y; - struct rk_lcdc_win *win0 = vop_dev->driver.win[0]; - - spin_lock(&vop_dev->reg_lock); - for (reg = 0; reg < vop_dev->len; reg += 4) { - val = vop_readl_backup(vop_dev, reg); - switch (reg) { - case WIN0_ACT_INFO: - win0->area[0].xact = (val & MASK(WIN0_ACT_WIDTH)) + 1; - win0->area[0].yact = - ((val & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1; - break; - case WIN0_DSP_INFO: - win0->area[0].xsize = (val & MASK(WIN0_DSP_WIDTH)) + 1; - win0->area[0].ysize = - ((val & MASK(WIN0_DSP_HEIGHT)) >> 16) + 1; - break; - case WIN0_DSP_ST: - st_x = val & MASK(WIN0_DSP_XST); - st_y = (val & MASK(WIN0_DSP_YST)) >> 16; - win0->area[0].xpos = st_x - h_pw_bp; - win0->area[0].ypos = st_y - V_pw_bp; - break; - case WIN0_CTRL0: - win0->state = val & MASK(WIN0_EN); - win0->area[0].fmt_cfg = - (val & MASK(WIN0_DATA_FMT)) >> 1; - win0->fmt_10 = (val & MASK(WIN0_FMT_10)) >> 4; - win0->area[0].format = win0->area[0].fmt_cfg; - break; - case WIN0_VIR: - win0->area[0].y_vir_stride = - val & MASK(WIN0_VIR_STRIDE); - win0->area[0].uv_vir_stride = - (val & MASK(WIN0_VIR_STRIDE_UV)) >> 16; - if (win0->area[0].format == ARGB888) - win0->area[0].xvir = win0->area[0].y_vir_stride; - else if (win0->area[0].format == RGB888) - win0->area[0].xvir = - win0->area[0].y_vir_stride * 4 / 3; - else if (win0->area[0].format == RGB565) - win0->area[0].xvir = - 2 * win0->area[0].y_vir_stride; - else - win0->area[0].xvir = - 4 * win0->area[0].y_vir_stride; - break; - case WIN0_YRGB_MST: - win0->area[0].smem_start = val; - break; - case WIN0_CBR_MST: - win0->area[0].cbr_start = val; - break; - default: - break; - } - } - spin_unlock(&vop_dev->reg_lock); -} - -/********do basic init*********/ -static int vop_pre_init(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - if (vop_dev->pre_init) - return 0; - vop_dev->hclk = devm_clk_get(vop_dev->dev, "hclk_lcdc"); - vop_dev->aclk = devm_clk_get(vop_dev->dev, "aclk_lcdc"); - vop_dev->dclk = devm_clk_get(vop_dev->dev, "dclk_lcdc"); - if (IS_ERR(vop_dev->aclk) || IS_ERR(vop_dev->dclk) || - IS_ERR(vop_dev->hclk)) { - dev_err(vop_dev->dev, "failed to get clk source\n"); - return -1; - } - vop_dev->hclk_noc = devm_clk_get(vop_dev->dev, "hclk_vop_noc"); - if (IS_ERR(vop_dev->hclk_noc)) { - vop_dev->hclk_noc = NULL; - dev_err(vop_dev->dev, "failed to get clk source\n"); - } - vop_dev->aclk_noc = devm_clk_get(vop_dev->dev, "aclk_vop_noc"); - if (IS_ERR(vop_dev->aclk_noc)) { - vop_dev->aclk_noc = NULL; - dev_err(vop_dev->dev, "failed to get clk source\n"); - } - if (!support_uboot_display()) - rk_disp_pwr_enable(dev_drv); - vop_clk_enable(vop_dev); - - memcpy(vop_dev->regsbak, vop_dev->regs, vop_dev->len); - /*backup reg config at uboot */ - lcdc_read_reg_defalut_cfg(vop_dev); - #ifndef CONFIG_RK_FPGA - /* - * Todo, not verified - * - if (vop_dev->pwr18 == 1) { - v = 0x00200020; - vop_grf_writel(vop_dev->pmugrf_base, - PMUGRF_SOC_CON0_VOP, v); - } else { - v = 0x00200000; - vop_grf_writel(vop_dev->pmugrf_base, - PMUGRF_SOC_CON0_VOP, v); - } - */ - #endif - vop_writel(vop_dev, FRC_LOWER01_0, 0x12844821); - vop_writel(vop_dev, FRC_LOWER01_1, 0x21488412); - vop_writel(vop_dev, FRC_LOWER10_0, 0xa55a9696); - vop_writel(vop_dev, FRC_LOWER10_1, 0x5aa56969); - vop_writel(vop_dev, FRC_LOWER11_0, 0xdeb77deb); - vop_writel(vop_dev, FRC_LOWER11_1, 0xed7bb7de); - - if (!dev_drv->cabc_mode) - vop_msk_reg(vop_dev, SYS_CTRL, V_AUTO_GATING_EN(0)); - vop_msk_reg(vop_dev, DSP_CTRL1, V_DITHER_UP_EN(1)); - vop_cfg_done(vop_dev); - if ((dev_drv->cur_screen->refresh_mode == SCREEN_CMD_MODE) && - (support_uboot_display() == 0)) - vop_msk_reg(vop_dev, SYS_CTRL, V_EDPI_WMS_MODE(1)); - vop_dev->pre_init = true; - - return 0; -} - -static void vop_deint(struct vop_device *vop_dev) -{ - if (vop_dev->clk_on) { - u64 val; - - vop_disable_irq(vop_dev); - spin_lock(&vop_dev->reg_lock); - vop_msk_reg(vop_dev, WIN0_CTRL0, V_WIN0_EN(0)); - vop_msk_reg(vop_dev, WIN1_CTRL0, V_WIN0_EN(0)); - - val = V_WIN2_EN(0) | V_WIN2_MST0_EN(0) | V_WIN2_MST1_EN(0) | - V_WIN2_MST2_EN(0) | V_WIN2_MST3_EN(0); - vop_msk_reg(vop_dev, WIN2_CTRL0, val); - vop_msk_reg(vop_dev, WIN3_CTRL0, val); - vop_cfg_done(vop_dev); - spin_unlock(&vop_dev->reg_lock); - mdelay(50); - } -} - -static void vop_win_csc_mode(struct vop_device *vop_dev, - struct rk_lcdc_win *win, - int csc_mode) -{ - u64 val; - - if (win->id == VOP_WIN0) { - val = V_WIN0_CSC_MODE(csc_mode); - vop_msk_reg(vop_dev, WIN0_CTRL0, val); - } else if (win->id == VOP_WIN1) { - val = V_WIN1_CSC_MODE(csc_mode); - vop_msk_reg(vop_dev, WIN1_CTRL0, val); - } else { - val = V_HWC_CSC_MODE(csc_mode); - vop_msk_reg(vop_dev, HWC_CTRL0, val); - } -} - -static int rk3399_vop_win_csc_cfg(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - int output_color = dev_drv->output_color; - int i; - - for (i = 0; i < dev_drv->lcdc_win_num && i < 4; i++) { - struct rk_lcdc_win *win = dev_drv->win[i]; - int shift = i * 8; - u64 val = V_WIN0_YUV2YUV_EN(0) | V_WIN0_YUV2YUV_R2Y_EN(0) | - V_WIN0_YUV2YUV_Y2R_EN(0); - - if (!win->state) - continue; - if (output_color == COLOR_RGB && - !(IS_YUV(win->area[0].fmt_cfg) || win->area[0].yuyv_fmt)) - goto post; - - if (output_color == COLOR_RGB) { - val |= V_WIN0_YUV2YUV_Y2R_EN(1); - if (win->colorspace == CSC_BT601) { - /* - * Win Y2Y moudle always use 10bit mode. - */ - LOAD_CSC(vop_dev, Y2R, - csc_y2r_bt601_full_10, i); - } else if (win->colorspace == CSC_BT709) { - LOAD_CSC(vop_dev, Y2R, - csc_y2r_bt709_full_10, i); - } else if (win->colorspace == CSC_BT2020) { - val |= V_WIN0_YUV2YUV_EN(1); - LOAD_CSC(vop_dev, Y2R, csc_y2r_bt2020, i); - LOAD_CSC(vop_dev, R2R, csc_r2r_bt2020to709, i); - } - } else if (output_color == COLOR_YCBCR || - output_color == COLOR_YCBCR_BT709) { - if (!(IS_YUV(win->area[0].fmt_cfg) || - win->area[0].yuyv_fmt)) { - val |= V_WIN0_YUV2YUV_R2Y_EN(1); - if ((win->id == 0) || (win->id == 1)) - LOAD_CSC(vop_dev, R2Y, csc_r2y_bt709_full_10, i); - else - val |= V_WIN0_YUV2YUV_R2Y_MODE(VOP_R2Y_CSC_BT709); - - } else if (win->colorspace == CSC_BT2020) { - val |= V_WIN0_YUV2YUV_EN(1) | - V_WIN0_YUV2YUV_Y2R_EN(1) | - V_WIN0_YUV2YUV_R2Y_EN(1); - LOAD_CSC(vop_dev, Y2R, csc_y2r_bt2020, i); - LOAD_CSC(vop_dev, R2R, csc_r2r_bt2020to709, i); - LOAD_CSC(vop_dev, R2Y, csc_r2y_bt709_full_10, i); - } - } else if (output_color == COLOR_YCBCR_BT2020) { - if (!(IS_YUV(win->area[0].fmt_cfg) || - win->area[0].yuyv_fmt)) { - LOAD_CSC(vop_dev, R2R, csc_r2r_bt709to2020, i); - val |= V_WIN0_YUV2YUV_R2Y_EN(1) | - V_WIN0_YUV2YUV_EN(1); - if ((win->id == 0) || (win->id == 1)) { - LOAD_CSC(vop_dev, R2Y, csc_r2y_bt2020, i); - } else { - val |= V_WIN0_YUV2YUV_R2Y_MODE(VOP_R2Y_CSC_BT2020); - } - } else if (win->colorspace == CSC_BT601 || - win->colorspace == CSC_BT709) { - val |= V_WIN0_YUV2YUV_Y2R_EN(1) | - V_WIN0_YUV2YUV_R2Y_EN(1) | - V_WIN0_YUV2YUV_EN(1); - LOAD_CSC(vop_dev, Y2R, csc_y2r_bt709_full_10, i); - LOAD_CSC(vop_dev, R2R, csc_r2r_bt709to2020, i); - LOAD_CSC(vop_dev, R2Y, csc_r2y_bt2020, i); - } - } -post: - vop_msk_reg(vop_dev, YUV2YUV_WIN, val << shift); - } - - return output_color; -} - -/* - * colorspace path: - * Input Win csc Post csc Output - * 1. YUV(2020) --> bypass ---+ Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709) - * RGB --> R2Y(709) __/ - * - * 2. YUV(2020) --> bypass ---+ bypass --> YUV_OUTPUT(2020) - * RGB --> R2Y(709) __/ - * - * 3. YUV(2020) --> bypass ---+ Y2R->2020To709 --> RGB_OUTPUT(709) - * RGB --> R2Y(709) __/ - * - * 4. YUV(601/709)-> bypass ---+ Y2R->709To2020->R2Y --> YUV_OUTPUT(2020) - * RGB --> R2Y(709) __/ - * - * 5. YUV(601/709)-> bypass ---+ bypass --> YUV_OUTPUT(709) - * RGB --> R2Y(709) __/ - * - * 6. YUV(601/709)-> bypass ---+ bypass --> YUV_OUTPUT(601) - * RGB --> R2Y(601) __/ - * - * 7. YUV(601) --> Y2R(601/mpeg)-+ bypass --> RGB_OUTPUT(709) - * RGB --> bypass ____/ - * - * 8. YUV(709) --> Y2R(709/hd) --+ bypass --> RGB_OUTPUT(709) - * RGB --> bypass ____/ - * - * 9. RGB --> bypass ---> 709To2020->R2Y --> YUV_OUTPUT(2020) - * - * 10. RGB --> R2Y(709) ---> bypass --> YUV_OUTPUT(709) - * - * 11. RGB --> R2Y(601) ---> bypass --> YUV_OUTPUT(601) - * - * 12. RGB --> bypass ---> bypass --> RGB_OUTPUT(709) - */ -static int rk3228_vop_win_csc_cfg(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_lcdc_win *win; - int output_color = dev_drv->output_color; - int win_csc = COLOR_RGB; - int r2y_mode = VOP_R2Y_CSC_BT709; - int i; - - for (i = 0; i < dev_drv->lcdc_win_num; i++) { - win = dev_drv->win[i]; - if (!win->state) - continue; - - if (IS_YUV(win->area[0].fmt_cfg)) { - if (win->colorspace == CSC_BT2020 && - win_csc < COLOR_YCBCR_BT2020) { - r2y_mode = VOP_R2Y_CSC_BT709; - win_csc = COLOR_YCBCR_BT2020; - } - - if (win->colorspace == CSC_BT709 && - win_csc < COLOR_YCBCR_BT709) { - r2y_mode = VOP_R2Y_CSC_BT709; - win_csc = COLOR_YCBCR_BT709; - } - - if (win->colorspace == CSC_BT601 && - win_csc < COLOR_YCBCR) { - r2y_mode = VOP_R2Y_CSC_BT709; - win_csc = COLOR_YCBCR; - } - } - } - - if (win_csc == COLOR_RGB) { - if (output_color == COLOR_YCBCR_BT709) { - r2y_mode = VOP_R2Y_CSC_BT709; - win_csc = COLOR_YCBCR_BT709; - } else if (output_color == COLOR_YCBCR) { - r2y_mode = VOP_R2Y_CSC_BT601; - win_csc = COLOR_YCBCR; - } - } - - for (i = 0; i < dev_drv->lcdc_win_num; i++) { - win = dev_drv->win[i]; - if (!win->state) - continue; - - if (win_csc != COLOR_RGB && !IS_YUV(win->area[0].fmt_cfg)) - vop_win_csc_mode(vop_dev, win, r2y_mode); - - if (IS_YUV(win->area[0].fmt_cfg)) { - if (win_csc == COLOR_YCBCR) - vop_win_csc_mode(vop_dev, win, - VOP_Y2R_CSC_MPEG); - else if (win_csc == COLOR_YCBCR_BT709) - vop_win_csc_mode(vop_dev, win, VOP_Y2R_CSC_HD); - } - } - - return win_csc; -} - -static int vop_post_csc_cfg(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - int output_color = dev_drv->output_color; - int win_csc = 0, overlay_mode = 0; - u64 val; - - if (VOP_CHIP(vop_dev) == VOP_RK322X) { - win_csc = rk3228_vop_win_csc_cfg(dev_drv); - } else if (VOP_CHIP(vop_dev) == VOP_RK3399) { - win_csc = rk3399_vop_win_csc_cfg(dev_drv); - - /* - * RK3399 not support post csc config. - */ - goto done; - } - - val = V_YUV2YUV_POST_Y2R_EN(0) | V_YUV2YUV_POST_EN(0) | - V_YUV2YUV_POST_R2Y_EN(0); - /* Y2R */ - if (win_csc == COLOR_YCBCR && output_color == COLOR_YCBCR_BT2020) { - val |= V_YUV2YUV_POST_Y2R_EN(1); - vop_load_csc_table(vop_dev, POST_YUV2YUV_Y2R_COE, - csc_y2r_bt709_full); - } - if (win_csc == COLOR_YCBCR_BT2020 && - output_color != COLOR_YCBCR_BT2020) { - val |= V_YUV2YUV_POST_Y2R_EN(1); - vop_load_csc_table(vop_dev, POST_YUV2YUV_Y2R_COE, - csc_y2r_bt2020); - } - - /* R2R */ - if ((win_csc == COLOR_YCBCR || - win_csc == COLOR_YCBCR_BT709 || - win_csc == COLOR_RGB) && output_color == COLOR_YCBCR_BT2020) { - val |= V_YUV2YUV_POST_EN(1); - vop_load_csc_table(vop_dev, POST_YUV2YUV_3x3_COE, - csc_r2r_bt709to2020); - } - if (win_csc == COLOR_YCBCR_BT2020 && - (output_color == COLOR_YCBCR || - output_color == COLOR_YCBCR_BT709 || - output_color == COLOR_RGB)) { - val |= V_YUV2YUV_POST_EN(1); - vop_load_csc_table(vop_dev, POST_YUV2YUV_3x3_COE, - csc_r2r_bt2020to709); - } - - /* Y2R */ - if (output_color != COLOR_RGB) { - val |= V_YUV2YUV_POST_R2Y_EN(1); - - if (output_color == COLOR_YCBCR_BT2020) - vop_load_csc_table(vop_dev, POST_YUV2YUV_R2Y_COE, - csc_r2y_bt2020); - else - vop_load_csc_table(vop_dev, POST_YUV2YUV_R2Y_COE, - csc_r2y_bt709_full); - } - - DBG(1, "win_csc=%d output_color=%d val=%llx\n", - win_csc, output_color, val); - vop_msk_reg(vop_dev, YUV2YUV_POST, val); -done: - overlay_mode = (win_csc != COLOR_RGB) ? VOP_YUV_DOMAIN : VOP_RGB_DOMAIN; - vop_msk_reg(vop_dev, SYS_CTRL, V_OVERLAY_MODE(overlay_mode)); - - return 0; -} - -static int vop_post_cfg(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u16 x_res = screen->mode.xres; - u16 y_res = screen->mode.yres; - u64 val; - u16 h_total, v_total; - u16 post_hsd_en, post_vsd_en; - u16 post_dsp_hact_st, post_dsp_hact_end; - u16 post_dsp_vact_st, post_dsp_vact_end; - u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1; - u16 post_h_fac, post_v_fac; - - screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200; - screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200; - screen->post_xsize = x_res * - (dev_drv->overscan.left + dev_drv->overscan.right) / 200; - screen->post_ysize = y_res * - (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200; - - h_total = screen->mode.hsync_len + screen->mode.left_margin + - x_res + screen->mode.right_margin; - v_total = screen->mode.vsync_len + screen->mode.upper_margin + - y_res + screen->mode.lower_margin; - - if (screen->post_dsp_stx + screen->post_xsize > x_res) { - dev_warn(vop_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n", - screen->post_dsp_stx, screen->post_xsize, x_res); - screen->post_dsp_stx = x_res - screen->post_xsize; - } - if (screen->x_mirror == 0) { - post_dsp_hact_st = screen->post_dsp_stx + - screen->mode.hsync_len + screen->mode.left_margin; - post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize; - } else { - post_dsp_hact_end = h_total - screen->mode.right_margin - - screen->post_dsp_stx; - post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize; - } - if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) { - post_hsd_en = 1; - post_h_fac = - GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize); - } else { - post_hsd_en = 0; - post_h_fac = 0x1000; - } - - if (screen->post_dsp_sty + screen->post_ysize > y_res) { - dev_warn(vop_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n", - screen->post_dsp_sty, screen->post_ysize, y_res); - screen->post_dsp_sty = y_res - screen->post_ysize; - } - - if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) { - post_vsd_en = 1; - post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res, - screen->post_ysize); - } else { - post_vsd_en = 0; - post_v_fac = 0x1000; - } - - if (screen->mode.vmode & FB_VMODE_INTERLACED) { - post_dsp_vact_st = screen->post_dsp_sty / 2 + - screen->mode.vsync_len + - screen->mode.upper_margin; - post_dsp_vact_end = post_dsp_vact_st + - screen->post_ysize / 2; - - post_dsp_vact_st_f1 = screen->mode.vsync_len + - screen->mode.upper_margin + - y_res / 2 + - screen->mode.lower_margin + - screen->mode.vsync_len + - screen->mode.upper_margin + - screen->post_dsp_sty / 2 + - 1; - post_dsp_vact_end_f1 = post_dsp_vact_st_f1 + - screen->post_ysize / 2; - } else { - if (screen->y_mirror == 0) { - post_dsp_vact_st = screen->post_dsp_sty + - screen->mode.vsync_len + - screen->mode.upper_margin; - post_dsp_vact_end = post_dsp_vact_st + - screen->post_ysize; - } else { - post_dsp_vact_end = v_total - - screen->mode.lower_margin - - screen->post_dsp_sty; - post_dsp_vact_st = post_dsp_vact_end - - screen->post_ysize; - } - post_dsp_vact_st_f1 = 0; - post_dsp_vact_end_f1 = 0; - } - DBG(1, "post:xsize=%d,ysize=%d,xpos=%d", - screen->post_xsize, screen->post_ysize, screen->xpos); - DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n", - screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac); - val = V_DSP_HACT_END_POST(post_dsp_hact_end) | - V_DSP_HACT_ST_POST(post_dsp_hact_st); - vop_msk_reg(vop_dev, POST_DSP_HACT_INFO, val); - - val = V_DSP_VACT_END_POST(post_dsp_vact_end) | - V_DSP_VACT_ST_POST(post_dsp_vact_st); - vop_msk_reg(vop_dev, POST_DSP_VACT_INFO, val); - - val = V_POST_HS_FACTOR_YRGB(post_h_fac) | - V_POST_VS_FACTOR_YRGB(post_v_fac); - vop_msk_reg(vop_dev, POST_SCL_FACTOR_YRGB, val); - val = V_DSP_VACT_END_POST(post_dsp_vact_end_f1) | - V_DSP_VACT_ST_POST(post_dsp_vact_st_f1); - vop_msk_reg(vop_dev, POST_DSP_VACT_INFO_F1, val); - val = V_POST_HOR_SD_EN(post_hsd_en) | V_POST_VER_SD_EN(post_vsd_en); - vop_msk_reg(vop_dev, POST_SCL_CTRL, val); - - vop_post_csc_cfg(dev_drv); - - return 0; -} - -static int vop_clr_key_cfg(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_lcdc_win *win; - u32 colorkey_r, colorkey_g, colorkey_b; - int i, key_val; - - for (i = 0; i < dev_drv->lcdc_win_num; i++) { - win = dev_drv->win[i]; - key_val = win->color_key_val; - colorkey_r = (key_val & 0xff) << 2; - colorkey_g = ((key_val >> 8) & 0xff) << 12; - colorkey_b = ((key_val >> 16) & 0xff) << 22; - /* color key dither 565/888->aaa */ - key_val = colorkey_r | colorkey_g | colorkey_b; - switch (i) { - case 0: - vop_writel(vop_dev, WIN0_COLOR_KEY, key_val); - break; - case 1: - vop_writel(vop_dev, WIN1_COLOR_KEY, key_val); - break; - case 2: - vop_writel(vop_dev, WIN2_COLOR_KEY, key_val); - break; - case 3: - vop_writel(vop_dev, WIN3_COLOR_KEY, key_val); - break; - default: - pr_info("%s:un support win num:%d\n", - __func__, i); - break; - } - } - return 0; -} - -static int vop_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - struct alpha_config alpha_config; - u64 val; - int ppixel_alpha = 0, global_alpha = 0, i; - u32 src_alpha_ctl = 0, dst_alpha_ctl = 0; - int alpha_en = 1; - - memset(&alpha_config, 0, sizeof(struct alpha_config)); - for (i = 0; i < win->area_num; i++) { - ppixel_alpha |= ((win->area[i].format == ARGB888) || - (win->area[i].format == FBDC_ARGB_888) || - (win->area[i].format == FBDC_ABGR_888) || - (win->area[i].format == ABGR888)) ? 1 : 0; - } - - global_alpha = (win->g_alpha_val == 0) ? 0 : 1; - - for (i = 0; i < dev_drv->lcdc_win_num; i++) { - if (!dev_drv->win[i]->state) - continue; - if (win->z_order > dev_drv->win[i]->z_order) - break; - } - - /* - * The bottom layer not support ppixel_alpha mode. - */ - if (i == dev_drv->lcdc_win_num) - ppixel_alpha = 0; - alpha_config.src_global_alpha_val = win->g_alpha_val; - win->alpha_mode = AB_SRC_OVER; - - switch (win->alpha_mode) { - case AB_USER_DEFINE: - break; - case AB_CLEAR: - alpha_config.src_factor_mode = AA_ZERO; - alpha_config.dst_factor_mode = AA_ZERO; - break; - case AB_SRC: - alpha_config.src_factor_mode = AA_ONE; - alpha_config.dst_factor_mode = AA_ZERO; - break; - case AB_DST: - alpha_config.src_factor_mode = AA_ZERO; - alpha_config.dst_factor_mode = AA_ONE; - break; - case AB_SRC_OVER: - alpha_config.src_color_mode = AA_SRC_PRE_MUL; - if (global_alpha) - alpha_config.src_factor_mode = AA_SRC_GLOBAL; - else - alpha_config.src_factor_mode = AA_ONE; - alpha_config.dst_factor_mode = AA_SRC_INVERSE; - break; - case AB_DST_OVER: - alpha_config.src_color_mode = AA_SRC_PRE_MUL; - alpha_config.src_factor_mode = AA_SRC_INVERSE; - alpha_config.dst_factor_mode = AA_ONE; - break; - case AB_SRC_IN: - alpha_config.src_color_mode = AA_SRC_PRE_MUL; - alpha_config.src_factor_mode = AA_SRC; - alpha_config.dst_factor_mode = AA_ZERO; - break; - case AB_DST_IN: - alpha_config.src_factor_mode = AA_ZERO; - alpha_config.dst_factor_mode = AA_SRC; - break; - case AB_SRC_OUT: - alpha_config.src_color_mode = AA_SRC_PRE_MUL; - alpha_config.src_factor_mode = AA_SRC_INVERSE; - alpha_config.dst_factor_mode = AA_ZERO; - break; - case AB_DST_OUT: - alpha_config.src_factor_mode = AA_ZERO; - alpha_config.dst_factor_mode = AA_SRC_INVERSE; - break; - case AB_SRC_ATOP: - alpha_config.src_color_mode = AA_SRC_PRE_MUL; - alpha_config.src_factor_mode = AA_SRC; - alpha_config.dst_factor_mode = AA_SRC_INVERSE; - break; - case AB_DST_ATOP: - alpha_config.src_color_mode = AA_SRC_PRE_MUL; - alpha_config.src_factor_mode = AA_SRC_INVERSE; - alpha_config.dst_factor_mode = AA_SRC; - break; - case XOR: - alpha_config.src_color_mode = AA_SRC_PRE_MUL; - alpha_config.src_factor_mode = AA_SRC_INVERSE; - alpha_config.dst_factor_mode = AA_SRC_INVERSE; - break; - case AB_SRC_OVER_GLOBAL: - alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL; - alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL; - alpha_config.src_factor_mode = AA_SRC_GLOBAL; - alpha_config.dst_factor_mode = AA_SRC_INVERSE; - break; - default: - pr_err("alpha mode error\n"); - break; - } - if ((ppixel_alpha == 1) && (global_alpha == 1)) - alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL; - else if (ppixel_alpha == 1) - alpha_config.src_global_alpha_mode = AA_PER_PIX; - else if (global_alpha == 1) - alpha_config.src_global_alpha_mode = AA_GLOBAL; - else - alpha_en = 0; - alpha_config.src_alpha_mode = AA_STRAIGHT; - alpha_config.src_alpha_cal_m0 = AA_NO_SAT; - - switch (win_id) { - case 0: - src_alpha_ctl = 0x60; - dst_alpha_ctl = 0x64; - break; - case 1: - src_alpha_ctl = 0xa0; - dst_alpha_ctl = 0xa4; - break; - case 2: - src_alpha_ctl = 0xdc; - dst_alpha_ctl = 0xec; - break; - case 3: - src_alpha_ctl = 0x12c; - dst_alpha_ctl = 0x13c; - break; - case 4: - src_alpha_ctl = 0x160; - dst_alpha_ctl = 0x164; - break; - } - val = V_WIN0_DST_FACTOR_MODE(alpha_config.dst_factor_mode); - vop_msk_reg(vop_dev, dst_alpha_ctl, val); - val = V_WIN0_SRC_ALPHA_EN(alpha_en) | - V_WIN0_SRC_COLOR_MODE(alpha_config.src_color_mode) | - V_WIN0_SRC_ALPHA_MODE(alpha_config.src_alpha_mode) | - V_WIN0_SRC_BLEND_MODE(alpha_config.src_global_alpha_mode) | - V_WIN0_SRC_ALPHA_CAL_MODE(alpha_config.src_alpha_cal_m0) | - V_WIN0_SRC_FACTOR_MODE(alpha_config.src_factor_mode) | - V_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val); - - vop_msk_reg(vop_dev, src_alpha_ctl, val); - - return 0; -} - -static int vop_axi_gather_cfg(struct vop_device *vop_dev, - struct rk_lcdc_win *win) -{ - u64 val; - u16 yrgb_gather_num = 3; - u16 cbcr_gather_num = 1; - - switch (win->area[0].format) { - case XRGB888: - case ARGB888: - case XBGR888: - case ABGR888: - case FBDC_ARGB_888: - case FBDC_RGBX_888: - case FBDC_ABGR_888: - yrgb_gather_num = 3; - break; - case RGB888: - case BGR888: - case RGB565: - case BGR565: - case FBDC_RGB_565: - yrgb_gather_num = 2; - break; - case YUV444: - case YUV422: - case YUV420: - case YUV420_A: - case YUV422_A: - case YUV444_A: - case YUV420_NV21: - case YUYV420: - case UYVY420: - yrgb_gather_num = 1; - cbcr_gather_num = 2; - break; - case YUYV422: - case UYVY422: - yrgb_gather_num = 2; - cbcr_gather_num = 2; - break; - default: - dev_err(vop_dev->driver.dev, "%s:un supported format[%d]\n", - __func__, win->area[0].format); - return -EINVAL; - } - - if ((win->id == VOP_WIN0) || (win->id == VOP_WIN1)) { - val = V_WIN0_YRGB_AXI_GATHER_EN(1) | - V_WIN0_CBR_AXI_GATHER_EN(1) | - V_WIN0_YRGB_AXI_GATHER_NUM(yrgb_gather_num) | - V_WIN0_CBR_AXI_GATHER_NUM(cbcr_gather_num); - vop_msk_reg(vop_dev, WIN0_CTRL1 + (win->id * 0x40), val); - } else if ((win->id == VOP_WIN2) || (win->id == VOP_WIN3)) { - val = V_WIN2_AXI_GATHER_EN(1) | - V_WIN2_AXI_GATHER_NUM(yrgb_gather_num); - vop_msk_reg(vop_dev, WIN2_CTRL1 + ((win->id - 2) * 0x50), val); - } else if (win->id == VOP_HWC) { - val = V_HWC_AXI_GATHER_EN(1) | - V_HWC_AXI_GATHER_NUM(yrgb_gather_num); - vop_msk_reg(vop_dev, HWC_CTRL1, val); - } - return 0; -} - -static int vop_fbdc_reg_update(struct vop_device *vop_dev, int win_id) -{ - struct rk_lcdc_win *win = vop_dev->driver.win[win_id]; - u64 val; - - val = V_VOP_FBDC_WIN_SEL(win_id) | - V_AFBCD_HREG_PIXEL_PACKING_FMT(win->area[0].fbdc_fmt_cfg) | - V_AFBCD_HREG_BLOCK_SPLIT(win->area[0].fbdc_cor_en); - vop_msk_reg(vop_dev, AFBCD0_CTRL, val); - - val = V_AFBCD_HREG_PIC_WIDTH(win->area[0].fbdc_mb_width - 1) | - V_AFBCD_HREG_PIC_HEIGHT(win->area[0].fbdc_mb_height - 1); - vop_msk_reg(vop_dev, AFBCD0_PIC_SIZE, val); - - return 0; -} - -static int vop_init_fbdc_config(struct vop_device *vop_dev, int win_id) -{ - struct rk_lcdc_driver *vop_drv = &vop_dev->driver; - struct rk_lcdc_win *win = vop_drv->win[win_id]; - struct rk_screen *screen = vop_drv->cur_screen; - - if (screen->mode.flag & FB_VMODE_INTERLACED) { - dev_err(vop_dev->dev, "unsupport fbdc+interlace!\n"); - return 0; - } - - if (VOP_CHIP(vop_dev) != VOP_RK3399) { - pr_err("soc: 0x%08x not support FBDC\n", VOP_CHIP(vop_dev)); - return 0; - } - - win->area[0].fbdc_mb_width = win->area[0].xvir; - win->area[0].fbdc_mb_height = win->area[0].yact; - win->area[0].fbdc_cor_en = 0; /* hreg_block_split */ - win->area[0].fbdc_fmt_cfg |= AFBDC_YUV_COLOR_TRANSFORM << 4; - - return 0; -} - -static int vop_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - u64 val; - u32 off; - int format; - struct rk_win_property *win_property = - &dev_drv->win[win_id]->property; - - off = win_id * 0x40; - - if (win->state == 1) { - if (!(win_property->feature & SUPPORT_HW_EXIST)) { - pr_err("vop[%d] win[%d] hardware unsupport\n", - vop_dev->id, win_id); - return 0; - } - vop_axi_gather_cfg(vop_dev, win); - if (win->area[0].fbdc_en) - vop_fbdc_reg_update(vop_dev, win_id); - /* - * rk322x have a bug on windows 0 and 1: - * - * When switch win format from RGB to YUV, would flash - * some green lines on the top of the windows. - * - * Use bg_en show one blank frame to skip the error frame. - */ - if (IS_YUV(win->area[0].fmt_cfg)) { - val = vop_readl(vop_dev, WIN0_CTRL0); - format = (val & MASK(WIN0_DATA_FMT)) >> 1; - - if (!IS_YUV(format)) { - if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) { - val = V_WIN0_DSP_BG_RED(0x200) | - V_WIN0_DSP_BG_GREEN(0x40) | - V_WIN0_DSP_BG_BLUE(0x200) | - V_WIN0_BG_EN(1); - vop_msk_reg(vop_dev, WIN0_DSP_BG + off, - val); - } else { - val = V_WIN0_DSP_BG_RED(0) | - V_WIN0_DSP_BG_GREEN(0) | - V_WIN0_DSP_BG_BLUE(0) | - V_WIN0_BG_EN(1); - vop_msk_reg(vop_dev, WIN0_DSP_BG + off, - val); - } - } else { - val = V_WIN0_BG_EN(0); - vop_msk_reg(vop_dev, WIN0_DSP_BG + off, val); - } - } else { - val = V_WIN0_BG_EN(0); - vop_msk_reg(vop_dev, WIN0_DSP_BG + off, val); - } - - val = V_WIN0_EN(win->state) | - V_WIN0_DATA_FMT(win->area[0].fmt_cfg) | - V_WIN0_FMT_10(win->fmt_10) | - V_WIN0_LB_MODE(win->win_lb_mode) | - V_WIN0_RB_SWAP(win->area[0].swap_rb) | - V_WIN0_X_MIR_EN(win->xmirror) | - V_WIN0_Y_MIR_EN(win->ymirror) | - V_WIN0_UV_SWAP(win->area[0].swap_uv); - if (VOP_CHIP(vop_dev) == VOP_RK3399) - val |= V_WIN0_YUYV(win->area[0].yuyv_fmt); - vop_msk_reg(vop_dev, WIN0_CTRL0 + off, val); - val = V_WIN0_BIC_COE_SEL(win->bic_coe_el) | - V_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) | - V_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) | - V_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) | - V_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) | - V_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) | - V_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) | - V_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) | - V_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) | - V_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) | - V_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) | - V_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) | - V_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) | - V_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) | - V_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode); - vop_msk_reg(vop_dev, WIN0_CTRL1 + off, val); - val = V_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) | - V_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride); - vop_writel(vop_dev, WIN0_VIR + off, val); - val = V_WIN0_ACT_WIDTH(win->area[0].xact - 1) | - V_WIN0_ACT_HEIGHT(win->area[0].yact - 1); - vop_writel(vop_dev, WIN0_ACT_INFO + off, val); - - val = V_WIN0_DSP_WIDTH(win->area[0].xsize - 1) | - V_WIN0_DSP_HEIGHT(win->area[0].ysize - 1); - vop_writel(vop_dev, WIN0_DSP_INFO + off, val); - - val = V_WIN0_DSP_XST(win->area[0].dsp_stx) | - V_WIN0_DSP_YST(win->area[0].dsp_sty); - vop_writel(vop_dev, WIN0_DSP_ST + off, val); - - val = V_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) | - V_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y); - vop_writel(vop_dev, WIN0_SCL_FACTOR_YRGB + off, val); - - val = V_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) | - V_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y); - vop_writel(vop_dev, WIN0_SCL_FACTOR_CBR + off, val); - } else { - val = V_WIN0_EN(win->state); - vop_msk_reg(vop_dev, WIN0_CTRL0 + off, val); - } - - return 0; -} - -static int area_xst(struct rk_lcdc_win *win, int area_num) -{ - struct rk_lcdc_win_area area_temp; - int i, j; - - for (i = 0; i < area_num; i++) { - for (j = i + 1; j < area_num; j++) { - if (win->area[i].dsp_stx > win->area[j].dsp_stx) { - memcpy(&area_temp, &win->area[i], - sizeof(struct rk_lcdc_win_area)); - memcpy(&win->area[i], &win->area[j], - sizeof(struct rk_lcdc_win_area)); - memcpy(&win->area[j], &area_temp, - sizeof(struct rk_lcdc_win_area)); - } - } - } - - return 0; -} - -static int vop_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - unsigned int off; - u64 val; - struct rk_win_property *win_property = - &dev_drv->win[win_id]->property; - - off = (win_id - 2) * 0x50; - area_xst(win, win->area_num); - - if (win->state == 1) { - if (!(win_property->feature & SUPPORT_HW_EXIST)) { - pr_err("vop[%d] win[%d] hardware unsupport\n", - vop_dev->id, win_id); - return 0; - } - vop_axi_gather_cfg(vop_dev, win); - if (win->area[0].fbdc_en) - vop_fbdc_reg_update(vop_dev, win_id); - val = V_WIN2_EN(1) | V_WIN1_CSC_MODE(win->csc_mode); - vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val); - /* area 0 */ - if (win->area[0].state == 1) { - val = V_WIN2_MST0_EN(win->area[0].state) | - V_WIN2_DATA_FMT0(win->area[0].fmt_cfg) | - V_WIN2_RB_SWAP0(win->area[0].swap_rb); - vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val); - - val = V_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride); - vop_msk_reg(vop_dev, WIN2_VIR0_1 + off, val); - - val = V_WIN2_DSP_WIDTH0(win->area[0].xsize - 1) | - V_WIN2_DSP_HEIGHT0(win->area[0].ysize - 1); - vop_writel(vop_dev, WIN2_DSP_INFO0 + off, val); - val = V_WIN2_DSP_XST0(win->area[0].dsp_stx) | - V_WIN2_DSP_YST0(win->area[0].dsp_sty); - vop_writel(vop_dev, WIN2_DSP_ST0 + off, val); - } else { - val = V_WIN2_MST0_EN(0); - vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val); - } - /* area 1 */ - if (win->area[1].state == 1) { - val = V_WIN2_MST1_EN(win->area[1].state) | - V_WIN2_DATA_FMT1(win->area[1].fmt_cfg) | - V_WIN2_RB_SWAP1(win->area[1].swap_rb); - vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val); - - val = V_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride); - vop_msk_reg(vop_dev, WIN2_VIR0_1 + off, val); - - val = V_WIN2_DSP_WIDTH1(win->area[1].xsize - 1) | - V_WIN2_DSP_HEIGHT1(win->area[1].ysize - 1); - vop_writel(vop_dev, WIN2_DSP_INFO1 + off, val); - val = V_WIN2_DSP_XST1(win->area[1].dsp_stx) | - V_WIN2_DSP_YST1(win->area[1].dsp_sty); - vop_writel(vop_dev, WIN2_DSP_ST1 + off, val); - } else { - val = V_WIN2_MST1_EN(0); - vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val); - } - /* area 2 */ - if (win->area[2].state == 1) { - val = V_WIN2_MST2_EN(win->area[2].state) | - V_WIN2_DATA_FMT2(win->area[2].fmt_cfg) | - V_WIN2_RB_SWAP2(win->area[2].swap_rb); - vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val); - - val = V_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride); - vop_msk_reg(vop_dev, WIN2_VIR2_3 + off, val); - - val = V_WIN2_DSP_WIDTH2(win->area[2].xsize - 1) | - V_WIN2_DSP_HEIGHT2(win->area[2].ysize - 1); - vop_writel(vop_dev, WIN2_DSP_INFO2 + off, val); - val = V_WIN2_DSP_XST2(win->area[2].dsp_stx) | - V_WIN2_DSP_YST2(win->area[2].dsp_sty); - vop_writel(vop_dev, WIN2_DSP_ST2 + off, val); - } else { - val = V_WIN2_MST2_EN(0); - vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val); - } - /* area 3 */ - if (win->area[3].state == 1) { - val = V_WIN2_MST3_EN(win->area[3].state) | - V_WIN2_DATA_FMT3(win->area[3].fmt_cfg) | - V_WIN2_RB_SWAP3(win->area[3].swap_rb); - vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val); - - val = V_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride); - vop_msk_reg(vop_dev, WIN2_VIR2_3 + off, val); - - val = V_WIN2_DSP_WIDTH3(win->area[3].xsize - 1) | - V_WIN2_DSP_HEIGHT3(win->area[3].ysize - 1); - vop_writel(vop_dev, WIN2_DSP_INFO3 + off, val); - val = V_WIN2_DSP_XST3(win->area[3].dsp_stx) | - V_WIN2_DSP_YST3(win->area[3].dsp_sty); - vop_writel(vop_dev, WIN2_DSP_ST3 + off, val); - } else { - val = V_WIN2_MST3_EN(0); - vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val); - } - } else { - val = V_WIN2_EN(win->state) | V_WIN2_MST0_EN(0) | - V_WIN2_MST1_EN(0) | V_WIN2_MST2_EN(0) | V_WIN2_MST3_EN(0); - vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val); - } - - return 0; -} - -static int vop_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - unsigned int hwc_size = 0; - u64 val; - - if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32)) { - hwc_size = 0; - } else if ((win->area[0].xsize == 64) && (win->area[0].ysize == 64)) { - hwc_size = 1; - } else if ((win->area[0].xsize == 96) && (win->area[0].ysize == 96)) { - hwc_size = 2; - } else if ((win->area[0].xsize == 128) && - (win->area[0].ysize == 128)) { - hwc_size = 3; - } else { - dev_err(vop_dev->dev, "un supported hwc size[%dx%d]!\n", - win->area[0].xsize, win->area[0].ysize); - return -EINVAL; - } - - if (win->state == 1) { - vop_axi_gather_cfg(vop_dev, win); - val = V_HWC_EN(1) | V_HWC_DATA_FMT(win->area[0].fmt_cfg) | - V_HWC_RB_SWAP(win->area[0].swap_rb); - vop_msk_reg(vop_dev, HWC_CTRL0, val); - - val = V_HWC_SIZE(hwc_size); - vop_msk_reg(vop_dev, HWC_CTRL0, val); - - val = V_HWC_DSP_XST(win->area[0].dsp_stx) | - V_HWC_DSP_YST(win->area[0].dsp_sty); - vop_msk_reg(vop_dev, HWC_DSP_ST, val); - } else { - val = V_HWC_EN(win->state); - vop_msk_reg(vop_dev, HWC_CTRL0, val); - } - - return 0; -} - -static int vop_layer_update_regs(struct vop_device *vop_dev, - struct rk_lcdc_win *win) -{ - struct rk_lcdc_driver *dev_drv = &vop_dev->driver; - - if (likely(vop_dev->clk_on)) { - vop_msk_reg(vop_dev, SYS_CTRL, - V_VOP_STANDBY_EN(vop_dev->standby)); - if ((win->id == VOP_WIN0) || (win->id == VOP_WIN1)) - vop_win_0_1_reg_update(dev_drv, win->id); - else if ((win->id == VOP_WIN2) || (win->id == VOP_WIN3)) - vop_win_2_3_reg_update(dev_drv, win->id); - else if (win->id == VOP_HWC) - vop_hwc_reg_update(dev_drv, win->id); - vop_cfg_done(vop_dev); - } - - DBG(2, "%s for lcdc%d\n", __func__, vop_dev->id); - return 0; -} - -static int __maybe_unused vop_mmu_en(struct rk_lcdc_driver *dev_drv) -{ - u64 val; - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - - if (unlikely(!vop_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on); - return 0; - } - if (dev_drv->iommu_enabled) { - if (!vop_dev->iommu_status && dev_drv->mmu_dev) { - if (likely(vop_dev->clk_on)) { - val = V_VOP_MMU_EN(1); - vop_msk_reg(vop_dev, SYS_CTRL, val); - val = V_AXI_OUTSTANDING_MAX_NUM(31) | - V_AXI_MAX_OUTSTANDING_EN(1); - vop_msk_reg(vop_dev, SYS_CTRL1, val); - } - vop_dev->iommu_status = 1; - rockchip_iovmm_activate(dev_drv->dev); - } - } - return 0; -} - -static int vop_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate) -{ - int ret = 0, fps = 0; - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; -#ifdef CONFIG_RK_FPGA - return 0; -#endif - if (reset_rate) - ret = clk_set_rate(vop_dev->dclk, screen->mode.pixclock); - if (ret) - dev_err(dev_drv->dev, "set lcdc%d dclk[%d] failed\n", - vop_dev->id, screen->mode.pixclock); - vop_dev->pixclock = - div_u64(1000000000000llu, clk_get_rate(vop_dev->dclk)); - vop_dev->driver.pixclock = vop_dev->pixclock; - - fps = rk_fb_calc_fps(screen, vop_dev->pixclock); - screen->ft = 1000 / fps; - dev_info(vop_dev->dev, "%s: dclk:%lu>>fps:%d ", - vop_dev->driver.name, clk_get_rate(vop_dev->dclk), fps); - return 0; -} - -static int vop_config_timing(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u16 hsync_len = screen->mode.hsync_len; - u16 left_margin = screen->mode.left_margin; - u16 right_margin = screen->mode.right_margin; - u16 vsync_len = screen->mode.vsync_len; - u16 upper_margin = screen->mode.upper_margin; - u16 lower_margin = screen->mode.lower_margin; - u16 x_res = screen->mode.xres; - u16 y_res = screen->mode.yres; - u64 val; - u16 h_total, v_total; - u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1; - - h_total = hsync_len + left_margin + x_res + right_margin; - v_total = vsync_len + upper_margin + y_res + lower_margin; - - val = V_DSP_HS_END(hsync_len) | V_DSP_HTOTAL(h_total); - vop_msk_reg(vop_dev, DSP_HTOTAL_HS_END, val); - - val = V_DSP_HACT_END(hsync_len + left_margin + x_res) | - V_DSP_HACT_ST(hsync_len + left_margin); - vop_msk_reg(vop_dev, DSP_HACT_ST_END, val); - - if (screen->mode.vmode & FB_VMODE_INTERLACED) { - /* First Field Timing */ - val = V_DSP_VS_END(vsync_len) | - V_DSP_VTOTAL(2 * (vsync_len + upper_margin + - lower_margin) + y_res + 1); - vop_msk_reg(vop_dev, DSP_VTOTAL_VS_END, val); - - val = V_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) | - V_DSP_VACT_ST(vsync_len + upper_margin); - vop_msk_reg(vop_dev, DSP_VACT_ST_END, val); - - /* Second Field Timing */ - vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin; - vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 + - lower_margin; - val = V_DSP_VS_ST_F1(vs_st_f1) | V_DSP_VS_END_F1(vs_end_f1); - vop_msk_reg(vop_dev, DSP_VS_ST_END_F1, val); - - vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res + - lower_margin + 1; - vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 + - lower_margin + 1; - val = V_DSP_VACT_END_F1(vact_end_f1) | - V_DSP_VACT_ST_F1(vact_st_f1); - vop_msk_reg(vop_dev, DSP_VACT_ST_END_F1, val); - vop_msk_reg(vop_dev, DSP_CTRL0, - V_DSP_INTERLACE(1) | V_DSP_FIELD_POL(0)); - - val = V_DSP_LINE_FLAG_NUM_0(lower_margin ? - vact_end_f1 : vact_end_f1 - 1); - - val |= V_DSP_LINE_FLAG_NUM_1(lower_margin ? - vact_end_f1 : vact_end_f1 - 1); - vop_msk_reg(vop_dev, LINE_FLAG, val); - } else { - val = V_DSP_VS_END(vsync_len) | V_DSP_VTOTAL(v_total); - vop_msk_reg(vop_dev, DSP_VTOTAL_VS_END, val); - - val = V_DSP_VACT_END(vsync_len + upper_margin + y_res) | - V_DSP_VACT_ST(vsync_len + upper_margin); - vop_msk_reg(vop_dev, DSP_VACT_ST_END, val); - - vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_INTERLACE(0) | - V_DSP_FIELD_POL(0)); - - val = V_DSP_LINE_FLAG_NUM_0(vsync_len + upper_margin + y_res) | - V_DSP_LINE_FLAG_NUM_1(vsync_len + upper_margin + y_res); - vop_msk_reg(vop_dev, LINE_FLAG, val); - } - vop_post_cfg(dev_drv); - if ((x_res <= VOP_INPUT_MAX_WIDTH / 2) && (vop_dev->id == 0)) - vop_msk_reg(vop_dev, SYS_CTRL, V_POST_LB_MODE(1)); - else - vop_msk_reg(vop_dev, SYS_CTRL, V_POST_LB_MODE(0)); - - return 0; -} - -static void vop_bcsh_path_sel(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - u32 bcsh_ctrl; - - vop_msk_reg(vop_dev, SYS_CTRL, V_OVERLAY_MODE(dev_drv->overlay_mode)); - if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) { - if (IS_YUV_COLOR(dev_drv->output_color)) /* bypass */ - vop_msk_reg(vop_dev, BCSH_CTRL, - V_BCSH_Y2R_EN(0) | V_BCSH_R2Y_EN(0)); - else /* YUV2RGB */ - vop_msk_reg(vop_dev, BCSH_CTRL, V_BCSH_Y2R_EN(1) | - V_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) | - V_BCSH_R2Y_EN(0)); - } else { - /* overlay_mode=VOP_RGB_DOMAIN */ - /* bypass --need check,if bcsh close? */ - if (dev_drv->output_color == COLOR_RGB) { - bcsh_ctrl = vop_readl(vop_dev, BCSH_CTRL); - if (((bcsh_ctrl & MASK(BCSH_EN)) == 1) || - (dev_drv->bcsh.enable == 1))/*bcsh enabled */ - vop_msk_reg(vop_dev, BCSH_CTRL, - V_BCSH_R2Y_EN(1) | - V_BCSH_Y2R_EN(1)); - else - vop_msk_reg(vop_dev, BCSH_CTRL, - V_BCSH_R2Y_EN(0) | - V_BCSH_Y2R_EN(0)); - } else { - /* RGB2YUV */ - vop_msk_reg(vop_dev, BCSH_CTRL, - V_BCSH_R2Y_EN(1) | - V_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) | - V_BCSH_Y2R_EN(0)); - } - } -} - -static int vop_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact, - u16 *yact, int *format, u32 *dsp_addr, - int *ymirror) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - u32 val; - - spin_lock(&vop_dev->reg_lock); - - val = vop_readl(vop_dev, WIN0_ACT_INFO); - *xact = (val & MASK(WIN0_ACT_WIDTH)) + 1; - *yact = ((val & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1; - - val = vop_readl(vop_dev, WIN0_CTRL0); - *format = (val & MASK(WIN0_DATA_FMT)) >> 1; - *ymirror = (val & MASK(WIN0_Y_MIR_EN)) >> 22; - *dsp_addr = vop_readl(vop_dev, WIN0_YRGB_MST); - - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst, - int format, u16 xact, u16 yact, u16 xvir, - int ymirror) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - int swap = (format == RGB888) ? 1 : 0; - struct rk_lcdc_win *win = dev_drv->win[0]; - u64 val; - - val = V_WIN0_DATA_FMT(format) | V_WIN0_RB_SWAP(swap) | - V_WIN0_Y_MIR_EN(ymirror); - vop_msk_reg(vop_dev, WIN0_CTRL0, val); - - vop_msk_reg(vop_dev, WIN0_VIR, V_WIN0_VIR_STRIDE(xvir)); - vop_writel(vop_dev, WIN0_ACT_INFO, V_WIN0_ACT_WIDTH(xact - 1) | - V_WIN0_ACT_HEIGHT(yact - 1)); - - vop_writel(vop_dev, WIN0_YRGB_MST, rgb_mst); - - vop_cfg_done(vop_dev); - - if (format == RGB888) - win->area[0].format = BGR888; - else - win->area[0].format = format; - - win->ymirror = ymirror; - win->state = 1; - win->last_state = 1; - - return 0; -} - -static int vop_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen) -{ - u16 face = 0; - u16 dclk_ddr = 0; - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u64 val = 0; - - if (unlikely(!vop_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on); - return 0; - } - - if (!vop_dev->standby && initscreen && (dev_drv->first_frame != 1)) - flush_kthread_worker(&dev_drv->update_regs_worker); - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - switch (screen->face) { - case OUT_P565: - face = OUT_P565; - val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) | - V_PRE_DITHER_DOWN_EN(1) | - V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(0); - break; - case OUT_P666: - face = OUT_P666; - val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) | - V_PRE_DITHER_DOWN_EN(1) | - V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(1); - break; - case OUT_D888_P565: - face = OUT_P888; - val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) | - V_PRE_DITHER_DOWN_EN(1) | - V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(0); - break; - case OUT_D888_P666: - face = OUT_P888; - val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) | - V_PRE_DITHER_DOWN_EN(1) | - V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(1); - break; - case OUT_P888: - face = OUT_P888; - val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) - | V_PRE_DITHER_DOWN_EN(1) | - V_DITHER_DOWN_SEL(0) | V_DITHER_DOWN_MODE(0); - break; - case OUT_S888x: - face = OUT_S888x; - val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) - | V_PRE_DITHER_DOWN_EN(1) | - V_DITHER_DOWN_SEL(0) | V_DITHER_DOWN_MODE(0); - break; - case OUT_S888: - face = OUT_S888; - val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) - | V_PRE_DITHER_DOWN_EN(1) | - V_DITHER_DOWN_SEL(0) | V_DITHER_DOWN_MODE(0); - break; - case OUT_YUV_420: - face = OUT_YUV_420; - dclk_ddr = 1; - val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) | - V_PRE_DITHER_DOWN_EN(1) | - V_DITHER_DOWN_SEL(0) | - V_DITHER_DOWN_MODE(0); - break; - case OUT_YUV_420_10BIT: - face = OUT_YUV_420; - dclk_ddr = 1; - val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) | - V_PRE_DITHER_DOWN_EN(0) | - V_DITHER_DOWN_SEL(0) | - V_DITHER_DOWN_MODE(0); - break; - case OUT_YUV_422: - face = OUT_YUV_422; - val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) | - V_PRE_DITHER_DOWN_EN(1) | - V_DITHER_DOWN_SEL(0) | - V_DITHER_DOWN_MODE(0); - break; - case OUT_YUV_422_10BIT: - face = OUT_YUV_422; - val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) | - V_PRE_DITHER_DOWN_EN(0) | - V_DITHER_DOWN_SEL(0) | - V_DITHER_DOWN_MODE(0); - break; - case OUT_P101010: - face = OUT_P101010; - val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) | - V_PRE_DITHER_DOWN_EN(0) | - V_DITHER_DOWN_SEL(0) | - V_DITHER_DOWN_MODE(0); - break; - default: - dev_err(vop_dev->dev, "un supported screen face[%d]!\n", - screen->face); - break; - } - - vop_msk_reg(vop_dev, DSP_CTRL1, val); - switch (screen->type) { - case SCREEN_TVOUT: - val = V_SW_UV_OFFSET_EN(1) | V_SW_IMD_TVE_DCLK_EN(1) | - V_SW_IMD_TVE_DCLK_EN(1) | - V_SW_IMD_TVE_DCLK_POL(1) | - V_SW_GENLOCK(1) | V_SW_DAC_SEL(1); - if (screen->mode.xres == 720 && - screen->mode.yres == 576) - val |= V_SW_TVE_MODE(1); - else - val |= V_SW_TVE_MODE(0); - vop_msk_reg(vop_dev, SYS_CTRL, val); - break; - case SCREEN_HDMI: - if ((VOP_CHIP(vop_dev) == VOP_RK3399) && - ((screen->face == OUT_P888) || - (screen->face == OUT_P101010))) { - if (vop_dev->id == 0) - face = OUT_P101010; /*RGB 10bit output*/ - else - face = OUT_P888; - } - val = V_HDMI_OUT_EN(1) | V_SW_UV_OFFSET_EN(0); - vop_msk_reg(vop_dev, SYS_CTRL, val); - val = V_HDMI_HSYNC_POL(screen->pin_hsync) | - V_HDMI_VSYNC_POL(screen->pin_vsync) | - V_HDMI_DEN_POL(screen->pin_den) | - V_HDMI_DCLK_POL(screen->pin_dclk); - /*hsync vsync den dclk polo,dither */ - vop_msk_reg(vop_dev, DSP_CTRL1, val); - break; - case SCREEN_RGB: - case SCREEN_LVDS: - val = V_RGB_OUT_EN(1); - vop_msk_reg(vop_dev, SYS_CTRL, val); - break; - case SCREEN_MIPI: - val = V_MIPI_OUT_EN(1); - vop_msk_reg(vop_dev, SYS_CTRL, val); - val = V_MIPI_HSYNC_POL(screen->pin_hsync) | - V_MIPI_VSYNC_POL(screen->pin_vsync) | - V_MIPI_DEN_POL(screen->pin_den) | - V_MIPI_DCLK_POL(screen->pin_dclk); - /*hsync vsync den dclk polo,dither */ - vop_msk_reg(vop_dev, DSP_CTRL1, val); - break; - case SCREEN_DUAL_MIPI: - val = V_MIPI_OUT_EN(1) | V_MIPI_DUAL_CHANNEL_EN(1); - vop_msk_reg(vop_dev, SYS_CTRL, val); - val = V_MIPI_HSYNC_POL(screen->pin_hsync) | - V_MIPI_VSYNC_POL(screen->pin_vsync) | - V_MIPI_DEN_POL(screen->pin_den) | - V_MIPI_DCLK_POL(screen->pin_dclk); - /*hsync vsync den dclk polo,dither */ - vop_msk_reg(vop_dev, DSP_CTRL1, val); - break; - case SCREEN_EDP: - if (VOP_CHIP(vop_dev) == VOP_RK3399) { - if (vop_dev->id == 0) - face = OUT_P101010; - else - face = OUT_P888; - } - val = V_EDP_OUT_EN(1); - vop_msk_reg(vop_dev, SYS_CTRL, val); - val = V_EDP_HSYNC_POL(screen->pin_hsync) | - V_EDP_VSYNC_POL(screen->pin_vsync) | - V_EDP_DEN_POL(screen->pin_den) | - V_EDP_DCLK_POL(screen->pin_dclk); - /*hsync vsync den dclk polo,dither */ - vop_msk_reg(vop_dev, DSP_CTRL1, val); - break; - case SCREEN_DP: - dclk_ddr = 0; - if ((VOP_CHIP(vop_dev) == VOP_RK3399) && - ((screen->face == OUT_P888) || - (screen->face == OUT_P101010))) { - if (vop_dev->id == 0) - face = OUT_P101010; - else - face = OUT_P888; - } - val = V_DP_OUT_EN(1); - vop_msk_reg(vop_dev, SYS_CTRL, val); - val = V_DP_HSYNC_POL(screen->pin_hsync) | - V_DP_VSYNC_POL(screen->pin_vsync) | - V_DP_DEN_POL(screen->pin_den) | - V_DP_DCLK_POL(screen->pin_dclk); - /*hsync vsync den dclk polo,dither */ - vop_msk_reg(vop_dev, DSP_CTRL1, val); - break; - default: - dev_err(vop_dev->dev, "un supported interface[%d]!\n", - screen->type); - break; - } - - if (screen->color_mode == COLOR_RGB) - dev_drv->overlay_mode = VOP_RGB_DOMAIN; - else - dev_drv->overlay_mode = VOP_YUV_DOMAIN; - -#ifndef CONFIG_RK_FPGA - /* - * Todo: - * writel_relaxed(v, RK_GRF_VIRT + vop_GRF_SOC_CON7); - * move to lvds driver - */ - /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */ -#endif - val = V_DSP_OUT_MODE(face) | V_DSP_DCLK_DDR(dclk_ddr) | - V_DSP_BG_SWAP(screen->swap_gb) | - V_DSP_RB_SWAP(screen->swap_rb) | - V_DSP_RG_SWAP(screen->swap_rg) | - V_DSP_DELTA_SWAP(screen->swap_delta) | - V_DSP_DUMMY_SWAP(screen->swap_dumy) | V_DSP_OUT_ZERO(0) | - V_DSP_BLANK_EN(0) | V_DSP_BLACK_EN(0) | - V_DSP_X_MIR_EN(screen->x_mirror) | - V_DSP_Y_MIR_EN(screen->y_mirror); - val |= V_SW_CORE_DCLK_SEL(!!screen->pixelrepeat); - if (screen->mode.vmode & FB_VMODE_INTERLACED) - val |= V_SW_HDMI_CLK_I_SEL(1); - else - val |= V_SW_HDMI_CLK_I_SEL(0); - vop_msk_reg(vop_dev, DSP_CTRL0, val); - - if (screen->mode.vmode & FB_VMODE_INTERLACED) - vop_msk_reg(vop_dev, SYS_CTRL1, V_REG_DONE_FRM(1)); - else - vop_msk_reg(vop_dev, SYS_CTRL1, V_REG_DONE_FRM(0)); - /* BG color */ - if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) { - val = V_DSP_OUT_RGB_YUV(1); - vop_msk_reg(vop_dev, POST_SCL_CTRL, val); - val = V_DSP_BG_BLUE(0x200) | V_DSP_BG_GREEN(0x40) | - V_DSP_BG_RED(0x200); - vop_msk_reg(vop_dev, DSP_BG, val); - } else { - val = V_DSP_OUT_RGB_YUV(0); - vop_msk_reg(vop_dev, POST_SCL_CTRL, val); - val = V_DSP_BG_BLUE(0x55) | V_DSP_BG_GREEN(0x55) | - V_DSP_BG_RED(0x55); - vop_msk_reg(vop_dev, DSP_BG, val); - } - dev_drv->output_color = screen->color_mode; - vop_bcsh_path_sel(dev_drv); - vop_config_timing(dev_drv); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - vop_set_dclk(dev_drv, 1); - if (screen->type != SCREEN_HDMI && screen->type != SCREEN_TVOUT && - dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - if (screen->init) - screen->init(); - - return 0; -} - -static int vop_early_suspend(struct rk_lcdc_driver *dev_drv); -static int vop_early_resume(struct rk_lcdc_driver *dev_drv); -/*enable layer,open:1,enable;0 disable*/ -static void vop_layer_enable(struct vop_device *vop_dev, - unsigned int win_id, bool open) -{ - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on) && - vop_dev->driver.win[win_id]->state != open) { - if (open) { - if (!vop_dev->atv_layer_cnt) { - dev_info(vop_dev->dev, - "wakeup from standby!\n"); - vop_dev->standby = 0; - } - vop_dev->atv_layer_cnt |= (1 << win_id); - } else { - if (vop_dev->atv_layer_cnt & (1 << win_id)) - vop_dev->atv_layer_cnt &= ~(1 << win_id); - } - vop_dev->driver.win[win_id]->state = open; - if (!open) { - vop_layer_update_regs(vop_dev, - vop_dev->driver.win[win_id]); - vop_cfg_done(vop_dev); - } - } - spin_unlock(&vop_dev->reg_lock); - /* if no layer used,disable lcdc */ - if (vop_dev->prop == EXTEND) { - if (!vop_dev->atv_layer_cnt && !open) { - if (!wait_event_timeout(vop_dev->wait_dmc_queue, - !vop_dev->dmc_in_process, HZ / 5)) - dev_warn(vop_dev->dev, - "Timeout waiting for dmc when vop disable\n"); - - vop_dev->vop_switch_status = 1; - vop_early_suspend(&vop_dev->driver); - dev_info(vop_dev->dev, - "no layer is used,go to standby!\n"); - vop_dev->standby = 1; - - vop_dev->vop_switch_status = 0; - wake_up(&vop_dev->wait_vop_switch_queue); - /* - * if clsoe enxtend vop need to enable dmc again. - */ - if (vop_dev->devfreq) { - if (vop_dev->devfreq_event_dev) - devfreq_event_enable_edev(vop_dev->devfreq_event_dev); - devfreq_resume_device(vop_dev->devfreq); - } - } else if (open) { - vop_early_resume(&vop_dev->driver); - vop_dev->vop_switch_status = 0; - wake_up(&vop_dev->wait_vop_switch_queue); - /* if enable two vop, need to disable dmc */ - if (vop_dev->devfreq) { - if (vop_dev->devfreq_event_dev) - devfreq_event_disable_edev(vop_dev->devfreq_event_dev); - devfreq_suspend_device(vop_dev->devfreq); - } - dev_info(vop_dev->dev, "wake up from standby!\n"); - } - } else if (vop_dev->prop == PRMRY) { - if ((open) && (!vop_dev->atv_layer_cnt)) { - vop_dev->vop_switch_status = 0; - wake_up(&vop_dev->wait_vop_switch_queue); - } - } -} - -static int vop_enable_irq(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = container_of(dev_drv, - struct vop_device, driver); - u64 val; - /* struct rk_screen *screen = dev_drv->cur_screen; */ - - vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, INTR_MASK); - - val = INTR_FS | INTR_LINE_FLAG0 | INTR_BUS_ERROR | INTR_LINE_FLAG1 | - INTR_WIN0_EMPTY | INTR_WIN1_EMPTY | INTR_HWC_EMPTY | - INTR_POST_BUF_EMPTY; - val |= val << 16; - - vop_msk_reg(vop_dev, INTR_EN0, val); - - return 0; -} - -static int dmc_notify(struct notifier_block *nb, unsigned long event, - void *data) -{ - struct vop_device *vop = container_of(nb, struct vop_device, dmc_nb); - - if (event == DEVFREQ_PRECHANGE) { - - /* - * check if vop in enable or disable process, - * if yes, wait until it finish, use 200ms as - * timeout. - */ - if (!wait_event_timeout(vop->wait_vop_switch_queue, - !vop->vop_switch_status, HZ / 5)) - dev_warn(vop->dev, - "Timeout waiting for vop swtich status\n"); - vop->dmc_in_process = 1; - } else if (event == DEVFREQ_POSTCHANGE) { - vop->dmc_in_process = 0; - wake_up(&vop->wait_dmc_queue); - } - - return NOTIFY_OK; -} - -static int vop_open(struct rk_lcdc_driver *dev_drv, int win_id, - bool open) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - - if (dev_drv->shutdown_flag) - return 0; - /* enable clk,when first layer open */ - if ((open) && (!vop_dev->atv_layer_cnt)) { - /* rockchip_set_system_status(sys_status); */ - if (!wait_event_timeout(vop_dev->wait_dmc_queue, - !vop_dev->dmc_in_process, HZ / 5)) - dev_warn(vop_dev->dev, - "Timeout waiting for dmc when vop enable\n"); - vop_dev->vop_switch_status = 1; - if (vop_pre_init(dev_drv)) - return -1; - vop_clk_enable(vop_dev); - vop_enable_irq(dev_drv); - if (dev_drv->iommu_enabled) { - if (!dev_drv->mmu_dev) { - dev_drv->mmu_dev = - rk_fb_get_sysmmu_device_by_compatible - (dev_drv->mmu_dts_name); - if (dev_drv->mmu_dev) { - rk_fb_platform_set_sysmmu - (dev_drv->mmu_dev, dev_drv->dev); - } else { - dev_err(dev_drv->dev, - "fail get rk iommu device\n"); - return -1; - } - } - } - if ((support_uboot_display() && (vop_dev->prop == PRMRY))) - vop_set_dclk(dev_drv, 0); - else - vop_load_screen(dev_drv, 1); - if (dev_drv->bcsh.enable) - vop_set_bcsh(dev_drv, 1); - vop_set_lut(dev_drv, dev_drv->cur_screen->dsp_lut); - vop_set_cabc(dev_drv, dev_drv->cur_screen->cabc_lut); - } - - if (win_id < dev_drv->lcdc_win_num) - vop_layer_enable(vop_dev, win_id, open); - else - dev_err(vop_dev->dev, "invalid win id:%d\n", win_id); - - dev_drv->first_frame = 0; - return 0; -} - -static int win_0_1_display(struct vop_device *vop_dev, - struct rk_lcdc_win *win) -{ - u32 y_addr; - u32 uv_addr; - unsigned int off; - - off = win->id * 0x40; - /*win->smem_start + win->y_offset; */ - y_addr = win->area[0].smem_start + win->area[0].y_offset; - uv_addr = win->area[0].cbr_start + win->area[0].c_offset; - DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x", - vop_dev->id, win->id, y_addr, uv_addr); - DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n", - win->area[0].y_offset, win->area[0].c_offset); - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - win->area[0].y_addr = y_addr; - win->area[0].uv_addr = uv_addr; - vop_writel(vop_dev, WIN0_YRGB_MST + off, win->area[0].y_addr); - vop_writel(vop_dev, WIN0_CBR_MST + off, win->area[0].uv_addr); - if (win->area[0].fbdc_en == 1) - vop_writel(vop_dev, AFBCD0_HDR_PTR, - win->area[0].y_addr); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int win_2_3_display(struct vop_device *vop_dev, - struct rk_lcdc_win *win) -{ - u32 i, y_addr; - unsigned int off; - - off = (win->id - 2) * 0x50; - y_addr = win->area[0].smem_start + win->area[0].y_offset; - DBG(2, "lcdc[%d]:win[%d]:", vop_dev->id, win->id); - - if (likely(vop_dev->clk_on)) { - for (i = 0; i < win->area_num; i++) { - DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n", - i, win->area[i].y_addr, win->area[i].y_offset); - win->area[i].y_addr = - win->area[i].smem_start + win->area[i].y_offset; - } - spin_lock(&vop_dev->reg_lock); - vop_writel(vop_dev, WIN2_MST0 + off, win->area[0].y_addr); - vop_writel(vop_dev, WIN2_MST1 + off, win->area[1].y_addr); - vop_writel(vop_dev, WIN2_MST2 + off, win->area[2].y_addr); - vop_writel(vop_dev, WIN2_MST3 + off, win->area[3].y_addr); - if (win->area[0].fbdc_en == 1) - vop_writel(vop_dev, AFBCD0_HDR_PTR, - win->area[0].y_addr); - spin_unlock(&vop_dev->reg_lock); - } - return 0; -} - -static int hwc_display(struct vop_device *vop_dev, struct rk_lcdc_win *win) -{ - u32 y_addr; - - y_addr = win->area[0].smem_start + win->area[0].y_offset; - DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n", - vop_dev->id, __func__, y_addr); - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - win->area[0].y_addr = y_addr; - vop_writel(vop_dev, HWC_MST, win->area[0].y_addr); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_pan_display(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_lcdc_win *win = NULL; - struct rk_screen *screen = dev_drv->cur_screen; - - win = dev_drv->win[win_id]; - if (!screen) { - dev_err(dev_drv->dev, "screen is null!\n"); - return -ENOENT; - } - if (unlikely(!vop_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on); - return 0; - } - if (win_id == 0) { - win_0_1_display(vop_dev, win); - } else if (win_id == 1) { - win_0_1_display(vop_dev, win); - } else if (win_id == 2) { - win_2_3_display(vop_dev, win); - } else if (win_id == 3) { - win_2_3_display(vop_dev, win); - } else if (win_id == 4) { - hwc_display(vop_dev, win); - } else { - dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id); - return -EINVAL; - } - - return 0; -} - -static int vop_cal_scl_fac(struct rk_lcdc_win *win, struct rk_screen *screen) -{ - u16 srcW = 0; - u16 srcH = 0; - u16 dstW = 0; - u16 dstH = 0; - u16 yrgb_srcW = 0; - u16 yrgb_srcH = 0; - u16 yrgb_dstW = 0; - u16 yrgb_dstH = 0; - u32 yrgb_vscalednmult = 0; - u32 yrgb_xscl_factor = 0; - u32 yrgb_yscl_factor = 0; - u8 yrgb_vsd_bil_gt2 = 0; - u8 yrgb_vsd_bil_gt4 = 0; - - u16 cbcr_srcW = 0; - u16 cbcr_srcH = 0; - u16 cbcr_dstW = 0; - u16 cbcr_dstH = 0; - u32 cbcr_vscalednmult = 0; - u32 cbcr_xscl_factor = 0; - u32 cbcr_yscl_factor = 0; - u8 cbcr_vsd_bil_gt2 = 0; - u8 cbcr_vsd_bil_gt4 = 0; - u8 yuv_fmt = 0; - - srcW = win->area[0].xact; - if ((screen->mode.vmode & FB_VMODE_INTERLACED) && - (win->area[0].yact == 2 * win->area[0].ysize)) { - srcH = win->area[0].yact / 2; - yrgb_vsd_bil_gt2 = 1; - cbcr_vsd_bil_gt2 = 1; - } else { - srcH = win->area[0].yact; - } - dstW = win->area[0].xsize; - dstH = win->area[0].ysize; - - /*yrgb scl mode */ - yrgb_srcW = srcW; - yrgb_srcH = srcH; - yrgb_dstW = dstW; - yrgb_dstH = dstH; - if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) { - pr_err("ERROR: yrgb scale exceed 8,"); - pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", - yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH); - } - if (yrgb_srcW < yrgb_dstW) - win->yrgb_hor_scl_mode = SCALE_UP; - else if (yrgb_srcW > yrgb_dstW) - win->yrgb_hor_scl_mode = SCALE_DOWN; - else - win->yrgb_hor_scl_mode = SCALE_NONE; - - if (yrgb_srcH < yrgb_dstH) - win->yrgb_ver_scl_mode = SCALE_UP; - else if (yrgb_srcH > yrgb_dstH) - win->yrgb_ver_scl_mode = SCALE_DOWN; - else - win->yrgb_ver_scl_mode = SCALE_NONE; - - /*cbcr scl mode */ - switch (win->area[0].format) { - case YUV422: - case YUYV422: - case UYVY422: - case YUV422_A: - cbcr_srcW = srcW / 2; - cbcr_dstW = dstW; - cbcr_srcH = srcH; - cbcr_dstH = dstH; - yuv_fmt = 1; - break; - case YUV420: - case YUYV420: - case UYVY420: - case YUV420_A: - case YUV420_NV21: - cbcr_srcW = srcW / 2; - cbcr_dstW = dstW; - cbcr_srcH = srcH / 2; - cbcr_dstH = dstH; - yuv_fmt = 1; - break; - case YUV444: - case YUV444_A: - cbcr_srcW = srcW; - cbcr_dstW = dstW; - cbcr_srcH = srcH; - cbcr_dstH = dstH; - yuv_fmt = 1; - break; - default: - cbcr_srcW = 0; - cbcr_dstW = 0; - cbcr_srcH = 0; - cbcr_dstH = 0; - yuv_fmt = 0; - break; - } - if (yuv_fmt) { - if ((cbcr_dstW * 8 <= cbcr_srcW) || - (cbcr_dstH * 8 <= cbcr_srcH)) { - pr_err("ERROR: cbcr scale exceed 8,"); - pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW, - cbcr_srcH, cbcr_dstW, cbcr_dstH); - } - } - - if (cbcr_srcW < cbcr_dstW) - win->cbr_hor_scl_mode = SCALE_UP; - else if (cbcr_srcW > cbcr_dstW) - win->cbr_hor_scl_mode = SCALE_DOWN; - else - win->cbr_hor_scl_mode = SCALE_NONE; - - if (cbcr_srcH < cbcr_dstH) - win->cbr_ver_scl_mode = SCALE_UP; - else if (cbcr_srcH > cbcr_dstH) - win->cbr_ver_scl_mode = SCALE_DOWN; - else - win->cbr_ver_scl_mode = SCALE_NONE; - - /* line buffer mode */ - if ((win->area[0].format == YUV422) || - (win->area[0].format == YUV420) || - (win->area[0].format == YUYV422) || - (win->area[0].format == YUYV420) || - (win->area[0].format == UYVY422) || - (win->area[0].format == UYVY420) || - (win->area[0].format == YUV420_NV21) || - (win->area[0].format == YUV422_A) || - (win->area[0].format == YUV420_A)) { - if (win->cbr_hor_scl_mode == SCALE_DOWN) { - if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) || - (cbcr_dstW == 0)) - pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n", - cbcr_dstW); - else if (cbcr_dstW > 1280) - win->win_lb_mode = LB_YUV_3840X5; - else - win->win_lb_mode = LB_YUV_2560X8; - } else { /* SCALE_UP or SCALE_NONE */ - if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) || - (cbcr_srcW == 0)) - pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n", - cbcr_srcW); - else if (cbcr_srcW > 1280) - win->win_lb_mode = LB_YUV_3840X5; - else - win->win_lb_mode = LB_YUV_2560X8; - } - } else { - if (win->yrgb_hor_scl_mode == SCALE_DOWN) { - if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) || - (yrgb_dstW == 0)) - pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW); - else if (yrgb_dstW > 2560) - win->win_lb_mode = LB_RGB_3840X2; - else if (yrgb_dstW > 1920) - win->win_lb_mode = LB_RGB_2560X4; - else if (yrgb_dstW > 1280) - win->win_lb_mode = LB_RGB_1920X5; - else - win->win_lb_mode = LB_RGB_1280X8; - } else { /* SCALE_UP or SCALE_NONE */ - if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) || - (yrgb_srcW == 0)) - pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW); - else if (yrgb_srcW > 2560) - win->win_lb_mode = LB_RGB_3840X2; - else if (yrgb_srcW > 1920) - win->win_lb_mode = LB_RGB_2560X4; - else if (yrgb_srcW > 1280) - win->win_lb_mode = LB_RGB_1920X5; - else - win->win_lb_mode = LB_RGB_1280X8; - } - } - DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode); - - /* vsd/vsu scale ALGORITHM */ - win->yrgb_hsd_mode = SCALE_DOWN_BIL; /*not to specify */ - win->cbr_hsd_mode = SCALE_DOWN_BIL; /*not to specify */ - win->yrgb_vsd_mode = SCALE_DOWN_BIL; /*not to specify */ - win->cbr_vsd_mode = SCALE_DOWN_BIL; /*not to specify */ - - /* if (VOP_CHIP(vop_dev) == VOP_RK3399) { */ - if ((win->area[0].format == YUYV422) || - (win->area[0].format == YUYV420) || - (win->area[0].format == UYVY422) || - (win->area[0].format == UYVY420)) { - yrgb_vscalednmult = - vop_get_hard_ware_vskiplines(yrgb_srcH, yrgb_dstH); - if (yrgb_vscalednmult == 4) { - yrgb_vsd_bil_gt4 = 1; - yrgb_vsd_bil_gt2 = 0; - } else if (yrgb_vscalednmult == 2) { - yrgb_vsd_bil_gt4 = 0; - yrgb_vsd_bil_gt2 = 1; - } else { - yrgb_vsd_bil_gt4 = 0; - yrgb_vsd_bil_gt2 = 0; - } - if ((win->area[0].format == YUYV420) || - (win->area[0].format == UYVY420)) { - if ((yrgb_vsd_bil_gt4 == 1) || (yrgb_vsd_bil_gt2 == 1)) - win->yrgb_vsd_mode = SCALE_DOWN_AVG; - } - - cbcr_vscalednmult = - vop_get_hard_ware_vskiplines(cbcr_srcH, cbcr_dstH); - if (cbcr_vscalednmult == 4) { - cbcr_vsd_bil_gt4 = 1; - cbcr_vsd_bil_gt2 = 0; - } else if (cbcr_vscalednmult == 2) { - cbcr_vsd_bil_gt4 = 0; - cbcr_vsd_bil_gt2 = 1; - } else { - cbcr_vsd_bil_gt4 = 0; - cbcr_vsd_bil_gt2 = 0; - } - if ((win->area[0].format == YUYV420) || - (win->area[0].format == UYVY420)) { - if ((cbcr_vsd_bil_gt4 == 1) || (cbcr_vsd_bil_gt2 == 1)) - win->cbr_vsd_mode = SCALE_DOWN_AVG; - } - /* CBCR vsd_mode must same to YRGB for YUYV when gt2 or gt4 */ - if ((cbcr_vsd_bil_gt4 == 1) || (cbcr_vsd_bil_gt2 == 1)) { - if (win->yrgb_vsd_mode != win->cbr_vsd_mode) - win->cbr_vsd_mode = win->yrgb_vsd_mode; - } - } - /* 3399 yuyv support*/ - if (win->ymirror == 1) { - if (win->yrgb_vsd_mode == SCALE_DOWN_AVG) - pr_info("y_mirror enable, y-vsd AVG mode unsupprot\n"); - win->yrgb_vsd_mode = SCALE_DOWN_BIL; - } - if (screen->mode.vmode & FB_VMODE_INTERLACED) { - if (win->yrgb_vsd_mode == SCALE_DOWN_AVG) - pr_info("interlace mode, y-vsd AVG mode unsupprot\n"); - /* interlace mode must bill */ - win->yrgb_vsd_mode = SCALE_DOWN_BIL; - win->cbr_vsd_mode = SCALE_DOWN_BIL; - } - switch (win->win_lb_mode) { - case LB_YUV_3840X5: - case LB_YUV_2560X8: - case LB_RGB_1920X5: - case LB_RGB_1280X8: - win->yrgb_vsu_mode = SCALE_UP_BIC; - win->cbr_vsu_mode = SCALE_UP_BIC; - break; - case LB_RGB_3840X2: - if (win->yrgb_ver_scl_mode != SCALE_NONE) - pr_err("ERROR : not allow yrgb ver scale\n"); - if (win->cbr_ver_scl_mode != SCALE_NONE) - pr_err("ERROR : not allow cbcr ver scale\n"); - break; - case LB_RGB_2560X4: - win->yrgb_vsu_mode = SCALE_UP_BIL; - win->cbr_vsu_mode = SCALE_UP_BIL; - break; - default: - pr_info("%s:un supported win_lb_mode:%d\n", - __func__, win->win_lb_mode); - break; - } - - if ((win->yrgb_ver_scl_mode == SCALE_DOWN) && - (win->area[0].fbdc_en == 1)) { - /* in this pattern,use bil mode,not support souble scd, - * use avg mode, support double scd, but aclk should be - * bigger than dclk. - */ - if (yrgb_srcH >= 2 * yrgb_dstH) { - pr_err("ERROR : fbdc mode,not support y scale down:"); - pr_err("srcH[%d] > 2 *dstH[%d]\n", - yrgb_srcH, yrgb_dstH); - } - } - DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n", - win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode, - win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode); - - /* SCALE FACTOR */ - - /* (1.1)YRGB HOR SCALE FACTOR */ - switch (win->yrgb_hor_scl_mode) { - case SCALE_NONE: - yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT); - break; - case SCALE_UP: - yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW); - break; - case SCALE_DOWN: - switch (win->yrgb_hsd_mode) { - case SCALE_DOWN_BIL: - yrgb_xscl_factor = - GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW); - break; - case SCALE_DOWN_AVG: - yrgb_xscl_factor = - GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW); - break; - default: - pr_info("%s:un supported yrgb_hsd_mode:%d\n", __func__, - win->yrgb_hsd_mode); - break; - } - break; - default: - pr_info("%s:un supported yrgb_hor_scl_mode:%d\n", - __func__, win->yrgb_hor_scl_mode); - break; - } - - /* (1.2)YRGB VER SCALE FACTOR */ - switch (win->yrgb_ver_scl_mode) { - case SCALE_NONE: - yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT); - break; - case SCALE_UP: - switch (win->yrgb_vsu_mode) { - case SCALE_UP_BIL: - yrgb_yscl_factor = - GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH); - break; - case SCALE_UP_BIC: - if (yrgb_srcH < 3) { - pr_err("yrgb_srcH should be"); - pr_err(" greater than 3 !!!\n"); - } - yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH, - yrgb_dstH); - break; - default: - pr_info("%s:un support yrgb_vsu_mode:%d\n", - __func__, win->yrgb_vsu_mode); - break; - } - break; - case SCALE_DOWN: - switch (win->yrgb_vsd_mode) { - case SCALE_DOWN_BIL: - yrgb_vscalednmult = - vop_get_hard_ware_vskiplines(yrgb_srcH, yrgb_dstH); - yrgb_yscl_factor = - GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH, - yrgb_vscalednmult); - if (yrgb_yscl_factor >= 0x2000) { - pr_err("yrgb_yscl_factor should less 0x2000"); - pr_err("yrgb_yscl_factor=%4x;\n", - yrgb_yscl_factor); - } - if (yrgb_vscalednmult == 4) { - yrgb_vsd_bil_gt4 = 1; - yrgb_vsd_bil_gt2 = 0; - } else if (yrgb_vscalednmult == 2) { - yrgb_vsd_bil_gt4 = 0; - yrgb_vsd_bil_gt2 = 1; - } else { - yrgb_vsd_bil_gt4 = 0; - yrgb_vsd_bil_gt2 = 0; - } - break; - case SCALE_DOWN_AVG: - yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH, - yrgb_dstH); - break; - default: - pr_info("%s:un support yrgb_vsd_mode:%d\n", - __func__, win->yrgb_vsd_mode); - break; - } /*win->yrgb_vsd_mode */ - break; - default: - pr_info("%s:un supported yrgb_ver_scl_mode:%d\n", - __func__, win->yrgb_ver_scl_mode); - break; - } - win->scale_yrgb_x = yrgb_xscl_factor; - win->scale_yrgb_y = yrgb_yscl_factor; - win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4; - win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2; - DBG(1, "yrgb:h_fac=%d, V_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor, - yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2); - - /*(2.1)CBCR HOR SCALE FACTOR */ - switch (win->cbr_hor_scl_mode) { - case SCALE_NONE: - cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT); - break; - case SCALE_UP: - cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW); - break; - case SCALE_DOWN: - switch (win->cbr_hsd_mode) { - case SCALE_DOWN_BIL: - cbcr_xscl_factor = - GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW); - break; - case SCALE_DOWN_AVG: - cbcr_xscl_factor = - GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW); - break; - default: - pr_info("%s:un support cbr_hsd_mode:%d\n", - __func__, win->cbr_hsd_mode); - break; - } - break; - default: - pr_info("%s:un supported cbr_hor_scl_mode:%d\n", - __func__, win->cbr_hor_scl_mode); - break; - } /*win->cbr_hor_scl_mode */ - - /* (2.2)CBCR VER SCALE FACTOR */ - switch (win->cbr_ver_scl_mode) { - case SCALE_NONE: - cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT); - break; - case SCALE_UP: - switch (win->cbr_vsu_mode) { - case SCALE_UP_BIL: - cbcr_yscl_factor = - GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH); - break; - case SCALE_UP_BIC: - if (cbcr_srcH < 3) { - pr_err("cbcr_srcH should be "); - pr_err("greater than 3 !!!\n"); - } - cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH, - cbcr_dstH); - break; - default: - pr_info("%s:un support cbr_vsu_mode:%d\n", - __func__, win->cbr_vsu_mode); - break; - } - break; - case SCALE_DOWN: - switch (win->cbr_vsd_mode) { - case SCALE_DOWN_BIL: - cbcr_vscalednmult = - vop_get_hard_ware_vskiplines(cbcr_srcH, cbcr_dstH); - cbcr_yscl_factor = - GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH, - cbcr_vscalednmult); - if (cbcr_yscl_factor >= 0x2000) { - pr_err("cbcr_yscl_factor should be less "); - pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n", - cbcr_yscl_factor); - } - - if (cbcr_vscalednmult == 4) { - cbcr_vsd_bil_gt4 = 1; - cbcr_vsd_bil_gt2 = 0; - } else if (cbcr_vscalednmult == 2) { - cbcr_vsd_bil_gt4 = 0; - cbcr_vsd_bil_gt2 = 1; - } else { - cbcr_vsd_bil_gt4 = 0; - cbcr_vsd_bil_gt2 = 0; - } - break; - case SCALE_DOWN_AVG: - cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH, - cbcr_dstH); - break; - default: - pr_info("%s:un support cbr_vsd_mode:%d\n", - __func__, win->cbr_vsd_mode); - break; - } - break; - default: - pr_info("%s:un supported cbr_ver_scl_mode:%d\n", - __func__, win->cbr_ver_scl_mode); - break; - } - win->scale_cbcr_x = cbcr_xscl_factor; - win->scale_cbcr_y = cbcr_yscl_factor; - win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4; - win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2; - - DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor, - cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2); - return 0; -} - -static int dsp_x_pos(int mirror_en, struct rk_screen *screen, - struct rk_lcdc_win_area *area) -{ - int pos; - - if (screen->x_mirror && mirror_en) - pr_err("not support both win and global mirror\n"); - - if ((!mirror_en) && (!screen->x_mirror)) - pos = area->xpos + screen->mode.left_margin + - screen->mode.hsync_len; - else - pos = screen->mode.xres - area->xpos - - area->xsize + screen->mode.left_margin + - screen->mode.hsync_len; - - return pos; -} - -static int dsp_y_pos(int mirror_en, struct rk_screen *screen, - struct rk_lcdc_win_area *area) -{ - int pos; - - if (screen->y_mirror && mirror_en) - pr_err("not support both win and global mirror\n"); - - if ((!mirror_en) && (!screen->y_mirror)) - pos = area->ypos + screen->mode.upper_margin + - screen->mode.vsync_len; - else - pos = screen->mode.yres - area->ypos - - area->ysize + screen->mode.upper_margin + - screen->mode.vsync_len; - - return pos; -} - -static int win_0_1_set_par(struct vop_device *vop_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - u32 xact = 0, yact = 0, xvir = 0, yvir = 0, xpos = 0, ypos = 0; - u8 fmt_cfg = 0, swap_rb = 0, swap_uv = 0; - char fmt[9] = "NULL"; - - xpos = dsp_x_pos(win->xmirror, screen, &win->area[0]); - ypos = dsp_y_pos(win->ymirror, screen, &win->area[0]); - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - vop_cal_scl_fac(win, screen); - switch (win->area[0].format) { - case FBDC_RGB_565: - fmt_cfg = 2; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = AFBDC_FMT_RGB565; - break; - case FBDC_ARGB_888: - fmt_cfg = 0; - swap_rb = 1; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8; - break; - case FBDC_ABGR_888: - fmt_cfg = 0; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8; - break; - case FBDC_RGBX_888: - fmt_cfg = 0; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8; - break; - case ARGB888: - fmt_cfg = 0; - swap_rb = 0; - win->fmt_10 = 0; - break; - case XBGR888: - case ABGR888: - fmt_cfg = 0; - swap_rb = 1; - win->fmt_10 = 0; - break; - case BGR888: - fmt_cfg = 1; - swap_rb = 1; - win->fmt_10 = 0; - break; - case RGB888: - fmt_cfg = 1; - swap_rb = 0; - win->fmt_10 = 0; - break; - case RGB565: - fmt_cfg = 2; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV422: - fmt_cfg = 5; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV420: - fmt_cfg = 4; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV420_NV21: - fmt_cfg = 4; - swap_rb = 0; - swap_uv = 1; - win->fmt_10 = 0; - break; - case YUV444: - fmt_cfg = 6; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV422_A: - fmt_cfg = 5; - swap_rb = 0; - win->fmt_10 = 1; - break; - case YUV420_A: - fmt_cfg = 4; - swap_rb = 0; - win->fmt_10 = 1; - break; - case YUV444_A: - fmt_cfg = 6; - swap_rb = 0; - win->fmt_10 = 1; - break; - case YUYV422: - fmt_cfg = 0; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].yuyv_fmt = 1; - break; - case YUYV420: - fmt_cfg = 1; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].yuyv_fmt = 1; - break; - case UYVY422: - fmt_cfg = 2; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].yuyv_fmt = 1; - break; - case UYVY420: - fmt_cfg = 3; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].yuyv_fmt = 1; - break; - default: - dev_err(vop_dev->dev, "%s:unsupport format[%d]!\n", - __func__, win->area[0].format); - break; - } - win->area[0].fmt_cfg = fmt_cfg; - win->area[0].swap_rb = swap_rb; - win->area[0].swap_uv = swap_uv; - win->area[0].dsp_stx = xpos; - win->area[0].dsp_sty = ypos; - xact = win->area[0].xact; - yact = win->area[0].yact; - xvir = win->area[0].xvir; - yvir = win->area[0].yvir; - } - if (win->area[0].fbdc_en) - vop_init_fbdc_config(vop_dev, win->id); - vop_win_0_1_reg_update(&vop_dev->driver, win->id); - spin_unlock(&vop_dev->reg_lock); - - DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d", - vop_dev->id, win->id, get_format_string(win->area[0].format, fmt), - xact, yact, win->area[0].xsize); - DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - win->area[0].ysize, xvir, yvir, xpos, ypos); - - return 0; -} - -static int win_2_3_set_par(struct vop_device *vop_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - int i; - u8 fmt_cfg = 0, swap_rb = 0; - char fmt[9] = "NULL"; - - if (VOP_CHIP(vop_dev) == VOP_RK322X) { - pr_err("rk3228 not support win2/3 set par\n"); - return -EINVAL; - } - if (win->ymirror) { - pr_err("win[%d] not support y mirror\n", win->id); - return -EINVAL; - } - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - DBG(2, "lcdc[%d]:win[%d]>>\n>\n", vop_dev->id, win->id); - for (i = 0; i < win->area_num; i++) { - switch (win->area[i].format) { - case FBDC_RGB_565: - fmt_cfg = 2; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = AFBDC_FMT_RGB565; - break; - case FBDC_ARGB_888: - fmt_cfg = 0; - swap_rb = 1; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8; - break; - case FBDC_ABGR_888: - fmt_cfg = 0; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8; - break; - case FBDC_RGBX_888: - fmt_cfg = 0; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8; - break; - case ARGB888: - fmt_cfg = 0; - swap_rb = 0; - break; - case XBGR888: - case ABGR888: - fmt_cfg = 0; - swap_rb = 1; - break; - case RGB888: - fmt_cfg = 1; - swap_rb = 0; - break; - case RGB565: - fmt_cfg = 2; - swap_rb = 0; - break; - default: - dev_err(vop_dev->driver.dev, - "%s:un supported format!\n", __func__); - spin_unlock(&vop_dev->reg_lock); - return -EINVAL; - } - win->area[i].fmt_cfg = fmt_cfg; - win->area[i].swap_rb = swap_rb; - win->area[i].dsp_stx = dsp_x_pos(win->xmirror, screen, - &win->area[i]); - win->area[i].dsp_sty = dsp_y_pos(win->ymirror, screen, - &win->area[i]); - if (((win->area[i].xact != win->area[i].xsize) || - (win->area[i].yact != win->area[i].ysize)) && - (screen->mode.vmode == FB_VMODE_NONINTERLACED)) { - pr_err("win[%d]->area[%d],not support scale\n", - win->id, i); - pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n", - win->area[i].xact, win->area[i].yact, - win->area[i].xsize, win->area[i].ysize); - win->area[i].xsize = win->area[i].xact; - win->area[i].ysize = win->area[i].yact; - } - DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n", - get_format_string(win->area[i].format, fmt), - win->area[i].xsize, win->area[i].ysize, - win->area[i].xpos, win->area[i].ypos); - } - } - if (win->area[0].fbdc_en) - vop_init_fbdc_config(vop_dev, win->id); - vop_win_2_3_reg_update(&vop_dev->driver, win->id); - spin_unlock(&vop_dev->reg_lock); - return 0; -} - -static int hwc_set_par(struct vop_device *vop_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - u32 xact = 0, yact = 0, xvir = 0, yvir = 0, xpos = 0, ypos = 0; - u8 fmt_cfg = 0, swap_rb = 0; - char fmt[9] = "NULL"; - - xpos = win->area[0].xpos + screen->mode.left_margin + - screen->mode.hsync_len; - ypos = win->area[0].ypos + screen->mode.upper_margin + - screen->mode.vsync_len; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - switch (win->area[0].format) { - case ARGB888: - fmt_cfg = 0; - swap_rb = 0; - break; - case XBGR888: - case ABGR888: - fmt_cfg = 0; - swap_rb = 1; - break; - case RGB888: - fmt_cfg = 1; - swap_rb = 0; - break; - case RGB565: - fmt_cfg = 2; - swap_rb = 0; - break; - default: - dev_err(vop_dev->dev, "%s:un supported format[%d]!\n", - __func__, win->area[0].format); - break; - } - win->area[0].fmt_cfg = fmt_cfg; - win->area[0].swap_rb = swap_rb; - win->area[0].dsp_stx = xpos; - win->area[0].dsp_sty = ypos; - xact = win->area[0].xact; - yact = win->area[0].yact; - xvir = win->area[0].xvir; - yvir = win->area[0].yvir; - } - vop_hwc_reg_update(&vop_dev->driver, 4); - spin_unlock(&vop_dev->reg_lock); - - DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d", - vop_dev->id, __func__, get_format_string(win->area[0].format, fmt), - xact, yact, win->area[0].xsize); - DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - win->area[0].ysize, xvir, yvir, xpos, ypos); - return 0; -} - -static int vop_set_par(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_lcdc_win *win = NULL; - struct rk_screen *screen = dev_drv->cur_screen; - - if (unlikely(!vop_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on); - return 0; - } - win = dev_drv->win[win_id]; - if (win) - switch (win_id) { - case 0: - win_0_1_set_par(vop_dev, screen, win); - break; - case 1: - win_0_1_set_par(vop_dev, screen, win); - break; - case 2: - win_2_3_set_par(vop_dev, screen, win); - break; - case 3: - win_2_3_set_par(vop_dev, screen, win); - break; - case 4: - hwc_set_par(vop_dev, screen, win); - break; - default: - dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id); - break; - } - return 0; -} - -static int vop_set_writeback(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - int output_color = dev_drv->output_color; - struct rk_screen *screen = dev_drv->cur_screen; - struct rk_fb_reg_wb_data *wb_data; - int xact = screen->mode.xres; - int yact = screen->mode.yres; - u32 fmt_cfg; - int xsize, ysize; - u64 v; - - if (unlikely(!vop_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on); - return 0; - } - wb_data = &dev_drv->wb_data; - if ((wb_data->xsize == 0) || (wb_data->ysize == 0)) - return 0; - - xsize = wb_data->xsize; - ysize = wb_data->ysize; - - /* - * RGB overlay mode support ARGB888, RGB888, RGB565, NV12, - * but YUV overlay mode only support NV12, it's hard to judge RGB - * or YUV overlay mode by userspace, so here force only support - * NV12 mode. - */ - if (wb_data->data_format != YUV420 && output_color != COLOR_RGB) { - pr_err("writeback only support NV12 when overlay is not RGB\n"); - return -EINVAL; - } - - if (ysize != yact && ysize != (yact / 2)) { - pr_err("WriteBack only support yact=%d, ysize=%d\n", - yact, ysize); - return -EINVAL; - } - - switch (wb_data->data_format) { - case ARGB888: - case ABGR888: - case XRGB888: - case XBGR888: - fmt_cfg = 0; - break; - case RGB888: - case BGR888: - fmt_cfg = 1; - break; - case RGB565: - case BGR565: - fmt_cfg = 2; - break; - case YUV420: - fmt_cfg = 8; - break; - default: - pr_info("unsupport fmt: %d\n", wb_data->data_format); - return -EINVAL; - } - - v = V_WB_EN(wb_data->state) | V_WB_FMT(fmt_cfg) | V_WB_RGB2YUV_MODE(1) | - V_WB_XPSD_BIL_EN(xact != xsize) | - V_WB_YTHROW_EN(ysize == (yact / 2)) | - V_WB_YTHROW_MODE(0); - - v |= V_WB_RGB2YUV_EN((output_color == COLOR_RGB) && - (wb_data->data_format == YUV420)); - - vop_msk_reg(vop_dev, WB_CTRL0, v); - - v = V_WB_WIDTH(xsize) | V_WB_XPSD_BIL_FACTOR((xact << 12) / xsize); - - vop_msk_reg(vop_dev, WB_CTRL1, v); - - vop_writel(vop_dev, WB_YRGB_MST, wb_data->smem_start); - if (wb_data->data_format == YUV420) - vop_writel(vop_dev, WB_CBR_MST, wb_data->smem_start); - - return 0; -} - -static int vop_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd, - unsigned long arg, int win_id) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - u32 panel_size[2]; - void __user *argp = (void __user *)arg; - struct color_key_cfg clr_key_cfg; - - switch (cmd) { - case RK_FBIOGET_PANEL_SIZE: - panel_size[0] = vop_dev->screen->mode.xres; - panel_size[1] = vop_dev->screen->mode.yres; - if (copy_to_user(argp, panel_size, 8)) - return -EFAULT; - break; - case RK_FBIOPUT_COLOR_KEY_CFG: - if (copy_from_user(&clr_key_cfg, argp, sizeof(clr_key_cfg))) - return -EFAULT; - vop_clr_key_cfg(dev_drv); - vop_writel(vop_dev, WIN0_COLOR_KEY, - clr_key_cfg.win0_color_key_cfg); - vop_writel(vop_dev, WIN1_COLOR_KEY, - clr_key_cfg.win1_color_key_cfg); - break; - - default: - break; - } - return 0; -} - -static int vop_get_backlight_device(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = container_of(dev_drv, - struct vop_device, driver); - struct device_node *backlight; - struct property *prop; - u32 *brightness_levels; - u32 length, max, last; - - if (vop_dev->backlight) - return 0; - backlight = of_parse_phandle(vop_dev->dev->of_node, "backlight", 0); - if (backlight) { - vop_dev->backlight = of_find_backlight_by_node(backlight); - if (!vop_dev->backlight) - dev_info(vop_dev->dev, "No find backlight device\n"); - } else { - dev_info(vop_dev->dev, "No find backlight device node\n"); - } - prop = of_find_property(backlight, "brightness-levels", &length); - if (!prop) - return -EINVAL; - max = length / sizeof(u32); - last = max - 1; - brightness_levels = kmalloc(256, GFP_KERNEL); - if (!brightness_levels) - return -ENOMEM; - - if (!of_property_read_u32_array(backlight, "brightness-levels", - brightness_levels, max)) { - if (brightness_levels[0] > brightness_levels[last]) - dev_drv->cabc_pwm_pol = 1;/*negative*/ - else - dev_drv->cabc_pwm_pol = 0;/*positive*/ - } else { - dev_info(vop_dev->dev, - "Can not read brightness-levels value\n"); - } - - kfree(brightness_levels); - - return 0; -} - -static int vop_early_suspend(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - - if (dev_drv->suspend_flag) - return 0; - - dev_drv->suspend_flag = 1; - /* ensure suspend_flag take effect on multi process */ - smp_wmb(); - flush_kthread_worker(&dev_drv->update_regs_worker); - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable) - dev_drv->trsm_ops->disable(); - - if (likely(vop_dev->clk_on)) { - spin_lock(&vop_dev->reg_lock); - vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLANK_EN(1)); - vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, INTR_MASK); - vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_OUT_ZERO(1)); - vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(1)); - if (VOP_CHIP(vop_dev) == VOP_RK3399) { - vop_msk_reg(vop_dev, WIN0_CTRL0, V_WIN0_EN(0)); - vop_msk_reg(vop_dev, WIN1_CTRL0, V_WIN1_EN(0)); - vop_msk_reg(vop_dev, WIN2_CTRL0, V_WIN2_EN(0)); - vop_msk_reg(vop_dev, WIN3_CTRL0, V_WIN3_EN(0)); - vop_msk_reg(vop_dev, AFBCD0_CTRL, V_VOP_FBDC_EN(0)); - } - vop_cfg_done(vop_dev); - - if (dev_drv->iommu_enabled && dev_drv->mmu_dev) { - mdelay(50); - rockchip_iovmm_deactivate(dev_drv->dev); - } - - spin_unlock(&vop_dev->reg_lock); - } - - vop_clk_disable(vop_dev); - rk_disp_pwr_disable(dev_drv); - - return 0; -} - -static int vop_early_resume(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - - if (!dev_drv->suspend_flag) - return 0; - rk_disp_pwr_enable(dev_drv); - - vop_clk_enable(vop_dev); - spin_lock(&vop_dev->reg_lock); - memcpy(vop_dev->regs, vop_dev->regsbak, vop_dev->len); - spin_unlock(&vop_dev->reg_lock); - - vop_set_lut(dev_drv, dev_drv->cur_screen->dsp_lut); - vop_set_cabc(dev_drv, dev_drv->cur_screen->cabc_lut); - spin_lock(&vop_dev->reg_lock); - - vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_OUT_ZERO(0)); - vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLANK_EN(0)); - vop_cfg_done(vop_dev); - spin_unlock(&vop_dev->reg_lock); - - if (dev_drv->iommu_enabled && dev_drv->mmu_dev) { - /* win address maybe effect after next frame start, - * but mmu maybe effect right now, so we delay 50ms - */ - mdelay(50); - rockchip_iovmm_activate(dev_drv->dev); - } - - spin_lock(&vop_dev->reg_lock); - vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(0)); - vop_cfg_done(vop_dev); - spin_unlock(&vop_dev->reg_lock); - - dev_drv->suspend_flag = 0; - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - - return 0; -} - -static int vop_blank(struct rk_lcdc_driver *dev_drv, int win_id, int blank_mode) -{ - switch (blank_mode) { - case FB_BLANK_UNBLANK: - vop_early_resume(dev_drv); - break; - case FB_BLANK_NORMAL: - vop_early_suspend(dev_drv); - break; - default: - vop_early_suspend(dev_drv); - break; - } - - dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode); - - return 0; -} - -static int vop_get_win_state(struct rk_lcdc_driver *dev_drv, - int win_id, int area_id) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - u32 area_status = 0, state = 0; - - switch (win_id) { - case 0: - area_status = vop_read_bit(vop_dev, WIN0_CTRL0, V_WIN0_EN(0)); - break; - case 1: - area_status = vop_read_bit(vop_dev, WIN1_CTRL0, V_WIN1_EN(0)); - break; - case 2: - if (area_id == 0) - area_status = vop_read_bit(vop_dev, WIN2_CTRL0, - V_WIN2_MST0_EN(0)); - if (area_id == 1) - area_status = vop_read_bit(vop_dev, WIN2_CTRL0, - V_WIN2_MST1_EN(0)); - if (area_id == 2) - area_status = vop_read_bit(vop_dev, WIN2_CTRL0, - V_WIN2_MST2_EN(0)); - if (area_id == 3) - area_status = vop_read_bit(vop_dev, WIN2_CTRL0, - V_WIN2_MST3_EN(0)); - break; - case 3: - if (area_id == 0) - area_status = vop_read_bit(vop_dev, WIN3_CTRL0, - V_WIN3_MST0_EN(0)); - if (area_id == 1) - area_status = vop_read_bit(vop_dev, WIN3_CTRL0, - V_WIN3_MST1_EN(0)); - if (area_id == 2) - area_status = vop_read_bit(vop_dev, WIN3_CTRL0, - V_WIN3_MST2_EN(0)); - if (area_id == 3) - area_status = vop_read_bit(vop_dev, WIN3_CTRL0, - V_WIN3_MST3_EN(0)); - break; - case 4: - area_status = vop_read_bit(vop_dev, HWC_CTRL0, V_HWC_EN(0)); - break; - default: - pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n", - __func__, win_id, area_id); - break; - } - - state = (area_status > 0) ? 1 : 0; - return state; -} - -static int vop_get_area_num(struct rk_lcdc_driver *dev_drv, - unsigned int *area_support) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - - area_support[0] = 1; - area_support[1] = 1; - - if (VOP_CHIP(vop_dev) == VOP_RK3399) { - area_support[2] = 4; - area_support[3] = 4; - } - - return 0; -} - -/*overlay will be do at regupdate*/ -static int vop_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, bool set) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_lcdc_win *win = NULL; - int i, ovl = 0; - u64 val; - int z_order_num = 0; - int layer0_sel = 0, layer1_sel = 1, layer2_sel = 2, layer3_sel = 3; - - if (swap == 0) { - for (i = 0; i < dev_drv->lcdc_win_num; i++) { - win = dev_drv->win[i]; - if (win->state == 1) - z_order_num++; - } - for (i = 0; i < dev_drv->lcdc_win_num; i++) { - win = dev_drv->win[i]; - if (win->state == 0) - win->z_order = z_order_num++; - switch (win->z_order) { - case 0: - layer0_sel = win->id; - break; - case 1: - layer1_sel = win->id; - break; - case 2: - layer2_sel = win->id; - break; - case 3: - layer3_sel = win->id; - break; - default: - break; - } - } - } else { - layer0_sel = swap % 10; - layer1_sel = swap / 10 % 10; - layer2_sel = swap / 100 % 10; - layer3_sel = swap / 1000; - } - - spin_lock(&vop_dev->reg_lock); - if (vop_dev->clk_on) { - if (set) { - val = V_DSP_LAYER0_SEL(layer0_sel) | - V_DSP_LAYER1_SEL(layer1_sel) | - V_DSP_LAYER2_SEL(layer2_sel) | - V_DSP_LAYER3_SEL(layer3_sel); - vop_msk_reg(vop_dev, DSP_CTRL1, val); - } else { - layer0_sel = vop_read_bit(vop_dev, DSP_CTRL1, - V_DSP_LAYER0_SEL(0)); - layer1_sel = vop_read_bit(vop_dev, DSP_CTRL1, - V_DSP_LAYER1_SEL(0)); - layer2_sel = vop_read_bit(vop_dev, DSP_CTRL1, - V_DSP_LAYER2_SEL(0)); - layer3_sel = vop_read_bit(vop_dev, DSP_CTRL1, - V_DSP_LAYER3_SEL(0)); - ovl = layer3_sel * 1000 + layer2_sel * 100 + - layer1_sel * 10 + layer0_sel; - } - } else { - ovl = -EPERM; - } - spin_unlock(&vop_dev->reg_lock); - - return ovl; -} - -static char *vop_format_to_string(int format, char *fmt) -{ - if (!fmt) - return NULL; - - switch (format) { - case 0: - strcpy(fmt, "ARGB888"); - break; - case 1: - strcpy(fmt, "RGB888"); - break; - case 2: - strcpy(fmt, "RGB565"); - break; - case 4: - strcpy(fmt, "YCbCr420"); - break; - case 5: - strcpy(fmt, "YCbCr422"); - break; - case 6: - strcpy(fmt, "YCbCr444"); - case 8: - strcpy(fmt, "YUYV422"); - break; - case 9: - strcpy(fmt, "YUYV420"); - break; - case 10: - strcpy(fmt, "UYVY422"); - break; - case 11: - strcpy(fmt, "UYVY420"); - break; - default: - strcpy(fmt, "invalid\n"); - break; - } - return fmt; -} - -static ssize_t vop_get_disp_info(struct rk_lcdc_driver *dev_drv, - char *buf, int win_id) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u16 hsync_len = screen->mode.hsync_len; - u16 left_margin = screen->mode.left_margin; - u16 vsync_len = screen->mode.vsync_len; - u16 upper_margin = screen->mode.upper_margin; - u32 h_pw_bp = hsync_len + left_margin; - u32 v_pw_bp = vsync_len + upper_margin; - u32 fmt_id; - char format_w0[9] = "NULL"; - char format_w1[9] = "NULL"; - char format_w2_0[9] = "NULL"; - char format_w2_1[9] = "NULL"; - char format_w2_2[9] = "NULL"; - char format_w2_3[9] = "NULL"; - char format_w3_0[9] = "NULL"; - char format_w3_1[9] = "NULL"; - char format_w3_2[9] = "NULL"; - char format_w3_3[9] = "NULL"; - char dsp_buf[100]; - u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st; - u32 y_factor, uv_factor; - u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel; - u8 w0_state, w1_state, w2_state, w3_state; - u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state; - u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state; - - u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y; - u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp; - u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y; - u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp; - u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac; - u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac; - - u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y; - u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x; - u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y; - u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp; - u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp; - u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp; - u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp; - - u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y; - u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x; - u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y; - u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp; - u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp; - u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp; - u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp; - u32 dclk_freq; - int size = 0; - - dclk_freq = screen->mode.pixclock; - /*vop_reg_dump(dev_drv); */ - - spin_lock(&vop_dev->reg_lock); - if (vop_dev->clk_on) { - zorder = vop_readl(vop_dev, DSP_CTRL1); - layer0_sel = (zorder & MASK(DSP_LAYER0_SEL)) >> 8; - layer1_sel = (zorder & MASK(DSP_LAYER1_SEL)) >> 10; - layer2_sel = (zorder & MASK(DSP_LAYER2_SEL)) >> 12; - layer3_sel = (zorder & MASK(DSP_LAYER3_SEL)) >> 14; - /* WIN0 */ - win_ctrl = vop_readl(vop_dev, WIN0_CTRL0); - w0_state = win_ctrl & MASK(WIN0_EN); - fmt_id = (win_ctrl & MASK(WIN0_DATA_FMT)) >> 1; - fmt_id |= (win_ctrl & MASK(WIN0_YUYV)) >> 14; /* yuyv*/ - vop_format_to_string(fmt_id, format_w0); - vir_info = vop_readl(vop_dev, WIN0_VIR); - act_info = vop_readl(vop_dev, WIN0_ACT_INFO); - dsp_info = vop_readl(vop_dev, WIN0_DSP_INFO); - dsp_st = vop_readl(vop_dev, WIN0_DSP_ST); - y_factor = vop_readl(vop_dev, WIN0_SCL_FACTOR_YRGB); - uv_factor = vop_readl(vop_dev, WIN0_SCL_FACTOR_CBR); - w0_vir_y = vir_info & MASK(WIN0_VIR_STRIDE); - w0_vir_uv = (vir_info & MASK(WIN0_VIR_STRIDE_UV)) >> 16; - w0_act_x = (act_info & MASK(WIN0_ACT_WIDTH)) + 1; - w0_act_y = ((act_info & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1; - w0_dsp_x = (dsp_info & MASK(WIN0_DSP_WIDTH)) + 1; - w0_dsp_y = ((dsp_info & MASK(WIN0_DSP_HEIGHT)) >> 16) + 1; - if (w0_state) { - w0_st_x = dsp_st & MASK(WIN0_DSP_XST); - w0_st_y = (dsp_st & MASK(WIN0_DSP_YST)) >> 16; - } - w0_y_h_fac = y_factor & MASK(WIN0_HS_FACTOR_YRGB); - w0_y_v_fac = (y_factor & MASK(WIN0_VS_FACTOR_YRGB)) >> 16; - w0_uv_h_fac = uv_factor & MASK(WIN0_HS_FACTOR_CBR); - w0_uv_v_fac = (uv_factor & MASK(WIN0_VS_FACTOR_CBR)) >> 16; - - /* WIN1 */ - win_ctrl = vop_readl(vop_dev, WIN1_CTRL0); - w1_state = win_ctrl & MASK(WIN1_EN); - fmt_id = (win_ctrl & MASK(WIN1_DATA_FMT)) >> 1; - fmt_id |= (win_ctrl & MASK(WIN1_YUYV)) >> 14; /* yuyv*/ - vop_format_to_string(fmt_id, format_w1); - vir_info = vop_readl(vop_dev, WIN1_VIR); - act_info = vop_readl(vop_dev, WIN1_ACT_INFO); - dsp_info = vop_readl(vop_dev, WIN1_DSP_INFO); - dsp_st = vop_readl(vop_dev, WIN1_DSP_ST); - y_factor = vop_readl(vop_dev, WIN1_SCL_FACTOR_YRGB); - uv_factor = vop_readl(vop_dev, WIN1_SCL_FACTOR_CBR); - w1_vir_y = vir_info & MASK(WIN1_VIR_STRIDE); - w1_vir_uv = (vir_info & MASK(WIN1_VIR_STRIDE_UV)) >> 16; - w1_act_x = (act_info & MASK(WIN1_ACT_WIDTH)) + 1; - w1_act_y = ((act_info & MASK(WIN1_ACT_HEIGHT)) >> 16) + 1; - w1_dsp_x = (dsp_info & MASK(WIN1_DSP_WIDTH)) + 1; - w1_dsp_y = ((dsp_info & MASK(WIN1_DSP_HEIGHT)) >> 16) + 1; - if (w1_state) { - w1_st_x = dsp_st & MASK(WIN1_DSP_XST); - w1_st_y = (dsp_st & MASK(WIN1_DSP_YST)) >> 16; - } - w1_y_h_fac = y_factor & MASK(WIN1_HS_FACTOR_YRGB); - w1_y_v_fac = (y_factor & MASK(WIN1_VS_FACTOR_YRGB)) >> 16; - w1_uv_h_fac = uv_factor & MASK(WIN1_HS_FACTOR_CBR); - w1_uv_v_fac = (uv_factor & MASK(WIN1_VS_FACTOR_CBR)) >> 16; - - /*WIN2 */ - win_ctrl = vop_readl(vop_dev, WIN2_CTRL0); - w2_state = win_ctrl & MASK(WIN2_EN); - w2_0_state = (win_ctrl & 0x10) >> 4; - w2_1_state = (win_ctrl & 0x100) >> 8; - w2_2_state = (win_ctrl & 0x1000) >> 12; - w2_3_state = (win_ctrl & 0x10000) >> 16; - vir_info = vop_readl(vop_dev, WIN2_VIR0_1); - w2_0_vir_y = vir_info & MASK(WIN2_VIR_STRIDE0); - w2_1_vir_y = (vir_info & MASK(WIN2_VIR_STRIDE1)) >> 16; - vir_info = vop_readl(vop_dev, WIN2_VIR2_3); - w2_2_vir_y = vir_info & MASK(WIN2_VIR_STRIDE2); - w2_3_vir_y = (vir_info & MASK(WIN2_VIR_STRIDE3)) >> 16; - - fmt_id = (win_ctrl & MASK(WIN2_DATA_FMT0)) >> 5; - vop_format_to_string(fmt_id, format_w2_0); - fmt_id = (win_ctrl & MASK(WIN2_DATA_FMT1)) >> 9; - vop_format_to_string(fmt_id, format_w2_1); - fmt_id = (win_ctrl & MASK(WIN2_DATA_FMT2)) >> 13; - vop_format_to_string(fmt_id, format_w2_2); - fmt_id = (win_ctrl & MASK(WIN2_DATA_FMT3)) >> 17; - vop_format_to_string(fmt_id, format_w2_3); - - dsp_info = vop_readl(vop_dev, WIN2_DSP_INFO0); - dsp_st = vop_readl(vop_dev, WIN2_DSP_ST0); - w2_0_dsp_x = (dsp_info & MASK(WIN2_DSP_WIDTH0)) + 1; - w2_0_dsp_y = ((dsp_info & MASK(WIN2_DSP_HEIGHT0)) >> 16) + 1; - if (w2_0_state) { - w2_0_st_x = dsp_st & MASK(WIN2_DSP_XST0); - w2_0_st_y = (dsp_st & MASK(WIN2_DSP_YST0)) >> 16; - } - dsp_info = vop_readl(vop_dev, WIN2_DSP_INFO1); - dsp_st = vop_readl(vop_dev, WIN2_DSP_ST1); - w2_1_dsp_x = (dsp_info & MASK(WIN2_DSP_WIDTH1)) + 1; - w2_1_dsp_y = ((dsp_info & MASK(WIN2_DSP_HEIGHT1)) >> 16) + 1; - if (w2_1_state) { - w2_1_st_x = dsp_st & MASK(WIN2_DSP_XST1); - w2_1_st_y = (dsp_st & MASK(WIN2_DSP_YST1)) >> 16; - } - dsp_info = vop_readl(vop_dev, WIN2_DSP_INFO2); - dsp_st = vop_readl(vop_dev, WIN2_DSP_ST2); - w2_2_dsp_x = (dsp_info & MASK(WIN2_DSP_WIDTH2)) + 1; - w2_2_dsp_y = ((dsp_info & MASK(WIN2_DSP_HEIGHT2)) >> 16) + 1; - if (w2_2_state) { - w2_2_st_x = dsp_st & MASK(WIN2_DSP_XST2); - w2_2_st_y = (dsp_st & MASK(WIN2_DSP_YST2)) >> 16; - } - dsp_info = vop_readl(vop_dev, WIN2_DSP_INFO3); - dsp_st = vop_readl(vop_dev, WIN2_DSP_ST3); - w2_3_dsp_x = (dsp_info & MASK(WIN2_DSP_WIDTH3)) + 1; - w2_3_dsp_y = ((dsp_info & MASK(WIN2_DSP_HEIGHT3)) >> 16) + 1; - if (w2_3_state) { - w2_3_st_x = dsp_st & MASK(WIN2_DSP_XST3); - w2_3_st_y = (dsp_st & MASK(WIN2_DSP_YST3)) >> 16; - } - - /*WIN3 */ - win_ctrl = vop_readl(vop_dev, WIN3_CTRL0); - w3_state = win_ctrl & MASK(WIN3_EN); - w3_0_state = (win_ctrl & 0x10) >> 4; - w3_1_state = (win_ctrl & 0x100) >> 8; - w3_2_state = (win_ctrl & 0x1000) >> 12; - w3_3_state = (win_ctrl & 0x10000) >> 16; - vir_info = vop_readl(vop_dev, WIN3_VIR0_1); - w3_0_vir_y = vir_info & MASK(WIN3_VIR_STRIDE0); - w3_1_vir_y = (vir_info & MASK(WIN3_VIR_STRIDE1)) >> 16; - vir_info = vop_readl(vop_dev, WIN3_VIR2_3); - w3_2_vir_y = vir_info & MASK(WIN3_VIR_STRIDE2); - w3_3_vir_y = (vir_info & MASK(WIN3_VIR_STRIDE3)) >> 16; - - fmt_id = (win_ctrl & MASK(WIN3_DATA_FMT0)) >> 5; - vop_format_to_string(fmt_id, format_w3_0); - fmt_id = (win_ctrl & MASK(WIN3_DATA_FMT1)) >> 9; - vop_format_to_string(fmt_id, format_w3_1); - fmt_id = (win_ctrl & MASK(WIN3_DATA_FMT2)) >> 13; - vop_format_to_string(fmt_id, format_w3_2); - fmt_id = (win_ctrl & MASK(WIN3_DATA_FMT3)) >> 17; - vop_format_to_string(fmt_id, format_w3_3); - - dsp_info = vop_readl(vop_dev, WIN3_DSP_INFO0); - dsp_st = vop_readl(vop_dev, WIN3_DSP_ST0); - w3_0_dsp_x = (dsp_info & MASK(WIN3_DSP_WIDTH0)) + 1; - w3_0_dsp_y = ((dsp_info & MASK(WIN3_DSP_HEIGHT0)) >> 16) + 1; - if (w3_0_state) { - w3_0_st_x = dsp_st & MASK(WIN3_DSP_XST0); - w3_0_st_y = (dsp_st & MASK(WIN3_DSP_YST0)) >> 16; - } - dsp_info = vop_readl(vop_dev, WIN3_DSP_INFO1); - dsp_st = vop_readl(vop_dev, WIN3_DSP_ST1); - w3_1_dsp_x = (dsp_info & MASK(WIN3_DSP_WIDTH1)) + 1; - w3_1_dsp_y = ((dsp_info & MASK(WIN3_DSP_HEIGHT1)) >> 16) + 1; - if (w3_1_state) { - w3_1_st_x = dsp_st & MASK(WIN3_DSP_XST1); - w3_1_st_y = (dsp_st & MASK(WIN3_DSP_YST1)) >> 16; - } - dsp_info = vop_readl(vop_dev, WIN3_DSP_INFO2); - dsp_st = vop_readl(vop_dev, WIN3_DSP_ST2); - w3_2_dsp_x = (dsp_info & MASK(WIN3_DSP_WIDTH2)) + 1; - w3_2_dsp_y = ((dsp_info & MASK(WIN3_DSP_HEIGHT2)) >> 16) + 1; - if (w3_2_state) { - w3_2_st_x = dsp_st & MASK(WIN3_DSP_XST2); - w3_2_st_y = (dsp_st & MASK(WIN3_DSP_YST2)) >> 16; - } - dsp_info = vop_readl(vop_dev, WIN3_DSP_INFO3); - dsp_st = vop_readl(vop_dev, WIN3_DSP_ST3); - w3_3_dsp_x = (dsp_info & MASK(WIN3_DSP_WIDTH3)) + 1; - w3_3_dsp_y = ((dsp_info & MASK(WIN3_DSP_HEIGHT3)) >> 16) + 1; - if (w3_3_state) { - w3_3_st_x = dsp_st & MASK(WIN3_DSP_XST3); - w3_3_st_y = (dsp_st & MASK(WIN3_DSP_YST3)) >> 16; - } - } else { - spin_unlock(&vop_dev->reg_lock); - return -EPERM; - } - spin_unlock(&vop_dev->reg_lock); - size += snprintf(dsp_buf, 80, - "z-order:\n win[%d]\n win[%d]\n win[%d]\n win[%d]\n", - layer3_sel, layer2_sel, layer1_sel, layer0_sel); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - /* win0 */ - size += snprintf(dsp_buf, 80, - "win0:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,", - w0_state, format_w0, w0_vir_y, w0_vir_uv); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n", - w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ", - w0_st_x - h_pw_bp, w0_st_y - v_pw_bp, w0_y_h_fac, w0_y_v_fac); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n", - w0_uv_h_fac, w0_uv_v_fac, vop_readl(vop_dev, WIN0_YRGB_MST), - vop_readl(vop_dev, WIN0_CBR_MST)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /* win1 */ - size += snprintf(dsp_buf, 80, - "win1:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,", - w1_state, format_w1, w1_vir_y, w1_vir_uv); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n", - w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ", - w1_st_x - h_pw_bp, w1_st_y - v_pw_bp, w1_y_h_fac, w1_y_v_fac); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n", - w1_uv_h_fac, w1_uv_v_fac, vop_readl(vop_dev, WIN1_YRGB_MST), - vop_readl(vop_dev, WIN1_CBR_MST)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*win2*/ - size += snprintf(dsp_buf, 80, - "win2:\n state:%d\n", - w2_state); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - /*area 0*/ - size += snprintf(dsp_buf, 80, - " area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp, - vop_readl(vop_dev, WIN2_MST0)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*area 1*/ - size += snprintf(dsp_buf, 80, - " area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp, - vop_readl(vop_dev, WIN2_MST1)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*area 2*/ - size += snprintf(dsp_buf, 80, - " area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp, - vop_readl(vop_dev, WIN2_MST2)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*area 3*/ - size += snprintf(dsp_buf, 80, - " area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp, - vop_readl(vop_dev, WIN2_MST3)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*win3*/ - size += snprintf(dsp_buf, 80, - "win3:\n state:%d\n", - w3_state); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - /*area 0*/ - size += snprintf(dsp_buf, 80, - " area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp, - vop_readl(vop_dev, WIN3_MST0)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*area 1*/ - size += snprintf(dsp_buf, 80, - " area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp, - vop_readl(vop_dev, WIN3_MST1)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*area 2*/ - size += snprintf(dsp_buf, 80, - " area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp, - vop_readl(vop_dev, WIN3_MST2)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*area 3*/ - size += snprintf(dsp_buf, 80, - " area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp, - vop_readl(vop_dev, WIN3_MST3)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - return size; -} - -static int vop_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, bool set) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_fb_vsync *vsync = &dev_drv->vsync_info; - int step_fps, old_fps; - u32 h_total, v_total; - unsigned long dclk; - u64 val; - int ret; - - dclk = clk_get_rate(vop_dev->dclk); - - spin_lock(&vop_dev->reg_lock); - - if (!vop_dev->clk_on) { - spin_unlock(&vop_dev->reg_lock); - return 0; - } - - val = vop_readl(vop_dev, DSP_HTOTAL_HS_END); - h_total = (val & MASK(DSP_HTOTAL)) >> 16; - - val = vop_readl(vop_dev, DSP_VTOTAL_VS_END); - v_total = (val & MASK(DSP_VTOTAL)) >> 16; - - spin_unlock(&vop_dev->reg_lock); - - old_fps = div_u64(dclk, v_total * h_total); - - if (!set) - return old_fps; - - /* - * Direct change fps to dest fps would may screen flash, - * Every frame change one step fps is safe, screen flash - * disappear. - */ - step_fps = old_fps; - while (step_fps != fps) { - ktime_t timestamp = vsync->timestamp; - - if (step_fps > fps) - step_fps--; - else - step_fps++; - spin_lock(&vop_dev->reg_lock); - if (!vop_dev->clk_on) { - spin_unlock(&vop_dev->reg_lock); - break; - } - h_total = div_u64(dclk, step_fps * v_total); - val = V_DSP_HTOTAL(h_total); - vop_msk_reg(vop_dev, DSP_HTOTAL_HS_END, val); - vop_cfg_done(vop_dev); - spin_unlock(&vop_dev->reg_lock); - - ret = wait_event_interruptible_timeout(vsync->wait, - !ktime_equal(timestamp, vsync->timestamp) && - (vsync->active > 0 || vsync->irq_stop), - msecs_to_jiffies(50)); - } - - dev_info(dev_drv->dev, "%s:dclk:%lu, htotal=%d, vtatol=%d, fps:%d\n", - __func__, dclk, h_total, v_total, fps); - - return fps; -} - -static int vop_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order) -{ - mutex_lock(&dev_drv->fb_win_id_mutex); - if (order == FB_DEFAULT_ORDER) - order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC; - dev_drv->fb4_win_id = order / 10000; - dev_drv->fb3_win_id = (order / 1000) % 10; - dev_drv->fb2_win_id = (order / 100) % 10; - dev_drv->fb1_win_id = (order / 10) % 10; - dev_drv->fb0_win_id = order % 10; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return 0; -} - -static int vop_get_win_id(struct rk_lcdc_driver *dev_drv, const char *id) -{ - int win_id = 0; - - mutex_lock(&dev_drv->fb_win_id_mutex); - if (!strcmp(id, "fb0") || !strcmp(id, "fb5")) - win_id = dev_drv->fb0_win_id; - else if (!strcmp(id, "fb1") || !strcmp(id, "fb6")) - win_id = dev_drv->fb1_win_id; - else if (!strcmp(id, "fb2") || !strcmp(id, "fb7")) - win_id = dev_drv->fb2_win_id; - else if (!strcmp(id, "fb3") || !strcmp(id, "fb8")) - win_id = dev_drv->fb3_win_id; - else if (!strcmp(id, "fb4") || !strcmp(id, "fb9")) - win_id = dev_drv->fb4_win_id; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return win_id; -} - -static int vop_config_done(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - int i, fbdc_en = 0; - u64 val; - struct rk_lcdc_win *win = NULL; - - spin_lock(&vop_dev->reg_lock); - vop_post_cfg(dev_drv); - vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(vop_dev->standby)); - for (i = 0; i < dev_drv->lcdc_win_num; i++) { - win = dev_drv->win[i]; - vop_alpha_cfg(dev_drv, i); - fbdc_en |= win->area[0].fbdc_en; - vop_dev->atv_layer_cnt &= ~(1 << win->id); - vop_dev->atv_layer_cnt |= (win->state << win->id); - if ((win->state == 0) && (win->last_state == 1)) { - switch (win->id) { - case 0: - val = V_WIN0_EN(0); - vop_msk_reg(vop_dev, WIN0_CTRL0, val); - break; - case 1: - val = V_WIN1_EN(0); - vop_msk_reg(vop_dev, WIN1_CTRL0, val); - break; - case 2: - val = V_WIN2_EN(0) | V_WIN2_MST0_EN(0) | - V_WIN2_MST1_EN(0) | - V_WIN2_MST2_EN(0) | V_WIN2_MST3_EN(0); - vop_msk_reg(vop_dev, WIN2_CTRL0, val); - break; - case 3: - val = V_WIN3_EN(0) | V_WIN3_MST0_EN(0) | - V_WIN3_MST1_EN(0) | - V_WIN3_MST2_EN(0) | V_WIN3_MST3_EN(0); - vop_msk_reg(vop_dev, WIN3_CTRL0, val); - break; - case 4: - val = V_HWC_EN(0); - vop_msk_reg(vop_dev, HWC_CTRL0, val); - break; - default: - break; - } - } - win->last_state = win->state; - } - if (VOP_CHIP(vop_dev) == VOP_RK3399) { - val = V_VOP_FBDC_EN(fbdc_en); - vop_msk_reg(vop_dev, AFBCD0_CTRL, val); - } - vop_cfg_done(vop_dev); - spin_unlock(&vop_dev->reg_lock); - return 0; -} - -static int vop_dpi_open(struct rk_lcdc_driver *dev_drv, bool open) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - spin_lock(&vop_dev->reg_lock); - vop_msk_reg(vop_dev, SYS_CTRL, V_DIRECT_PATH_EN(open)); - vop_cfg_done(vop_dev); - spin_unlock(&vop_dev->reg_lock); - return 0; -} - -static int vop_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct vop_device *vop_dev = container_of(dev_drv, - struct vop_device, driver); - spin_lock(&vop_dev->reg_lock); - vop_msk_reg(vop_dev, SYS_CTRL, V_DIRECT_PATH_LAYER_SEL(win_id)); - vop_cfg_done(vop_dev); - spin_unlock(&vop_dev->reg_lock); - return 0; -} - -static int vop_dpi_status(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - int ovl; - - spin_lock(&vop_dev->reg_lock); - ovl = vop_read_bit(vop_dev, SYS_CTRL, V_DIRECT_PATH_EN(0)); - spin_unlock(&vop_dev->reg_lock); - return ovl; -} - -static int vop_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv, int enable) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - if (enable) - enable_irq(vop_dev->irq); - else - disable_irq_nosync(vop_dev->irq); - return 0; -} - -int vop_poll_vblank(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - u32 int_reg; - int ret; - - if (vop_dev->clk_on && (!dev_drv->suspend_flag)) { - int_reg = vop_readl(vop_dev, INTR_STATUS0); - if (int_reg & INTR_LINE_FLAG0) { - vop_dev->driver.frame_time.last_framedone_t = - vop_dev->driver.frame_time.framedone_t; - vop_dev->driver.frame_time.framedone_t = cpu_clock(0); - vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_LINE_FLAG0, - INTR_LINE_FLAG0); - ret = RK_LF_STATUS_FC; - } else { - ret = RK_LF_STATUS_FR; - } - } else { - ret = RK_LF_STATUS_NC; - } - - return ret; -} - -static int vop_get_dsp_addr(struct rk_lcdc_driver *dev_drv, - unsigned int dsp_addr[][4]) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - spin_lock(&vop_dev->reg_lock); - if (vop_dev->clk_on) { - dsp_addr[0][0] = vop_readl(vop_dev, WIN0_YRGB_MST); - dsp_addr[1][0] = vop_readl(vop_dev, WIN1_YRGB_MST); - dsp_addr[2][0] = vop_readl(vop_dev, WIN2_MST0); - dsp_addr[2][1] = vop_readl(vop_dev, WIN2_MST1); - dsp_addr[2][2] = vop_readl(vop_dev, WIN2_MST2); - dsp_addr[2][3] = vop_readl(vop_dev, WIN2_MST3); - dsp_addr[3][0] = vop_readl(vop_dev, WIN3_MST0); - dsp_addr[3][1] = vop_readl(vop_dev, WIN3_MST1); - dsp_addr[3][2] = vop_readl(vop_dev, WIN3_MST2); - dsp_addr[3][3] = vop_readl(vop_dev, WIN3_MST3); - dsp_addr[4][0] = vop_readl(vop_dev, HWC_MST); - } - spin_unlock(&vop_dev->reg_lock); - return 0; -} - - -int vop_update_pwm(int bl_pwm_period, int bl_pwm_duty) -{ - /* - * TODO: - * pwm_period_hpr = bl_pwm_period; - * pwm_duty_lpr = bl_pwm_duty; - * pr_info("bl_pwm_period_hpr = 0x%x, bl_pwm_duty_lpr = 0x%x\n", - * bl_pwm_period, bl_pwm_duty); - */ - - return 0; -} - -/* - * a:[-30~0]: - * sin_hue = sin(a)*256 +0x100; - * cos_hue = cos(a)*256; - * a:[0~30] - * sin_hue = sin(a)*256; - * cos_hue = cos(a)*256; - */ -static int vop_get_bcsh_hue(struct rk_lcdc_driver *dev_drv, bcsh_hue_mode mode) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - u32 val = 0; - - spin_lock(&vop_dev->reg_lock); - if (vop_dev->clk_on) { - val = vop_readl(vop_dev, BCSH_H); - switch (mode) { - case H_SIN: - val &= MASK(SIN_HUE); - break; - case H_COS: - val &= MASK(COS_HUE); - val >>= 16; - break; - default: - break; - } - } - spin_unlock(&vop_dev->reg_lock); - - return val; -} - -static int vop_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode, - int calc, int up, int down, int global) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u32 total_pixel, calc_pixel, stage_up, stage_down; - u32 pixel_num, global_dn; - u64 val = 0; - ktime_t timestamp; - int ret = 0; - - if (!vop_dev->cabc_lut_addr_base) { - pr_err("vop chip[%d] not supoort cabc\n", VOP_CHIP(vop_dev)); - return 0; - } - - if (!screen->cabc_lut) { - pr_err("screen cabc lut not config, so not open cabc\n"); - return 0; - } - - if (!mode) { - if (VOP_CHIP(vop_dev) == VOP_RK3399) { - calc = 0; - up = 256; - down = 255; - global = 0; - } else { - spin_lock(&vop_dev->reg_lock); - if (vop_dev->clk_on) { - vop_msk_reg(vop_dev, CABC_CTRL0, - V_CABC_EN(0) | V_CABC_HANDLE_EN(0)); - vop_cfg_done(vop_dev); - } - pr_info("mode = 0, close cabc\n"); - spin_unlock(&vop_dev->reg_lock); - return 0; - } - } - - total_pixel = screen->mode.xres * screen->mode.yres; - pixel_num = 1000 - calc; - calc_pixel = (total_pixel * pixel_num) / 1000; - stage_up = up; - stage_down = down; - global_dn = global; - pr_info("enable cabc:mode=%d, calc=%d, up=%d, down=%d, global=%d\n", - mode, calc, stage_up, stage_down, global_dn); - - spin_lock(&vop_dev->reg_lock); - if (vop_dev->clk_on) { - val = V_PWM_CONFIG_MODE(STAGE_BY_STAGE) | - V_CABC_CALC_PIXEL_NUM(calc_pixel); - vop_msk_reg(vop_dev, CABC_CTRL0, val); - - val = V_CABC_LUT_EN(1) | V_CABC_TOTAL_NUM(total_pixel); - vop_msk_reg(vop_dev, CABC_CTRL1, val); - - val = V_CABC_STAGE_DOWN(stage_down) | - V_CABC_STAGE_UP(stage_up) | - V_CABC_STAGE_UP_MODE(0) | V_MAX_SCALE_CFG_VALUE(1) | - V_MAX_SCALE_CFG_ENABLE(0); - vop_msk_reg(vop_dev, CABC_CTRL2, val); - - val = V_CABC_GLOBAL_DN(global_dn) | - V_CABC_GLOBAL_DN_LIMIT_EN(1); - vop_msk_reg(vop_dev, CABC_CTRL3, val); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - timestamp = dev_drv->vsync_info.timestamp; - ret = wait_event_interruptible_timeout(dev_drv->vsync_info.wait, - !ktime_equal(timestamp, dev_drv->vsync_info.timestamp), - msecs_to_jiffies(50)); - if (ret < 0) - return ret; - else if (ret == 0) - pr_err("%s wait vsync time out\n", __func__); - - spin_lock(&vop_dev->reg_lock); - if (vop_dev->clk_on) { - val = V_CABC_EN(1) | V_CABC_HANDLE_EN(1); - vop_msk_reg(vop_dev, CABC_CTRL0, val); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_set_bcsh_hue(struct rk_lcdc_driver *dev_drv, - int sin_hue, int cos_hue) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - u64 val; - - spin_lock(&vop_dev->reg_lock); - if (vop_dev->clk_on) { - val = V_SIN_HUE(sin_hue) | V_COS_HUE(cos_hue); - vop_msk_reg(vop_dev, BCSH_H, val); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv, - bcsh_bcs_mode mode, int value) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - u64 val = 0; - - spin_lock(&vop_dev->reg_lock); - if (vop_dev->clk_on) { - switch (mode) { - case BRIGHTNESS: - /*from 0 to 255,typical is 128 */ - if (value < 0x80) - value += 0x80; - else if (value >= 0x80) - value = value - 0x80; - val = V_BRIGHTNESS(value); - break; - case CONTRAST: - /*from 0 to 510,typical is 256 */ - val = V_CONTRAST(value); - break; - case SAT_CON: - /*from 0 to 1015,typical is 256 */ - val = V_SAT_CON(value); - break; - default: - break; - } - vop_msk_reg(vop_dev, BCSH_BCS, val); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - return val; -} - -static int vop_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv, bcsh_bcs_mode mode) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - u64 val = 0; - - spin_lock(&vop_dev->reg_lock); - if (vop_dev->clk_on) { - val = vop_readl(vop_dev, BCSH_BCS); - switch (mode) { - case BRIGHTNESS: - val &= MASK(BRIGHTNESS); - if (val > 0x80) - val -= 0x80; - else - val += 0x80; - break; - case CONTRAST: - val &= MASK(CONTRAST); - val >>= 8; - break; - case SAT_CON: - val &= MASK(SAT_CON); - val >>= 20; - break; - default: - break; - } - } - spin_unlock(&vop_dev->reg_lock); - return val; -} - -static int vop_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - - spin_lock(&vop_dev->reg_lock); - if (vop_dev->clk_on) { - if (open) { - vop_writel(vop_dev, BCSH_COLOR_BAR, 0x1); - vop_writel(vop_dev, BCSH_BCS, 0xd0010000); - vop_writel(vop_dev, BCSH_H, 0x01000000); - dev_drv->bcsh.enable = 1; - } else { - vop_msk_reg(vop_dev, BCSH_COLOR_BAR, V_BCSH_EN(0)); - dev_drv->bcsh.enable = 0; - } - vop_bcsh_path_sel(dev_drv); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable) -{ - if (!enable || !dev_drv->bcsh.enable) { - vop_open_bcsh(dev_drv, false); - return 0; - } - - if (dev_drv->bcsh.brightness <= 255 || - dev_drv->bcsh.contrast <= 510 || - dev_drv->bcsh.sat_con <= 1015 || - (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) { - vop_open_bcsh(dev_drv, true); - if (dev_drv->bcsh.brightness <= 255) - vop_set_bcsh_bcs(dev_drv, BRIGHTNESS, - dev_drv->bcsh.brightness); - if (dev_drv->bcsh.contrast <= 510) - vop_set_bcsh_bcs(dev_drv, CONTRAST, - dev_drv->bcsh.contrast); - if (dev_drv->bcsh.sat_con <= 1015) - vop_set_bcsh_bcs(dev_drv, SAT_CON, - dev_drv->bcsh.sat_con); - if (dev_drv->bcsh.sin_hue <= 511 && - dev_drv->bcsh.cos_hue <= 511) - vop_set_bcsh_hue(dev_drv, dev_drv->bcsh.sin_hue, - dev_drv->bcsh.cos_hue); - } - - return 0; -} - -static int __maybe_unused -vop_dsp_black(struct rk_lcdc_driver *dev_drv, int enable) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - - if (enable) { - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLACK_EN(1)); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - } else { - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLACK_EN(0)); - - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - } - - return 0; -} - -static int vop_backlight_close(struct rk_lcdc_driver *dev_drv, int enable) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - - if (unlikely(!vop_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on); - return 0; - } - vop_get_backlight_device(dev_drv); - - if (enable) { - /* close the backlight */ - if (vop_dev->backlight) { - vop_dev->backlight->props.power = FB_BLANK_POWERDOWN; - backlight_update_status(vop_dev->backlight); - } - if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable) - dev_drv->trsm_ops->disable(); - } else { - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - msleep(100); - /* open the backlight */ - if (vop_dev->backlight) { - vop_dev->backlight->props.power = FB_BLANK_UNBLANK; - backlight_update_status(vop_dev->backlight); - } - } - - return 0; -} - -static int vop_set_overscan(struct rk_lcdc_driver *dev_drv, - struct overscan *overscan) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - - if (unlikely(!vop_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on); - return 0; - } - /*vop_post_cfg(dev_drv);*/ - - return 0; -} - -static int vop_extern_func(struct rk_lcdc_driver *dev_drv, int cmd) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - u64 val; - - if (unlikely(!vop_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on); - return 0; - } - - switch (cmd) { - case UPDATE_CABC_PWM: - vop_cfg_done(vop_dev); - break; - case SET_DSP_MIRROR: - val = V_DSP_X_MIR_EN(dev_drv->cur_screen->x_mirror) | - V_DSP_Y_MIR_EN(dev_drv->cur_screen->y_mirror); - vop_msk_reg(vop_dev, DSP_CTRL0, val); - pr_info("%s: xmirror: %d, ymirror: %d\n", - __func__, dev_drv->cur_screen->x_mirror, - dev_drv->cur_screen->y_mirror); - break; - default: - break; - } - - return 0; -} - -static struct rk_lcdc_drv_ops lcdc_drv_ops = { - .open = vop_open, - .win_direct_en = vop_win_direct_en, - .load_screen = vop_load_screen, - .get_dspbuf_info = vop_get_dspbuf_info, - .post_dspbuf = vop_post_dspbuf, - .set_par = vop_set_par, - .pan_display = vop_pan_display, - .set_wb = vop_set_writeback, - .direct_set_addr = vop_direct_set_win_addr, - /*.lcdc_reg_update = vop_reg_update,*/ - .blank = vop_blank, - .ioctl = vop_ioctl, - .suspend = vop_early_suspend, - .resume = vop_early_resume, - .get_win_state = vop_get_win_state, - .area_support_num = vop_get_area_num, - .ovl_mgr = vop_ovl_mgr, - .get_disp_info = vop_get_disp_info, - .fps_mgr = vop_fps_mgr, - .fb_get_win_id = vop_get_win_id, - .fb_win_remap = vop_fb_win_remap, - .poll_vblank = vop_poll_vblank, - .dpi_open = vop_dpi_open, - .dpi_win_sel = vop_dpi_win_sel, - .dpi_status = vop_dpi_status, - .get_dsp_addr = vop_get_dsp_addr, - .set_dsp_lut = vop_set_lut, - .set_cabc_lut = vop_set_cabc, - .set_dsp_cabc = vop_set_dsp_cabc, - .set_dsp_bcsh_hue = vop_set_bcsh_hue, - .set_dsp_bcsh_bcs = vop_set_bcsh_bcs, - .get_dsp_bcsh_hue = vop_get_bcsh_hue, - .get_dsp_bcsh_bcs = vop_get_bcsh_bcs, - .open_bcsh = vop_open_bcsh, - .dump_reg = vop_reg_dump, - .cfg_done = vop_config_done, - .set_irq_to_cpu = vop_set_irq_to_cpu, - /*.dsp_black = vop_dsp_black,*/ - .backlight_close = vop_backlight_close, - .mmu_en = vop_mmu_en, - .set_overscan = vop_set_overscan, - .extern_func = vop_extern_func, -}; - -static irqreturn_t vop_isr(int irq, void *dev_id) -{ - struct vop_device *vop_dev = (struct vop_device *)dev_id; - ktime_t timestamp = ktime_get(); - u32 intr_status; - unsigned long flags; - - spin_lock_irqsave(&vop_dev->irq_lock, flags); - - intr_status = vop_readl(vop_dev, INTR_STATUS0); - vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, intr_status); - - spin_unlock_irqrestore(&vop_dev->irq_lock, flags); - /* This is expected for vop iommu irqs, since the irq is shared */ - if (!intr_status) - return IRQ_NONE; - - if (intr_status & INTR_FS) { - timestamp = ktime_get(); - if (vop_dev->driver.wb_data.state) { - u32 wb_status; - - spin_lock_irqsave(&vop_dev->irq_lock, flags); - wb_status = vop_read_bit(vop_dev, WB_CTRL0, V_WB_EN(0)); - - if (wb_status) - vop_clr_bit(vop_dev, WB_CTRL0, V_WB_EN(0)); - - vop_cfg_done(vop_dev); - vop_dev->driver.wb_data.state = 0; - spin_unlock_irqrestore(&vop_dev->irq_lock, flags); - } - vop_dev->driver.vsync_info.timestamp = timestamp; - wake_up_interruptible_all(&vop_dev->driver.vsync_info.wait); - intr_status &= ~INTR_FS; - } - - if (intr_status & INTR_LINE_FLAG0) - intr_status &= ~INTR_LINE_FLAG0; - - if (intr_status & INTR_LINE_FLAG1) - intr_status &= ~INTR_LINE_FLAG1; - - if (intr_status & INTR_FS_NEW) - intr_status &= ~INTR_FS_NEW; - - if (intr_status & INTR_BUS_ERROR) { - intr_status &= ~INTR_BUS_ERROR; - dev_warn_ratelimited(vop_dev->dev, "bus error!"); - } - - if (intr_status & INTR_WIN0_EMPTY) { - intr_status &= ~INTR_WIN0_EMPTY; - dev_warn_ratelimited(vop_dev->dev, "intr win0 empty!"); - } - - if (intr_status & INTR_WIN1_EMPTY) { - intr_status &= ~INTR_WIN1_EMPTY; - dev_warn_ratelimited(vop_dev->dev, "intr win1 empty!"); - } - - if (intr_status & INTR_HWC_EMPTY) { - intr_status &= ~INTR_HWC_EMPTY; - dev_warn_ratelimited(vop_dev->dev, "intr hwc empty!"); - } - - if (intr_status & INTR_POST_BUF_EMPTY) { - intr_status &= ~INTR_POST_BUF_EMPTY; - dev_warn_ratelimited(vop_dev->dev, "intr post buf empty!"); - } - - if (intr_status) - dev_err(vop_dev->dev, "Unknown VOP IRQs: %#02x\n", intr_status); - - return IRQ_HANDLED; -} - -#if defined(CONFIG_PM) -static int vop_suspend(struct platform_device *pdev, pm_message_t state) -{ - return 0; -} - -static int vop_resume(struct platform_device *pdev) -{ - return 0; -} -#else -#define vop_suspend NULL -#define vop_resume NULL -#endif - -static int vop_parse_dt(struct vop_device *vop_dev) -{ - struct device_node *np = vop_dev->dev->of_node; - struct rk_lcdc_driver *dev_drv = &vop_dev->driver; - int val; - - if (of_property_read_u32(np, "rockchip,prop", &val)) - vop_dev->prop = PRMRY; /*default set it as primary */ - else - vop_dev->prop = val; - - if (of_property_read_u32(np, "rockchip,mirror", &val)) - dev_drv->rotate_mode = NO_MIRROR; - else - dev_drv->rotate_mode = val; - - if (of_property_read_u32(np, "rockchip,cabc_mode", &val)) - dev_drv->cabc_mode = 0; /* default set close cabc */ - else - dev_drv->cabc_mode = val; - - if (of_property_read_u32(np, "rockchip,pwr18", &val)) - /*default set it as 3.xv power supply */ - vop_dev->pwr18 = false; - else - vop_dev->pwr18 = (val ? true : false); - - if (of_property_read_u32(np, "rockchip,fb-win-map", &val)) - dev_drv->fb_win_map = FB_DEFAULT_ORDER; - else - dev_drv->fb_win_map = val; - - if (of_property_read_u32(np, "rockchip,bcsh-en", &val)) - dev_drv->bcsh.enable = false; - else - dev_drv->bcsh.enable = (val ? true : false); - - if (of_property_read_u32(np, "rockchip,brightness", &val)) - dev_drv->bcsh.brightness = 0xffff; - else - dev_drv->bcsh.brightness = val; - - if (of_property_read_u32(np, "rockchip,contrast", &val)) - dev_drv->bcsh.contrast = 0xffff; - else - dev_drv->bcsh.contrast = val; - - if (of_property_read_u32(np, "rockchip,sat-con", &val)) - dev_drv->bcsh.sat_con = 0xffff; - else - dev_drv->bcsh.sat_con = val; - - if (of_property_read_u32(np, "rockchip,hue", &val)) { - dev_drv->bcsh.sin_hue = 0xffff; - dev_drv->bcsh.cos_hue = 0xffff; - } else { - dev_drv->bcsh.sin_hue = val & 0xff; - dev_drv->bcsh.cos_hue = (val >> 8) & 0xff; - } - - if (of_property_read_u32(np, "rockchip,iommu-enabled", &val)) - dev_drv->iommu_enabled = 0; - else - dev_drv->iommu_enabled = val; - - if (of_property_read_u32(np, "rockchip,dsp_mode", &val)) - dev_drv->dsp_mode = DEFAULT_MODE; - else - dev_drv->dsp_mode = val; - - return 0; -} - -static struct platform_device *rk322x_pdev; - -int vop_register_dmc(void) -{ - struct platform_device *pdev = rk322x_pdev; - struct vop_device *vop_dev; - struct device *dev = &pdev->dev; - struct devfreq *devfreq; - struct devfreq_event_dev *event_dev; - - if (!pdev) - return -ENODEV; - - vop_dev = platform_get_drvdata(pdev);; - if (!vop_dev) - return -ENODEV; - - dev = &pdev->dev; - devfreq = devfreq_get_devfreq_by_phandle(dev, 0); - if (IS_ERR(devfreq)) { - dev_err(vop_dev->dev, "fail to get devfreq for dmc\n"); - return -ENODEV; - } - - vop_dev->devfreq = devfreq; - vop_dev->dmc_nb.notifier_call = dmc_notify; - devfreq_register_notifier(vop_dev->devfreq, &vop_dev->dmc_nb, - DEVFREQ_TRANSITION_NOTIFIER); - - event_dev = devfreq_event_get_edev_by_phandle(vop_dev->devfreq->dev.parent, - 0); - if (IS_ERR(event_dev)) { - dev_err(vop_dev->dev, "fail to get edev for dmc\n"); - return -ENODEV; - } - - vop_dev->devfreq_event_dev = event_dev; - return 0; -} - -static int vop_wms_refresh(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = - container_of(dev_drv, struct vop_device, driver); - - if (unlikely(!vop_dev->clk_on)) { - dev_info_ratelimited(vop_dev->dev, "%s,clk_on = %d\n", - __func__, vop_dev->clk_on); - return 0; - } - vop_msk_reg_nobak(vop_dev, SYS_CTRL, V_EDPI_WMS_FS(1)); - vop_msk_reg(vop_dev, SYS_CTRL, V_EDPI_WMS_MODE(0)); - vop_msk_reg(vop_dev, SYS_CTRL, V_EDPI_WMS_MODE(1)); - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->refresh) - dev_drv->trsm_ops->refresh(0, 0, dev_drv->cur_screen->mode.xres, - dev_drv->cur_screen->mode.yres); - - return 0; -} - -static irqreturn_t te_irq_handle(int irq, void *dev_id) -{ - struct rk_lcdc_driver *dev_drv = (struct rk_lcdc_driver *)dev_id; - - vop_wms_refresh(dev_drv); - - return IRQ_HANDLED; -} - -static int vop_probe(struct platform_device *pdev) -{ - struct vop_device *vop_dev = NULL; - struct rk_lcdc_driver *dev_drv; - const struct of_device_id *of_id; - struct device *dev = &pdev->dev; - struct resource *res; - struct device_node *np = pdev->dev.of_node; - int prop; - int ret = 0; - int te_pin; - - /* if the primary lcdc has not registered ,the extend - * lcdc register later - */ - of_property_read_u32(np, "rockchip,prop", &prop); - if (prop == EXTEND) { - if (!is_prmry_rk_lcdc_registered()) - return -EPROBE_DEFER; - } - vop_dev = devm_kzalloc(dev, sizeof(struct vop_device), GFP_KERNEL); - if (!vop_dev) - return -ENOMEM; - of_id = of_match_device(vop_dt_ids, dev); - vop_dev->data = of_id->data; - if (VOP_CHIP(vop_dev) != VOP_RK322X && VOP_CHIP(vop_dev) != VOP_RK3399) - return -ENODEV; - platform_set_drvdata(pdev, vop_dev); - vop_dev->dev = dev; - vop_parse_dt(vop_dev); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) - /* enable power domain */ - pm_runtime_enable(dev); -#endif - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - vop_dev->reg_phy_base = res->start; - vop_dev->len = resource_size(res); - vop_dev->regs = devm_ioremap(&pdev->dev, res->start, - resource_size(res)); - if (IS_ERR(vop_dev->regs)) - return PTR_ERR(vop_dev->regs); - - dev_info(dev, "vop_dev->regs=0x%lx\n", (long)vop_dev->regs); - - vop_dev->regsbak = devm_kzalloc(dev, vop_dev->len, GFP_KERNEL); - if (IS_ERR(vop_dev->regsbak)) - return PTR_ERR(vop_dev->regsbak); - if (VOP_CHIP(vop_dev) == VOP_RK3399) { - vop_dev->dsp_lut_addr_base = vop_dev->regs + GAMMA_LUT_ADDR; - vop_dev->cabc_lut_addr_base = vop_dev->regs + - CABC_GAMMA_LUT_ADDR; - } - vop_dev->grf_base = - syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); - if (IS_ERR(vop_dev->grf_base)) { - dev_err(&pdev->dev, "can't find lcdc grf property\n"); - vop_dev->grf_base = NULL; - } - - vop_dev->id = vop_get_id(vop_dev, vop_dev->reg_phy_base); - dev_set_name(vop_dev->dev, "vop%d", vop_dev->id); - dev_drv = &vop_dev->driver; - dev_drv->dev = dev; - dev_drv->prop = prop; - dev_drv->id = vop_dev->id; - dev_drv->ops = &lcdc_drv_ops; - dev_drv->lcdc_win_num = vop_dev->data->n_wins; - dev_drv->reserved_fb = 0; - spin_lock_init(&vop_dev->reg_lock); - spin_lock_init(&vop_dev->irq_lock); - vop_dev->irq = platform_get_irq(pdev, 0); - if (vop_dev->irq < 0) { - dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n", - vop_dev->id); - return -ENXIO; - } - - ret = devm_request_irq(dev, vop_dev->irq, vop_isr, - IRQF_SHARED, dev_name(dev), vop_dev); - if (ret) { - dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", - vop_dev->irq, ret); - return ret; - } - if (dev_drv->iommu_enabled) { - if (VOP_CHIP(vop_dev) == VOP_RK322X) { - strcpy(dev_drv->mmu_dts_name, - VOP_IOMMU_COMPATIBLE_NAME); - } else { - if (vop_dev->id == 0) - strcpy(dev_drv->mmu_dts_name, - VOPB_IOMMU_COMPATIBLE_NAME); - else - strcpy(dev_drv->mmu_dts_name, - VOPL_IOMMU_COMPATIBLE_NAME); - } - } - if (VOP_CHIP(vop_dev) == VOP_RK3399) - dev_drv->property.feature |= SUPPORT_WRITE_BACK | SUPPORT_AFBDC; - dev_drv->property.feature |= SUPPORT_VOP_IDENTIFY | - SUPPORT_YUV420_OUTPUT; - dev_drv->property.max_output_x = 4096; - dev_drv->property.max_output_y = 2160; - - init_waitqueue_head(&vop_dev->wait_vop_switch_queue); - vop_dev->vop_switch_status = 0; - init_waitqueue_head(&vop_dev->wait_dmc_queue); - vop_dev->dmc_in_process = 0; - - ret = rk_fb_register(dev_drv, vop_dev->data->win, vop_dev->id); - if (ret < 0) { - dev_err(dev, "register fb for lcdc%d failed!\n", vop_dev->id); - return ret; - } - - if ((VOP_CHIP(vop_dev) == VOP_RK3399) && (vop_dev->id == 1)) { - dev_drv->win[1]->property.feature &= ~SUPPORT_HW_EXIST; - dev_drv->win[3]->property.feature &= ~SUPPORT_HW_EXIST; - } - - vop_dev->screen = dev_drv->screen0; - dev_info(dev, "lcdc%d probe ok, iommu %s\n", - vop_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled"); - - rk322x_pdev = pdev; - - if (dev_drv->cur_screen->refresh_mode == SCREEN_CMD_MODE) { - te_pin = of_get_named_gpio_flags(np, "te-gpio", 0, NULL); - if (IS_ERR_VALUE(te_pin)) { - dev_err(dev, "define te pin for cmd mode!\n"); - return 0; - } - ret = devm_gpio_request(dev, te_pin, "vop-te-gpio"); - if (ret) { - dev_err(dev, "request gpio %d failed\n", te_pin); - return 0; - } - gpio_direction_input(te_pin); - dev_drv->te_irq = gpio_to_irq(te_pin); - ret = devm_request_threaded_irq(dev, - dev_drv->te_irq, - NULL, te_irq_handle, - IRQ_TYPE_EDGE_FALLING | IRQF_ONESHOT, - "te_irq", dev_drv); - if (ret < 0) - dev_err(dev, "request te irq failed, ret: %d\n", ret); - } - return 0; -} - -static int vop_remove(struct platform_device *pdev) -{ - return 0; -} - -static void vop_shutdown(struct platform_device *pdev) -{ - struct vop_device *vop_dev = platform_get_drvdata(pdev); - struct rk_lcdc_driver *dev_drv = &vop_dev->driver; - - dev_drv->suspend_flag = 1; - dev_drv->shutdown_flag = 1; - /* ensure suspend_flag take effect on multi process */ - smp_wmb(); - flush_kthread_worker(&dev_drv->update_regs_worker); - kthread_stop(dev_drv->update_regs_thread); - vop_deint(vop_dev); - - vop_clk_disable(vop_dev); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) - pm_runtime_disable(vop_dev->dev); -#endif - rk_disp_pwr_disable(dev_drv); -} - -static struct platform_driver vop_driver = { - .probe = vop_probe, - .remove = vop_remove, - .driver = { - .name = "rk322x-lcdc", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(vop_dt_ids), - }, - .suspend = vop_suspend, - .resume = vop_resume, - .shutdown = vop_shutdown, -}; - -static int __init vop_module_init(void) -{ - return platform_driver_register(&vop_driver); -} - -static void __exit vop_module_exit(void) -{ - platform_driver_unregister(&vop_driver); -} - -fs_initcall(vop_module_init); -module_exit(vop_module_exit); diff --git a/drivers/video/rockchip/lcdc/rk322x_lcdc.h b/drivers/video/rockchip/lcdc/rk322x_lcdc.h deleted file mode 100644 index 13e573c62ed4..000000000000 --- a/drivers/video/rockchip/lcdc/rk322x_lcdc.h +++ /dev/null @@ -1,1797 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef RK322X_LCDC_H_ -#define RK322X_LCDC_H_ - -#include -#include -#include -#include -#include - -#define VOP_INPUT_MAX_WIDTH 4096 -/* - * Registers in this file - * REG_CFG_DONE: Register config done flag - * VERSION_INFO: Version for vop - * SYS_CTRL: System control register0 - * SYS_CTRL1: System control register1 - * DSP_CTRL0: Display control register0 - * DSP_CTRL1: Display control register1 - * DSP_BG: Background color - * MCU_CTRL: MCU mode control register - * WB_CTRL0: write back ctrl0 - * WB_CTRL1: write back ctrl1 - * WB_YRGB_MST: write back yrgb mst - * WB_CBR_MST: write back cbr mst - * WIN0_CTRL0: Win0 ctrl register0 - * WIN0_CTRL1: Win0 ctrl register1 - * WIN0_COLOR_KEY: Win0 color key register - * WIN0_VIR: Win0 virtual stride - * WIN0_YRGB_MST: Win0 YRGB memory start address - * WIN0_CBR_MST: Win0 Cbr memory start address - * WIN0_ACT_INFO: Win0 active window width/height - * WIN0_DSP_INFO: Win0 display width/height on panel - * WIN0_DSP_ST: Win0 display start point on panel - * WIN0_SCL_FACTOR_YRGB: Win0 YRGB scaling factor - * WIN0_SCL_FACTOR_CBR: Win0 Cbr scaling factor - * WIN0_SCL_OFFSET: Win0 scaling start point offset - * WIN0_SRC_ALPHA_CTRL: Win0 alpha source control register - * WIN0_DST_ALPHA_CTRL: Win0 alpha destination control register - * WIN0_FADING_CTRL: Win0 fading contrl register - * WIN0_CTRL2: Win0 ctrl register2 - * WIN1_CTRL0: Win1 ctrl register0 - * WIN1_CTRL1: Win1 ctrl register1 - * WIN1_COLOR_KEY: Win1 color key register - * WIN1_VIR: win1 virtual stride - * WIN1_YRGB_MST: Win1 YRGB memory start address - * WIN1_CBR_MST: Win1 Cbr memory start address - * WIN1_ACT_INFO: Win1 active window width/height - * WIN1_DSP_INFO: Win1 display width/height on panel - * WIN1_DSP_ST: Win1 display start point on panel - * WIN1_SCL_FACTOR_YRGB: Win1 YRGB scaling factor - * WIN1_SCL_FACTOR_CBR: Win1 Cbr scaling factor - * WIN1_SCL_OFFSET: Win1 scaling start point offset - * WIN1_SRC_ALPHA_CTRL: Win1 alpha source control register - * WIN1_DST_ALPHA_CTRL: Win1 alpha destination control register - * WIN1_FADING_CTRL: Win1 fading contrl register - * WIN1_CTRL2: Win1 ctrl register2 - * WIN2_CTRL0: win2 ctrl register0 - * WIN2_CTRL1: win2 ctrl register1 - * WIN2_VIR0_1: Win2 virtual stride0 and virtaul stride1 - * WIN2_VIR2_3: Win2 virtual stride2 and virtaul stride3 - * WIN2_MST0: Win2 memory start address0 - * WIN2_DSP_INFO0: Win2 display width0/height0 on panel - * WIN2_DSP_ST0: Win2 display start point0 on panel - * WIN2_COLOR_KEY: Win2 color key register - * WIN2_MST1: Win2 memory start address1 - * WIN2_DSP_INFO1: Win2 display width1/height1 on panel - * WIN2_DSP_ST1: Win2 display start point1 on panel - * WIN2_SRC_ALPHA_CTRL: Win2 alpha source control register - * WIN2_MST2: Win2 memory start address2 - * WIN2_DSP_INFO2: Win2 display width2/height2 on panel - * WIN2_DSP_ST2: Win2 display start point2 on panel - * WIN2_DST_ALPHA_CTRL: Win2 alpha destination control register - * WIN2_MST3: Win2 memory start address3 - * WIN2_DSP_INFO3: Win2 display width3/height3 on panel - * WIN2_DSP_ST3: Win2 display start point3 on panel - * WIN2_FADING_CTRL: Win2 fading contrl register - * WIN3_CTRL0: Win3 ctrl register0 - * WIN3_CTRL1: Win3 ctrl register1 - * WIN3_VIR0_1: Win3 virtual stride0 and virtaul stride1 - * WIN3_VIR2_3: Win3 virtual stride2 and virtaul stride3 - * WIN3_MST0: Win3 memory start address0 - * WIN3_DSP_INFO0: Win3 display width0/height0 on panel - * WIN3_DSP_ST0: Win3 display start point0 on panel - * WIN3_COLOR_KEY: Win3 color key register - * WIN3_MST1: Win3 memory start address1 - * WIN3_DSP_INFO1: Win3 display width1/height1 on panel - * WIN3_DSP_ST1: Win3 display start point1 on panel - * WIN3_SRC_ALPHA_CTRL: Win3 alpha source control register - * WIN3_MST2: Win3 memory start address2 - * WIN3_DSP_INFO2: Win3 display width2/height2 on panel - * WIN3_DSP_ST2: Win3 display start point2 on panel - * WIN3_DST_ALPHA_CTRL: Win3 alpha destination control register - * WIN3_MST3: Win3 memory start address3 - * WIN3_DSP_INFO3: Win3 display width3/height3 on panel - * WIN3_DSP_ST3: Win3 display start point3 on panel - * WIN3_FADING_CTRL: Win3 fading contrl register - * HWC_CTRL0: Hwc ctrl register0 - * HWC_CTRL1: Hwc ctrl register1 - * HWC_MST: Hwc memory start address - * HWC_DSP_ST: Hwc display start point on panel - * HWC_SRC_ALPHA_CTRL: Hwc alpha source control register - * HWC_DST_ALPHA_CTRL: Hwc alpha destination control register - * HWC_FADING_CTRL: Hwc fading contrl register - * HWC_RESERVED1: Hwc reserved - * POST_DSP_HACT_INFO: Post scaler down horizontal start and end - * POST_DSP_VACT_INFO: Panel active horizontal scanning start point - * and end point - * POST_SCL_FACTOR_YRGB: Post yrgb scaling factor - * POST_RESERVED: Post reserved - * POST_SCL_CTRL: Post scaling start point offset - * POST_DSP_VACT_INFO_F1: Panel active horizontal scanning start point - * and end point F1 - * DSP_HTOTAL_HS_END: Panel scanning horizontal width and hsync pulse end point - * DSP_HACT_ST_END: Panel active horizontal scanning start point and end point - * DSP_VTOTAL_VS_END: Panel scanning vertical height and vsync pulse end point - * DSP_VACT_ST_END: Panel active vertical scanning start point and end point - * DSP_VS_ST_END_F1: Vertical scanning start point and vsync pulse end point - * of even filed in interlace mode - * DSP_VACT_ST_END_F1: Vertical scanning active start point and end point of - * even filed in interlace mode - * PWM_CTRL: PWM Control Register - * PWM_PERIOD_HPR: PWM Period Register/High Polarity Capture Register - * PWM_DUTY_LPR: PWM Duty Register/Low Polarity Capture Register - * PWM_CNT: PWM Counter Register - * BCSH_COLOR_BAR: Color bar config register - * BCSH_BCS: Brightness contrast saturation*contrast config register - * BCSH_H: Sin hue and cos hue config register - * BCSH_CTRL: BCSH contrl register - * CABC_CTRL0: Content Adaptive Backlight Control register0 - * CABC_CTRL1: Content Adaptive Backlight Control register1 - * CABC_CTRL2: Content Adaptive Backlight Control register2 - * CABC_CTRL3: Content Adaptive Backlight Control register3 - * CABC_GAUSS_LINE0_0: CABC gauss line config register00 - * CABC_GAUSS_LINE0_1: CABC gauss line config register01 - * CABC_GAUSS_LINE1_0: CABC gauss line config register10 - * CABC_GAUSS_LINE1_1: CABC gauss line config register11 - * CABC_GAUSS_LINE2_0: CABC gauss line config register20 - * CABC_GAUSS_LINE2_1: CABC gauss line config register21 - * FRC_LOWER01_0: FRC lookup table config register010 - * FRC_LOWER01_1: FRC lookup table config register011 - * FRC_LOWER10_0: FRC lookup table config register100 - * FRC_LOWER10_1: FRC lookup table config register101 - * FRC_LOWER11_0: FRC lookup table config register110 - * FRC_LOWER11_1: FRC lookup table config register111 - * AFBCD0_CTRL: - * AFBCD0_HDR_PTR: - * AFBCD0_PIC_SIZE: - * AFBCD0_STATUS: - * AFBCD1_CTRL: - * AFBCD1_HDR_PTR: - * AFBCD1_PIC_SIZE: - * AFBCD1_STATUS: - * AFBCD2_CTRL: - * AFBCD2_HDR_PTR: - * AFBCD2_PIC_SIZE: - * AFBCD2_STATUS: - * AFBCD3_CTRL: - * AFBCD3_HDR_PTR: - * AFBCD3_PIC_SIZE: - * AFBCD3_STATUS: - * INTR_EN0: Interrupt enable register - * INTR_CLEAR0: Interrupt clear register - * INTR_STATUS0: interrupt status - * INTR_RAW_STATUS0: raw interrupt status - * INTR_EN1: Interrupt enable register - * INTR_CLEAR1: Interrupt clear register - * INTR_STATUS1: interrupt status - * INTR_RAW_STATUS1: raw interrupt status - * LINE_FLAG: Line flag config register - * VOP_STATUS: vop status register - * BLANKING_VALUE: Register0000 Abstract - * MCU_BYPASS_PORT: Mcu bypass value - * WIN0_DSP_BG: Win0 layer background color - * WIN1_DSP_BG: Win1 layer background color - * WIN2_DSP_BG: Win2 layer background color - * WIN3_DSP_BG: Win3 layer background color - * YUV2YUV_WIN: YUV to YUV win - * YUV2YUV_POST: Post YUV to YUV - * AUTO_GATING_EN: Auto gating enable - * DBG_PERF_LATENCY_CTRL0: Axi performance latency module contrl register0 - * DBG_PERF_RD_MAX_LATENCY_NUM0: Read max latency number - * DBG_PERF_RD_LATENCY_THR_NUM0: The number of bigger than configed - * threshold value - * DBG_PERF_RD_LATENCY_SAMP_NUM0: Total sample number - * DBG_CABC0: CABC debug register0 - * DBG_CABC1: CABC debug register1 - * DBG_CABC2: CABC debug register2 - * DBG_CABC3: CABC debug register3 - * DBG_WIN0_REG0: Vop debug win0 register0 - * DBG_WIN0_REG1: Vop debug win0 register1 - * DBG_WIN0_REG2: Vop debug win0 register2 - * DBG_WIN0_RESERVED: Vop debug win0 register3 reserved - * DBG_WIN1_REG0: Vop debug win1 register0 - * DBG_WIN1_REG1: Vop debug win1 register1 - * DBG_WIN1_REG2: Vop debug win1 register2 - * DBG_WIN1_RESERVED: Vop debug win1 register3 reserved - * DBG_WIN2_REG0: Vop debug win2 register0 - * DBG_WIN2_REG1: Vop debug win2 register1 - * DBG_WIN2_REG2: Vop debug win2 register2 - * DBG_WIN2_REG3: Vop debug win2 register3 - * DBG_WIN3_REG0: Vop debug win3 register0 - * DBG_WIN3_REG1: Vop debug win3 register1 - * DBG_WIN3_REG2: Vop debug win3 register2 - * DBG_WIN3_REG3: Vop debug win3 register3 - * DBG_PRE_REG0: Vop debug pre register0 - * DBG_PRE_RESERVED: Vop debug pre register1 reserved - * DBG_POST_REG0: Vop debug post register0 - * DBG_POST_REG1: Vop debug - * DBG_DATAO: debug data output path - * DBG_DATAO_2: debug data output path 2 - * WIN2_LUT_ADDR: Win2 lut base address - * WIN3_LUT_ADDR: Win3 lut base address - * HWC_LUT_ADDR: Hwc lut base address - * GAMMA0_LUT_ADDR: GAMMA lut base address - * GAMMA1_LUT_ADDR: GAMMA lut base address - * CABC_GAMMA_LUT_ADDR: CABC GAMMA lut base address - * MCU_BYPASS_WPORT: - * MCU_BYPASS_RPORT: - */ - -static inline u64 val_mask(int val, u64 msk, int shift) -{ - return (msk << (shift + 32)) | ((msk & val) << shift); -} - -#define VAL_MASK(x, width, shift) val_mask(x, (1 << width) - 1, shift) - -#define MASK(x) (V_##x(0) >> 32) - -#define REG_CFG_DONE 0x00000000 -#define V_REG_LOAD_EN(x) VAL_MASK(x, 1, 0) -#define V_REG_LOAD_WIN0_EN(x) VAL_MASK(x, 1, 1) -#define V_REG_LOAD_WIN1_EN(x) VAL_MASK(x, 1, 2) -#define V_REG_LOAD_WIN2_EN(x) VAL_MASK(x, 1, 3) -#define V_REG_LOAD_WIN3_EN(x) VAL_MASK(x, 1, 4) -#define V_REG_LOAD_HWC_EN(x) VAL_MASK(x, 1, 5) -#define V_REG_LOAD_IEP_EN(x) VAL_MASK(x, 1, 6) -#define V_REG_LOAD_FBDC_EN(x) VAL_MASK(x, 1, 7) -#define V_REG_LOAD_SYS_EN(x) VAL_MASK(x, 1, 8) -#define V_WRITE_MASK(x) VAL_MASK(x, 16, 16) -#define VERSION_INFO 0x00000004 -#define V_SVNBUILD(x) VAL_MASK(x, 16, 0) -#define V_MINOR(x) VAL_MASK(x, 8, 16) -#define V_MAJOR(x) VAL_MASK(x, 8, 24) -#define SYS_CTRL 0x00000008 -#define V_DIRECT_PATH_EN(x) VAL_MASK(x, 1, 0) -#define V_DIRECT_PATH_LAYER_SEL(x) VAL_MASK(x, 2, 1) -#define V_MIPI_DUAL_CHANNEL_EN(x) VAL_MASK(x, 1, 3) -#define V_EDPI_HALT_EN(x) VAL_MASK(x, 1, 8) -#define V_EDPI_WMS_MODE(x) VAL_MASK(x, 1, 9) -#define V_EDPI_WMS_FS(x) VAL_MASK(x, 1, 10) -#define V_GLOBAL_REGDONE_EN(x) VAL_MASK(x, 1, 11) -#define V_RGB_OUT_EN(x) VAL_MASK(x, 1, 12) -#define V_HDMI_OUT_EN(x) VAL_MASK(x, 1, 13) -#define V_EDP_OUT_EN(x) VAL_MASK(x, 1, 14) -#define V_MIPI_OUT_EN(x) VAL_MASK(x, 1, 15) -#define V_OVERLAY_MODE(x) VAL_MASK(x, 1, 16) -/* rk3399 only*/ -#define V_DP_OUT_EN(x) VAL_MASK(x, 1, 11) -/* rk322x only */ -#define V_FS_SAME_ADDR_MASK_EN(x) VAL_MASK(x, 1, 17) -#define V_POST_LB_MODE(x) VAL_MASK(x, 1, 18) -#define V_WIN23_PRI_OPT_MODE(x) VAL_MASK(x, 1, 19) -/* rk322x only */ -#define V_VOP_MMU_EN(x) VAL_MASK(x, 1, 20) -/* rk3399 only */ -#define V_VOP_FIELD_TVE_TIMING_POL(x) VAL_MASK(x, 1, 20) -#define V_VOP_DMA_STOP(x) VAL_MASK(x, 1, 21) -#define V_VOP_STANDBY_EN(x) VAL_MASK(x, 1, 22) -#define V_AUTO_GATING_EN(x) VAL_MASK(x, 1, 23) -#define V_SW_IMD_TVE_DCLK_EN(x) VAL_MASK(x, 1, 24) -#define V_SW_IMD_TVE_DCLK_POL(x) VAL_MASK(x, 1, 25) -#define V_SW_TVE_MODE(x) VAL_MASK(x, 1, 26) -#define V_SW_UV_OFFSET_EN(x) VAL_MASK(x, 1, 27) -#define V_SW_GENLOCK(x) VAL_MASK(x, 1, 28) -#define V_SW_DAC_SEL(x) VAL_MASK(x, 1, 29) -#define V_VOP_FIELD_TVE_POL(x) VAL_MASK(x, 1, 30) -#define V_IO_PAD_CLK_SEL(x) VAL_MASK(x, 1, 31) -#define SYS_CTRL1 0x0000000c -#define V_NOC_HURRY_EN(x) VAL_MASK(x, 1, 0) -#define V_NOC_HURRY_VALUE(x) VAL_MASK(x, 2, 1) -#define V_NOC_HURRY_THRESHOLD(x) VAL_MASK(x, 6, 3) -#define V_NOC_QOS_EN(x) VAL_MASK(x, 1, 9) -#define V_NOC_WIN_QOS(x) VAL_MASK(x, 2, 10) -#define V_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 12) -#define V_AXI_OUTSTANDING_MAX_NUM(x) VAL_MASK(x, 5, 13) -#define V_NOC_HURRY_W_MODE(x) VAL_MASK(x, 2, 20) -#define V_NOC_HURRY_W_VALUE(x) VAL_MASK(x, 2, 22) -#define V_REG_DONE_FRM(x) VAL_MASK(x, 1, 24) -#define V_DSP_FP_STANDBY(x) VAL_MASK(x, 1, 31) -#define DSP_CTRL0 0x00000010 -#define V_DSP_OUT_MODE(x) VAL_MASK(x, 4, 0) -#define V_SW_CORE_DCLK_SEL(x) VAL_MASK(x, 1, 4) -/* rk322x */ -#define V_SW_HDMI_CLK_I_SEL(x) VAL_MASK(x, 1, 5) -/* rk3399 */ -#define V_P2I_EN(x) VAL_MASK(x, 1, 5) -#define V_DSP_DCLK_DDR(x) VAL_MASK(x, 1, 8) -#define V_DSP_DDR_PHASE(x) VAL_MASK(x, 1, 9) -#define V_DSP_INTERLACE(x) VAL_MASK(x, 1, 10) -#define V_DSP_FIELD_POL(x) VAL_MASK(x, 1, 11) -#define V_DSP_BG_SWAP(x) VAL_MASK(x, 1, 12) -#define V_DSP_RB_SWAP(x) VAL_MASK(x, 1, 13) -#define V_DSP_RG_SWAP(x) VAL_MASK(x, 1, 14) -#define V_DSP_DELTA_SWAP(x) VAL_MASK(x, 1, 15) -#define V_DSP_DUMMY_SWAP(x) VAL_MASK(x, 1, 16) -#define V_DSP_OUT_ZERO(x) VAL_MASK(x, 1, 17) -#define V_DSP_BLANK_EN(x) VAL_MASK(x, 1, 18) -#define V_DSP_BLACK_EN(x) VAL_MASK(x, 1, 19) -#define V_DSP_CCIR656_AVG(x) VAL_MASK(x, 1, 20) -#define V_DSP_YUV_CLIP(x) VAL_MASK(x, 1, 21) -#define V_DSP_X_MIR_EN(x) VAL_MASK(x, 1, 22) -#define V_DSP_Y_MIR_EN(x) VAL_MASK(x, 1, 23) -/* rk3399 only */ -#define V_SW_TVE_OUTPUT_SEL(x) VAL_MASK(x, 1, 25) -#define V_DSP_FIELD(x) VAL_MASK(x, 1, 31) -#define DSP_CTRL1 0x00000014 -#define V_DSP_LUT_EN(x) VAL_MASK(x, 1, 0) -#define V_PRE_DITHER_DOWN_EN(x) VAL_MASK(x, 1, 1) -#define V_DITHER_DOWN_EN(x) VAL_MASK(x, 1, 2) -#define V_DITHER_DOWN_MODE(x) VAL_MASK(x, 1, 3) -#define V_DITHER_DOWN_SEL(x) VAL_MASK(x, 1, 4) -#define V_DITHER_UP_EN(x) VAL_MASK(x, 1, 6) -#define V_UPDATE_GAMMA_LUT(x) VAL_MASK(x, 1, 7) -#define V_DSP_LAYER0_SEL(x) VAL_MASK(x, 2, 8) -#define V_DSP_LAYER1_SEL(x) VAL_MASK(x, 2, 10) -#define V_DSP_LAYER2_SEL(x) VAL_MASK(x, 2, 12) -#define V_DSP_LAYER3_SEL(x) VAL_MASK(x, 2, 14) -#define V_RGB_LVDS_HSYNC_POL(x) VAL_MASK(x, 1, 16) -#define V_RGB_LVDS_VSYNC_POL(x) VAL_MASK(x, 1, 17) -#define V_RGB_LVDS_DEN_POL(x) VAL_MASK(x, 1, 18) -#define V_RGB_LVDS_DCLK_POL(x) VAL_MASK(x, 1, 19) -#define V_HDMI_HSYNC_POL(x) VAL_MASK(x, 1, 20) -#define V_HDMI_VSYNC_POL(x) VAL_MASK(x, 1, 21) -#define V_HDMI_DEN_POL(x) VAL_MASK(x, 1, 22) -#define V_HDMI_DCLK_POL(x) VAL_MASK(x, 1, 23) -#define V_EDP_HSYNC_POL(x) VAL_MASK(x, 1, 24) -#define V_EDP_VSYNC_POL(x) VAL_MASK(x, 1, 25) -#define V_EDP_DEN_POL(x) VAL_MASK(x, 1, 26) -#define V_EDP_DCLK_POL(x) VAL_MASK(x, 1, 27) -#define V_MIPI_HSYNC_POL(x) VAL_MASK(x, 1, 28) -#define V_MIPI_VSYNC_POL(x) VAL_MASK(x, 1, 29) -#define V_MIPI_DEN_POL(x) VAL_MASK(x, 1, 30) -#define V_MIPI_DCLK_POL(x) VAL_MASK(x, 1, 31) -/* rk3399 only*/ -#define V_DP_HSYNC_POL(x) VAL_MASK(x, 1, 16) -#define V_DP_VSYNC_POL(x) VAL_MASK(x, 1, 17) -#define V_DP_DEN_POL(x) VAL_MASK(x, 1, 18) -#define V_DP_DCLK_POL(x) VAL_MASK(x, 1, 19) -#define DSP_BG 0x00000018 -#define V_DSP_BG_BLUE(x) VAL_MASK(x, 10, 0) -#define V_DSP_BG_GREEN(x) VAL_MASK(x, 10, 10) -#define V_DSP_BG_RED(x) VAL_MASK(x, 10, 20) -#define MCU_CTRL 0x0000001c -#define V_MCU_PIX_TOTAL(x) VAL_MASK(x, 6, 0) -#define V_MCU_CS_PST(x) VAL_MASK(x, 4, 6) -#define V_MCU_CS_PEND(x) VAL_MASK(x, 6, 10) -#define V_MCU_RW_PST(x) VAL_MASK(x, 4, 16) -#define V_MCU_RW_PEND(x) VAL_MASK(x, 6, 20) -#define V_MCU_CLK_SEL(x) VAL_MASK(x, 1, 26) -#define V_MCU_HOLD_MODE(x) VAL_MASK(x, 1, 27) -#define V_MCU_FRAME_ST(x) VAL_MASK(x, 1, 28) -#define V_MCU_RS(x) VAL_MASK(x, 1, 29) -#define V_MCU_BYPASS(x) VAL_MASK(x, 1, 30) -#define V_MCU_TYPE(x) VAL_MASK(x, 1, 31) -#define WB_CTRL0 0x00000020 -#define V_WB_EN(x) VAL_MASK(x, 1, 0) -#define V_WB_FMT(x) VAL_MASK(x, 3, 1) -#define V_WB_DITHER_EN(x) VAL_MASK(x, 1, 4) -#define V_WB_RGB2YUV_EN(x) VAL_MASK(x, 1, 5) -#define V_WB_RGB2YUV_MODE(x) VAL_MASK(x, 1, 6) -#define V_WB_XPSD_BIL_EN(x) VAL_MASK(x, 1, 7) -#define V_WB_YTHROW_EN(x) VAL_MASK(x, 1, 8) -#define V_WB_YTHROW_MODE(x) VAL_MASK(x, 1, 9) -#define V_WB_HANDSHAKE_MODE(x) VAL_MASK(x, 1, 11) -#define V_WB_YRGB_ID(x) VAL_MASK(x, 4, 24) -#define V_WB_UV_ID(x) VAL_MASK(x, 4, 28) -#define WB_CTRL1 0x00000024 -#define V_WB_WIDTH(x) VAL_MASK(x, 12, 0) -#define V_WB_XPSD_BIL_FACTOR(x) VAL_MASK(x, 14, 16) -#define WB_YRGB_MST 0x00000028 -#define V_WB_YRGB_MST(x) VAL_MASK(x, 32, 0) -#define WB_CBR_MST 0x0000002c -#define V_WB_CBR_MST(x) VAL_MASK(x, 32, 0) -#define WIN0_CTRL0 0x00000030 -#define V_WIN0_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN0_DATA_FMT(x) VAL_MASK(x, 3, 1) -#define V_WIN0_FMT_10(x) VAL_MASK(x, 1, 4) -#define V_WIN0_LB_MODE(x) VAL_MASK(x, 3, 5) -#define V_WIN0_INTERLACE_READ(x) VAL_MASK(x, 1, 8) -#define V_WIN0_NO_OUTSTANDING(x) VAL_MASK(x, 1, 9) -#define V_WIN0_CSC_MODE(x) VAL_MASK(x, 2, 10) -#define V_WIN0_RB_SWAP(x) VAL_MASK(x, 1, 12) -#define V_WIN0_ALPHA_SWAP(x) VAL_MASK(x, 1, 13) -#define V_WIN0_MID_SWAP(x) VAL_MASK(x, 1, 14) -#define V_WIN0_UV_SWAP(x) VAL_MASK(x, 1, 15) -#define V_WIN0_HW_PRE_MUL_EN(x) VAL_MASK(x, 1, 16) -/* rk3399 only */ -#define V_WIN0_YUYV(x) VAL_MASK(x, 1, 17) -#define V_WIN0_YRGB_DEFLICK(x) VAL_MASK(x, 1, 18) -#define V_WIN0_CBR_DEFLICK(x) VAL_MASK(x, 1, 19) -#define V_WIN0_YUV_CLIP(x) VAL_MASK(x, 1, 20) -#define V_WIN0_X_MIR_EN(x) VAL_MASK(x, 1, 21) -#define V_WIN0_Y_MIR_EN(x) VAL_MASK(x, 1, 22) -#define V_WIN0_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 24) -#define V_WIN0_AXI_OUTSTANDING_MAX_NUM(x) VAL_MASK(x, 5, 25) -#define V_WIN0_DMA_BURST_LENGTH(x) VAL_MASK(x, 2, 30) -#define WIN0_CTRL1 0x00000034 -#define V_WIN0_YRGB_AXI_GATHER_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN0_CBR_AXI_GATHER_EN(x) VAL_MASK(x, 1, 1) -#define V_WIN0_BIC_COE_SEL(x) VAL_MASK(x, 2, 2) -#define V_WIN0_VSD_YRGB_GT4(x) VAL_MASK(x, 1, 4) -#define V_WIN0_VSD_YRGB_GT2(x) VAL_MASK(x, 1, 5) -#define V_WIN0_VSD_CBR_GT4(x) VAL_MASK(x, 1, 6) -#define V_WIN0_VSD_CBR_GT2(x) VAL_MASK(x, 1, 7) -#define V_WIN0_YRGB_AXI_GATHER_NUM(x) VAL_MASK(x, 4, 8) -#define V_WIN0_CBR_AXI_GATHER_NUM(x) VAL_MASK(x, 3, 12) -#define V_WIN0_LINE_LOAD_MODE(x) VAL_MASK(x, 1, 15) -#define V_WIN0_YRGB_HOR_SCL_MODE(x) VAL_MASK(x, 2, 16) -#define V_WIN0_YRGB_VER_SCL_MODE(x) VAL_MASK(x, 2, 18) -#define V_WIN0_YRGB_HSD_MODE(x) VAL_MASK(x, 2, 20) -#define V_WIN0_YRGB_VSU_MODE(x) VAL_MASK(x, 1, 22) -#define V_WIN0_YRGB_VSD_MODE(x) VAL_MASK(x, 1, 23) -#define V_WIN0_CBR_HOR_SCL_MODE(x) VAL_MASK(x, 2, 24) -#define V_WIN0_CBR_VER_SCL_MODE(x) VAL_MASK(x, 2, 26) -#define V_WIN0_CBR_HSD_MODE(x) VAL_MASK(x, 2, 28) -#define V_WIN0_CBR_VSU_MODE(x) VAL_MASK(x, 1, 30) -#define V_WIN0_CBR_VSD_MODE(x) VAL_MASK(x, 1, 31) -#define WIN0_COLOR_KEY 0x00000038 -#define V_WIN0_KEY_COLOR(x) VAL_MASK(x, 24, 0) -#define V_WIN0_KEY_EN(x) VAL_MASK(x, 1, 31) -#define WIN0_VIR 0x0000003c -#define V_WIN0_VIR_STRIDE(x) VAL_MASK(x, 16, 0) -#define V_WIN0_VIR_STRIDE_UV(x) VAL_MASK(x, 16, 16) -#define WIN0_YRGB_MST 0x00000040 -#define V_WIN0_YRGB_MST(x) VAL_MASK(x, 32, 0) -#define WIN0_CBR_MST 0x00000044 -#define V_WIN0_CBR_MST(x) VAL_MASK(x, 32, 0) -#define WIN0_ACT_INFO 0x00000048 -#define V_WIN0_ACT_WIDTH(x) VAL_MASK(x, 13, 0) -#define V_FIELD0002(x) VAL_MASK(x, 1, 13) -#define V_FIELD0001(x) VAL_MASK(x, 1, 14) -#define V_FIELD0000(x) VAL_MASK(x, 1, 15) -#define V_WIN0_ACT_HEIGHT(x) VAL_MASK(x, 13, 16) -#define WIN0_DSP_INFO 0x0000004c -#define V_WIN0_DSP_WIDTH(x) VAL_MASK(x, 12, 0) -#define V_WIN0_DSP_HEIGHT(x) VAL_MASK(x, 12, 16) -#define WIN0_DSP_ST 0x00000050 -#define V_WIN0_DSP_XST(x) VAL_MASK(x, 13, 0) -#define V_WIN0_DSP_YST(x) VAL_MASK(x, 13, 16) -#define WIN0_SCL_FACTOR_YRGB 0x00000054 -#define V_WIN0_HS_FACTOR_YRGB(x) VAL_MASK(x, 16, 0) -#define V_WIN0_VS_FACTOR_YRGB(x) VAL_MASK(x, 16, 16) -#define WIN0_SCL_FACTOR_CBR 0x00000058 -#define V_WIN0_HS_FACTOR_CBR(x) VAL_MASK(x, 16, 0) -#define V_WIN0_VS_FACTOR_CBR(x) VAL_MASK(x, 16, 16) -#define WIN0_SCL_OFFSET 0x0000005c -#define V_WIN0_HS_OFFSET_YRGB(x) VAL_MASK(x, 8, 0) -#define V_WIN0_HS_OFFSET_CBR(x) VAL_MASK(x, 8, 8) -#define V_WIN0_VS_OFFSET_YRGB(x) VAL_MASK(x, 8, 16) -#define V_WIN0_VS_OFFSET_CBR(x) VAL_MASK(x, 8, 24) -#define WIN0_SRC_ALPHA_CTRL 0x00000060 -#define V_WIN0_SRC_ALPHA_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN0_SRC_COLOR_MODE(x) VAL_MASK(x, 1, 1) -#define V_WIN0_SRC_ALPHA_MODE(x) VAL_MASK(x, 1, 2) -#define V_WIN0_SRC_BLEND_MODE(x) VAL_MASK(x, 2, 3) -#define V_WIN0_SRC_ALPHA_CAL_MODE(x) VAL_MASK(x, 1, 5) -#define V_WIN0_SRC_FACTOR_MODE(x) VAL_MASK(x, 3, 6) -#define V_WIN0_SRC_GLOBAL_ALPHA(x) VAL_MASK(x, 8, 16) -#define V_WIN0_FADING_VALUE(x) VAL_MASK(x, 8, 24) -#define WIN0_DST_ALPHA_CTRL 0x00000064 -#define V_WIN0_DST_M0_RESERVED(x) VAL_MASK(x, 6, 0) -#define V_WIN0_DST_FACTOR_MODE(x) VAL_MASK(x, 3, 6) -#define WIN0_FADING_CTRL 0x00000068 -#define V_LAYER0_FADING_OFFSET_R(x) VAL_MASK(x, 8, 0) -#define V_LAYER0_FADING_OFFSET_G(x) VAL_MASK(x, 8, 8) -#define V_LAYER0_FADING_OFFSET_B(x) VAL_MASK(x, 8, 16) -#define V_LAYER0_FADING_EN(x) VAL_MASK(x, 1, 24) -#define WIN0_CTRL2 0x0000006c -#define V_WIN_RID_WIN0_YRGB(x) VAL_MASK(x, 4, 0) -#define V_WIN_RID_WIN0_CBR(x) VAL_MASK(x, 4, 4) -#define WIN1_CTRL0 0x00000070 -#define V_WIN1_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN1_DATA_FMT(x) VAL_MASK(x, 3, 1) -#define V_WIN1_FMT_10(x) VAL_MASK(x, 1, 4) -#define V_WIN1_LB_MODE(x) VAL_MASK(x, 3, 5) -#define V_WIN1_INTERLACE_READ(x) VAL_MASK(x, 1, 8) -#define V_WIN1_NO_OUTSTANDING(x) VAL_MASK(x, 1, 9) -#define V_WIN1_CSC_MODE(x) VAL_MASK(x, 2, 10) -#define V_WIN1_RB_SWAP(x) VAL_MASK(x, 1, 12) -#define V_WIN1_ALPHA_SWAP(x) VAL_MASK(x, 1, 13) -#define V_WIN1_MID_SWAP(x) VAL_MASK(x, 1, 14) -#define V_WIN1_UV_SWAP(x) VAL_MASK(x, 1, 15) -#define V_WIN1_HW_PRE_MUL_EN(x) VAL_MASK(x, 1, 16) -/* rk3399 only */ -#define V_WIN1_YUYV(x) VAL_MASK(x, 1, 17) -#define V_WIN1_YRGB_DEFLICK(x) VAL_MASK(x, 1, 18) -#define V_WIN1_CBR_DEFLICK(x) VAL_MASK(x, 1, 19) -#define V_WIN1_YUV_CLIP(x) VAL_MASK(x, 1, 20) -#define V_WIN1_X_MIR_EN(x) VAL_MASK(x, 1, 21) -#define V_WIN1_Y_MIR_EN(x) VAL_MASK(x, 1, 22) -#define V_WIN1_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 24) -#define V_WIN1_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 25) -#define V_WIN1_DMA_BURST_LENGTH(x) VAL_MASK(x, 2, 30) -#define WIN1_CTRL1 0x00000074 -#define V_WIN1_YRGB_AXI_GATHER_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN1_CBR_AXI_GATHER_EN(x) VAL_MASK(x, 1, 1) -#define V_WIN1_BIC_COE_SEL(x) VAL_MASK(x, 2, 2) -#define V_WIN1_VSD_YRGB_GT4(x) VAL_MASK(x, 1, 4) -#define V_WIN1_VSD_YRGB_GT2(x) VAL_MASK(x, 1, 5) -#define V_WIN1_VSD_CBR_GT4(x) VAL_MASK(x, 1, 6) -#define V_WIN1_VSD_CBR_GT2(x) VAL_MASK(x, 1, 7) -#define V_WIN1_YRGB_AXI_GATHER_NUM(x) VAL_MASK(x, 4, 8) -#define V_WIN1_CBR_AXI_GATHER_NUM(x) VAL_MASK(x, 3, 12) -#define V_WIN1_LINE_LOAD_MODE(x) VAL_MASK(x, 1, 15) -#define V_WIN1_YRGB_HOR_SCL_MODE(x) VAL_MASK(x, 2, 16) -#define V_WIN1_YRGB_VER_SCL_MODE(x) VAL_MASK(x, 2, 18) -#define V_WIN1_YRGB_HSD_MODE(x) VAL_MASK(x, 2, 20) -#define V_WIN1_YRGB_VSU_MODE(x) VAL_MASK(x, 1, 22) -#define V_WIN1_YRGB_VSD_MODE(x) VAL_MASK(x, 1, 23) -#define V_WIN1_CBR_HOR_SCL_MODE(x) VAL_MASK(x, 2, 24) -#define V_WIN1_CBR_VER_SCL_MODE(x) VAL_MASK(x, 2, 26) -#define V_WIN1_CBR_HSD_MODE(x) VAL_MASK(x, 2, 28) -#define V_WIN1_CBR_VSU_MODE(x) VAL_MASK(x, 1, 30) -#define V_WIN1_CBR_VSD_MODE(x) VAL_MASK(x, 1, 31) -#define WIN1_COLOR_KEY 0x00000078 -#define V_WIN1_KEY_COLOR(x) VAL_MASK(x, 24, 0) -#define V_WIN1_KEY_EN(x) VAL_MASK(x, 1, 31) -#define WIN1_VIR 0x0000007c -#define V_WIN1_VIR_STRIDE(x) VAL_MASK(x, 16, 0) -#define V_WIN1_VIR_STRIDE_UV(x) VAL_MASK(x, 16, 16) -#define WIN1_YRGB_MST 0x00000080 -#define V_WIN1_YRGB_MST(x) VAL_MASK(x, 32, 0) -#define WIN1_CBR_MST 0x00000084 -#define V_WIN1_CBR_MST(x) VAL_MASK(x, 32, 0) -#define WIN1_ACT_INFO 0x00000088 -#define V_WIN1_ACT_WIDTH(x) VAL_MASK(x, 13, 0) -#define V_WIN1_ACT_HEIGHT(x) VAL_MASK(x, 13, 16) -#define WIN1_DSP_INFO 0x0000008c -#define V_WIN1_DSP_WIDTH(x) VAL_MASK(x, 12, 0) -#define V_WIN1_DSP_HEIGHT(x) VAL_MASK(x, 12, 16) -#define WIN1_DSP_ST 0x00000090 -#define V_WIN1_DSP_XST(x) VAL_MASK(x, 13, 0) -#define V_WIN1_DSP_YST(x) VAL_MASK(x, 13, 16) -#define WIN1_SCL_FACTOR_YRGB 0x00000094 -#define V_WIN1_HS_FACTOR_YRGB(x) VAL_MASK(x, 16, 0) -#define V_WIN1_VS_FACTOR_YRGB(x) VAL_MASK(x, 16, 16) -#define WIN1_SCL_FACTOR_CBR 0x00000098 -#define V_WIN1_HS_FACTOR_CBR(x) VAL_MASK(x, 16, 0) -#define V_WIN1_VS_FACTOR_CBR(x) VAL_MASK(x, 16, 16) -#define WIN1_SCL_OFFSET 0x0000009c -#define V_WIN1_HS_OFFSET_YRGB(x) VAL_MASK(x, 8, 0) -#define V_WIN1_HS_OFFSET_CBR(x) VAL_MASK(x, 8, 8) -#define V_WIN1_VS_OFFSET_YRGB(x) VAL_MASK(x, 8, 16) -#define V_WIN1_VS_OFFSET_CBR(x) VAL_MASK(x, 8, 24) -#define WIN1_SRC_ALPHA_CTRL 0x000000a0 -#define V_WIN1_SRC_ALPHA_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN1_SRC_COLOR_MODE(x) VAL_MASK(x, 1, 1) -#define V_WIN1_SRC_ALPHA_MODE(x) VAL_MASK(x, 1, 2) -#define V_WIN1_SRC_BLEND_MODE(x) VAL_MASK(x, 2, 3) -#define V_WIN1_SRC_ALPHA_CAL_MODE(x) VAL_MASK(x, 1, 5) -#define V_WIN1_SRC_FACTOR_MODE(x) VAL_MASK(x, 3, 6) -#define V_WIN1_SRC_GLOBAL_ALPHA(x) VAL_MASK(x, 8, 16) -#define V_WIN1_FADING_VALUE(x) VAL_MASK(x, 8, 24) -#define WIN1_DST_ALPHA_CTRL 0x000000a4 -#define V_WIN1_DSP_M0_RESERVED(x) VAL_MASK(x, 6, 0) -#define V_WIN1_DST_FACTOR_M0(x) VAL_MASK(x, 3, 6) -#define WIN1_FADING_CTRL 0x000000a8 -#define V_WIN1_FADING_OFFSET_R(x) VAL_MASK(x, 8, 0) -#define V_WIN1_FADING_OFFSET_G(x) VAL_MASK(x, 8, 8) -#define V_WIN1_FADING_OFFSET_B(x) VAL_MASK(x, 8, 16) -#define V_WIN1_FADING_EN(x) VAL_MASK(x, 1, 24) -#define WIN1_CTRL2 0x000000ac -#define V_WIN_RID_WIN1_YRGB(x) VAL_MASK(x, 4, 0) -#define V_WIN_RID_WIN1_CBR(x) VAL_MASK(x, 4, 4) -#define WIN2_CTRL0 0x000000b0 -#define V_WIN2_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN2_INTERLACE_READ(x) VAL_MASK(x, 1, 1) -#define V_WIN2_CSC_MODE(x) VAL_MASK(x, 2, 2) -#define V_WIN2_MST0_EN(x) VAL_MASK(x, 1, 4) -#define V_WIN2_DATA_FMT0(x) VAL_MASK(x, 2, 5) -#define V_WIN2_MST1_EN(x) VAL_MASK(x, 1, 8) -#define V_WIN2_DATA_FMT1(x) VAL_MASK(x, 2, 9) -#define V_WIN2_MST2_EN(x) VAL_MASK(x, 1, 12) -#define V_WIN2_DATA_FMT2(x) VAL_MASK(x, 2, 13) -#define V_WIN2_MST3_EN(x) VAL_MASK(x, 1, 16) -#define V_WIN2_DATA_FMT3(x) VAL_MASK(x, 2, 17) -#define V_WIN2_RB_SWAP0(x) VAL_MASK(x, 1, 20) -#define V_WIN2_ALPHA_SWAP0(x) VAL_MASK(x, 1, 21) -#define V_WIN2_ENDIAN_SWAP0(x) VAL_MASK(x, 1, 22) -#define V_WIN2_RB_SWAP1(x) VAL_MASK(x, 1, 23) -#define V_WIN2_ALPHA_SWAP1(x) VAL_MASK(x, 1, 24) -#define V_WIN2_ENDIAN_SWAP1(x) VAL_MASK(x, 1, 25) -#define V_WIN2_RB_SWAP2(x) VAL_MASK(x, 1, 26) -#define V_WIN2_ALPHA_SWAP2(x) VAL_MASK(x, 1, 27) -#define V_WIN2_ENDIAN_SWAP2(x) VAL_MASK(x, 1, 28) -#define V_WIN2_RB_SWAP3(x) VAL_MASK(x, 1, 29) -#define V_WIN2_ALPHA_SWAP3(x) VAL_MASK(x, 1, 30) -#define V_WIN2_ENDIAN_SWAP3(x) VAL_MASK(x, 1, 31) -#define WIN2_CTRL1 0x000000b4 -#define V_WIN2_AXI_GATHER_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN2_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 1) -#define V_WIN2_DMA_BURST_LENGTH(x) VAL_MASK(x, 2, 2) -#define V_WIN2_AXI_GATHER_NUM(x) VAL_MASK(x, 4, 4) -#define V_WIN2_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 8) -#define V_WIN2_NO_OUTSTANDING(x) VAL_MASK(x, 1, 14) -#define V_WIN2_Y_MIR_EN(x) VAL_MASK(x, 1, 15) -#define V_WIN2_LUT_EN(x) VAL_MASK(x, 1, 16) -#define V_WIN_RID_WIN2(x) VAL_MASK(x, 4, 20) -#define WIN2_VIR0_1 0x000000b8 -#define V_WIN2_VIR_STRIDE0(x) VAL_MASK(x, 16, 0) -#define V_WIN2_VIR_STRIDE1(x) VAL_MASK(x, 16, 16) -#define WIN2_VIR2_3 0x000000bc -#define V_WIN2_VIR_STRIDE2(x) VAL_MASK(x, 16, 0) -#define V_WIN2_VIR_STRIDE3(x) VAL_MASK(x, 16, 16) -#define WIN2_MST0 0x000000c0 -#define V_WIN2_MST0(x) VAL_MASK(x, 32, 0) -#define WIN2_DSP_INFO0 0x000000c4 -#define V_WIN2_DSP_WIDTH0(x) VAL_MASK(x, 12, 0) -#define V_WIN2_DSP_HEIGHT0(x) VAL_MASK(x, 12, 16) -#define WIN2_DSP_ST0 0x000000c8 -#define V_WIN2_DSP_XST0(x) VAL_MASK(x, 13, 0) -#define V_WIN2_DSP_YST0(x) VAL_MASK(x, 13, 16) -#define WIN2_COLOR_KEY 0x000000cc -#define V_WIN2_KEY_COLOR(x) VAL_MASK(x, 24, 0) -#define V_WIN2_KEY_EN(x) VAL_MASK(x, 1, 24) -#define WIN2_MST1 0x000000d0 -#define V_WIN2_MST1(x) VAL_MASK(x, 32, 0) -#define WIN2_DSP_INFO1 0x000000d4 -#define V_WIN2_DSP_WIDTH1(x) VAL_MASK(x, 12, 0) -#define V_WIN2_DSP_HEIGHT1(x) VAL_MASK(x, 12, 16) -#define WIN2_DSP_ST1 0x000000d8 -#define V_WIN2_DSP_XST1(x) VAL_MASK(x, 13, 0) -#define V_WIN2_DSP_YST1(x) VAL_MASK(x, 13, 16) -#define WIN2_SRC_ALPHA_CTRL 0x000000dc -#define V_WIN2_SRC_ALPHA_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN2_SRC_COLOR_MODE(x) VAL_MASK(x, 1, 1) -#define V_WIN2_SRC_ALPHA_MODE(x) VAL_MASK(x, 1, 2) -#define V_WIN2_SRC_BLEND_MODE(x) VAL_MASK(x, 2, 3) -#define V_WIN2_SRC_ALPHA_CAL_MODE(x) VAL_MASK(x, 1, 5) -#define V_WIN2_SRC_FACTOR_MODE(x) VAL_MASK(x, 3, 6) -#define V_WIN2_SRC_GLOBAL_ALPHA(x) VAL_MASK(x, 8, 16) -#define V_WIN2_FADING_VALUE(x) VAL_MASK(x, 8, 24) -#define WIN2_MST2 0x000000e0 -#define V_WIN2_MST2(x) VAL_MASK(x, 32, 0) -#define WIN2_DSP_INFO2 0x000000e4 -#define V_WIN2_DSP_WIDTH2(x) VAL_MASK(x, 12, 0) -#define V_WIN2_DSP_HEIGHT2(x) VAL_MASK(x, 12, 16) -#define WIN2_DSP_ST2 0x000000e8 -#define V_WIN2_DSP_XST2(x) VAL_MASK(x, 13, 0) -#define V_WIN2_DSP_YST2(x) VAL_MASK(x, 13, 16) -#define WIN2_DST_ALPHA_CTRL 0x000000ec -#define V_WIN2_DST_M0_RESERVED(x) VAL_MASK(x, 6, 0) -#define V_WIN2_DST_FACTOR_MODE(x) VAL_MASK(x, 3, 6) -#define WIN2_MST3 0x000000f0 -#define V_WIN2_MST3(x) VAL_MASK(x, 32, 0) -#define WIN2_DSP_INFO3 0x000000f4 -#define V_WIN2_DSP_WIDTH3(x) VAL_MASK(x, 12, 0) -#define V_WIN2_DSP_HEIGHT3(x) VAL_MASK(x, 12, 16) -#define WIN2_DSP_ST3 0x000000f8 -#define V_WIN2_DSP_XST3(x) VAL_MASK(x, 13, 0) -#define V_WIN2_DSP_YST3(x) VAL_MASK(x, 13, 16) -#define WIN2_FADING_CTRL 0x000000fc -#define V_WIN2_FADING_OFFSET_R(x) VAL_MASK(x, 8, 0) -#define V_WIN2_FADING_OFFSET_G(x) VAL_MASK(x, 8, 8) -#define V_WIN2_FADING_OFFSET_B(x) VAL_MASK(x, 8, 16) -#define V_WIN2_FADING_EN(x) VAL_MASK(x, 1, 24) -#define WIN3_CTRL0 0x00000100 -#define V_WIN3_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN3_INTERLACE_READ(x) VAL_MASK(x, 1, 1) -#define V_WIN3_CSC_MODE(x) VAL_MASK(x, 2, 2) -#define V_WIN3_MST0_EN(x) VAL_MASK(x, 1, 4) -#define V_WIN3_DATA_FMT0(x) VAL_MASK(x, 2, 5) -#define V_WIN3_MST1_EN(x) VAL_MASK(x, 1, 8) -#define V_WIN3_DATA_FMT1(x) VAL_MASK(x, 2, 9) -#define V_WIN3_MST2_EN(x) VAL_MASK(x, 1, 12) -#define V_WIN3_DATA_FMT2(x) VAL_MASK(x, 2, 13) -#define V_WIN3_MST3_EN(x) VAL_MASK(x, 1, 16) -#define V_WIN3_DATA_FMT3(x) VAL_MASK(x, 2, 17) -#define V_WIN3_RB_SWAP0(x) VAL_MASK(x, 1, 20) -#define V_WIN3_ALPHA_SWAP0(x) VAL_MASK(x, 1, 21) -#define V_WIN3_ENDIAN_SWAP0(x) VAL_MASK(x, 1, 22) -#define V_WIN3_RB_SWAP1(x) VAL_MASK(x, 1, 23) -#define V_WIN3_ALPHA_SWAP1(x) VAL_MASK(x, 1, 24) -#define V_WIN3_ENDIAN_SWAP1(x) VAL_MASK(x, 1, 25) -#define V_WIN3_RB_SWAP2(x) VAL_MASK(x, 1, 26) -#define V_WIN3_ALPHA_SWAP2(x) VAL_MASK(x, 1, 27) -#define V_WIN3_ENDIAN_SWAP2(x) VAL_MASK(x, 1, 28) -#define V_WIN3_RB_SWAP3(x) VAL_MASK(x, 1, 29) -#define V_WIN3_ALPHA_SWAP3(x) VAL_MASK(x, 1, 30) -#define V_WIN3_ENDIAN_SWAP3(x) VAL_MASK(x, 1, 31) -#define WIN3_CTRL1 0x00000104 -#define V_WIN3_AXI_GATHER_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN3_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 1) -#define V_WIN3_DMA_BURST_LENGTH(x) VAL_MASK(x, 2, 2) -#define V_WIN3_AXI_GATHER_NUM(x) VAL_MASK(x, 4, 4) -#define V_WIN3_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 8) -#define V_WIN3_NO_OUTSTANDING(x) VAL_MASK(x, 1, 14) -#define V_WIN3_Y_MIR_EN(x) VAL_MASK(x, 1, 15) -#define V_WIN3_LUT_EN(x) VAL_MASK(x, 1, 16) -#define V_WIN_RID_WIN3(x) VAL_MASK(x, 4, 20) -#define WIN3_VIR0_1 0x00000108 -#define V_WIN3_VIR_STRIDE0(x) VAL_MASK(x, 16, 0) -#define V_WIN3_VIR_STRIDE1(x) VAL_MASK(x, 16, 16) -#define WIN3_VIR2_3 0x0000010c -#define V_WIN3_VIR_STRIDE2(x) VAL_MASK(x, 16, 0) -#define V_WIN3_VIR_STRIDE3(x) VAL_MASK(x, 16, 16) -#define WIN3_MST0 0x00000110 -#define V_WIN3_MST0(x) VAL_MASK(x, 32, 0) -#define WIN3_DSP_INFO0 0x00000114 -#define V_WIN3_DSP_WIDTH0(x) VAL_MASK(x, 12, 0) -#define V_WIN3_DSP_HEIGHT0(x) VAL_MASK(x, 12, 16) -#define WIN3_DSP_ST0 0x00000118 -#define V_WIN3_DSP_XST0(x) VAL_MASK(x, 13, 0) -#define V_WIN3_DSP_YST0(x) VAL_MASK(x, 13, 16) -#define WIN3_COLOR_KEY 0x0000011c -#define V_WIN3_KEY_COLOR(x) VAL_MASK(x, 24, 0) -#define V_WIN3_KEY_EN(x) VAL_MASK(x, 1, 24) -#define WIN3_MST1 0x00000120 -#define V_WIN3_MST1(x) VAL_MASK(x, 32, 0) -#define WIN3_DSP_INFO1 0x00000124 -#define V_WIN3_DSP_WIDTH1(x) VAL_MASK(x, 12, 0) -#define V_WIN3_DSP_HEIGHT1(x) VAL_MASK(x, 12, 16) -#define WIN3_DSP_ST1 0x00000128 -#define V_WIN3_DSP_XST1(x) VAL_MASK(x, 13, 0) -#define V_WIN3_DSP_YST1(x) VAL_MASK(x, 13, 16) -#define WIN3_SRC_ALPHA_CTRL 0x0000012c -#define V_WIN3_SRC_ALPHA_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN3_SRC_COLOR_MODE(x) VAL_MASK(x, 1, 1) -#define V_WIN3_SRC_ALPHA_MODE(x) VAL_MASK(x, 1, 2) -#define V_WIN3_SRC_BLEND_MODE(x) VAL_MASK(x, 2, 3) -#define V_WIN3_SRC_ALPHA_CAL_MODE(x) VAL_MASK(x, 1, 5) -#define V_WIN3_SRC_FACTOR_MODE(x) VAL_MASK(x, 3, 6) -#define V_WIN3_SRC_GLOBAL_ALPHA(x) VAL_MASK(x, 8, 16) -#define V_WIN3_FADING_VALUE(x) VAL_MASK(x, 8, 24) -#define WIN3_MST2 0x00000130 -#define V_WIN3_MST2(x) VAL_MASK(x, 32, 0) -#define WIN3_DSP_INFO2 0x00000134 -#define V_WIN3_DSP_WIDTH2(x) VAL_MASK(x, 12, 0) -#define V_WIN3_DSP_HEIGHT2(x) VAL_MASK(x, 12, 16) -#define WIN3_DSP_ST2 0x00000138 -#define V_WIN3_DSP_XST2(x) VAL_MASK(x, 13, 0) -#define V_WIN3_DSP_YST2(x) VAL_MASK(x, 13, 16) -#define WIN3_DST_ALPHA_CTRL 0x0000013c -#define V_WIN3_DST_FACTOR_RESERVED(x) VAL_MASK(x, 6, 0) -#define V_WIN3_DST_FACTOR_MODE(x) VAL_MASK(x, 3, 6) -#define WIN3_MST3 0x00000140 -#define V_WIN3_MST3(x) VAL_MASK(x, 32, 0) -#define WIN3_DSP_INFO3 0x00000144 -#define V_WIN3_DSP_WIDTH3(x) VAL_MASK(x, 12, 0) -#define V_WIN3_DSP_HEIGHT3(x) VAL_MASK(x, 12, 16) -#define WIN3_DSP_ST3 0x00000148 -#define V_WIN3_DSP_XST3(x) VAL_MASK(x, 13, 0) -#define V_WIN3_DSP_YST3(x) VAL_MASK(x, 13, 16) -#define WIN3_FADING_CTRL 0x0000014c -#define V_WIN3_FADING_OFFSET_R(x) VAL_MASK(x, 8, 0) -#define V_WIN3_FADING_OFFSET_G(x) VAL_MASK(x, 8, 8) -#define V_WIN3_FADING_OFFSET_B(x) VAL_MASK(x, 8, 16) -#define V_WIN3_FADING_EN(x) VAL_MASK(x, 1, 24) -#define HWC_CTRL0 0x00000150 -#define V_HWC_EN(x) VAL_MASK(x, 1, 0) -#define V_HWC_DATA_FMT(x) VAL_MASK(x, 3, 1) -#define V_HWC_MODE(x) VAL_MASK(x, 1, 4) -#define V_HWC_SIZE(x) VAL_MASK(x, 2, 5) -#define V_HWC_INTERLACE_READ(x) VAL_MASK(x, 1, 8) -#define V_HWC_CSC_MODE(x) VAL_MASK(x, 2, 10) -#define V_HWC_RB_SWAP(x) VAL_MASK(x, 1, 12) -#define V_HWC_ALPHA_SWAP(x) VAL_MASK(x, 1, 13) -#define V_HWC_ENDIAN_SWAP(x) VAL_MASK(x, 1, 14) -#define HWC_CTRL1 0x00000154 -#define V_HWC_AXI_GATHER_EN(x) VAL_MASK(x, 1, 0) -#define V_HWC_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 1) -#define V_HWC_DMA_BURST_LENGTH(x) VAL_MASK(x, 2, 2) -#define V_HWC_AXI_GATHER_NUM(x) VAL_MASK(x, 3, 4) -#define V_HWC_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 8) -#define V_HWC_RGB2YUV_EN(x) VAL_MASK(x, 1, 13) -#define V_HWC_NO_OUTSTANDING(x) VAL_MASK(x, 1, 14) -#define V_HWC_Y_MIR_EN(x) VAL_MASK(x, 1, 15) -#define V_HWC_LUT_EN(x) VAL_MASK(x, 1, 16) -#define V_WIN_RID_HWC(x) VAL_MASK(x, 4, 20) -#define HWC_MST 0x00000158 -#define V_HWC_MST(x) VAL_MASK(x, 32, 0) -#define HWC_DSP_ST 0x0000015c -#define V_HWC_DSP_XST(x) VAL_MASK(x, 13, 0) -#define V_HWC_DSP_YST(x) VAL_MASK(x, 13, 16) -#define HWC_SRC_ALPHA_CTRL 0x00000160 -#define V_HWC_SRC_ALPHA_EN(x) VAL_MASK(x, 1, 0) -#define V_HWC_SRC_COLOR_MODE(x) VAL_MASK(x, 1, 1) -#define V_HWC_SRC_ALPHA_MODE(x) VAL_MASK(x, 1, 2) -#define V_HWC_SRC_BLEND_MODE(x) VAL_MASK(x, 2, 3) -#define V_HWC_SRC_ALPHA_CAL_MODE(x) VAL_MASK(x, 1, 5) -#define V_HWC_SRC_FACTOR_MODE(x) VAL_MASK(x, 3, 6) -#define V_HWC_SRC_GLOBAL_ALPHA(x) VAL_MASK(x, 8, 16) -#define V_HWC_FADING_VALUE(x) VAL_MASK(x, 8, 24) -#define HWC_DST_ALPHA_CTRL 0x00000164 -#define V_HWC_DST_M0_RESERVED(x) VAL_MASK(x, 6, 0) -#define V_HWC_DST_FACTOR_MODE(x) VAL_MASK(x, 3, 6) -#define HWC_FADING_CTRL 0x00000168 -#define V_HWC_FADING_OFFSET_R(x) VAL_MASK(x, 8, 0) -#define V_HWC_FADING_OFFSET_G(x) VAL_MASK(x, 8, 8) -#define V_HWC_FADING_OFFSET_B(x) VAL_MASK(x, 8, 16) -#define V_HWC_FADING_EN(x) VAL_MASK(x, 1, 24) -#define HWC_RESERVED1 0x0000016c -#define POST_DSP_HACT_INFO 0x00000170 -#define V_DSP_HACT_END_POST(x) VAL_MASK(x, 13, 0) -#define V_DSP_HACT_ST_POST(x) VAL_MASK(x, 13, 16) -#define POST_DSP_VACT_INFO 0x00000174 -#define V_DSP_VACT_END_POST(x) VAL_MASK(x, 13, 0) -#define V_DSP_VACT_ST_POST(x) VAL_MASK(x, 13, 16) -#define POST_SCL_FACTOR_YRGB 0x00000178 -#define V_POST_HS_FACTOR_YRGB(x) VAL_MASK(x, 16, 0) -#define V_POST_VS_FACTOR_YRGB(x) VAL_MASK(x, 16, 16) -#define POST_RESERVED 0x0000017c -#define POST_SCL_CTRL 0x00000180 -#define V_POST_HOR_SD_EN(x) VAL_MASK(x, 1, 0) -#define V_POST_VER_SD_EN(x) VAL_MASK(x, 1, 1) -#define V_DSP_OUT_RGB_YUV(x) VAL_MASK(x, 1, 2) -#define POST_DSP_VACT_INFO_F1 0x00000184 -#define V_DSP_VACT_END_POST(x) VAL_MASK(x, 13, 0) -#define V_DSP_VACT_ST_POST(x) VAL_MASK(x, 13, 16) -#define DSP_HTOTAL_HS_END 0x00000188 -#define V_DSP_HS_END(x) VAL_MASK(x, 13, 0) -#define V_DSP_HTOTAL(x) VAL_MASK(x, 13, 16) -#define DSP_HACT_ST_END 0x0000018c -#define V_DSP_HACT_END(x) VAL_MASK(x, 13, 0) -#define V_DSP_HACT_ST(x) VAL_MASK(x, 13, 16) -#define DSP_VTOTAL_VS_END 0x00000190 -#define V_DSP_VS_END(x) VAL_MASK(x, 13, 0) -#define V_SW_DSP_VTOTAL_IMD(x) VAL_MASK(x, 1, 15) -#define V_DSP_VTOTAL(x) VAL_MASK(x, 13, 16) -#define DSP_VACT_ST_END 0x00000194 -#define V_DSP_VACT_END(x) VAL_MASK(x, 13, 0) -#define V_DSP_VACT_ST(x) VAL_MASK(x, 13, 16) -#define DSP_VS_ST_END_F1 0x00000198 -#define V_DSP_VS_END_F1(x) VAL_MASK(x, 13, 0) -#define V_DSP_VS_ST_F1(x) VAL_MASK(x, 13, 16) -#define DSP_VACT_ST_END_F1 0x0000019c -#define V_DSP_VACT_END_F1(x) VAL_MASK(x, 13, 0) -#define V_DSP_VACT_ST_F1(x) VAL_MASK(x, 13, 16) -#define PWM_CTRL 0x000001a0 -#define V_PWM_EN(x) VAL_MASK(x, 1, 0) -#define V_PWM_MODE(x) VAL_MASK(x, 2, 1) -#define V_DUTY_POL(x) VAL_MASK(x, 1, 3) -#define V_INACTIVE_POL(x) VAL_MASK(x, 1, 4) -#define V_OUTPUT_MODE(x) VAL_MASK(x, 1, 5) -#define V_LP_EN(x) VAL_MASK(x, 1, 8) -#define V_CLK_SEL(x) VAL_MASK(x, 1, 9) -#define V_PRESCALE(x) VAL_MASK(x, 3, 12) -#define V_SCALE(x) VAL_MASK(x, 8, 16) -#define V_RPT(x) VAL_MASK(x, 8, 24) -#define PWM_PERIOD_HPR 0x000001a4 -#define V_PWM_PERIOD(x) VAL_MASK(x, 32, 0) -#define PWM_DUTY_LPR 0x000001a8 -#define V_PWM_DUTY(x) VAL_MASK(x, 32, 0) -#define PWM_CNT 0x000001ac -#define V_PWM_CNT(x) VAL_MASK(x, 32, 0) -#define BCSH_COLOR_BAR 0x000001b0 -#define V_BCSH_EN(x) VAL_MASK(x, 1, 0) -#define V_COLOR_BAR_Y(x) VAL_MASK(x, 8, 8) -#define V_COLOR_BAR_U(x) VAL_MASK(x, 8, 16) -#define V_COLOR_BAR_V(x) VAL_MASK(x, 8, 24) -#define BCSH_BCS 0x000001b4 -#define V_BRIGHTNESS(x) VAL_MASK(x, 8, 0) -#define V_CONTRAST(x) VAL_MASK(x, 9, 8) -#define V_SAT_CON(x) VAL_MASK(x, 10, 20) -#define V_OUT_MODE(x) VAL_MASK(x, 2, 30) -#define BCSH_H 0x000001b8 -#define V_SIN_HUE(x) VAL_MASK(x, 9, 0) -#define V_COS_HUE(x) VAL_MASK(x, 9, 16) -#define BCSH_CTRL 0x000001bc -#define V_BCSH_Y2R_EN(x) VAL_MASK(x, 1, 0) -#define V_BCSH_Y2R_CSC_MODE(x) VAL_MASK(x, 2, 2) -#define V_BCSH_R2Y_EN(x) VAL_MASK(x, 1, 4) -#define V_BCSH_R2Y_CSC_MODE(x) VAL_MASK(x, 1, 6) -#define CABC_CTRL0 0x000001c0 -#define V_CABC_EN(x) VAL_MASK(x, 1, 0) -#define V_CABC_HANDLE_EN(x) VAL_MASK(x, 1, 1) -#define V_PWM_CONFIG_MODE(x) VAL_MASK(x, 2, 2) -#define V_CABC_CALC_PIXEL_NUM(x) VAL_MASK(x, 23, 4) -#define CABC_CTRL1 0x000001c4 -#define V_CABC_LUT_EN(x) VAL_MASK(x, 1, 0) -#define V_CABC_TOTAL_NUM(x) VAL_MASK(x, 23, 4) -#define CABC_CTRL2 0x000001c8 -#define V_CABC_STAGE_DOWN(x) VAL_MASK(x, 8, 0) -#define V_CABC_STAGE_UP(x) VAL_MASK(x, 9, 8) -#define V_CABC_STAGE_UP_MODE(x) VAL_MASK(x, 1, 19) -#define V_MAX_SCALE_CFG_VALUE(x) VAL_MASK(x, 9, 20) -#define V_MAX_SCALE_CFG_ENABLE(x) VAL_MASK(x, 1, 31) -#define CABC_CTRL3 0x000001cc -#define V_CABC_GLOBAL_DN(x) VAL_MASK(x, 8, 0) -#define V_CABC_GLOBAL_DN_LIMIT_EN(x) VAL_MASK(x, 1, 8) -#define CABC_GAUSS_LINE0_0 0x000001d0 -#define V_T_LINE0_0(x) VAL_MASK(x, 8, 0) -#define V_T_LINE0_1(x) VAL_MASK(x, 8, 8) -#define V_T_LINE0_2(x) VAL_MASK(x, 8, 16) -#define V_T_LINE0_3(x) VAL_MASK(x, 8, 24) -#define CABC_GAUSS_LINE0_1 0x000001d4 -#define V_T_LINE0_4(x) VAL_MASK(x, 8, 0) -#define V_T_LINE0_5(x) VAL_MASK(x, 8, 8) -#define V_T_LINE0_6(x) VAL_MASK(x, 8, 16) -#define CABC_GAUSS_LINE1_0 0x000001d8 -#define V_T_LINE1_0(x) VAL_MASK(x, 8, 0) -#define V_T_LINE1_1(x) VAL_MASK(x, 8, 8) -#define V_T_LINE1_2(x) VAL_MASK(x, 8, 16) -#define V_T_LINE1_3(x) VAL_MASK(x, 8, 24) -#define CABC_GAUSS_LINE1_1 0x000001dc -#define V_T_LINE1_4(x) VAL_MASK(x, 8, 0) -#define V_T_LINE1_5(x) VAL_MASK(x, 8, 8) -#define V_T_LINE1_6(x) VAL_MASK(x, 8, 16) -#define CABC_GAUSS_LINE2_0 0x000001e0 -#define V_T_LINE2_0(x) VAL_MASK(x, 8, 0) -#define V_T_LINE2_1(x) VAL_MASK(x, 8, 8) -#define V_T_LINE2_2(x) VAL_MASK(x, 8, 16) -#define V_T_LINE2_3(x) VAL_MASK(x, 8, 24) -#define CABC_GAUSS_LINE2_1 0x000001e4 -#define V_T_LINE2_4(x) VAL_MASK(x, 8, 0) -#define V_T_LINE2_5(x) VAL_MASK(x, 8, 8) -#define V_T_LINE2_6(x) VAL_MASK(x, 8, 16) -#define FRC_LOWER01_0 0x000001e8 -#define V_LOWER01_FRM0(x) VAL_MASK(x, 16, 0) -#define V_LOWER01_FRM1(x) VAL_MASK(x, 16, 16) -#define FRC_LOWER01_1 0x000001ec -#define V_LOWER01_FRM2(x) VAL_MASK(x, 16, 0) -#define V_LOWER01_FRM3(x) VAL_MASK(x, 16, 16) -#define FRC_LOWER10_0 0x000001f0 -#define V_LOWER10_FRM0(x) VAL_MASK(x, 16, 0) -#define V_LOWER10_FRM1(x) VAL_MASK(x, 16, 16) -#define FRC_LOWER10_1 0x000001f4 -#define V_LOWER10_FRM2(x) VAL_MASK(x, 16, 0) -#define V_LOWER10_FRM3(x) VAL_MASK(x, 16, 16) -#define FRC_LOWER11_0 0x000001f8 -#define V_LOWER11_FRM0(x) VAL_MASK(x, 16, 0) -#define V_LOWER11_FRM1(x) VAL_MASK(x, 16, 16) -#define FRC_LOWER11_1 0x000001fc -#define V_LOWER11_FRM2(x) VAL_MASK(x, 16, 0) -#define V_LOWER11_FRM3(x) VAL_MASK(x, 16, 16) -#define AFBCD0_CTRL 0x00000200 -#define V_VOP_FBDC_EN(x) VAL_MASK(x, 1, 0) -#define V_VOP_FBDC_WIN_SEL(x) VAL_MASK(x, 2, 1) -#define V_FBDC_RSTN(x) VAL_MASK(x, 1, 3) -#define V_VOP_FBDC_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 4) -#define V_VOP_FBDC_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 9) -#define V_FBDC_RID(x) VAL_MASK(x, 4, 12) -#define V_AFBCD_HREG_PIXEL_PACKING_FMT(x) VAL_MASK(x, 5, 16) -#define V_AFBCD_HREG_BLOCK_SPLIT(x) VAL_MASK(x, 1, 21) -#define AFBCD0_HDR_PTR 0x00000204 -#define V_AFBCD_HREG_HDR_PTR(x) VAL_MASK(x, 32, 0) -#define AFBCD0_PIC_SIZE 0x00000208 -#define V_AFBCD_HREG_PIC_WIDTH(x) VAL_MASK(x, 16, 0) -#define V_AFBCD_HREG_PIC_HEIGHT(x) VAL_MASK(x, 16, 16) -#define AFBCD0_STATUS 0x0000020c -#define V_AFBCD_HREG_IDLE_N(x) VAL_MASK(x, 1, 0) -#define V_AFBCD_HREG_DEC_RESP(x) VAL_MASK(x, 1, 1) -#define V_AFBCD_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 2) -#define AFBCD1_CTRL 0x00000220 -#define V_VOP_FBDC1_EN(x) VAL_MASK(x, 1, 0) -#define V_VOP_FBDC1_WIN_SEL(x) VAL_MASK(x, 2, 1) -#define V_FBDC1_RSTN(x) VAL_MASK(x, 1, 3) -#define V_VOP_FBDC1_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 4) -#define V_VOP_FBDC1_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 9) -#define V_FBDC1_RID(x) VAL_MASK(x, 4, 12) -#define V_AFBCD1_HREG_PIXEL_PACKING_FMT(x) VAL_MASK(x, 5, 16) -#define V_AFBCD1_HREG_BLOCK_SPLIT(x) VAL_MASK(x, 1, 21) -#define AFBCD1_HDR_PTR 0x00000224 -#define V_AFBCD1_HREG_HDR_PTR(x) VAL_MASK(x, 32, 0) -#define AFBCD1_PIC_SIZE 0x00000228 -#define V_AFBCD1_HREG_PIC_WIDTH(x) VAL_MASK(x, 16, 0) -#define V_AFBCD1_HREG_PIC_HEIGHT(x) VAL_MASK(x, 16, 16) -#define AFBCD1_STATUS 0x0000022c -#define V_AFBCD1_HREG_IDLE_N(x) VAL_MASK(x, 1, 0) -#define V_AFBCD1_HREG_DEC_RESP(x) VAL_MASK(x, 1, 1) -#define V_AFBCD1_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 2) -#define AFBCD2_CTRL 0x00000240 -#define V_VOP_FBDC2_EN(x) VAL_MASK(x, 1, 0) -#define V_VOP_FBDC2_WIN_SEL(x) VAL_MASK(x, 2, 1) -#define V_FBDC2_RSTN(x) VAL_MASK(x, 1, 3) -#define V_VOP_FBDC2_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 4) -#define V_VOP_FBDC2_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 9) -#define V_FBDC2_RID(x) VAL_MASK(x, 4, 12) -#define V_AFBCD2_HREG_PIXEL_PACKING_FMT(x) VAL_MASK(x, 5, 16) -#define V_AFBCD2_HREG_BLOCK_SPLIT(x) VAL_MASK(x, 1, 21) -#define AFBCD2_HDR_PTR 0x00000244 -#define V_AFBCD2_HREG_HDR_PTR(x) VAL_MASK(x, 32, 0) -#define AFBCD2_PIC_SIZE 0x00000248 -#define V_AFBCD2_HREG_PIC_WIDTH(x) VAL_MASK(x, 16, 0) -#define V_AFBCD2_HREG_PIC_HEIGHT(x) VAL_MASK(x, 16, 16) -#define AFBCD2_STATUS 0x0000024c -#define V_AFBCD2_HREG_IDLE_N(x) VAL_MASK(x, 1, 0) -#define V_AFBCD2_HREG_DEC_RESP(x) VAL_MASK(x, 1, 1) -#define V_AFBCD2_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 2) -#define AFBCD3_CTRL 0x00000260 -#define V_VOP_FBDC3_EN(x) VAL_MASK(x, 1, 0) -#define V_VOP_FBDC3_WIN_SEL(x) VAL_MASK(x, 1, 1) -#define V_FBDC3_RSTN(x) VAL_MASK(x, 1, 2) -#define V_VOP_FBDC3_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 3) -#define V_VOP_FBDC3_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 8) -#define V_FBDC3_RID(x) VAL_MASK(x, 4, 12) -#define V_AFBCD3_HREG_PIXEL_PACKING_FMT(x) VAL_MASK(x, 5, 16) -#define V_AFBCD3_HREG_BLOCK_SPLIT(x) VAL_MASK(x, 1, 21) -#define AFBCD3_HDR_PTR 0x00000264 -#define V_AFBCD3_HREG_HDR_PTR(x) VAL_MASK(x, 32, 0) -#define AFBCD3_PIC_SIZE 0x00000268 -#define V_AFBCD3_HREG_PIC_WIDTH(x) VAL_MASK(x, 16, 0) -#define V_AFBCD3_HREG_PIC_HEIGHT(x) VAL_MASK(x, 16, 16) -#define AFBCD3_STATUS 0x0000026c -#define V_AFBCD3_HREG_IDLE_N(x) VAL_MASK(x, 1, 0) -#define V_AFBCD3_HREG_DEC_RESP(x) VAL_MASK(x, 1, 1) -#define V_AFBCD3_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 2) -#define INTR_EN0 0x00000280 -#define V_INTR_EN_FS(x) VAL_MASK(x, 1, 0) -#define V_INTR_EN_FS_NEW(x) VAL_MASK(x, 1, 1) -#define V_INTR_EN_ADDR_SAME(x) VAL_MASK(x, 1, 2) -#define V_INTR_EN_LINE_FLAG0(x) VAL_MASK(x, 1, 3) -#define V_INTR_EN_LINE_FLAG1(x) VAL_MASK(x, 1, 4) -#define V_INTR_EN_BUS_ERROR(x) VAL_MASK(x, 1, 5) -#define V_INTR_EN_WIN0_EMPTY(x) VAL_MASK(x, 1, 6) -#define V_INTR_EN_WIN1_EMPTY(x) VAL_MASK(x, 1, 7) -#define V_INTR_EN_WIN2_EMPTY(x) VAL_MASK(x, 1, 8) -#define V_INTR_EN_WIN3_EMPTY(x) VAL_MASK(x, 1, 9) -#define V_INTR_EN_HWC_EMPTY(x) VAL_MASK(x, 1, 10) -#define V_INTR_EN_POST_BUF_EMPTY(x) VAL_MASK(x, 1, 11) -/* rk3399 only */ -#define V_INTR_EN_FS_FIELD(x) VAL_MASK(x, 1, 12) -/* rk322x only */ -#define V_INTR_EN_PWM_GEN(x) VAL_MASK(x, 1, 12) -#define V_INTR_EN_DSP_HOLD_VALID(x) VAL_MASK(x, 1, 13) -#define V_INTR_EN_MMU(x) VAL_MASK(x, 1, 14) -#define V_INTR_EN_DMA_FINISH(x) VAL_MASK(x, 1, 15) -#define V_WRITE_MASK(x) VAL_MASK(x, 16, 16) -#define INTR_CLEAR0 0x00000284 -#define V_INT_CLR_FS(x) VAL_MASK(x, 1, 0) -#define V_INT_CLR_FS_NEW(x) VAL_MASK(x, 1, 1) -#define V_INT_CLR_ADDR_SAME(x) VAL_MASK(x, 1, 2) -#define V_INT_CLR_LINE_FLAG0(x) VAL_MASK(x, 1, 3) -#define V_INT_CLR_LINE_FLAG1(x) VAL_MASK(x, 1, 4) -#define V_INT_CLR_BUS_ERROR(x) VAL_MASK(x, 1, 5) -#define V_INT_CLR_WIN0_EMPTY(x) VAL_MASK(x, 1, 6) -#define V_INT_CLR_WIN1_EMPTY(x) VAL_MASK(x, 1, 7) -#define V_INT_CLR_WIN2_EMPTY(x) VAL_MASK(x, 1, 8) -#define V_INT_CLR_WIN3_EMPTY(x) VAL_MASK(x, 1, 9) -#define V_INT_CLR_HWC_EMPTY(x) VAL_MASK(x, 1, 10) -#define V_INT_CLR_POST_BUF_EMPTY(x) VAL_MASK(x, 1, 11) -/* rk3399 only */ -#define V_INT_CLR_FS_FIELD(x) VAL_MASK(x, 1, 12) -/* rk322x only */ -#define V_INT_CLR_PWM_GEN(x) VAL_MASK(x, 1, 12) -#define V_INT_CLR_DSP_HOLD_VALID(x) VAL_MASK(x, 1, 13) -#define V_INT_CLR_MMU(x) VAL_MASK(x, 1, 14) -#define V_INT_CLR_DMA_FINISH(x) VAL_MASK(x, 1, 15) -#define V_WRITE_MASK(x) VAL_MASK(x, 16, 16) -#define INTR_STATUS0 0x00000288 -#define V_INT_STATUS_FS(x) VAL_MASK(x, 1, 0) -#define V_INT_STATUS_FS_NEW(x) VAL_MASK(x, 1, 1) -#define V_INT_STATUS_ADDR_SAME(x) VAL_MASK(x, 1, 2) -#define V_INT_STATUS_LINE_FLAG0(x) VAL_MASK(x, 1, 3) -#define V_INT_STATUS_LINE_FLAG1(x) VAL_MASK(x, 1, 4) -#define V_INT_STATUS_BUS_ERROR(x) VAL_MASK(x, 1, 5) -#define V_INT_STATUS_WIN0_EMPTY(x) VAL_MASK(x, 1, 6) -#define V_INT_STATUS_WIN1_EMPTY(x) VAL_MASK(x, 1, 7) -#define V_INT_STATUS_WIN2_EMPTY(x) VAL_MASK(x, 1, 8) -#define V_INT_STATUS_WIN3_EMPTY(x) VAL_MASK(x, 1, 9) -#define V_INT_STATUS_HWC_EMPTY(x) VAL_MASK(x, 1, 10) -#define V_INT_STATUS_POST_BUF_EMPTY(x) VAL_MASK(x, 1, 11) -/* rk3399 only */ -#define V_INT_STATUS_FS_FIELD(x) VAL_MASK(x, 1, 12) -/* rk322x only */ -#define V_INT_STATUS_PWM_GEN(x) VAL_MASK(x, 1, 12) -#define V_INT_STATUS_DSP_HOLD_VALID(x) VAL_MASK(x, 1, 13) -#define V_INT_STATUS_MMU(x) VAL_MASK(x, 1, 14) -#define V_INT_STATUS_DMA_FINISH(x) VAL_MASK(x, 1, 15) -#define INTR_RAW_STATUS0 0x0000028c -#define V_INT_RAW_STATUS_FS(x) VAL_MASK(x, 1, 0) -#define V_INT_RAW_STATUS_FS_NEW(x) VAL_MASK(x, 1, 1) -#define V_INT_RAW_STATUS_ADDR_SAME(x) VAL_MASK(x, 1, 2) -#define V_INT_RAW_STATUS_LINE_FRAG0(x) VAL_MASK(x, 1, 3) -#define V_INT_RAW_STATUS_LINE_FRAG1(x) VAL_MASK(x, 1, 4) -#define V_INT_RAW_STATUS_BUS_ERROR(x) VAL_MASK(x, 1, 5) -#define V_INT_RAW_STATUS_WIN0_EMPTY(x) VAL_MASK(x, 1, 6) -#define V_INT_RAW_STATUS_WIN1_EMPTY(x) VAL_MASK(x, 1, 7) -#define V_INT_RAW_STATUS_WIN2_EMPTY(x) VAL_MASK(x, 1, 8) -#define V_INT_RAW_STATUS_WIN3_EMPTY(x) VAL_MASK(x, 1, 9) -#define V_INT_RAW_STATUS_HWC_EMPTY(x) VAL_MASK(x, 1, 10) -#define V_INT_RAW_STATUS_POST_BUF_EMPTY(x) VAL_MASK(x, 1, 11) -/* rk3399 only */ -#define V_INT_RAW_STATUS_FS_FIELD(x) VAL_MASK(x, 1, 12) -/* rk322x only */ -#define V_INT_RAW_STATUS_PWM_GEN(x) VAL_MASK(x, 1, 12) -#define V_INT_RAW_STATUS_DSP_HOLD_VALID(x) VAL_MASK(x, 1, 13) -#define V_INT_RAW_STATUS_MMU(x) VAL_MASK(x, 1, 14) -#define V_INT_RAW_STATUS_DMA_FINISH(x) VAL_MASK(x, 1, 15) -#define INTR_EN1 0x00000290 -#define V_INT_EN_FBCD0(x) VAL_MASK(x, 1, 0) -#define V_INT_EN_FBCD1(x) VAL_MASK(x, 1, 1) -#define V_INT_EN_FBCD2(x) VAL_MASK(x, 1, 2) -#define V_INT_EN_FBCD3(x) VAL_MASK(x, 1, 3) -#define V_INT_EN_AFBCD0_HREG_DEC_RESP(x) VAL_MASK(x, 1, 4) -#define V_INT_EN_AFBCD0_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 5) -#define V_INT_EN_AFBCD1_HREG_DEC_RESP(x) VAL_MASK(x, 1, 6) -#define V_INT_EN_AFBCD1_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 7) -#define V_INT_EN_AFBCD2_HREG_DEC_RESP(x) VAL_MASK(x, 1, 8) -#define V_INT_EN_AFBCD2_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 9) -#define V_INT_EN_AFBCD3_HREG_DEC_RESP(x) VAL_MASK(x, 1, 10) -#define V_INT_EN_AFBCD3_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 11) -#define V_INT_EN_WB_YRGB_FIFO_FULL(x) VAL_MASK(x, 1, 12) -#define V_INT_EN_WB_UV_FIFO_FULL(x) VAL_MASK(x, 1, 13) -#define V_INT_EN_WB_FINISH(x) VAL_MASK(x, 1, 14) -#define V_INT_EN_VFP(x) VAL_MASK(x, 1, 15) -#define V_WRITE_MASK(x) VAL_MASK(x, 16, 16) -#define INTR_CLEAR1 0x00000294 -#define V_INT_CLR_FBCD0(x) VAL_MASK(x, 1, 0) -#define V_INT_CLR_FBCD1(x) VAL_MASK(x, 1, 1) -#define V_INT_CLR_FBCD2(x) VAL_MASK(x, 1, 2) -#define V_INT_CLR_FBCD3(x) VAL_MASK(x, 1, 3) -#define V_INT_CLR_AFBCD0_HREG_DEC_RESP(x) VAL_MASK(x, 1, 4) -#define V_INT_CLR_AFBCD0_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 5) -#define V_INT_CLR_AFBCD1_HREG_DEC_RESP(x) VAL_MASK(x, 1, 6) -#define V_INT_CLR_AFBCD1_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 7) -#define V_INT_CLR_AFBCD2_HREG_DEC_RESP(x) VAL_MASK(x, 1, 8) -#define V_INT_CLR_AFBCD2_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 9) -#define V_INT_CLR_AFBCD3_HREG_DEC_RESP(x) VAL_MASK(x, 1, 10) -#define V_INT_CLR_AFBCD3_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 11) -#define V_INT_CLR_WB_YRGB_FIFO_FULL(x) VAL_MASK(x, 1, 12) -#define V_INT_CLR_WB_UV_FIFO_FULL(x) VAL_MASK(x, 1, 13) -#define V_INT_CLR_WB_DMA_FINISH(x) VAL_MASK(x, 1, 14) -#define V_INT_CLR_VFP(x) VAL_MASK(x, 1, 15) -#define INTR_STATUS1 0x00000298 -#define V_INT_STATUS_FBCD0(x) VAL_MASK(x, 1, 0) -#define V_INT_STATUS_FBCD1(x) VAL_MASK(x, 1, 1) -#define V_INT_STATUS_FBCD2(x) VAL_MASK(x, 1, 2) -#define V_INT_STATUS_FBCD3(x) VAL_MASK(x, 1, 3) -#define V_INT_STATUS_AFBCD0_HREG_DEC_RESP(x) VAL_MASK(x, 1, 4) -#define V_INT_STATUS_AFBCD0_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 5) -#define V_INT_STATUS_AFBCD1_HREG_DEC_RESP(x) VAL_MASK(x, 1, 6) -#define V_INT_STATUS_AFBCD1_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 7) -#define V_INT_STATUS_AFBCD2_HREG_DEC_RESP(x) VAL_MASK(x, 1, 8) -#define V_INT_STATUS_AFBCD2_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 9) -#define V_INT_STATUS_AFBCD3_HREG_DEC_RESP(x) VAL_MASK(x, 1, 10) -#define V_INT_STATUS_AFBCD4_HREG_DEC_RESP(x) VAL_MASK(x, 1, 11) -#define V_INT_STATUS_WB_YRGB_FIFO_FULL(x) VAL_MASK(x, 1, 12) -#define V_INT_STATUS_WB_UV_FIFO_FULL(x) VAL_MASK(x, 1, 13) -#define V_INT_STATUS_WB_DMA_FINISH(x) VAL_MASK(x, 1, 14) -#define V_INT_STATUS_VFP(x) VAL_MASK(x, 1, 15) -#define INTR_RAW_STATUS1 0x0000029c -#define V_INT_RAW_STATUS_FBCD0(x) VAL_MASK(x, 1, 0) -#define V_INT_RAW_STATUS_FBCD1(x) VAL_MASK(x, 1, 1) -#define V_INT_RAW_STATUS_FBCD2(x) VAL_MASK(x, 1, 2) -#define V_INT_RAW_STATUS_FBCD3(x) VAL_MASK(x, 1, 3) -#define V_INT_RAW_STATUS_AFBCD0_HREG_DEC_RESP(x) VAL_MASK(x, 1, 4) -#define V_INT_RAW_STATUS_AFBCD0_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 5) -#define V_INT_RAW_STATUS_AFBCD1_HREG_DEC_RESP(x) VAL_MASK(x, 1, 6) -#define V_INT_RAW_STATUS_AFBCD1_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 7) -#define V_INT_RAW_STATUS_AFBCD2_HREG_DEC_RESP(x) VAL_MASK(x, 1, 8) -#define V_INT_RAW_STATUS_AFBCD2_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 9) -#define V_INT_RAW_STATUS_AFBCD3_HREG_DEC_RESP(x) VAL_MASK(x, 1, 10) -#define V_INT_RAW_STATUS_AFBCD3_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 11) -#define V_INT_RAW_STATUS_WB_YRGB_FIFO_FULL(x) VAL_MASK(x, 1, 12) -#define V_INT_RAW_STATUS_WB_UV_FIFO_FULL(x) VAL_MASK(x, 1, 13) -#define V_INT_RAW_STATUS_WB_DMA_FINISH(x) VAL_MASK(x, 1, 14) -#define V_INT_RAW_STATUS_VFP(x) VAL_MASK(x, 1, 15) -#define LINE_FLAG 0x000002a0 -#define V_DSP_LINE_FLAG_NUM_0(x) VAL_MASK(x, 13, 0) -#define V_DSP_LINE_FLAG_NUM_1(x) VAL_MASK(x, 13, 16) -#define VOP_STATUS 0x000002a4 -#define V_DSP_VCNT(x) VAL_MASK(x, 13, 0) -#define V_MMU_IDLE(x) VAL_MASK(x, 1, 16) -#define V_DMA_STOP_VALID(x) VAL_MASK(x, 1, 17) -#define BLANKING_VALUE 0x000002a8 -#define V_BLANKING_VALUE(x) VAL_MASK(x, 24, 0) -#define V_BLANKING_VALUE_CONFIG_EN(x) VAL_MASK(x, 1, 24) -#define MCU_BYPASS_PORT 0x000002ac -#define WIN0_DSP_BG 0x000002b0 -#define V_WIN0_DSP_BG_BLUE(x) VAL_MASK(x, 10, 0) -#define V_WIN0_DSP_BG_GREEN(x) VAL_MASK(x, 10, 10) -#define V_WIN0_DSP_BG_RED(x) VAL_MASK(x, 10, 20) -#define V_WIN0_BG_EN(x) VAL_MASK(x, 1, 31) -#define WIN1_DSP_BG 0x000002b4 -#define V_WIN1_DSP_BG_BLUE(x) VAL_MASK(x, 10, 0) -#define V_WIN1_DSP_BG_GREEN(x) VAL_MASK(x, 10, 10) -#define V_WIN1_DSP_BG_RED(x) VAL_MASK(x, 10, 20) -#define V_WIN1_BG_EN(x) VAL_MASK(x, 1, 31) -#define WIN2_DSP_BG 0x000002b8 -#define V_WIN2_DSP_BG_BLUE(x) VAL_MASK(x, 10, 0) -#define V_WIN2_DSP_BG_GREEN(x) VAL_MASK(x, 10, 10) -#define V_WIN2_DSP_BG_RED(x) VAL_MASK(x, 10, 20) -#define V_WIN2_BG_EN(x) VAL_MASK(x, 1, 31) -#define WIN3_DSP_BG 0x000002bc -#define V_WIN3_DSP_BG_BLUE(x) VAL_MASK(x, 10, 0) -#define V_WIN3_DSP_BG_GREEN(x) VAL_MASK(x, 10, 10) -#define V_WIN3_DSP_BG_RED(x) VAL_MASK(x, 10, 20) -#define V_WIN3_BG_EN(x) VAL_MASK(x, 1, 31) -#define YUV2YUV_WIN 0x000002c0 -#define V_WIN0_YUV2YUV_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN0_YUV2YUV_Y2R_EN(x) VAL_MASK(x, 1, 1) -#define V_WIN0_YUV2YUV_R2Y_EN(x) VAL_MASK(x, 1, 2) -#define V_WIN0_YUV2YUV_GAMMA_MODE(x) VAL_MASK(x, 1, 3) -#define V_WIN0_YUV2YUV_Y2R_MODE(x) VAL_MASK(x, 2, 4) -#define V_WIN0_YUV2YUV_R2Y_MODE(x) VAL_MASK(x, 2, 6) -#define V_WIN1_YUV2YUV_EN(x) VAL_MASK(x, 1, 8) -#define V_WIN1_YUV2YUV_Y2R_EN(x) VAL_MASK(x, 1, 9) -#define V_WIN1_YUV2YUV_R2Y_EN(x) VAL_MASK(x, 1, 10) -#define V_WIN1_YUV2YUV_GAMMA_MODE(x) VAL_MASK(x, 1, 11) -#define V_WIN1_YUV2YUV_Y2R_MODE(x) VAL_MASK(x, 2, 12) -#define V_WIN1_YUV2YUV_R2Y_MODE(x) VAL_MASK(x, 2, 14) -#define V_WIN2_YUV2YUV_EN(x) VAL_MASK(x, 1, 16) -#define V_WIN2_YUV2YUV_R2Y_EN(x) VAL_MASK(x, 1, 18) -#define V_WIN2_YUV2YUV_GAMMA_MODE(x) VAL_MASK(x, 1, 19) -#define V_WIN2_YUV2YUV_R2Y_MODE(x) VAL_MASK(x, 2, 22) -#define V_WIN3_YUV2YUV_EN(x) VAL_MASK(x, 1, 24) -#define V_WIN3_YUV2YUV_R2Y_EN(x) VAL_MASK(x, 1, 26) -#define V_WIN3_YUV2YUV_GAMMA_MODE(x) VAL_MASK(x, 1, 27) -#define V_WIN3_YUV2YUV_R2Y_MODE(x) VAL_MASK(x, 2, 30) -#define YUV2YUV_POST 0x000002c4 -#define V_YUV2YUV_POST_EN(x) VAL_MASK(x, 1, 0) -#define V_YUV2YUV_POST_Y2R_EN(x) VAL_MASK(x, 1, 1) -#define V_YUV2YUV_POST_R2Y_EN(x) VAL_MASK(x, 1, 2) -#define V_YUV2YUV_GAMMA_MODE(x) VAL_MASK(x, 1, 3) -#define V_YUV2YUV_POST_Y2R_MODE(x) VAL_MASK(x, 2, 4) -#define V_YUV2YUV_POST_R2Y_MODE(x) VAL_MASK(x, 2, 6) -#define AUTO_GATING_EN 0x000002cc -#define V_WIN0_ACLK_GATING_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN1_ACLK_GATING_EN(x) VAL_MASK(x, 1, 1) -#define V_WIN2_ACLK_GATING_EN(x) VAL_MASK(x, 1, 2) -#define V_WIN3_ACLK_GATING_EN(x) VAL_MASK(x, 1, 3) -#define V_HWC_ACLK_GATING_EN(x) VAL_MASK(x, 1, 4) -#define V_OVERLAY_ACLK_GATING_EN(x) VAL_MASK(x, 1, 5) -#define V_GAMMA_ACLK_GATING_EN(x) VAL_MASK(x, 1, 6) -#define V_CABC_ACLK_GATING_EN(x) VAL_MASK(x, 1, 7) -#define V_WB_ACLK_GATING_EN(x) VAL_MASK(x, 1, 8) -#define V_PWM_PWMCLK_GATING_EN(x) VAL_MASK(x, 1, 9) -#define V_DIRECT_PATH_ACLK_GATING_EN(x) VAL_MASK(x, 1, 10) -#define V_FBCD0_ACLK_GATING_EN(x) VAL_MASK(x, 1, 12) -#define V_FBCD1_ACLK_GATING_EN(x) VAL_MASK(x, 1, 13) -#define V_FBCD2_ACLK_GATING_EN(x) VAL_MASK(x, 1, 14) -#define V_FBCD3_ACLK_GATING_EN(x) VAL_MASK(x, 1, 15) -#define DBG_PERF_LATENCY_CTRL0 0x00000300 -#define V_RD_LATENCY_EN(x) VAL_MASK(x, 1, 0) -#define V_HAND_LATENCY_CLR(x) VAL_MASK(x, 1, 1) -#define V_RD_LATENCY_MODE(x) VAL_MASK(x, 1, 2) -#define V_RD_LATENCY_ID0(x) VAL_MASK(x, 4, 4) -#define V_RD_LATENCY_THR(x) VAL_MASK(x, 12, 8) -#define V_RD_LATENCY_ST_NUM(x) VAL_MASK(x, 5, 20) -#define DBG_PERF_RD_MAX_LATENCY_NUM0 0x00000304 -#define V_RD_MAX_LATENCY_NUM_CH0(x) VAL_MASK(x, 12, 0) -#define V_RD_LATENCY_OVERFLOW_CH0(x) VAL_MASK(x, 1, 16) -#define DBG_PERF_RD_LATENCY_THR_NUM0 0x00000308 -#define V_RD_LATENCY_THR_NUM_CH0(x) VAL_MASK(x, 24, 0) -#define DBG_PERF_RD_LATENCY_SAMP_NUM0 0x0000030c -#define V_RD_LATENCY_SAMP_NUM_CH0(x) VAL_MASK(x, 24, 0) -#define DBG_CABC0 0x00000310 -#define DBG_CABC1 0x00000314 -#define DBG_CABC2 0x00000318 -#define V_PWM_MUL_POST_VALUE(x) VAL_MASK(x, 8, 8) -#define DBG_CABC3 0x0000031c -#define DBG_WIN0_REG0 0x00000320 -#define DBG_WIN0_REG1 0x00000324 -#define DBG_WIN0_REG2 0x00000328 -#define V_DBG_WIN0_YRGB_CMD_LINE_CNT(x) VAL_MASK(x, 13, 16) -#define DBG_WIN0_RESERVED 0x0000032c -#define DBG_WIN1_REG0 0x00000330 -#define DBG_WIN1_REG1 0x00000334 -#define DBG_WIN1_REG2 0x00000338 -#define DBG_WIN1_RESERVED 0x0000033c -#define DBG_WIN2_REG0 0x00000340 -#define DBG_WIN2_REG1 0x00000344 -#define DBG_WIN2_REG2 0x00000348 -#define DBG_WIN2_REG3 0x0000034c -#define DBG_WIN3_REG0 0x00000350 -#define DBG_WIN3_REG1 0x00000354 -#define DBG_WIN3_REG2 0x00000358 -#define DBG_WIN3_REG3 0x0000035c -#define DBG_PRE_REG0 0x00000360 -#define DBG_PRE_RESERVED 0x00000364 -#define DBG_POST_REG0 0x00000368 -#define DBG_POST_REG1 0x0000036c -#define V_GAMMA_A2HCLK_CHANGE_DONE(x) VAL_MASK(x, 1, 0) -#define V_WHICH_GAMMA_LUT_WORKING(x) VAL_MASK(x, 1, 1) -#define DBG_DATAO 0x00000370 -#define V_SW_DATAO_SEL(x) VAL_MASK(x, 2, 30) -#define DBG_DATAO_2 0x00000374 -#define V_VOP_DATA_O_2(x) VAL_MASK(x, 30, 0) -#define V_SW_DATAO_SEL_2(x) VAL_MASK(x, 2, 30) -#define WIN0_CSC_COE 0x000003a0 -#define WIN1_CSC_COE 0x000003c0 -#define WIN2_CSC_COE 0x000003e0 -#define WIN3_CSC_COE 0x00000400 -#define HWC_CSC_COE 0x00000420 -#define BCSH_R2Y_CSC_COE 0x00000440 -#define BCSH_Y2R_CSC_COE 0x00000460 -#define POST_YUV2YUV_Y2R_COE 0x00000480 -#define POST_YUV2YUV_3x3_COE 0x000004a0 -#define POST_YUV2YUV_R2Y_COE 0x000004c0 -#define WIN0_YUV2YUV_Y2R 0x000004e0 -#define WIN0_YUV2YUV_R2R 0x00000500 -#define WIN0_YUV2YUV_R2Y 0x00000520 -#define WIN1_YUV2YUV_Y2R 0x00000540 -#define WIN1_YUV2YUV_R2R 0x00000560 -#define WIN1_YUV2YUV_R2Y 0x00000580 -#define WIN2_YUV2YUV_Y2R 0x000005a0 -#define WIN2_YUV2YUV_R2R 0x000005c0 -#define WIN2_YUV2YUV_R2Y 0x000005e0 -#define WIN3_YUV2YUV_Y2R 0x00000600 -#define WIN3_YUV2YUV_R2R 0x00000620 -#define WIN3_YUV2YUV_R2Y 0x00000640 -#define WIN2_LUT_ADDR 0x00001000 -#define V_WIN2_LUT_ADDR(x) VAL_MASK(x, 32, 0) -#define WIN3_LUT_ADDR 0x00001400 -#define V_WIN3_LUT_ADDR(x) VAL_MASK(x, 32, 0) -#define HWC_LUT_ADDR 0x00001800 -#define V_HWC_LUT_ADDR(x) VAL_MASK(x, 32, 0) -#define CABC_GAMMA_LUT_ADDR 0x00001c00 -#define V_GAMMA_LUT_ADDR(x) VAL_MASK(x, 32, 0) -#define GAMMA_LUT_ADDR 0x00002000 -#define V_GAMMA_LUT_ADDR(x) VAL_MASK(x, 32, 0) -#define TVE 0x00003e00 - -#define INTR_FS (1 << 0) -#define INTR_FS_NEW (1 << 1) -#define INTR_ADDR_SAME (1 << 2) -#define INTR_LINE_FLAG0 (1 << 3) -#define INTR_LINE_FLAG1 (1 << 4) -#define INTR_BUS_ERROR (1 << 5) -#define INTR_WIN0_EMPTY (1 << 6) -#define INTR_WIN1_EMPTY (1 << 7) -#define INTR_WIN2_EMPTY (1 << 8) -#define INTR_WIN3_EMPTY (1 << 9) -#define INTR_HWC_EMPTY (1 << 10) -#define INTR_POST_BUF_EMPTY (1 << 11) -/* rk322x */ -#define INTR_PWM_GEN (1 << 12) -/* rk3399 */ -#define INTR_FS_FIELD (1 << 12) -#define INTR_DSP_HOLD_VALID (1 << 13) -#define INTR_MMU (1 << 14) -#define INTR_DMA_FINISH (1 << 15) - -#define INTR_MASK (INTR_FS | INTR_FS_NEW | INTR_ADDR_SAME | INTR_LINE_FLAG0 | \ - INTR_LINE_FLAG1 | INTR_BUS_ERROR | INTR_WIN0_EMPTY | \ - INTR_WIN1_EMPTY | INTR_WIN2_EMPTY | INTR_WIN3_EMPTY | \ - INTR_HWC_EMPTY | INTR_POST_BUF_EMPTY | INTR_PWM_GEN | \ - INTR_DSP_HOLD_VALID | INTR_MMU | INTR_DMA_FINISH) - -#define INTR1_FBCD0 (1 << 0) -#define INTR1_FBCD1 (1 << 1) -#define INTR1_FBCD2 (1 << 2) -#define INTR1_FBCD3 (1 << 3) -#define INTR1_AFBCD0_HREG_DEC_RESP (1 << 4) -#define INTR1_AFBCD0_HREG_AXI_RRESP (1 << 5) -#define INTR1_AFBCD1_HREG_DEC_RESP (1 << 6) -#define INTR1_AFBCD1_HREG_AXI_RRESP (1 << 7) -#define INTR1_AFBCD2_HREG_DEC_RESP (1 << 8) -#define INTR1_AFBCD2_HREG_AXI_RRESP (1 << 9) -#define INTR1_AFBCD3_HREG_DEC_RESP (1 << 10) -#define INTR1_AFBCD3_HREG_AXI_RRESP (1 << 11) -#define INTR1_WB_YRGB_FIFO_FULL (1 << 12) -#define INTR1_WB_UV_FIFO_FULL (1 << 13) -#define INTR1_WB_FINISH (1 << 14) - -#define OUT_CCIR656_MODE_0 5 -#define OUT_CCIR656_MODE_1 6 -#define OUT_CCIR656_MODE_2 7 - -#define AFBDC_RGB_COLOR_TRANSFORM 0 -#define AFBDC_YUV_COLOR_TRANSFORM 1 - -enum cabc_stage_mode { - LAST_FRAME_PWM_VAL = 0x0, - CUR_FRAME_PWM_VAL = 0x1, - STAGE_BY_STAGE = 0x2 -}; - -enum { - VOP_RK322X, - VOP_RK3399, -}; - -enum { - VOP_WIN0, - VOP_WIN1, - VOP_WIN2, - VOP_WIN3, - VOP_HWC, - VOP_WIN_MAX, -}; - -struct vop_data { - int chip_type; - struct rk_lcdc_win *win; - int n_wins; -}; - -struct vop_device { - int id; - const struct vop_data *data; - struct rk_lcdc_driver driver; - struct device *dev; - struct rk_screen *screen; - struct regmap *grf_base; - - void __iomem *regs; - void *regsbak; - u32 reg_phy_base; - u32 len; - - int __iomem *dsp_lut_addr_base; - int __iomem *cabc_lut_addr_base; - /* one time only one process allowed to config the register */ - spinlock_t reg_lock; - - int prop; /*used for primary or extended display device*/ - bool pre_init; - bool pwr18; /*if lcdc use 1.8v power supply*/ - /*if aclk or hclk is closed ,acess to register is not allowed*/ - bool clk_on; - /*active layer counter,when atv_layer_cnt = 0,disable lcdc*/ - u8 atv_layer_cnt; - /* point write back status */ - bool wb_on; - - unsigned int irq; - - struct clk *hclk; /*lcdc AHP clk*/ - struct clk *dclk; /*lcdc dclk*/ - struct clk *aclk; /*lcdc share memory frequency*/ - struct clk *hclk_noc; - struct clk *aclk_noc; - u32 pixclock; - - u32 standby; /*1:standby,0:wrok*/ - u32 iommu_status; - struct backlight_device *backlight; - struct clk *pll_sclk; - - /* lock vop irq reg */ - spinlock_t irq_lock; - struct devfreq *devfreq; - struct devfreq_event_dev *devfreq_event_dev; - struct notifier_block dmc_nb; - int dmc_in_process; - int vop_switch_status; - wait_queue_head_t wait_dmc_queue; - wait_queue_head_t wait_vop_switch_queue; -}; - -static inline void vop_writel(struct vop_device *vop_dev, u32 offset, u32 v) -{ - u32 *_pv = (u32 *)vop_dev->regsbak; - - _pv += (offset >> 2); - *_pv = v; - writel_relaxed(v, vop_dev->regs + offset); -} - -static inline u32 vop_readl(struct vop_device *vop_dev, u32 offset) -{ - u32 v; - - v = readl_relaxed(vop_dev->regs + offset); - return v; -} - -static inline u32 vop_readl_backup(struct vop_device *vop_dev, u32 offset) -{ - u32 v; - u32 *_pv = (u32 *)vop_dev->regsbak; - - _pv += (offset >> 2); - v = readl_relaxed(vop_dev->regs + offset); - *_pv = v; - return v; -} - -static inline u32 vop_read_bit(struct vop_device *vop_dev, u32 offset, u64 v) -{ - u32 _v = readl_relaxed(vop_dev->regs + offset); - - _v &= v >> 32; - v = (_v ? 1 : 0); - return v; -} - -static inline void vop_set_bit(struct vop_device *vop_dev, u32 offset, u64 v) -{ - u32 *_pv = (u32 *)vop_dev->regsbak; - - _pv += (offset >> 2); - (*_pv) |= v >> 32; - writel_relaxed(*_pv, vop_dev->regs + offset); -} - -static inline void vop_clr_bit(struct vop_device *vop_dev, u32 offset, u64 v) -{ - u32 *_pv = (u32 *)vop_dev->regsbak; - - _pv += (offset >> 2); - (*_pv) &= (~(v >> 32)); - writel_relaxed(*_pv, vop_dev->regs + offset); -} - -static inline void vop_msk_reg(struct vop_device *vop_dev, u32 offset, u64 v) -{ - u32 *_pv = (u32 *)vop_dev->regsbak; - - _pv += (offset >> 2); - (*_pv) &= (~(v >> 32)); - (*_pv) |= (u32)v; - writel_relaxed(*_pv, vop_dev->regs + offset); -} - -static inline void vop_msk_reg_nobak(struct vop_device *vop_dev, - u32 offset, u64 v) -{ - u32 *_pv = (u32 *)vop_dev->regsbak; - - _pv += (offset >> 2); - writel_relaxed((*_pv & (~(v >> 32))) | (u32)v, vop_dev->regs + offset); -} - -static inline void vop_mask_writel(struct vop_device *vop_dev, u32 offset, - u32 mask, u32 v) -{ - v = mask << 16 | v; - writel_relaxed(v , vop_dev->regs + offset); -} - -static inline void vop_cfg_done(struct vop_device *vop_dev) -{ - writel_relaxed(0x001f001f, vop_dev->regs + REG_CFG_DONE); - dsb(sy); -} - -static inline int vop_grf_writel(struct regmap *base, u32 offset, u32 val) -{ - regmap_write(base, offset, val); - dsb(sy); - - return 0; -} - -static inline int vop_cru_writel(struct regmap *base, u32 offset, u32 val) -{ - regmap_write(base, offset, val); - dsb(sy); - - return 0; -} - -static inline int vop_cru_readl(struct regmap *base, u32 offset) -{ - u32 v; - - regmap_read(base, offset, &v); - - return v; -} - -enum lb_mode { - LB_YUV_3840X5 = 0x0, - LB_YUV_2560X8 = 0x1, - LB_RGB_3840X2 = 0x2, - LB_RGB_2560X4 = 0x3, - LB_RGB_1920X5 = 0x4, - LB_RGB_1280X8 = 0x5 -}; - -enum sacle_up_mode { - SCALE_UP_BIL = 0x0, - SCALE_UP_BIC = 0x1 -}; - -enum scale_down_mode { - SCALE_DOWN_BIL = 0x0, - SCALE_DOWN_AVG = 0x1 -}; - -/*ALPHA BLENDING MODE*/ -enum alpha_mode { /* Fs Fd */ - AB_USER_DEFINE = 0x0, - AB_CLEAR = 0x1,/* 0 0*/ - AB_SRC = 0x2,/* 1 0*/ - AB_DST = 0x3,/* 0 1 */ - AB_SRC_OVER = 0x4,/* 1 1-As''*/ - AB_DST_OVER = 0x5,/* 1-Ad'' 1*/ - AB_SRC_IN = 0x6, - AB_DST_IN = 0x7, - AB_SRC_OUT = 0x8, - AB_DST_OUT = 0x9, - AB_SRC_ATOP = 0xa, - AB_DST_ATOP = 0xb, - XOR = 0xc, - AB_SRC_OVER_GLOBAL = 0xd -}; /*alpha_blending_mode*/ - -enum src_alpha_mode { - AA_STRAIGHT = 0x0, - AA_INVERSE = 0x1 -};/*src_alpha_mode*/ - -enum global_alpha_mode { - AA_GLOBAL = 0x0, - AA_PER_PIX = 0x1, - AA_PER_PIX_GLOBAL = 0x2 -};/*src_global_alpha_mode*/ - -enum src_alpha_sel { - AA_SAT = 0x0, - AA_NO_SAT = 0x1 -};/*src_alpha_sel*/ - -enum src_color_mode { - AA_SRC_PRE_MUL = 0x0, - AA_SRC_NO_PRE_MUL = 0x1 -};/*src_color_mode*/ - -enum factor_mode { - AA_ZERO = 0x0, - AA_ONE = 0x1, - AA_SRC = 0x2, - AA_SRC_INVERSE = 0x3, - AA_SRC_GLOBAL = 0x4 -};/*src_factor_mode && dst_factor_mode*/ - -enum _vop_r2y_csc_mode { - VOP_R2Y_CSC_BT601 = 0, - VOP_R2Y_CSC_BT709, - VOP_R2Y_CSC_BT601_F, - VOP_R2Y_CSC_BT2020 -}; - -enum _vop_y2r_csc_mode { - VOP_Y2R_CSC_MPEG = 0, - VOP_Y2R_CSC_JPEG, - VOP_Y2R_CSC_HD, - VOP_Y2R_CSC_BYPASS -}; -enum _vop_format { - VOP_FORMAT_ARGB888 = 0, - VOP_FORMAT_RGB888, - VOP_FORMAT_RGB565, - VOP_FORMAT_YCBCR420 = 4, - VOP_FORMAT_YCBCR422, - VOP_FORMAT_YCBCR444 -}; - -#define IS_YUV(x) ((x) >= VOP_FORMAT_YCBCR420) - -enum _vop_overlay_mode { - VOP_RGB_DOMAIN, - VOP_YUV_DOMAIN -}; - -struct alpha_config { - enum src_alpha_mode src_alpha_mode; /*win0_src_alpha_m0*/ - u32 src_global_alpha_val; /*win0_src_global_alpha*/ - enum global_alpha_mode src_global_alpha_mode;/*win0_src_blend_m0*/ - enum src_alpha_sel src_alpha_cal_m0; /*win0_src_alpha_cal_m0*/ - enum src_color_mode src_color_mode; /*win0_src_color_m0*/ - enum factor_mode src_factor_mode; /*win0_src_factor_m0*/ - enum factor_mode dst_factor_mode; /*win0_dst_factor_m0*/ -}; - -struct lcdc_cabc_mode { - u32 pixel_num; /* pixel precent number */ - u16 stage_up; /* up stride */ - u16 stage_down; /* down stride */ - u16 global_su; -}; - -#define CUBIC_PRECISE 0 -#define CUBIC_SPLINE 1 -#define CUBIC_CATROM 2 -#define CUBIC_MITCHELL 3 - -#define AFBDC_FMT_RGB565 0x0 -#define AFBDC_FMT_U8U8U8U8 0x5 /*ARGB888*/ -#define AFBDC_FMT_U8U8U8 0x4 /*RGBP888*/ - -#define CUBIC_MODE_SELETION CUBIC_PRECISE - -/*************************************************************/ -#define SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT 12 /* 4.12*/ -#define SCALE_FACTOR_BILI_DN_FIXPOINT(x) \ - ((INT32)((x) * (1 << SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT))) - -#define SCALE_FACTOR_BILI_UP_FIXPOINT_SHIFT 16 /* 0.16*/ - -#define SCALE_FACTOR_AVRG_FIXPOINT_SHIFT 16 /*0.16*/ -#define SCALE_FACTOR_AVRG_FIXPOINT(x) \ - ((INT32)((x) * (1 << SCALE_FACTOR_AVRG_FIXPOINT_SHIFT))) - -#define SCALE_FACTOR_BIC_FIXPOINT_SHIFT 16 /* 0.16*/ -#define SCALE_FACTOR_BIC_FIXPOINT(x) \ - ((INT32)((x) * (1 << SCALE_FACTOR_BIC_FIXPOINT_SHIFT))) - -#define SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT 12 /*NONE SCALE,vsd_bil*/ -#define SCALE_FACTOR_VSDBIL_FIXPOINT_SHIFT 12 /*VER SCALE DOWN BIL*/ - -/*********************************************************/ - -/*#define GET_SCALE_FACTOR_BILI(src, dst) \ - ((((src) - 1) << SCALE_FACTOR_BILI_FIXPOINT_SHIFT) / ((dst) - 1))*/ -/*#define GET_SCALE_FACTOR_BIC(src, dst) \ - ((((src) - 1) << SCALE_FACTOR_BIC_FIXPOINT_SHIFT) / ((dst) - 1))*/ -/*modified by hpz*/ -#define GET_SCALE_FACTOR_BILI_DN(src, dst) \ - ((((src) * 2 - 3) << (SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT - 1)) \ - / ((dst) - 1)) -#define GET_SCALE_FACTOR_BILI_UP(src, dst) \ - ((((src) * 2 - 3) << (SCALE_FACTOR_BILI_UP_FIXPOINT_SHIFT - 1)) \ - / ((dst) - 1)) -#define GET_SCALE_FACTOR_BIC(src, dst) \ - ((((src) * 2 - 3) << (SCALE_FACTOR_BIC_FIXPOINT_SHIFT - 1)) \ - / ((dst) - 1)) - -/*********************************************************/ -/*NOTE: hardware in order to save resource , srch first to get interlace line -(srch+vscalednmult-1)/vscalednmult; and do scale*/ -#define GET_SCALE_DN_ACT_HEIGHT(srch, vscalednmult) \ - (((srch) + (vscalednmult) - 1) / (vscalednmult)) - -/*#define VSKIP_MORE_PRECISE*/ - -#ifdef VSKIP_MORE_PRECISE -#define MIN_SCALE_FACTOR_AFTER_VSKIP 1.5f -#define GET_SCALE_FACTOR_BILI_DN_VSKIP(srch, dsth, vscalednmult) \ - (GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT((srch),\ - (vscalednmult)), (dsth))) -#else -#define MIN_SCALE_FACTOR_AFTER_VSKIP 1 -#define GET_SCALE_FACTOR_BILI_DN_VSKIP(srch, dsth, vscalednmult) \ - ((GET_SCALE_DN_ACT_HEIGHT((srch) , (vscalednmult)) == (dsth)) \ - ? (GET_SCALE_FACTOR_BILI_DN((srch) , (dsth)) / (vscalednmult)) \ - : (GET_SCALE_DN_ACT_HEIGHT((srch) , (vscalednmult)) == ((dsth) * 2)) \ - ? GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT(((srch) - 1),\ - (vscalednmult)) , (dsth)) : \ - GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT((srch),\ - (vscalednmult)) , (dsth))) - -#endif -/*****************************************************************/ - -/*scalefactor must >= dst/src, or pixels at end of line may be unused*/ -/*scalefactor must < dst/(src-1), or dst buffer may overflow*/ -/*avrg old code: ((((dst) << SCALE_FACTOR_AVRG_FIXPOINT_SHIFT))\ - /((src) - 1)) hxx_chgsrc*/ -/*modified by hpz:*/ -#define GET_SCALE_FACTOR_AVRG(src, dst) ((((dst) << \ - (SCALE_FACTOR_AVRG_FIXPOINT_SHIFT + 1))) / (2 * (src) - 1)) - -/*************************************************************************/ -/*Scale Coordinate Accumulate, x.16*/ -#define SCALE_COOR_ACC_FIXPOINT_SHIFT 16 -#define SCALE_COOR_ACC_FIXPOINT_ONE (1 << SCALE_COOR_ACC_FIXPOINT_SHIFT) -#define SCALE_COOR_ACC_FIXPOINT(x) \ - ((INT32)((x)*(1 << SCALE_COOR_ACC_FIXPOINT_SHIFT))) -#define SCALE_COOR_ACC_FIXPOINT_REVERT(x) \ - ((((x) >> (SCALE_COOR_ACC_FIXPOINT_SHIFT - 1)) + 1) >> 1) - -#define SCALE_GET_COOR_ACC_FIXPOINT(scalefactor, factorfixpointshift) \ - ((scalefactor) << \ - (SCALE_COOR_ACC_FIXPOINT_SHIFT - (factorfixpointshift))) - -/************************************************************************/ -/*CoarsePart of Scale Coordinate Accumulate, used for pixel mult-add factor, 0.8*/ -#define SCALE_FILTER_FACTOR_FIXPOINT_SHIFT 8 -#define SCALE_FILTER_FACTOR_FIXPOINT_ONE \ - (1 << SCALE_FILTER_FACTOR_FIXPOINT_SHIFT) -#define SCALE_FILTER_FACTOR_FIXPOINT(x) \ - ((INT32)((x) * (1 << SCALE_FILTER_FACTOR_FIXPOINT_SHIFT))) -#define SCALE_FILTER_FACTOR_FIXPOINT_REVERT(x) \ - ((((x) >> (SCALE_FILTER_FACTOR_FIXPOINT_SHIFT-1)) + 1) >> 1) - -#define SCALE_GET_FILTER_FACTOR_FIXPOINT(cooraccumulate, \ - cooraccfixpointshift) \ - (((cooraccumulate) >> \ - ((cooraccfixpointshift) - SCALE_FILTER_FACTOR_FIXPOINT_SHIFT)) & \ - (SCALE_FILTER_FACTOR_FIXPOINT_ONE - 1)) - -#define SCALE_OFFSET_FIXPOINT_SHIFT 8 -#define SCALE_OFFSET_FIXPOINT(x) \ - ((INT32)((x) * (1 << SCALE_OFFSET_FIXPOINT_SHIFT))) - -static inline u32 vop_get_hard_ware_vskiplines(u32 srch, u32 dsth) -{ - u32 vscalednmult; - - if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP)) - vscalednmult = 4; - else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP)) - vscalednmult = 2; - else - vscalednmult = 1; - - return vscalednmult; -} - -#endif diff --git a/drivers/video/rockchip/lcdc/rk3288_lcdc.c b/drivers/video/rockchip/lcdc/rk3288_lcdc.c deleted file mode 100755 index 870d22f678da..000000000000 --- a/drivers/video/rockchip/lcdc/rk3288_lcdc.c +++ /dev/null @@ -1,4238 +0,0 @@ -/* - * drivers/video/rockchip/lcdc/rk3288_lcdc.c - * - * Copyright (C) 2014 ROCKCHIP, Inc. - *Author:hjc - *This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "rk3288_lcdc.h" - -#if defined(CONFIG_HAS_EARLYSUSPEND) -#include -#endif - -static int dbg_thresd; -module_param(dbg_thresd, int, S_IRUGO | S_IWUSR); - -#define DBG(level, x...) do { \ - if (unlikely(dbg_thresd >= level)) \ - printk(KERN_INFO x); } while (0) - -static int rk3288_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, - bool enable); - -struct fb_info *rk_get_fb(int fb_id); -/*#define WAIT_FOR_SYNC 1*/ - -static int rk3288_lcdc_get_id(u32 phy_base) -{ - if (cpu_is_rk3288()) { - if (phy_base == 0xff930000)/*vop big*/ - return 0; - else if (phy_base == 0xff940000)/*vop lit*/ - return 1; - else - return -EINVAL; - } else { - pr_err("un supported platform \n"); - return -EINVAL; - } -} - -static int rk3288_lcdc_set_lut(struct rk_lcdc_driver *dev_drv) -{ - int i,j; - int __iomem *c; - u32 v,r,g,b; - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device,driver); - if (dev_drv->cur_screen->dsp_lut) - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, - v_DSP_LUT_EN(0)); - if ((dev_drv->cur_screen->cabc_lut) && - (dev_drv->version == VOP_FULL_RK3288_V1_1)) - lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN, - v_CABC_LUT_EN(0)); - lcdc_cfg_done(lcdc_dev); - mdelay(25); - if (dev_drv->cur_screen->dsp_lut) { - for (i = 0; i < 256; i++) { - v = dev_drv->cur_screen->dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base + (i << 2); - b = (v & 0xff) << 2; - g = (v & 0xff00) << 4; - r = (v & 0xff0000) << 6; - v = r + g + b; - for (j = 0; j < 4; j++) { - writel_relaxed(v, c); - v += (1 + (1 << 10) + (1 << 20)); - c++; - } - } - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, - v_DSP_LUT_EN(1)); - } - if ((dev_drv->cur_screen->cabc_lut) && - (dev_drv->version == VOP_FULL_RK3288_V1_1)) { - for (i = 0; i < 128; i++) { - v = dev_drv->cur_screen->cabc_lut[i]; - lcdc_writel(lcdc_dev, i * 4 + CABC_LUT_ADDR, v); - } - lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN, - v_CABC_LUT_EN(1)); - } - - return 0; - -} - -static int rk3288_lcdc_clk_enable(struct lcdc_device *lcdc_dev) -{ -#ifdef CONFIG_RK_FPGA - lcdc_dev->clk_on = 1; - return 0; -#endif - if (!lcdc_dev->clk_on) { - clk_prepare_enable(lcdc_dev->hclk); - clk_prepare_enable(lcdc_dev->dclk); - clk_prepare_enable(lcdc_dev->aclk); - clk_prepare_enable(lcdc_dev->pd); - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 1; - spin_unlock(&lcdc_dev->reg_lock); - } - - return 0; -} - -static int rk3288_lcdc_clk_disable(struct lcdc_device *lcdc_dev) -{ -#ifdef CONFIG_RK_FPGA - lcdc_dev->clk_on = 0; - return 0; -#endif - if (lcdc_dev->clk_on) { - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 0; - spin_unlock(&lcdc_dev->reg_lock); - mdelay(25); - clk_disable_unprepare(lcdc_dev->dclk); - clk_disable_unprepare(lcdc_dev->hclk); - clk_disable_unprepare(lcdc_dev->aclk); - clk_disable_unprepare(lcdc_dev->pd); - } - - return 0; -} - -static int rk3288_lcdc_disable_irq(struct lcdc_device *lcdc_dev) -{ - u32 mask, val; - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - mask = m_DSP_HOLD_VALID_INTR_EN | m_FS_INTR_EN | - m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_EN; - val = v_DSP_HOLD_VALID_INTR_EN(0) | v_FS_INTR_EN(0) | - v_LINE_FLAG_INTR_EN(0) | v_BUS_ERROR_INTR_EN(0); - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val); - - mask = m_DSP_HOLD_VALID_INTR_CLR | m_FS_INTR_CLR | - m_LINE_FLAG_INTR_CLR | m_LINE_FLAG_INTR_CLR; - val = v_DSP_HOLD_VALID_INTR_CLR(0) | v_FS_INTR_CLR(0) | - v_LINE_FLAG_INTR_CLR(0) | v_BUS_ERROR_INTR_CLR(0); - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val); - - mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN | - m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN | - m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN | - m_POST_BUF_EMPTY_INTR_EN; - val = v_WIN0_EMPTY_INTR_EN(0) | v_WIN1_EMPTY_INTR_EN(0) | - v_WIN2_EMPTY_INTR_EN(0) | v_WIN3_EMPTY_INTR_EN(0) | - v_HWC_EMPTY_INTR_EN(0) | v_POST_BUF_EMPTY_INTR_EN(0) | - v_PWM_GEN_INTR_EN(0); - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val); - - mask = m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR | - m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR | - m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR | - m_POST_BUF_EMPTY_INTR_CLR; - val = v_WIN0_EMPTY_INTR_CLR(0) | v_WIN1_EMPTY_INTR_CLR(0) | - v_WIN2_EMPTY_INTR_CLR(0) | v_WIN3_EMPTY_INTR_CLR(0) | - v_HWC_EMPTY_INTR_CLR(0) | v_POST_BUF_EMPTY_INTR_CLR(0) | - v_PWM_GEN_INTR_CLR(0); - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - } - mdelay(1); - return 0; -} -static int rk3288_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, - driver); - int *cbase = (int *)lcdc_dev->regs; - int *regsbak = (int *)lcdc_dev->regsbak; - int i, j; - - printk("back up reg:\n"); - for (i = 0; i <= (0x200 >> 4); i++) { - printk("0x%04x: ",i*16); - for (j = 0; j < 4; j++) - printk("%08x ", *(regsbak + i * 4 + j)); - printk("\n"); - } - - printk("lcdc reg:\n"); - for (i = 0; i <= (0x200 >> 4); i++) { - printk("0x%04x: ",i*16); - for (j = 0; j < 4; j++) - printk("%08x ", readl_relaxed(cbase + i * 4 + j)); - printk("\n"); - } - return 0; - -} - -#define WIN_EN(id) \ -static int win##id##_enable(struct lcdc_device *lcdc_dev, int en) \ -{ \ - u32 msk, val; \ - spin_lock(&lcdc_dev->reg_lock); \ - msk = m_WIN##id##_EN; \ - val = v_WIN##id##_EN(en); \ - lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val); \ - lcdc_cfg_done(lcdc_dev); \ - /*val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk); \ - while (val != (!!en)) { \ - val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk); \ - }*/ \ - spin_unlock(&lcdc_dev->reg_lock); \ - return 0; \ -} - -WIN_EN(0); -WIN_EN(1); -WIN_EN(2); -WIN_EN(3); -/*enable/disable win directly*/ -static int rk3288_lcdc_win_direct_en - (struct rk_lcdc_driver *drv, int win_id , int en) -{ - struct lcdc_device *lcdc_dev = container_of(drv, - struct lcdc_device, driver); - if (win_id == 0) - win0_enable(lcdc_dev, en); - else if (win_id == 1) - win1_enable(lcdc_dev, en); - else if (win_id == 2) - win2_enable(lcdc_dev, en); - else if (win_id == 3) - win3_enable(lcdc_dev, en); - else - dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id); - return 0; - -} - -#define SET_WIN_ADDR(id) \ -static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \ -{ \ - u32 msk, val; \ - spin_lock(&lcdc_dev->reg_lock); \ - lcdc_writel(lcdc_dev,WIN##id##_YRGB_MST,addr); \ - msk = m_WIN##id##_EN; \ - val = v_WIN0_EN(1); \ - lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk,val); \ - lcdc_cfg_done(lcdc_dev); \ - spin_unlock(&lcdc_dev->reg_lock); \ - return 0; \ -} - -SET_WIN_ADDR(0); -SET_WIN_ADDR(1); -int rk3288_lcdc_direct_set_win_addr - (struct rk_lcdc_driver *dev_drv, int win_id, u32 addr) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - if (win_id == 0) - set_win0_addr(lcdc_dev, addr); - else - set_win1_addr(lcdc_dev, addr); - - return 0; -} - -static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev) -{ - int reg = 0; - u32 val = 0; - struct rk_screen *screen = lcdc_dev->driver.cur_screen; - u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin; - u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin; - u32 st_x, st_y; - struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0]; - - spin_lock(&lcdc_dev->reg_lock); - memcpy(lcdc_dev->regsbak, lcdc_dev->regs, FRC_LOWER11_1); - for (reg = 0; reg < FRC_LOWER11_1; reg += 4) { - val = lcdc_readl(lcdc_dev, reg); - switch (reg) { - case VERSION_INFO: - lcdc_dev->driver.version = val; - break; - case WIN0_ACT_INFO: - win0->area[0].xact = - (val & m_WIN0_ACT_WIDTH) + 1; - win0->area[0].yact = - ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1; - break; - case WIN0_DSP_INFO: - win0->area[0].xsize = - (val & m_WIN0_DSP_WIDTH) + 1; - win0->area[0].ysize = - ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1; - break; - case WIN0_DSP_ST: - st_x = val & m_WIN0_DSP_XST; - st_y = (val & m_WIN0_DSP_YST) >> 16; - win0->area[0].xpos = st_x - h_pw_bp; - win0->area[0].ypos = st_y - v_pw_bp; - break; - case WIN0_CTRL0: - win0->state = val & m_WIN0_EN; - win0->area[0].fmt_cfg = - (val & m_WIN0_DATA_FMT) >> 1; - win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4; - win0->area[0].format = win0->area[0].fmt_cfg; - break; - case WIN0_VIR: - win0->area[0].y_vir_stride = - val & m_WIN0_VIR_STRIDE; - win0->area[0].uv_vir_stride = - (val & m_WIN0_VIR_STRIDE_UV) >> 16; - if (win0->area[0].format == ARGB888) - win0->area[0].xvir = - win0->area[0].y_vir_stride; - else if (win0->area[0].format == RGB888) - win0->area[0].xvir = - win0->area[0].y_vir_stride * 4 / 3; - else if (win0->area[0].format == RGB565) - win0->area[0].xvir = - 2 * win0->area[0].y_vir_stride; - else /* YUV */ - win0->area[0].xvir = - 4 * win0->area[0].y_vir_stride; - break; - case WIN0_YRGB_MST: - win0->area[0].smem_start = val; - break; - case WIN0_CBR_MST: - win0->area[0].cbr_start = val; - break; - case DSP_VACT_ST_END: - if (support_uboot_display()) { - screen->mode.yres = - (val & 0x1fff) - ((val >> 16) & 0x1fff); - win0->area[0].ypos = - st_y - ((val >> 16) & 0x1fff); - } - break; - case DSP_HACT_ST_END: - if (support_uboot_display()) { - screen->mode.xres = - (val & 0x1fff) - ((val >> 16) & 0x1fff); - win0->area[0].xpos = - st_x - ((val >> 16) & 0x1fff); - } - break; - default: - break; - } - } - spin_unlock(&lcdc_dev->reg_lock); - -} - -/********do basic init*********/ -static int rk3288_lcdc_pre_init(struct rk_lcdc_driver *dev_drv) -{ - int v; - u32 mask,val; - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct - lcdc_device, - driver); - if (lcdc_dev->pre_init) - return 0; - - lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc"); - lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc"); - lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc"); - lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc"); - - if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) || - (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) { - dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n", - lcdc_dev->id); - } - if (!support_uboot_display()) - rk_disp_pwr_enable(dev_drv); - rk3288_lcdc_clk_enable(lcdc_dev); - - /*backup reg config at uboot*/ - lcdc_read_reg_defalut_cfg(lcdc_dev); - v = 0; -#ifndef CONFIG_RK_FPGA - if (lcdc_dev->pwr18 == true) { - v = 0x00010001; /*bit14: 1,1.8v;0,3.3v*/ - writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL); - } else { - v = 0x00010000; - writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL); - } -#endif - lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_0,0x15110903); - lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_1,0x00030911); - lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_0,0x1a150b04); - lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_1,0x00040b15); - lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_0,0x15110903); - lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_1,0x00030911); - - lcdc_writel(lcdc_dev,FRC_LOWER01_0,0x12844821); - lcdc_writel(lcdc_dev,FRC_LOWER01_1,0x21488412); - lcdc_writel(lcdc_dev,FRC_LOWER10_0,0xa55a9696); - lcdc_writel(lcdc_dev,FRC_LOWER10_1,0x5aa56969); - lcdc_writel(lcdc_dev,FRC_LOWER11_0,0xdeb77deb); - lcdc_writel(lcdc_dev,FRC_LOWER11_1,0xed7bb7de); - - mask = m_AUTO_GATING_EN; - val = v_AUTO_GATING_EN(0); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask,val); - lcdc_cfg_done(lcdc_dev); - /*disable win0 to workaround iommu pagefault */ - /*if (dev_drv->iommu_enabled) */ - /* win0_enable(lcdc_dev, 0); */ - lcdc_dev->pre_init = true; - - - return 0; -} - -static void rk3288_lcdc_deint(struct lcdc_device *lcdc_dev) -{ - - - rk3288_lcdc_disable_irq(lcdc_dev); - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_dev->clk_on = 0; - lcdc_set_bit(lcdc_dev, SYS_CTRL, m_STANDBY_EN); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - } - mdelay(1); -} -static int rk3288_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u16 x_res = screen->mode.xres; - u16 y_res = screen->mode.yres; - u32 mask, val; - u16 h_total,v_total; - u16 post_hsd_en,post_vsd_en; - u16 post_dsp_hact_st,post_dsp_hact_end; - u16 post_dsp_vact_st,post_dsp_vact_end; - u16 post_dsp_vact_st_f1,post_dsp_vact_end_f1; - u16 post_h_fac,post_v_fac; - - screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200; - screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200; - screen->post_xsize = x_res * - (dev_drv->overscan.left + dev_drv->overscan.right) / 200; - screen->post_ysize = y_res * - (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200; - h_total = screen->mode.hsync_len+screen->mode.left_margin + - x_res + screen->mode.right_margin; - v_total = screen->mode.vsync_len+screen->mode.upper_margin + - y_res + screen->mode.lower_margin; - - if(screen->post_dsp_stx + screen->post_xsize > x_res){ - dev_warn(lcdc_dev->dev, "post:stx[%d] + xsize[%d] > x_res[%d]\n", - screen->post_dsp_stx,screen->post_xsize,x_res); - screen->post_dsp_stx = x_res - screen->post_xsize; - } - if(screen->x_mirror == 0){ - post_dsp_hact_st=screen->post_dsp_stx + - screen->mode.hsync_len+screen->mode.left_margin; - post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize; - }else{ - post_dsp_hact_end = h_total - screen->mode.right_margin - - screen->post_dsp_stx; - post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize; - } - if((screen->post_xsize < x_res)&&(screen->post_xsize != 0)){ - post_hsd_en = 1; - post_h_fac = - GET_SCALE_FACTOR_BILI_DN(x_res , screen->post_xsize); - }else{ - post_hsd_en = 0; - post_h_fac = 0x1000; - } - - - if(screen->post_dsp_sty + screen->post_ysize > y_res){ - dev_warn(lcdc_dev->dev, "post:sty[%d] + ysize[%d] > y_res[%d]\n", - screen->post_dsp_sty,screen->post_ysize,y_res); - screen->post_dsp_sty = y_res - screen->post_ysize; - } - - if(screen->y_mirror == 0){ - post_dsp_vact_st = screen->post_dsp_sty + - screen->mode.vsync_len+screen->mode.upper_margin; - post_dsp_vact_end = post_dsp_vact_st + screen->post_ysize; - }else{ - post_dsp_vact_end = v_total - screen->mode.lower_margin - - - screen->post_dsp_sty; - post_dsp_vact_st = post_dsp_vact_end - screen->post_ysize; - } - if((screen->post_ysize < y_res)&&(screen->post_ysize != 0)){ - post_vsd_en = 1; - post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res, screen->post_ysize); - }else{ - post_vsd_en = 0; - post_v_fac = 0x1000; - } - - if(screen->interlace == 1){ - post_dsp_vact_st_f1 = v_total + post_dsp_vact_st; - post_dsp_vact_end_f1 = post_dsp_vact_st_f1 + screen->post_ysize; - }else{ - post_dsp_vact_st_f1 = 0; - post_dsp_vact_end_f1 = 0; - } - DBG(1,"post:xsize=%d,ysize=%d,xpos=%d,ypos=%d," - "hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n", - screen->post_xsize,screen->post_ysize,screen->xpos,screen->ypos, - post_hsd_en,post_h_fac,post_vsd_en,post_v_fac); - mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST; - val = v_DSP_HACT_END_POST(post_dsp_hact_end) | - v_DSP_HACT_ST_POST(post_dsp_hact_st); - lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val); - - mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST; - val = v_DSP_VACT_END_POST(post_dsp_vact_end) | - v_DSP_VACT_ST_POST(post_dsp_vact_st); - lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val); - - mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB; - val = v_POST_HS_FACTOR_YRGB(post_h_fac) | - v_POST_VS_FACTOR_YRGB(post_v_fac); - lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val); - - mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1; - val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) | - v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1); - lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val); - - mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN; - val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en); - lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val); - return 0; -} - -static int rk3288_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct - lcdc_device, - driver); - struct rk_lcdc_win *win; - u32 colorkey_r,colorkey_g,colorkey_b; - int i,key_val; - for(i=0;i<4;i++){ - win = dev_drv->win[i]; - key_val = win->color_key_val; - colorkey_r = (key_val & 0xff)<<2; - colorkey_g = ((key_val>>8)&0xff)<<12; - colorkey_b = ((key_val>>16)&0xff)<<22; - /*color key dither 565/888->aaa*/ - key_val = colorkey_r | colorkey_g | colorkey_b; - switch(i){ - case 0: - lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val); - break; - case 1: - lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val); - break; - case 2: - lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val); - break; - case 3: - lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val); - break; - default: - printk(KERN_WARNING "%s:un support win num:%d\n", - __func__,i); - break; - } - } - return 0; -} - -static int rk3288_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv,int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - struct alpha_config alpha_config; - - u32 mask, val; - int ppixel_alpha,global_alpha; - u32 src_alpha_ctl,dst_alpha_ctl; - ppixel_alpha = ((win->area[0].format == ARGB888) || - (win->area[0].format == ABGR888)) ? 1 : 0; - global_alpha = (win->g_alpha_val == 0) ? 0 : 1; - alpha_config.src_global_alpha_val = win->g_alpha_val; - win->alpha_mode = AB_SRC_OVER; - /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n", - __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,global_alpha);*/ - switch(win->alpha_mode){ - case AB_USER_DEFINE: - break; - case AB_CLEAR: - alpha_config.src_factor_mode=AA_ZERO; - alpha_config.dst_factor_mode=AA_ZERO; - break; - case AB_SRC: - alpha_config.src_factor_mode=AA_ONE; - alpha_config.dst_factor_mode=AA_ZERO; - break; - case AB_DST: - alpha_config.src_factor_mode=AA_ZERO; - alpha_config.dst_factor_mode=AA_ONE; - break; - case AB_SRC_OVER: - alpha_config.src_color_mode=AA_SRC_PRE_MUL; - if(global_alpha) - alpha_config.src_factor_mode=AA_SRC_GLOBAL; - else - alpha_config.src_factor_mode=AA_ONE; - alpha_config.dst_factor_mode=AA_SRC_INVERSE; - break; - case AB_DST_OVER: - alpha_config.src_color_mode=AA_SRC_PRE_MUL; - alpha_config.src_factor_mode=AA_SRC_INVERSE; - alpha_config.dst_factor_mode=AA_ONE; - break; - case AB_SRC_IN: - alpha_config.src_color_mode=AA_SRC_PRE_MUL; - alpha_config.src_factor_mode=AA_SRC; - alpha_config.dst_factor_mode=AA_ZERO; - break; - case AB_DST_IN: - alpha_config.src_factor_mode=AA_ZERO; - alpha_config.dst_factor_mode=AA_SRC; - break; - case AB_SRC_OUT: - alpha_config.src_color_mode=AA_SRC_PRE_MUL; - alpha_config.src_factor_mode=AA_SRC_INVERSE; - alpha_config.dst_factor_mode=AA_ZERO; - break; - case AB_DST_OUT: - alpha_config.src_factor_mode=AA_ZERO; - alpha_config.dst_factor_mode=AA_SRC_INVERSE; - break; - case AB_SRC_ATOP: - alpha_config.src_color_mode=AA_SRC_PRE_MUL; - alpha_config.src_factor_mode=AA_SRC; - alpha_config.dst_factor_mode=AA_SRC_INVERSE; - break; - case AB_DST_ATOP: - alpha_config.src_color_mode=AA_SRC_PRE_MUL; - alpha_config.src_factor_mode=AA_SRC_INVERSE; - alpha_config.dst_factor_mode=AA_SRC; - break; - case XOR: - alpha_config.src_color_mode=AA_SRC_PRE_MUL; - alpha_config.src_factor_mode=AA_SRC_INVERSE; - alpha_config.dst_factor_mode=AA_SRC_INVERSE; - break; - case AB_SRC_OVER_GLOBAL: - alpha_config.src_global_alpha_mode=AA_PER_PIX_GLOBAL; - alpha_config.src_color_mode=AA_SRC_NO_PRE_MUL; - alpha_config.src_factor_mode=AA_SRC_GLOBAL; - alpha_config.dst_factor_mode=AA_SRC_INVERSE; - break; - default: - pr_err("alpha mode error\n"); - break; - } - if((ppixel_alpha == 1)&&(global_alpha == 1)){ - alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL; - }else if(ppixel_alpha == 1){ - alpha_config.src_global_alpha_mode = AA_PER_PIX; - }else if(global_alpha == 1){ - alpha_config.src_global_alpha_mode = AA_GLOBAL; - }else{ - dev_warn(lcdc_dev->dev,"alpha_en should be 0\n"); - } - alpha_config.src_alpha_mode = AA_STRAIGHT; - alpha_config.src_alpha_cal_m0 = AA_NO_SAT; - - switch(win_id){ - case 0: - src_alpha_ctl = 0x60; - dst_alpha_ctl = 0x64; - break; - case 1: - src_alpha_ctl = 0xa0; - dst_alpha_ctl = 0xa4; - break; - case 2: - src_alpha_ctl = 0xdc; - dst_alpha_ctl = 0xec; - break; - case 3: - src_alpha_ctl = 0x12c; - dst_alpha_ctl = 0x13c; - break; - } - mask = m_WIN0_DST_FACTOR_M0; - val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode); - lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val); - mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 | - m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 | - m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0| - m_WIN0_SRC_GLOBAL_ALPHA; - val = v_WIN0_SRC_ALPHA_EN(1) | - v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) | - v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) | - v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) | - v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) | - v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) | - v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val); - lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val); - - return 0; -} -static int rk3288_lcdc_area_swap(struct rk_lcdc_win *win,int area_num) -{ - struct rk_lcdc_win_area area_temp; - switch(area_num){ - case 2: - area_temp = win->area[0]; - win->area[0] = win->area[1]; - win->area[1] = area_temp; - break; - case 3: - area_temp = win->area[0]; - win->area[0] = win->area[2]; - win->area[2] = area_temp; - break; - case 4: - area_temp = win->area[0]; - win->area[0] = win->area[3]; - win->area[3] = area_temp; - - area_temp = win->area[1]; - win->area[1] = win->area[2]; - win->area[2] = area_temp; - break; - default: - printk(KERN_WARNING "un supported area num!\n"); - break; - } - return 0; -} - -static int rk3288_win_area_check_var(int win_id,int area_num,struct rk_lcdc_win_area *area_pre, - struct rk_lcdc_win_area *area_now) -{ - if((area_pre->ypos >= area_now->ypos) || - (area_pre->ypos+area_pre->ysize > area_now->ypos)){ - area_now->state = 0; - pr_err("win[%d]:\n" - "area_pre[%d]:ypos[%d],ysize[%d]\n" - "area_now[%d]:ypos[%d],ysize[%d]\n", - win_id, - area_num-1,area_pre->ypos,area_pre->ysize, - area_num, area_now->ypos,area_now->ysize); - return -EINVAL; - } - return 0; -} - -static int rk3288_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv,int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - unsigned int mask, val, off; - off = win_id * 0x40; - if((win->win_lb_mode == 5) && - (dev_drv->version == VOP_FULL_RK3288_V1_0)) - win->win_lb_mode = 4; - - if(win->state == 1){ - mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 | - m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_UV_SWAP; - val = v_WIN0_EN(win->state) | - v_WIN0_DATA_FMT(win->area[0].fmt_cfg) | - v_WIN0_FMT_10(win->fmt_10) | - v_WIN0_LB_MODE(win->win_lb_mode) | - v_WIN0_RB_SWAP(win->area[0].swap_rb) | - v_WIN0_UV_SWAP(win->area[0].swap_uv); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val); - - mask = m_WIN0_BIC_COE_SEL | - m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 | - m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 | - m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE | - m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE | - m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE | - m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE | - m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE; - val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) | - v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) | - v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) | - v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) | - v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) | - v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) | - v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) | - v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) | - v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) | - v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) | - v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) | - v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) | - v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) | - v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) | - v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL1+off, mask,val); - - val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) | - v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride); - lcdc_writel(lcdc_dev, WIN0_VIR+off, val); - /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off, win->area[0].y_addr); - lcdc_writel(lcdc_dev, WIN0_CBR_MST+off, win->area[0].uv_addr);*/ - val = v_WIN0_ACT_WIDTH(win->area[0].xact) | - v_WIN0_ACT_HEIGHT(win->area[0].yact); - lcdc_writel(lcdc_dev, WIN0_ACT_INFO+off, val); - - val = v_WIN0_DSP_WIDTH(win->area[0].xsize) | - v_WIN0_DSP_HEIGHT(win->area[0].ysize); - lcdc_writel(lcdc_dev, WIN0_DSP_INFO+off, val); - - val = v_WIN0_DSP_XST(win->area[0].dsp_stx) | - v_WIN0_DSP_YST(win->area[0].dsp_sty); - lcdc_writel(lcdc_dev, WIN0_DSP_ST+off, val); - - val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) | - v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y); - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB+off, val); - - val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) | - v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y); - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR+off, val); - if(win->alpha_en == 1) - rk3288_lcdc_alpha_cfg(dev_drv,win_id); - else{ - mask = m_WIN0_SRC_ALPHA_EN; - val = v_WIN0_SRC_ALPHA_EN(0); - lcdc_msk_reg(lcdc_dev,WIN0_SRC_ALPHA_CTRL+off,mask,val); - } - /*offset*/ - }else{ - mask = m_WIN0_EN; - val = v_WIN0_EN(win->state); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val); - } - return 0; -} - -static int rk3288_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv,int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - struct rk_screen *screen = dev_drv->cur_screen; - unsigned int mask, val, off; - struct fb_info *fb0 = rk_get_fb(0); - - off = (win_id-2) * 0x50; - if((screen->y_mirror == 1)&&(win->area_num > 1)){ - rk3288_lcdc_area_swap(win,win->area_num); - } - - if(win->state == 1){ - mask = m_WIN2_EN | m_WIN2_DATA_FMT | m_WIN2_RB_SWAP; - val = v_WIN2_EN(1) | - v_WIN2_DATA_FMT(win->area[0].fmt_cfg) | - v_WIN2_RB_SWAP(win->area[0].swap_rb); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - /*area 0*/ - if(win->area[0].state == 1){ - mask = m_WIN2_MST0_EN; - val = v_WIN2_MST0_EN(win->area[0].state); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - - mask = m_WIN2_VIR_STRIDE0; - val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride); - lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val); - - /*lcdc_writel(lcdc_dev,WIN2_MST0+off,win->area[0].y_addr);*/ - val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) | - v_WIN2_DSP_HEIGHT0(win->area[0].ysize); - lcdc_writel(lcdc_dev,WIN2_DSP_INFO0+off,val); - val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) | - v_WIN2_DSP_YST0(win->area[0].dsp_sty); - lcdc_writel(lcdc_dev,WIN2_DSP_ST0+off,val); - }else{ - mask = m_WIN2_MST0_EN; - val = v_WIN2_MST0_EN(0); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - lcdc_writel(lcdc_dev, WIN2_MST0 + off, - fb0->fix.smem_start); - } - /*area 1*/ - if(win->area[1].state == 1){ - rk3288_win_area_check_var(win_id,1,&win->area[0],&win->area[1]); - - mask = m_WIN2_MST1_EN; - val = v_WIN2_MST1_EN(win->area[1].state); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - - mask = m_WIN2_VIR_STRIDE1; - val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride); - lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val); - - /*lcdc_writel(lcdc_dev,WIN2_MST1+off,win->area[1].y_addr);*/ - val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) | - v_WIN2_DSP_HEIGHT1(win->area[1].ysize); - lcdc_writel(lcdc_dev,WIN2_DSP_INFO1+off,val); - val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) | - v_WIN2_DSP_YST1(win->area[1].dsp_sty); - lcdc_writel(lcdc_dev,WIN2_DSP_ST1+off,val); - }else{ - mask = m_WIN2_MST1_EN; - val = v_WIN2_MST1_EN(0); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - lcdc_writel(lcdc_dev, WIN2_MST1 + off, - fb0->fix.smem_start); - } - /*area 2*/ - if(win->area[2].state == 1){ - rk3288_win_area_check_var(win_id,2,&win->area[1],&win->area[2]); - - mask = m_WIN2_MST2_EN; - val = v_WIN2_MST2_EN(win->area[2].state); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - - mask = m_WIN2_VIR_STRIDE2; - val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride); - lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val); - - /*lcdc_writel(lcdc_dev,WIN2_MST2+off,win->area[2].y_addr);*/ - val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) | - v_WIN2_DSP_HEIGHT2(win->area[2].ysize); - lcdc_writel(lcdc_dev,WIN2_DSP_INFO2+off,val); - val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) | - v_WIN2_DSP_YST2(win->area[2].dsp_sty); - lcdc_writel(lcdc_dev,WIN2_DSP_ST2+off,val); - }else{ - mask = m_WIN2_MST2_EN; - val = v_WIN2_MST2_EN(0); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - lcdc_writel(lcdc_dev, WIN2_MST2 + off, - fb0->fix.smem_start); - } - /*area 3*/ - if(win->area[3].state == 1){ - rk3288_win_area_check_var(win_id,3,&win->area[2],&win->area[3]); - - mask = m_WIN2_MST3_EN; - val = v_WIN2_MST3_EN(win->area[3].state); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - - mask = m_WIN2_VIR_STRIDE3; - val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride); - lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val); - - /*lcdc_writel(lcdc_dev,WIN2_MST3+off,win->area[3].y_addr);*/ - val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) | - v_WIN2_DSP_HEIGHT3(win->area[3].ysize); - lcdc_writel(lcdc_dev,WIN2_DSP_INFO3+off,val); - val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) | - v_WIN2_DSP_YST3(win->area[3].dsp_sty); - lcdc_writel(lcdc_dev,WIN2_DSP_ST3+off,val); - }else{ - mask = m_WIN2_MST3_EN; - val = v_WIN2_MST3_EN(0); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - lcdc_writel(lcdc_dev, WIN2_MST3 + off, - fb0->fix.smem_start); - } - - if(win->alpha_en == 1) - rk3288_lcdc_alpha_cfg(dev_drv,win_id); - else{ - mask = m_WIN2_SRC_ALPHA_EN; - val = v_WIN2_SRC_ALPHA_EN(0); - lcdc_msk_reg(lcdc_dev,WIN2_SRC_ALPHA_CTRL+off,mask,val); - } - }else{ - mask = m_WIN2_EN | m_WIN2_MST0_EN | - m_WIN2_MST0_EN | m_WIN2_MST2_EN | - m_WIN2_MST3_EN; - val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) | - v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | - v_WIN2_MST3_EN(0); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0+off, mask,val); - } - return 0; -} - -static int rk3288_lcdc_reg_update(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int timeout; - unsigned long flags; - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, - v_STANDBY_EN(lcdc_dev->standby)); - rk3288_win_0_1_reg_update(dev_drv,0); - rk3288_win_0_1_reg_update(dev_drv,1); - rk3288_win_2_3_reg_update(dev_drv,2); - rk3288_win_2_3_reg_update(dev_drv,3); - /*rk3288_lcdc_post_cfg(dev_drv);*/ - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - /*if (dev_drv->wait_fs) {*/ - if (0){ - spin_lock_irqsave(&dev_drv->cpl_lock, flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock, flags); - timeout = wait_for_completion_timeout(&dev_drv->frame_done, - msecs_to_jiffies - (dev_drv->cur_screen->ft + - 5)); - if (!timeout && (!dev_drv->frame_done.done)) { - dev_warn(lcdc_dev->dev, "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } - } - DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id); - return 0; - -} - -static int rk3288_lcdc_reg_restore(struct lcdc_device *lcdc_dev) -{ - memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0x1fc); - return 0; -} -static int rk3288_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv) -{ - u32 mask,val; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if (unlikely(!lcdc_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on); - return 0; - } - if (dev_drv->iommu_enabled) { - if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) { - - if (likely(lcdc_dev->clk_on)) { - spin_lock(&lcdc_dev->reg_lock); - mask = m_MMU_EN; - val = v_MMU_EN(1); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - mask = m_AXI_MAX_OUTSTANDING_EN | m_AXI_OUTSTANDING_MAX_NUM; - val = v_AXI_OUTSTANDING_MAX_NUM(31) | v_AXI_MAX_OUTSTANDING_EN(1); - lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val); - spin_unlock(&lcdc_dev->reg_lock); - } - lcdc_dev->iommu_status = 1; - rockchip_iovmm_activate(dev_drv->dev); - } - } - return 0; -} - -static int rk3288_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate) -{ -#ifdef CONFIG_RK_FPGA - return 0; -#endif - int ret = 0,fps; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - - if (reset_rate) - ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */ - if (ret) - dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id); - lcdc_dev->pixclock = - div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - lcdc_dev->driver.pixclock = lcdc_dev->pixclock; - - fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock); - screen->ft = 1000 / fps; - dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ", - lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps); - return 0; - -} - -static void rk3288_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 bcsh_color_bar; - - if (dev_drv->output_color == COLOR_RGB) { - bcsh_color_bar = lcdc_readl(lcdc_dev, BCSH_COLOR_BAR); - if (((bcsh_color_bar & m_BCSH_EN) == 1) || - (dev_drv->bcsh.enable == 1))/*bcsh enabled */ - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, - m_BCSH_R2Y_EN | m_BCSH_Y2R_EN, - v_BCSH_R2Y_EN(1) | v_BCSH_Y2R_EN(1)); - else - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, - m_BCSH_R2Y_EN | m_BCSH_Y2R_EN, - v_BCSH_R2Y_EN(0) | v_BCSH_Y2R_EN(0)); - } else { /* RGB2YUV */ - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, - m_BCSH_R2Y_EN | m_BCSH_Y2R_EN, - v_BCSH_R2Y_EN(1) | v_BCSH_Y2R_EN(0)); - } -} - -static int rk3288_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact, - u16 *yact, int *format, u32 *dsp_addr, - int *ymirror) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - u32 val; - - spin_lock(&lcdc_dev->reg_lock); - - val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO); - *xact = (val & m_WIN0_ACT_WIDTH) + 1; - *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1; - - val = lcdc_readl(lcdc_dev, WIN0_CTRL0); - *format = (val & m_WIN0_DATA_FMT) >> 1; - *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST); - - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int rk3288_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst, - int format, u16 xact, u16 yact, u16 xvir, - int ymirror) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - u32 val, mask; - struct rk_lcdc_win *win = dev_drv->win[0]; - int swap = (format == RGB888) ? 1 : 0; - - mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP; - val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val); - - lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE, - v_WIN0_VIR_STRIDE(xvir)); - lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) | - v_WIN0_ACT_HEIGHT(yact)); - - lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst); - - lcdc_cfg_done(lcdc_dev); - win->state = 1; - win->last_state = 1; - - return 0; -} - -static int rk3288_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen) -{ - u16 face = 0; - u16 dclk_ddr = 0; - u32 v=0; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u16 hsync_len = screen->mode.hsync_len; - u16 left_margin = screen->mode.left_margin; - u16 right_margin = screen->mode.right_margin; - u16 vsync_len = screen->mode.vsync_len; - u16 upper_margin = screen->mode.upper_margin; - u16 lower_margin = screen->mode.lower_margin; - u16 x_res = screen->mode.xres; - u16 y_res = screen->mode.yres; - u32 mask, val; - u16 h_total,v_total; - int ret = 0; - int hdmi_dclk_out_en = 0; - - if (unlikely(!lcdc_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on); - return 0; - } - - h_total = hsync_len + left_margin + x_res + right_margin; - v_total = vsync_len + upper_margin + y_res + lower_margin; - - screen->post_dsp_stx = x_res * (100 - screen->overscan.left) / 200; - screen->post_dsp_sty = y_res * (100 - screen->overscan.top) / 200; - screen->post_xsize = x_res * (screen->overscan.left + screen->overscan.right) / 200; - screen->post_ysize = y_res * (screen->overscan.top + screen->overscan.bottom) / 200; - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - switch (screen->face) { - case OUT_P565: - face = OUT_P565; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL | m_DITHER_UP_EN | - m_PRE_DITHER_DOWN_EN; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) | - v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) | - v_PRE_DITHER_DOWN_EN(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_P666: - face = OUT_P666; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL | m_DITHER_UP_EN | - m_PRE_DITHER_DOWN_EN; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) | - v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) | - v_PRE_DITHER_DOWN_EN(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_D888_P565: - face = OUT_P888; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL | m_DITHER_UP_EN | - m_PRE_DITHER_DOWN_EN; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) | - v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) | - v_PRE_DITHER_DOWN_EN(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_D888_P666: - face = OUT_P888; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL | m_DITHER_UP_EN | - m_PRE_DITHER_DOWN_EN; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) | - v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) | - v_PRE_DITHER_DOWN_EN(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_P888: - face = OUT_P888; - mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN | - m_PRE_DITHER_DOWN_EN; - val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) | - v_PRE_DITHER_DOWN_EN(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_YUV_420: - hdmi_dclk_out_en = 1; - face = OUT_YUV_420; - dclk_ddr = 1; - mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN | - m_PRE_DITHER_DOWN_EN; - val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) | - v_PRE_DITHER_DOWN_EN(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_YUV_420_10BIT: - hdmi_dclk_out_en = 1; - face = OUT_YUV_420; - dclk_ddr = 1; - mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN | - m_PRE_DITHER_DOWN_EN; - val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) | - v_PRE_DITHER_DOWN_EN(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_P101010: - face = OUT_P101010; - mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN | - m_PRE_DITHER_DOWN_EN; - val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) | - v_PRE_DITHER_DOWN_EN(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - default: - dev_err(lcdc_dev->dev,"un supported interface!\n"); - break; - } - switch(screen->type){ - case SCREEN_RGB: - case SCREEN_LVDS: - case SCREEN_DUAL_LVDS: - case SCREEN_LVDS_10BIT: - case SCREEN_DUAL_LVDS_10BIT: - mask = m_RGB_OUT_EN; - val = v_RGB_OUT_EN(1); - v = 1 << (3+16); - v |= (lcdc_dev->id << 3); - break; - case SCREEN_HDMI: - if ((screen->face == OUT_P888) || - (screen->face == OUT_P101010)) - face = OUT_P101010;/*RGB 101010 output*/ - mask = m_HDMI_OUT_EN; - val = v_HDMI_OUT_EN(1); - break; - case SCREEN_MIPI: - mask = m_MIPI_OUT_EN; - val = v_MIPI_OUT_EN(1); - break; - case SCREEN_DUAL_MIPI: - mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN; - val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1); - break; - case SCREEN_EDP: - face = OUT_P101010; /*RGB 101010 output*/ - mask = m_EDP_OUT_EN; - val = v_EDP_OUT_EN(1); - break; - default: - mask = 0; - val = 0; - pr_info("unknow screen type: %d\n", screen->type); - break; - } - if (dev_drv->version == VOP_FULL_RK3288_V1_1) { - mask |= m_HDMI_DCLK_OUT_EN; - val |= v_HDMI_DCLK_OUT_EN(hdmi_dclk_out_en); - } - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); -#ifndef CONFIG_RK_FPGA - writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_SOC_CON6); -#endif - mask = m_DSP_OUT_MODE | m_DSP_HSYNC_POL | m_DSP_VSYNC_POL | - m_DSP_DEN_POL | m_DSP_DCLK_POL | m_DSP_BG_SWAP | - m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP | - m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN | - m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN | - m_DSP_DCLK_DDR; - val = v_DSP_OUT_MODE(face) | v_DSP_HSYNC_POL(screen->pin_hsync) | - v_DSP_VSYNC_POL(screen->pin_vsync) | - v_DSP_DEN_POL(screen->pin_den) | v_DSP_DCLK_POL(screen->pin_dclk) | - v_DSP_BG_SWAP(screen->swap_gb) | v_DSP_RB_SWAP(screen->swap_rb) | - v_DSP_RG_SWAP(screen->swap_rg) | - v_DSP_DELTA_SWAP(screen->swap_delta) | - v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) | - v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) | - v_DSP_X_MIR_EN(screen->x_mirror) | - v_DSP_Y_MIR_EN(screen->y_mirror) | - v_DSP_DCLK_DDR(dclk_ddr); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - - mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED; - val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) | v_DSP_BG_RED(0); - lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val); - - mask = m_DSP_HS_PW | m_DSP_HTOTAL; - val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total); - lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val); - - mask = m_DSP_HACT_END | m_DSP_HACT_ST; - val = v_DSP_HACT_END(hsync_len + left_margin + x_res) | - v_DSP_HACT_ST(hsync_len + left_margin); - lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val); - - mask = m_DSP_VS_PW | m_DSP_VTOTAL; - val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total); - lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val); - - mask = m_DSP_VACT_END | m_DSP_VACT_ST; - val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) | - v_DSP_VACT_ST(vsync_len + upper_margin); - lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val); - - rk3288_lcdc_post_cfg(dev_drv); - mask = m_DSP_LINE_FLAG_NUM; - val = v_DSP_LINE_FLAG_NUM(vsync_len + upper_margin + y_res); - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val); - dev_drv->output_color = screen->color_mode; - if (dev_drv->version == VOP_FULL_RK3288_V1_1) { - rk3288_lcdc_bcsh_path_sel(dev_drv); - } else { - if (dev_drv->output_color != COLOR_RGB) { - pr_err("vop ver:%x,unsupport output color:%d\n", - dev_drv->version, dev_drv->output_color); - ret = -1; - } - } - } - spin_unlock(&lcdc_dev->reg_lock); - rk3288_lcdc_set_dclk(dev_drv, 1); - if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops && - dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - if (screen->init) - screen->init(); - - return ret; -} - -/*enable layer,open:1,enable;0 disable*/ -static int win0_open(struct lcdc_device *lcdc_dev, bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - if (open) { - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "wakeup from standby!\n"); - lcdc_dev->standby = 0; - } - lcdc_dev->atv_layer_cnt++; - } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.win[0]->state = open; - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n"); - lcdc_dev->standby = 1; - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win1_open(struct lcdc_device *lcdc_dev, bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - if (open) { - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "wakeup from standby!\n"); - lcdc_dev->standby = 0; - } - lcdc_dev->atv_layer_cnt++; - } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.win[1]->state = open; - - /*if no layer used,disable lcdc*/ - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n"); - lcdc_dev->standby = 1; - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win2_open(struct lcdc_device *lcdc_dev, bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - if (open) { - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "wakeup from standby!\n"); - lcdc_dev->standby = 0; - } - lcdc_dev->atv_layer_cnt++; - } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.win[2]->state = open; - - /*if no layer used,disable lcdc*/ - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n"); - lcdc_dev->standby = 1; - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win3_open(struct lcdc_device *lcdc_dev, bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - if (open) { - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "wakeup from standby!\n"); - lcdc_dev->standby = 0; - } - lcdc_dev->atv_layer_cnt++; - } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.win[3]->state = open; - - /*if no layer used,disable lcdc*/ - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n"); - lcdc_dev->standby = 1; - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} -static int rk3288_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - u32 mask,val; - - mask = m_FS_INTR_CLR | m_FS_INTR_EN | m_LINE_FLAG_INTR_CLR | - m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_CLR | - m_BUS_ERROR_INTR_EN; - val = v_FS_INTR_CLR(1) | v_FS_INTR_EN(1) | v_LINE_FLAG_INTR_CLR(1) | - v_LINE_FLAG_INTR_EN(1) | v_BUS_ERROR_INTR_CLR(1) | v_BUS_ERROR_INTR_EN(0); - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val); -#ifdef LCDC_IRQ_EMPTY_DEBUG - mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN | m_WIN2_EMPTY_INTR_EN | - m_WIN3_EMPTY_INTR_EN |m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN | - m_PWM_GEN_INTR_EN; - val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) | v_WIN2_EMPTY_INTR_EN(1) | - v_WIN3_EMPTY_INTR_EN(1)| v_HWC_EMPTY_INTR_EN(1) | v_POST_BUF_EMPTY_INTR_EN(1) | - v_PWM_GEN_INTR_EN(1); - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val); -#endif - return 0; -} - -static int rk3288_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id, - bool open) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - int sys_status = (dev_drv->id == 0) ? - SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1; - - /*enable clk,when first layer open */ - if ((open) && (!lcdc_dev->atv_layer_cnt)) { - rockchip_set_system_status(sys_status); - rk3288_lcdc_pre_init(dev_drv); - rk3288_lcdc_clk_enable(lcdc_dev); - rk3288_lcdc_enable_irq(dev_drv); - if (dev_drv->iommu_enabled) { - if (!dev_drv->mmu_dev) { - dev_drv->mmu_dev = - rk_fb_get_sysmmu_device_by_compatible(dev_drv->mmu_dts_name); - if (dev_drv->mmu_dev) { - rk_fb_platform_set_sysmmu(dev_drv->mmu_dev, - dev_drv->dev); - } else { - dev_err(dev_drv->dev, - "failed to get rockchip iommu device\n"); - return -1; - } - } - } - rk3288_lcdc_reg_restore(lcdc_dev); - /*if (dev_drv->iommu_enabled) - rk3368_lcdc_mmu_en(dev_drv); */ - if ((support_uboot_display()&&(lcdc_dev->prop == PRMRY))) { - rk3288_lcdc_set_dclk(dev_drv, 0); - /* rk3288_lcdc_enable_irq(dev_drv); */ - } else { - rk3288_load_screen(dev_drv, 1); - } - if (dev_drv->bcsh.enable) - rk3288_lcdc_set_bcsh(dev_drv, 1); - spin_lock(&lcdc_dev->reg_lock); - rk3288_lcdc_set_lut(dev_drv); - spin_unlock(&lcdc_dev->reg_lock); - } - - if (win_id == 0) - win0_open(lcdc_dev, open); - else if (win_id == 1) - win1_open(lcdc_dev, open); - else if (win_id == 2) - win2_open(lcdc_dev, open); - else if (win_id == 3) - win3_open(lcdc_dev, open); - else - dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id); - - /* when all layer closed,disable clk */ - if ((!open) && (!lcdc_dev->atv_layer_cnt)) { - rk3288_lcdc_disable_irq(lcdc_dev); - rk3288_lcdc_reg_update(dev_drv); - if (dev_drv->iommu_enabled) { - if (dev_drv->mmu_dev) { - rockchip_iovmm_deactivate(dev_drv->dev); - lcdc_dev->iommu_status = 0; - } - } - rk3288_lcdc_clk_disable(lcdc_dev); - rockchip_clear_system_status(sys_status); - } - - return 0; -} - -static int win0_display(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 y_addr; - u32 uv_addr; - y_addr = win->area[0].smem_start+win->area[0].y_offset;/*win->smem_start + win->y_offset;*/ - uv_addr = win->area[0].cbr_start + win->area[0].c_offset; - DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n", - lcdc_dev->id, __func__, y_addr, uv_addr,win->area[0].y_offset); - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - win->area[0].y_addr = y_addr; - win->area[0].uv_addr = uv_addr; - lcdc_writel(lcdc_dev, WIN0_YRGB_MST, win->area[0].y_addr); - lcdc_writel(lcdc_dev, WIN0_CBR_MST, win->area[0].uv_addr); - /*lcdc_cfg_done(lcdc_dev);*/ - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_display(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 y_addr; - u32 uv_addr; - y_addr = win->area[0].smem_start + win->area[0].y_offset; - uv_addr = win->area[0].cbr_start + win->area[0].c_offset; - DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n", - lcdc_dev->id, __func__, y_addr, uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - win->area[0].y_addr = y_addr; - win->area[0].uv_addr = uv_addr; - lcdc_writel(lcdc_dev, WIN1_YRGB_MST, win->area[0].y_addr); - lcdc_writel(lcdc_dev, WIN1_CBR_MST, win->area[0].uv_addr); - } - spin_unlock(&lcdc_dev->reg_lock); - - - return 0; -} - -static int win2_display(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 i,y_addr; - y_addr = win->area[0].smem_start + win->area[0].y_offset; - DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n", - lcdc_dev->id, __func__, y_addr); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)){ - for(i=0;iarea_num;i++) - win->area[i].y_addr = - win->area[i].smem_start + win->area[i].y_offset; - if (win->area[0].state) - lcdc_writel(lcdc_dev, WIN2_MST0, - win->area[0].y_addr); - if (win->area[1].state) - lcdc_writel(lcdc_dev, WIN2_MST1, - win->area[1].y_addr); - if (win->area[2].state) - lcdc_writel(lcdc_dev, WIN2_MST2, - win->area[2].y_addr); - if (win->area[3].state) - lcdc_writel(lcdc_dev, WIN2_MST3, - win->area[3].y_addr); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int win3_display(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 i,y_addr; - y_addr = win->area[0].smem_start + win->area[0].y_offset; - DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n", - lcdc_dev->id, __func__, y_addr); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)){ - for(i=0;iarea_num;i++) - win->area[i].y_addr = - win->area[i].smem_start + win->area[i].y_offset; - if (win->area[0].state) - lcdc_writel(lcdc_dev, WIN3_MST0, - win->area[0].y_addr); - if (win->area[1].state) - lcdc_writel(lcdc_dev, WIN3_MST1, - win->area[1].y_addr); - if (win->area[2].state) - lcdc_writel(lcdc_dev, WIN3_MST2, - win->area[2].y_addr); - if (win->area[3].state) - lcdc_writel(lcdc_dev, WIN3_MST3, - win->area[3].y_addr); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk3288_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct rk_lcdc_win *win = NULL; - struct rk_screen *screen = dev_drv->cur_screen; - -#if defined(WAIT_FOR_SYNC) - int timeout; - unsigned long flags; -#endif - win = dev_drv->win[win_id]; - if (!screen) { - dev_err(dev_drv->dev, "screen is null!\n"); - return -ENOENT; - } - if(win_id == 0){ - win0_display(lcdc_dev, win); - }else if(win_id == 1){ - win1_display(lcdc_dev, win); - }else if(win_id == 2){ - win2_display(lcdc_dev, win); - }else if(win_id == 3){ - win3_display(lcdc_dev, win); - }else{ - dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id); - return -EINVAL; - } - - /*this is the first frame of the system ,enable frame start interrupt */ - if ((dev_drv->first_frame)) { - dev_drv->first_frame = 0; - rk3288_lcdc_enable_irq(dev_drv); - } -#if defined(WAIT_FOR_SYNC) - spin_lock_irqsave(&dev_drv->cpl_lock, flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock, flags); - timeout = wait_for_completion_timeout(&dev_drv->frame_done, - msecs_to_jiffies(dev_drv-> - cur_screen->ft + - 5)); - if (!timeout && (!dev_drv->frame_done.done)) { - dev_info(dev_drv->dev, "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } -#endif - return 0; -} - -static int rk3288_lcdc_cal_scl_fac(struct rk_lcdc_win *win) -{ - u16 srcW; - u16 srcH; - u16 dstW; - u16 dstH; - u16 yrgb_srcW; - u16 yrgb_srcH; - u16 yrgb_dstW; - u16 yrgb_dstH; - u32 yrgb_vScaleDnMult; - u32 yrgb_xscl_factor; - u32 yrgb_yscl_factor; - u8 yrgb_vsd_bil_gt2=0; - u8 yrgb_vsd_bil_gt4=0; - - u16 cbcr_srcW; - u16 cbcr_srcH; - u16 cbcr_dstW; - u16 cbcr_dstH; - u32 cbcr_vScaleDnMult; - u32 cbcr_xscl_factor; - u32 cbcr_yscl_factor; - u8 cbcr_vsd_bil_gt2=0; - u8 cbcr_vsd_bil_gt4=0; - u8 yuv_fmt=0; - - - srcW = win->area[0].xact; - srcH = win->area[0].yact; - dstW = win->area[0].xsize; - dstH = win->area[0].ysize; - - /*yrgb scl mode*/ - yrgb_srcW = srcW; - yrgb_srcH = srcH; - yrgb_dstW = dstW; - yrgb_dstH = dstH; - if ((yrgb_dstW*8 <= yrgb_srcW) || (yrgb_dstH*8 <= yrgb_srcH)) { - pr_err("ERROR: yrgb scale exceed 8," - "srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", - yrgb_srcW,yrgb_srcH,yrgb_dstW,yrgb_dstH); - } - if(yrgb_srcW < yrgb_dstW){ - win->yrgb_hor_scl_mode = SCALE_UP; - }else if(yrgb_srcW > yrgb_dstW){ - win->yrgb_hor_scl_mode = SCALE_DOWN; - }else{ - win->yrgb_hor_scl_mode = SCALE_NONE; - } - - if(yrgb_srcH < yrgb_dstH){ - win->yrgb_ver_scl_mode = SCALE_UP; - }else if (yrgb_srcH > yrgb_dstH){ - win->yrgb_ver_scl_mode = SCALE_DOWN; - }else{ - win->yrgb_ver_scl_mode = SCALE_NONE; - } - - /*cbcr scl mode*/ - switch (win->area[0].format) { - case YUV422: - case YUV422_A: - cbcr_srcW = srcW/2; - cbcr_dstW = dstW; - cbcr_srcH = srcH; - cbcr_dstH = dstH; - yuv_fmt = 1; - break; - case YUV420: - case YUV420_A: - cbcr_srcW = srcW/2; - cbcr_dstW = dstW; - cbcr_srcH = srcH/2; - cbcr_dstH = dstH; - yuv_fmt = 1; - break; - case YUV444: - case YUV444_A: - cbcr_srcW = srcW; - cbcr_dstW = dstW; - cbcr_srcH = srcH; - cbcr_dstH = dstH; - yuv_fmt = 1; - break; - default: - cbcr_srcW = 0; - cbcr_dstW = 0; - cbcr_srcH = 0; - cbcr_dstH = 0; - yuv_fmt = 0; - break; - } - if (yuv_fmt) { - if ((cbcr_dstW*8 <= cbcr_srcW) || (cbcr_dstH*8 <= cbcr_srcH)) { - pr_err("ERROR: cbcr scale exceed 8," - "srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", - cbcr_srcW,cbcr_srcH,cbcr_dstW,cbcr_dstH); - } - } - - if(cbcr_srcW < cbcr_dstW){ - win->cbr_hor_scl_mode = SCALE_UP; - }else if(cbcr_srcW > cbcr_dstW){ - win->cbr_hor_scl_mode = SCALE_DOWN; - }else{ - win->cbr_hor_scl_mode = SCALE_NONE; - } - - if(cbcr_srcH < cbcr_dstH){ - win->cbr_ver_scl_mode = SCALE_UP; - }else if(cbcr_srcH > cbcr_dstH){ - win->cbr_ver_scl_mode = SCALE_DOWN; - }else{ - win->cbr_ver_scl_mode = SCALE_NONE; - } - DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n" - "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n" - "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n" - ,srcW,srcH,dstW,dstH,yrgb_srcW,yrgb_srcH,yrgb_dstW, - yrgb_dstH,win->yrgb_hor_scl_mode,win->yrgb_ver_scl_mode, - cbcr_srcW,cbcr_srcH,cbcr_dstW,cbcr_dstH, - win->cbr_hor_scl_mode,win->cbr_ver_scl_mode); - - /*line buffer mode*/ - if ((win->area[0].format == YUV422) || - (win->area[0].format == YUV420) || - (win->area[0].format == YUV422_A) || - (win->area[0].format == YUV420_A)) { - if (win->cbr_hor_scl_mode == SCALE_DOWN) { - if ((cbcr_dstW > 3840) || (cbcr_dstW == 0)) { - pr_err("ERROR cbcr_dstW = %d\n",cbcr_dstW); - } else if (cbcr_dstW > 2560) { - win->win_lb_mode = LB_RGB_3840X2; - } else if (cbcr_dstW > 1920) { - if (win->yrgb_hor_scl_mode == SCALE_DOWN) { - if(yrgb_dstW > 3840){ - pr_err("ERROR yrgb_dst_width exceeds 3840\n"); - }else if(yrgb_dstW > 2560){ - win->win_lb_mode = LB_RGB_3840X2; - }else if(yrgb_dstW > 1920){ - win->win_lb_mode = LB_RGB_2560X4; - }else{ - pr_err("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n"); - } - } - } else if (cbcr_dstW > 1280) { - win->win_lb_mode = LB_YUV_3840X5; - } else { - win->win_lb_mode = LB_YUV_2560X8; - } - } else { /*SCALE_UP or SCALE_NONE*/ - if ((cbcr_srcW > 3840) || (cbcr_srcW == 0)) { - pr_err("ERROR cbcr_srcW = %d\n",cbcr_srcW); - }else if(cbcr_srcW > 2560){ - win->win_lb_mode = LB_RGB_3840X2; - }else if(cbcr_srcW > 1920){ - if(win->yrgb_hor_scl_mode == SCALE_DOWN){ - if(yrgb_dstW > 3840){ - pr_err("ERROR yrgb_dst_width exceeds 3840\n"); - }else if(yrgb_dstW > 2560){ - win->win_lb_mode = LB_RGB_3840X2; - }else if(yrgb_dstW > 1920){ - win->win_lb_mode = LB_RGB_2560X4; - }else{ - pr_err("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n"); - } - } - }else if(cbcr_srcW > 1280){ - win->win_lb_mode = LB_YUV_3840X5; - }else{ - win->win_lb_mode = LB_YUV_2560X8; - } - } - }else { - if(win->yrgb_hor_scl_mode == SCALE_DOWN){ - if ((yrgb_dstW > 3840) || (yrgb_dstW == 0)) { - pr_err("ERROR yrgb_dstW = %d\n",yrgb_dstW); - }else if(yrgb_dstW > 2560){ - win->win_lb_mode = LB_RGB_3840X2; - }else if(yrgb_dstW > 1920){ - win->win_lb_mode = LB_RGB_2560X4; - }else if(yrgb_dstW > 1280){ - win->win_lb_mode = LB_RGB_1920X5; - }else{ - win->win_lb_mode = LB_RGB_1280X8; - } - }else{ /*SCALE_UP or SCALE_NONE*/ - if ((yrgb_srcW > 3840) || (yrgb_srcW == 0)) { - pr_err("ERROR yrgb_srcW = %d\n",yrgb_srcW); - }else if(yrgb_srcW > 2560){ - win->win_lb_mode = LB_RGB_3840X2; - }else if(yrgb_srcW > 1920){ - win->win_lb_mode = LB_RGB_2560X4; - }else if(yrgb_srcW > 1280){ - win->win_lb_mode = LB_RGB_1920X5; - }else{ - win->win_lb_mode = LB_RGB_1280X8; - } - } - } - DBG(1,"win->win_lb_mode = %d;\n",win->win_lb_mode); - - /*vsd/vsu scale ALGORITHM*/ - win->yrgb_hsd_mode = SCALE_DOWN_BIL;/*not to specify*/ - win->cbr_hsd_mode = SCALE_DOWN_BIL;/*not to specify*/ - win->yrgb_vsd_mode = SCALE_DOWN_BIL;/*not to specify*/ - win->cbr_vsd_mode = SCALE_DOWN_BIL;/*not to specify*/ - switch(win->win_lb_mode){ - case LB_YUV_3840X5: - case LB_YUV_2560X8: - case LB_RGB_1920X5: - case LB_RGB_1280X8: - win->yrgb_vsu_mode = SCALE_UP_BIC; - win->cbr_vsu_mode = SCALE_UP_BIC; - break; - case LB_RGB_3840X2: - if(win->yrgb_ver_scl_mode != SCALE_NONE) { - pr_err("ERROR : not allow yrgb ver scale\n"); - } - if(win->cbr_ver_scl_mode != SCALE_NONE) { - pr_err("ERROR : not allow cbcr ver scale\n"); - } - break; - case LB_RGB_2560X4: - win->yrgb_vsu_mode = SCALE_UP_BIL; - win->cbr_vsu_mode = SCALE_UP_BIL; - break; - default: - printk(KERN_WARNING "%s:un supported win_lb_mode:%d\n", - __func__,win->win_lb_mode); - break; - } - DBG(1,"yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n", - win->yrgb_hsd_mode,win->yrgb_vsd_mode,win->yrgb_vsu_mode, - win->cbr_hsd_mode,win->cbr_vsd_mode,win->cbr_vsu_mode); - - /*SCALE FACTOR*/ - - /*(1.1)YRGB HOR SCALE FACTOR*/ - switch(win->yrgb_hor_scl_mode){ - case SCALE_NONE: - yrgb_xscl_factor = (1<yrgb_hsd_mode) - { - case SCALE_DOWN_BIL: - yrgb_xscl_factor = GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW); - break; - case SCALE_DOWN_AVG: - yrgb_xscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW); - break; - default : - printk(KERN_WARNING "%s:un supported yrgb_hsd_mode:%d\n", - __func__,win->yrgb_hsd_mode); - break; - } - break; - default : - printk(KERN_WARNING "%s:un supported yrgb_hor_scl_mode:%d\n", - __func__,win->yrgb_hor_scl_mode); - break; - } /*win->yrgb_hor_scl_mode*/ - - /*(1.2)YRGB VER SCALE FACTOR*/ - switch(win->yrgb_ver_scl_mode) - { - case SCALE_NONE: - yrgb_yscl_factor = (1<yrgb_vsu_mode) - { - case SCALE_UP_BIL: - yrgb_yscl_factor = GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH); - break; - case SCALE_UP_BIC: - if(yrgb_srcH < 3){ - pr_err("yrgb_srcH should be greater than 3 !!!\n"); - } - yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH, yrgb_dstH); - break; - default : - printk(KERN_WARNING "%s:un supported yrgb_vsu_mode:%d\n", - __func__,win->yrgb_vsu_mode); - break; - } - break; - case SCALE_DOWN: - switch(win->yrgb_vsd_mode) - { - case SCALE_DOWN_BIL: - yrgb_vScaleDnMult = getHardWareVSkipLines(yrgb_srcH, yrgb_dstH); - yrgb_yscl_factor = GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH, yrgb_vScaleDnMult); - if(yrgb_vScaleDnMult == 4){ - yrgb_vsd_bil_gt4 = 1; - yrgb_vsd_bil_gt2 = 0; - }else if(yrgb_vScaleDnMult == 2){ - yrgb_vsd_bil_gt4 = 0; - yrgb_vsd_bil_gt2 = 1; - }else{ - yrgb_vsd_bil_gt4 = 0; - yrgb_vsd_bil_gt2 = 0; - } - break; - case SCALE_DOWN_AVG: - yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH, yrgb_dstH); - break; - default: - printk(KERN_WARNING "%s:un supported yrgb_vsd_mode:%d\n", - __func__,win->yrgb_vsd_mode); - break; - } /*win->yrgb_vsd_mode*/ - break; - default : - printk(KERN_WARNING "%s:un supported yrgb_ver_scl_mode:%d\n", - __func__,win->yrgb_ver_scl_mode); - break; - } - win->scale_yrgb_x = yrgb_xscl_factor; - win->scale_yrgb_y = yrgb_yscl_factor; - win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4; - win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2; - DBG(1,"yrgb:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",yrgb_xscl_factor, - yrgb_yscl_factor,yrgb_vsd_bil_gt4,yrgb_vsd_bil_gt2); - - /*(2.1)CBCR HOR SCALE FACTOR*/ - switch(win->cbr_hor_scl_mode) - { - case SCALE_NONE: - cbcr_xscl_factor = (1<cbr_hsd_mode) - { - case SCALE_DOWN_BIL: - cbcr_xscl_factor = GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW); - break; - case SCALE_DOWN_AVG: - cbcr_xscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW); - break; - default : - printk(KERN_WARNING "%s:un supported cbr_hsd_mode:%d\n", - __func__,win->cbr_hsd_mode); - break; - } - break; - default : - printk(KERN_WARNING "%s:un supported cbr_hor_scl_mode:%d\n", - __func__,win->cbr_hor_scl_mode); - break; - } /*win->cbr_hor_scl_mode*/ - - /*(2.2)CBCR VER SCALE FACTOR*/ - switch(win->cbr_ver_scl_mode) - { - case SCALE_NONE: - cbcr_yscl_factor = (1<cbr_vsu_mode) - { - case SCALE_UP_BIL: - cbcr_yscl_factor = GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH); - break; - case SCALE_UP_BIC: - if(cbcr_srcH < 3) { - pr_err("cbcr_srcH should be greater than 3 !!!\n"); - } - cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH, cbcr_dstH); - break; - default : - printk(KERN_WARNING "%s:un supported cbr_vsu_mode:%d\n", - __func__,win->cbr_vsu_mode); - break; - } - break; - case SCALE_DOWN: - switch(win->cbr_vsd_mode) - { - case SCALE_DOWN_BIL: - cbcr_vScaleDnMult = getHardWareVSkipLines(cbcr_srcH, cbcr_dstH); - cbcr_yscl_factor = GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH, cbcr_vScaleDnMult); - if(cbcr_vScaleDnMult == 4){ - cbcr_vsd_bil_gt4 = 1; - cbcr_vsd_bil_gt2 = 0; - }else if(cbcr_vScaleDnMult == 2){ - cbcr_vsd_bil_gt4 = 0; - cbcr_vsd_bil_gt2 = 1; - }else{ - cbcr_vsd_bil_gt4 = 0; - cbcr_vsd_bil_gt2 = 0; - } - break; - case SCALE_DOWN_AVG: - cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH, cbcr_dstH); - break; - default : - printk(KERN_WARNING "%s:un supported cbr_vsd_mode:%d\n", - __func__,win->cbr_vsd_mode); - break; - } - break; - default : - printk(KERN_WARNING "%s:un supported cbr_ver_scl_mode:%d\n", - __func__,win->cbr_ver_scl_mode); - break; - } - win->scale_cbcr_x = cbcr_xscl_factor; - win->scale_cbcr_y = cbcr_yscl_factor; - win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4; - win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2; - - DBG(1,"cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",cbcr_xscl_factor, - cbcr_yscl_factor,cbcr_vsd_bil_gt4,cbcr_vsd_bil_gt2); - return 0; -} - - - -static int win0_set_par(struct lcdc_device *lcdc_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - u32 xact,yact,xvir, yvir,xpos, ypos; - u8 fmt_cfg = 0, swap_rb, swap_uv = 0; - char fmt[9] = "NULL"; - - xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len; - ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len; - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)){ - rk3288_lcdc_cal_scl_fac(win);/*fac,lb,gt2,gt4*/ - switch (win->area[0].format) { - case ARGB888: - fmt_cfg = 0; - swap_rb = 0; - win->fmt_10 = 0; - break; - case XBGR888: - case ABGR888: - fmt_cfg = 0; - swap_rb = 1; - win->fmt_10 = 0; - break; - case RGB888: - fmt_cfg = 1; - swap_rb = 0; - win->fmt_10 = 0; - break; - case RGB565: - fmt_cfg = 2; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV422: - fmt_cfg = 5; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV420: - fmt_cfg = 4; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV420_NV21: - fmt_cfg = 4; - swap_rb = 0; - swap_uv = 1; - win->fmt_10 = 0; - break; - case YUV444: - fmt_cfg = 6; - swap_rb = 0; - win->fmt_10 = 0; - case YUV422_A: - fmt_cfg = 5; - swap_rb = 0; - win->fmt_10 = 1; - break; - case YUV420_A: - fmt_cfg = 4; - swap_rb = 0; - win->fmt_10 = 1; - break; - case YUV444_A: - fmt_cfg = 6; - swap_rb = 0; - win->fmt_10 = 1; - break; - default: - dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n", - __func__); - break; - } - win->area[0].fmt_cfg = fmt_cfg; - win->area[0].swap_rb = swap_rb; - win->area[0].dsp_stx = xpos; - win->area[0].dsp_sty = ypos; - win->area[0].swap_uv = swap_uv; - xact = win->area[0].xact; - yact = win->area[0].yact; - xvir = win->area[0].xvir; - yvir = win->area[0].yvir; - } - rk3288_win_0_1_reg_update(&lcdc_dev->driver,0); - spin_unlock(&lcdc_dev->reg_lock); - - DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n" - ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, - __func__, get_format_string(win->area[0].format, fmt), xact, - yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos); - return 0; - -} - -static int win1_set_par(struct lcdc_device *lcdc_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u8 fmt_cfg = 0, swap_rb, swap_uv = 0; - char fmt[9] = "NULL"; - - xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len; - ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len; - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - rk3288_lcdc_cal_scl_fac(win);/*fac,lb,gt2,gt4*/ - switch (win->area[0].format) { - case ARGB888: - fmt_cfg = 0; - swap_rb = 0; - win->fmt_10 = 0; - break; - case XBGR888: - case ABGR888: - fmt_cfg = 0; - swap_rb = 1; - win->fmt_10 = 0; - break; - case RGB888: - fmt_cfg = 1; - swap_rb = 0; - win->fmt_10 = 0; - break; - case RGB565: - fmt_cfg = 2; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV422: - fmt_cfg = 5; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV420: - fmt_cfg = 4; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV420_NV21: - fmt_cfg = 4; - swap_rb = 0; - swap_uv = 1; - win->fmt_10 = 0; - break; - case YUV444: - fmt_cfg = 6; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV422_A: - fmt_cfg = 5; - swap_rb = 0; - win->fmt_10 = 1; - break; - case YUV420_A: - fmt_cfg = 4; - swap_rb = 0; - win->fmt_10 = 1; - break; - case YUV444_A: - fmt_cfg = 6; - swap_rb = 0; - win->fmt_10 = 1; - break; - default: - dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n", - __func__); - break; - } - win->area[0].fmt_cfg = fmt_cfg; - win->area[0].swap_rb = swap_rb; - win->area[0].dsp_stx = xpos; - win->area[0].dsp_sty = ypos; - win->area[0].swap_uv = swap_uv; - xact = win->area[0].xact; - yact = win->area[0].yact; - xvir = win->area[0].xvir; - yvir = win->area[0].yvir; - } - rk3288_win_0_1_reg_update(&lcdc_dev->driver,1); - spin_unlock(&lcdc_dev->reg_lock); - - DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n" - ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, - __func__, get_format_string(win->area[0].format, fmt), xact, - yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos); - return 0; - -} - -static int win2_set_par(struct lcdc_device *lcdc_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - int i; - u8 fmt_cfg, swap_rb; - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - for (i = 0; i < win->area_num; i++) { - switch (win->area[i].format) { - case ARGB888: - fmt_cfg = 0; - swap_rb = 0; - break; - case XBGR888: - case ABGR888: - fmt_cfg = 0; - swap_rb = 1; - break; - case RGB888: - fmt_cfg = 1; - swap_rb = 0; - break; - case RGB565: - fmt_cfg = 2; - swap_rb = 0; - break; - default: - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", - __func__); - break; - } - win->area[i].fmt_cfg = fmt_cfg; - win->area[i].swap_rb = swap_rb; - win->area[i].dsp_stx = win->area[i].xpos + - screen->mode.left_margin + - screen->mode.hsync_len; - if (screen->y_mirror == 1) { - win->area[i].dsp_sty = screen->mode.yres - - win->area[i].ypos - - win->area[i].ysize + - screen->mode.upper_margin + - screen->mode.vsync_len; - } else { - win->area[i].dsp_sty = win->area[i].ypos + - screen->mode.upper_margin + - screen->mode.vsync_len; - } - if ((win->area[i].xact != win->area[i].xsize) || - (win->area[i].yact != win->area[i].ysize)) { - pr_err("win[%d]->area[%d],not support scale\n", - win->id, i); - pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n", - win->area[i].xact,win->area[i].yact, - win->area[i].xsize,win->area[i].ysize); - win->area[i].xsize = win->area[i].xact; - win->area[i].ysize = win->area[i].yact; - } - } - } - rk3288_win_2_3_reg_update(&lcdc_dev->driver,2); - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int win3_set_par(struct lcdc_device *lcdc_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) - -{ - int i; - u8 fmt_cfg, swap_rb; - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - for (i = 0; i < win->area_num; i++) { - switch (win->area[i].format) { - case ARGB888: - fmt_cfg = 0; - swap_rb = 0; - break; - case XBGR888: - case ABGR888: - fmt_cfg = 0; - swap_rb = 1; - break; - case RGB888: - fmt_cfg = 1; - swap_rb = 0; - break; - case RGB565: - fmt_cfg = 2; - swap_rb = 0; - break; - default: - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", - __func__); - break; - } - win->area[i].fmt_cfg = fmt_cfg; - win->area[i].swap_rb = swap_rb; - win->area[i].dsp_stx = win->area[i].xpos + - screen->mode.left_margin + - screen->mode.hsync_len; - if (screen->y_mirror == 1) { - win->area[i].dsp_sty = screen->mode.yres - - win->area[i].ypos - - win->area[i].ysize + - screen->mode.upper_margin + - screen->mode.vsync_len; - } else { - win->area[i].dsp_sty = win->area[i].ypos + - screen->mode.upper_margin + - screen->mode.vsync_len; - } - if ((win->area[i].xact != win->area[i].xsize) || - (win->area[i].yact != win->area[i].ysize)) { - pr_err("win[%d]->area[%d],not support scale\n", - win->id, i); - pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n", - win->area[i].xact, win->area[i].yact, - win->area[i].xsize, win->area[i].ysize); - win->area[i].xsize = win->area[i].xact; - win->area[i].ysize = win->area[i].yact; - } - } - } - rk3288_win_2_3_reg_update(&lcdc_dev->driver,3); - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk3288_lcdc_set_par(struct rk_lcdc_driver *dev_drv,int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = NULL; - struct rk_screen *screen = dev_drv->cur_screen; - win = dev_drv->win[win_id]; - - switch(win_id) - { - case 0: - win0_set_par(lcdc_dev, screen, win); - break; - case 1: - win1_set_par(lcdc_dev, screen, win); - break; - case 2: - win2_set_par(lcdc_dev, screen, win); - break; - case 3: - win3_set_par(lcdc_dev, screen, win); - break; - default: - dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id); - break; - } - return 0; -} - -static int rk3288_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd, - unsigned long arg, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct - lcdc_device, - driver); - u32 panel_size[2]; - void __user *argp = (void __user *)arg; - struct color_key_cfg clr_key_cfg; - - switch (cmd) { - case RK_FBIOGET_PANEL_SIZE: - panel_size[0] = lcdc_dev->screen->mode.xres; - panel_size[1] = lcdc_dev->screen->mode.yres; - if (copy_to_user(argp, panel_size, 8)) - return -EFAULT; - break; - case RK_FBIOPUT_COLOR_KEY_CFG: - if (copy_from_user(&clr_key_cfg, argp, - sizeof(struct color_key_cfg))) - return -EFAULT; - rk3288_lcdc_clr_key_cfg(dev_drv); - lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, - clr_key_cfg.win0_color_key_cfg); - lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, - clr_key_cfg.win1_color_key_cfg); - break; - - default: - break; - } - return 0; -} - -static int rk3288_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv) -{ - u32 reg; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - if (dev_drv->suspend_flag) - return 0; - - dev_drv->suspend_flag = 1; - flush_kthread_worker(&dev_drv->update_regs_worker); - - for (reg = MMU_DTE_ADDR; reg <= MMU_AUTO_GATING; reg +=4) - lcdc_readl(lcdc_dev, reg); - if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable) - dev_drv->trsm_ops->disable(); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN, - v_DSP_BLANK_EN(1)); - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_FS_INTR_CLR | m_LINE_FLAG_INTR_CLR, - v_FS_INTR_CLR(1) | v_LINE_FLAG_INTR_CLR(1)); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO, - v_DSP_OUT_ZERO(1)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, - v_STANDBY_EN(1)); - lcdc_cfg_done(lcdc_dev); - - if (dev_drv->iommu_enabled) { - if (dev_drv->mmu_dev) - rockchip_iovmm_deactivate(dev_drv->dev); - } - - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - rk3288_lcdc_clk_disable(lcdc_dev); - rk_disp_pwr_disable(dev_drv); - return 0; -} - -static int rk3288_lcdc_early_resume(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if (!dev_drv->suspend_flag) - return 0; - rk_disp_pwr_enable(dev_drv); - dev_drv->suspend_flag = 0; - - if (lcdc_dev->atv_layer_cnt) { - rk3288_lcdc_clk_enable(lcdc_dev); - rk3288_lcdc_reg_restore(lcdc_dev); - - spin_lock(&lcdc_dev->reg_lock); - rk3288_lcdc_set_lut(dev_drv); - - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO, - v_DSP_OUT_ZERO(0)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, - v_STANDBY_EN(0)); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN, - v_DSP_BLANK_EN(0)); - lcdc_cfg_done(lcdc_dev); - - if (dev_drv->iommu_enabled) { - if (dev_drv->mmu_dev) - rockchip_iovmm_activate(dev_drv->dev); - } - - spin_unlock(&lcdc_dev->reg_lock); - } - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - - return 0; -} - -static int rk3288_lcdc_blank(struct rk_lcdc_driver *dev_drv, - int win_id, int blank_mode) -{ - switch (blank_mode) { - case FB_BLANK_UNBLANK: - rk3288_lcdc_early_resume(dev_drv); - break; - case FB_BLANK_NORMAL: - rk3288_lcdc_early_suspend(dev_drv); - break; - default: - rk3288_lcdc_early_suspend(dev_drv); - break; - } - - dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode); - - return 0; -} - -static int rk3288_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, - int win_id, int area_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 win_ctrl = 0; - u32 area_status = 0; - - switch (win_id) { - case 0: - win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0); - area_status = win_ctrl & m_WIN0_EN; - break; - case 1: - win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0); - area_status = win_ctrl & m_WIN1_EN; - break; - case 2: - win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0); - if (area_id == 0) - area_status = win_ctrl & m_WIN2_MST0_EN; - if (area_id == 1) - area_status = win_ctrl & m_WIN2_MST1_EN; - if (area_id == 2) - area_status = win_ctrl & m_WIN2_MST2_EN; - if (area_id == 3) - area_status = win_ctrl & m_WIN2_MST3_EN; - break; - case 3: - win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0); - if (area_id == 0) - area_status = win_ctrl & m_WIN3_MST0_EN; - if (area_id == 1) - area_status = win_ctrl & m_WIN3_MST1_EN; - if (area_id == 2) - area_status = win_ctrl & m_WIN3_MST2_EN; - if (area_id == 3) - area_status = win_ctrl & m_WIN3_MST3_EN; - break; - case 4: - win_ctrl = lcdc_readl(lcdc_dev, HWC_CTRL0); - area_status = win_ctrl & m_HWC_EN; - break; - default: - pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n",__func__,win_id,area_id); - break; - } - return area_status; -} - -static int rk3288_lcdc_get_area_num(struct rk_lcdc_driver *dev_drv, - unsigned int *area_support) -{ - area_support[0] = 1; - area_support[1] = 1; - area_support[2] = 4; - area_support[3] = 4; - - return 0; -} - -/*overlay will be do at regupdate*/ -static int rk3288_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, - bool set) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = NULL; - int i,ovl; - unsigned int mask, val; - int z_order_num=0; - int layer0_sel,layer1_sel,layer2_sel,layer3_sel; - if(swap == 0){ - for(i=0;i<4;i++){ - win = dev_drv->win[i]; - if(win->state == 1){ - z_order_num++; - } - } - for(i=0;i<4;i++){ - win = dev_drv->win[i]; - if(win->state == 0) - win->z_order = z_order_num++; - switch(win->z_order){ - case 0: - layer0_sel = win->id; - break; - case 1: - layer1_sel = win->id; - break; - case 2: - layer2_sel = win->id; - break; - case 3: - layer3_sel = win->id; - break; - default: - break; - } - } - }else{ - layer0_sel = swap %10;; - layer1_sel = swap /10 % 10; - layer2_sel = swap / 100 %10; - layer3_sel = swap / 1000; - } - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on){ - if(set){ - mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL | - m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL; - val = v_DSP_LAYER0_SEL(layer0_sel) | - v_DSP_LAYER1_SEL(layer1_sel) | - v_DSP_LAYER2_SEL(layer2_sel) | - v_DSP_LAYER3_SEL(layer3_sel); - lcdc_msk_reg(lcdc_dev,DSP_CTRL1,mask,val); - }else{ - layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER0_SEL); - layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER1_SEL); - layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER2_SEL); - layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER3_SEL); - ovl = layer3_sel*1000 + layer2_sel*100 + layer1_sel *10 + layer0_sel; - } - }else{ - ovl = -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - - return ovl; -} - -static ssize_t rk3288_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv, - char *buf, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct - lcdc_device, - driver); - struct rk_screen *screen = dev_drv->cur_screen; - u16 hsync_len = screen->mode.hsync_len; - u16 left_margin = screen->mode.left_margin; - u16 vsync_len = screen->mode.vsync_len; - u16 upper_margin = screen->mode.upper_margin; - u32 h_pw_bp = hsync_len + left_margin; - u32 v_pw_bp = vsync_len + upper_margin; - u32 fmt_id; - char format_w0[9] = "NULL"; - char format_w1[9] = "NULL"; - char format_w2[9] = "NULL"; - char format_w3[9] = "NULL"; - u32 win_ctrl,zorder,vir_info,act_info,dsp_info,dsp_st,y_factor,uv_factor; - u8 layer0_sel,layer1_sel,layer2_sel,layer3_sel; - u8 w0_state,w1_state,w2_state,w3_state; - u8 w2_0_state,w2_1_state,w2_2_state,w2_3_state; - u8 w3_0_state,w3_1_state,w3_2_state,w3_3_state; - - u32 w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y,w0_dsp_x,w0_dsp_y,w0_st_x=h_pw_bp,w0_st_y=v_pw_bp; - u32 w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y,w1_dsp_x,w1_dsp_y,w1_st_x=h_pw_bp,w1_st_y=v_pw_bp; - u32 w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac,w0_uv_v_fac; - u32 w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac,w1_uv_v_fac; - - u32 w2_0_vir_y,w2_1_vir_y,w2_2_vir_y,w2_3_vir_y; - u32 w2_0_dsp_x,w2_1_dsp_x,w2_2_dsp_x,w2_3_dsp_x; - u32 w2_0_dsp_y,w2_1_dsp_y,w2_2_dsp_y,w2_3_dsp_y; - u32 w2_0_st_x=h_pw_bp,w2_1_st_x=h_pw_bp,w2_2_st_x=h_pw_bp,w2_3_st_x=h_pw_bp; - u32 w2_0_st_y=v_pw_bp,w2_1_st_y=v_pw_bp,w2_2_st_y=v_pw_bp,w2_3_st_y=v_pw_bp; - - u32 w3_0_vir_y,w3_1_vir_y,w3_2_vir_y,w3_3_vir_y; - u32 w3_0_dsp_x,w3_1_dsp_x,w3_2_dsp_x,w3_3_dsp_x; - u32 w3_0_dsp_y,w3_1_dsp_y,w3_2_dsp_y,w3_3_dsp_y; - u32 w3_0_st_x=h_pw_bp,w3_1_st_x=h_pw_bp,w3_2_st_x=h_pw_bp,w3_3_st_x=h_pw_bp; - u32 w3_0_st_y=v_pw_bp,w3_1_st_y=v_pw_bp,w3_2_st_y=v_pw_bp,w3_3_st_y=v_pw_bp; - u32 dclk_freq; - - dclk_freq = screen->mode.pixclock; - /*rk3288_lcdc_reg_dump(dev_drv);*/ - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - zorder = lcdc_readl(lcdc_dev, DSP_CTRL1); - layer0_sel = (zorder & m_DSP_LAYER0_SEL)>>8; - layer1_sel = (zorder & m_DSP_LAYER1_SEL)>>10; - layer2_sel = (zorder & m_DSP_LAYER2_SEL)>>12; - layer3_sel = (zorder & m_DSP_LAYER3_SEL)>>14; - /*WIN0*/ - win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0); - w0_state = win_ctrl & m_WIN0_EN; - fmt_id = (win_ctrl & m_WIN0_DATA_FMT)>>1; - switch (fmt_id) { - case 0: - strcpy(format_w0, "ARGB888"); - break; - case 1: - strcpy(format_w0, "RGB888"); - break; - case 2: - strcpy(format_w0, "RGB565"); - break; - case 4: - strcpy(format_w0, "YCbCr420"); - break; - case 5: - strcpy(format_w0, "YCbCr422"); - break; - case 6: - strcpy(format_w0, "YCbCr444"); - break; - default: - strcpy(format_w0, "invalid\n"); - break; - } - vir_info = lcdc_readl(lcdc_dev,WIN0_VIR); - act_info = lcdc_readl(lcdc_dev,WIN0_ACT_INFO); - dsp_info = lcdc_readl(lcdc_dev,WIN0_DSP_INFO); - dsp_st = lcdc_readl(lcdc_dev,WIN0_DSP_ST); - y_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_YRGB); - uv_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_CBR); - w0_vir_y = vir_info & m_WIN0_VIR_STRIDE; - w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV)>>16; - w0_act_x = (act_info & m_WIN0_ACT_WIDTH)+1; - w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT)>>16)+1; - w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH)+1; - w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT)>>16)+1; - if (w0_state) { - w0_st_x = dsp_st & m_WIN0_DSP_XST; - w0_st_y = (dsp_st & m_WIN0_DSP_YST)>>16; - } - w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB; - w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB)>>16; - w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR; - w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR)>>16; - - /*WIN1*/ - win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0); - w1_state = win_ctrl & m_WIN1_EN; - fmt_id = (win_ctrl & m_WIN1_DATA_FMT)>>1; - switch (fmt_id) { - case 0: - strcpy(format_w1, "ARGB888"); - break; - case 1: - strcpy(format_w1, "RGB888"); - break; - case 2: - strcpy(format_w1, "RGB565"); - break; - case 4: - strcpy(format_w1, "YCbCr420"); - break; - case 5: - strcpy(format_w1, "YCbCr422"); - break; - case 6: - strcpy(format_w1, "YCbCr444"); - break; - default: - strcpy(format_w1, "invalid\n"); - break; - } - vir_info = lcdc_readl(lcdc_dev,WIN1_VIR); - act_info = lcdc_readl(lcdc_dev,WIN1_ACT_INFO); - dsp_info = lcdc_readl(lcdc_dev,WIN1_DSP_INFO); - dsp_st = lcdc_readl(lcdc_dev,WIN1_DSP_ST); - y_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_YRGB); - uv_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_CBR); - w1_vir_y = vir_info & m_WIN1_VIR_STRIDE; - w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV)>>16; - w1_act_x = (act_info & m_WIN1_ACT_WIDTH)+1; - w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT)>>16)+1; - w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH)+1; - w1_dsp_y =((dsp_info & m_WIN1_DSP_HEIGHT)>>16)+1; - if (w1_state) { - w1_st_x = dsp_st & m_WIN1_DSP_XST; - w1_st_y = (dsp_st & m_WIN1_DSP_YST)>>16; - } - w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB; - w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB)>>16; - w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR; - w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR)>>16; - /*WIN2*/ - win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0); - w2_state = win_ctrl & m_WIN2_EN; - w2_0_state = (win_ctrl & m_WIN2_MST0_EN)>>4; - w2_1_state = (win_ctrl & m_WIN2_MST1_EN)>>5; - w2_2_state = (win_ctrl & m_WIN2_MST2_EN)>>6; - w2_3_state = (win_ctrl & m_WIN2_MST3_EN)>>7; - vir_info = lcdc_readl(lcdc_dev,WIN2_VIR0_1); - w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0; - w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1)>>16; - vir_info = lcdc_readl(lcdc_dev,WIN2_VIR2_3); - w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2; - w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3)>>16; - fmt_id = (win_ctrl & m_WIN2_DATA_FMT)>>1; - switch (fmt_id) { - case 0: - strcpy(format_w2, "ARGB888"); - break; - case 1: - strcpy(format_w2, "RGB888"); - break; - case 2: - strcpy(format_w2, "RGB565"); - break; - case 4: - strcpy(format_w2,"8bpp"); - break; - case 5: - strcpy(format_w2,"4bpp"); - break; - case 6: - strcpy(format_w2,"2bpp"); - break; - case 7: - strcpy(format_w2,"1bpp"); - break; - default: - strcpy(format_w2, "invalid\n"); - break; - } - dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO0); - dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST0); - w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0)+1; - w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0)>>16)+1; - if (w2_0_state) { - w2_0_st_x = dsp_st & m_WIN2_DSP_XST0; - w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0)>>16; - } - dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO1); - dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST1); - w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1)+1; - w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1)>>16)+1; - if (w2_1_state) { - w2_1_st_x = dsp_st & m_WIN2_DSP_XST1; - w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1)>>16; - } - dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO2); - dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST2); - w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2)+1; - w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2)>>16)+1; - if (w2_2_state) { - w2_2_st_x = dsp_st & m_WIN2_DSP_XST2; - w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2)>>16; - } - dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO3); - dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST3); - w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3)+1; - w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3)>>16)+1; - if (w2_3_state) { - w2_3_st_x = dsp_st & m_WIN2_DSP_XST3; - w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3)>>16; - } - - /*WIN3*/ - win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0); - w3_state = win_ctrl & m_WIN3_EN; - w3_0_state = (win_ctrl & m_WIN3_MST0_EN)>>4; - w3_1_state = (win_ctrl & m_WIN3_MST1_EN)>>5; - w3_2_state = (win_ctrl & m_WIN3_MST2_EN)>>6; - w3_3_state = (win_ctrl & m_WIN3_MST3_EN)>>7; - vir_info = lcdc_readl(lcdc_dev,WIN3_VIR0_1); - w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0; - w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1)>>16; - vir_info = lcdc_readl(lcdc_dev,WIN3_VIR2_3); - w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2; - w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3)>>16; - fmt_id = (win_ctrl & m_WIN3_DATA_FMT)>>1; - switch (fmt_id) { - case 0: - strcpy(format_w3, "ARGB888"); - break; - case 1: - strcpy(format_w3, "RGB888"); - break; - case 2: - strcpy(format_w3, "RGB565"); - break; - case 4: - strcpy(format_w3,"8bpp"); - break; - case 5: - strcpy(format_w3,"4bpp"); - break; - case 6: - strcpy(format_w3,"2bpp"); - break; - case 7: - strcpy(format_w3,"1bpp"); - break; - default: - strcpy(format_w3, "invalid"); - break; - } - dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO0); - dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST0); - w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0)+1; - w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0)>>16)+1; - if (w3_0_state) { - w3_0_st_x = dsp_st & m_WIN3_DSP_XST0; - w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0)>>16; - } - - dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO1); - dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST1); - w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1)+1; - w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1)>>16)+1; - if (w3_1_state) { - w3_1_st_x = dsp_st & m_WIN3_DSP_XST1; - w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1)>>16; - } - - dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO2); - dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST2); - w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2)+1; - w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2)>>16)+1; - if (w3_2_state) { - w3_2_st_x = dsp_st & m_WIN3_DSP_XST2; - w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2)>>16; - } - - dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO3); - dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST3); - w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3)+1; - w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3)>>16)+1; - if (w3_3_state) { - w3_3_st_x = dsp_st & m_WIN3_DSP_XST3; - w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3)>>16; - } - - } else { - spin_unlock(&lcdc_dev->reg_lock); - return -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - return snprintf(buf, PAGE_SIZE, - "z-order:\n" - " layer3_sel_win[%d]\n" - " layer2_sel_win[%d]\n" - " layer1_sel_win[%d]\n" - " layer0_sel_win[%d]\n" - "win0:\n" - " state:%d, " - " fmt:%s, " - " y_vir:%d, " - " uv_vir:%d\n" - " xact:%4d, " - " yact:%4d, " - " dsp_x:%4d, " - " dsp_y:%4d, " - " x_st:%4d, " - " y_st:%4d\n" - " y_h_fac:%8d, " - " y_v_fac:%8d, " - " uv_h_fac:%8d, " - " uv_v_fac:%8d\n" - " y_addr: 0x%08x, " - " uv_addr:0x%08x\n" - "win1:\n" - " state:%d, " - " fmt:%s, " - " y_vir:%d, " - " uv_vir:%d\n" - " xact:%4d, " - " yact:%4d, " - " dsp_x:%4d, " - " dsp_y:%4d, " - " x_st:%4d, " - " y_st:%4d\n" - " y_h_fac:%8d, " - " y_v_fac:%8d, " - " uv_h_fac:%8d, " - " uv_v_fac:%8d\n" - " y_addr: 0x%08x, " - " uv_addr:0x%08x\n" - "win2:\n" - " state:%d\n" - " fmt:%s\n" - " area0:" - " state:%d," - " y_vir:%4d," - " dsp_x:%4d," - " dsp_y:%4d," - " x_st:%4d," - " y_st:%4d," - " addr:0x%08x\n" - " area1:" - " state:%d," - " y_vir:%4d," - " dsp_x:%4d," - " dsp_y:%4d," - " x_st:%4d," - " y_st:%4d," - " addr:0x%08x\n" - " area2:" - " state:%d," - " y_vir:%4d," - " dsp_x:%4d," - " dsp_y:%4d," - " x_st:%4d," - " y_st:%4d," - " addr:0x%08x\n" - " area3:" - " state:%d," - " y_vir:%4d," - " dsp_x:%4d," - " dsp_y:%4d," - " x_st:%4d," - " y_st:%4d," - " addr:0x%08x\n" - "win3:\n" - " state:%d\n" - " fmt:%s\n" - " area0:" - " state:%d," - " y_vir:%4d," - " dsp_x:%4d," - " dsp_y:%4d," - " x_st:%4d," - " y_st:%4d," - " addr:0x%08x\n" - " area1:" - " state:%d," - " y_vir:%4d," - " dsp_x:%4d," - " dsp_y:%4d," - " x_st:%4d," - " y_st:%4d " - " addr:0x%08x\n" - " area2:" - " state:%d," - " y_vir:%4d," - " dsp_x:%4d," - " dsp_y:%4d," - " x_st:%4d," - " y_st:%4d," - " addr:0x%08x\n" - " area3:" - " state:%d," - " y_vir:%4d," - " dsp_x:%4d," - " dsp_y:%4d," - " x_st:%4d," - " y_st:%4d," - " addr:0x%08x\n", - layer3_sel,layer2_sel,layer1_sel,layer0_sel, - w0_state,format_w0,w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y, - w0_dsp_x,w0_dsp_y,w0_st_x-h_pw_bp,w0_st_y-v_pw_bp,w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac, - w0_uv_v_fac,lcdc_readl(lcdc_dev, WIN0_YRGB_MST), - lcdc_readl(lcdc_dev, WIN0_CBR_MST), - - w1_state,format_w1,w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y, - w1_dsp_x,w1_dsp_y,w1_st_x-h_pw_bp,w1_st_y-v_pw_bp,w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac, - w1_uv_v_fac,lcdc_readl(lcdc_dev, WIN1_YRGB_MST), - lcdc_readl(lcdc_dev, WIN1_CBR_MST), - - w2_state,format_w2, - w2_0_state,w2_0_vir_y,w2_0_dsp_x,w2_0_dsp_y, - w2_0_st_x-h_pw_bp,w2_0_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST0), - - w2_1_state,w2_1_vir_y,w2_1_dsp_x,w2_1_dsp_y, - w2_1_st_x-h_pw_bp,w2_1_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST1), - - w2_2_state,w2_2_vir_y,w2_2_dsp_x,w2_2_dsp_y, - w2_2_st_x-h_pw_bp,w2_2_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST2), - - w2_3_state,w2_3_vir_y,w2_3_dsp_x,w2_3_dsp_y, - w2_3_st_x-h_pw_bp,w2_3_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST3), - - w3_state,format_w3, - w3_0_state,w3_0_vir_y,w3_0_dsp_x,w3_0_dsp_y, - w3_0_st_x-h_pw_bp,w3_0_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST0), - - w3_1_state,w3_1_vir_y,w3_1_dsp_x,w3_1_dsp_y, - w3_1_st_x-h_pw_bp,w3_1_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST1), - - w3_2_state,w3_2_vir_y,w3_2_dsp_x,w3_2_dsp_y, - w3_2_st_x-h_pw_bp,w3_2_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST2), - - w3_3_state,w3_3_vir_y,w3_3_dsp_x,w3_3_dsp_y, - w3_3_st_x-h_pw_bp,w3_3_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST3) - ); - -} - -static int rk3288_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, - bool set) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u64 ft = 0; - u32 dotclk; - int ret; - u32 pixclock; - u32 x_total, y_total; - if (set) { - if (fps == 0) { - dev_info(dev_drv->dev, "unsupport set fps=0\n"); - return 0; - } - ft = div_u64(1000000000000llu, fps); - x_total = - screen->mode.upper_margin + screen->mode.lower_margin + - screen->mode.yres + screen->mode.vsync_len; - y_total = - screen->mode.left_margin + screen->mode.right_margin + - screen->mode.xres + screen->mode.hsync_len; - dev_drv->pixclock = div_u64(ft, x_total * y_total); - dotclk = div_u64(1000000000000llu, dev_drv->pixclock); - ret = clk_set_rate(lcdc_dev->dclk, dotclk); - } - - pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - dev_drv->pixclock = lcdc_dev->pixclock = pixclock; - fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock); - screen->ft = 1000 / fps; /*one frame time in ms */ - - if (set) - dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__, - clk_get_rate(lcdc_dev->dclk), fps); - - return fps; -} - -static int rk3288_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order) -{ - mutex_lock(&dev_drv->fb_win_id_mutex); - if (order == FB_DEFAULT_ORDER) - order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3; - dev_drv->fb3_win_id = order / 1000; - dev_drv->fb2_win_id = (order / 100) % 10; - dev_drv->fb1_win_id = (order / 10) % 10; - dev_drv->fb0_win_id = order % 10; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return 0; -} - -static int rk3288_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv, - const char *id) -{ - int win_id = 0; - mutex_lock(&dev_drv->fb_win_id_mutex); - if (!strcmp(id, "fb0") || !strcmp(id, "fb4")) - win_id = dev_drv->fb0_win_id; - else if (!strcmp(id, "fb1") || !strcmp(id, "fb5")) - win_id = dev_drv->fb1_win_id; - else if (!strcmp(id, "fb2") || !strcmp(id, "fb6")) - win_id = dev_drv->fb2_win_id; - else if (!strcmp(id, "fb3") || !strcmp(id, "fb7")) - win_id = dev_drv->fb3_win_id; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return win_id; -} - -static int rk3288_set_dsp_lut(struct rk_lcdc_driver *dev_drv, int *lut) -{ - int i,j; - int __iomem *c; - int v, r, g, b; - int ret = 0; - - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0)); - lcdc_cfg_done(lcdc_dev); - mdelay(25); - if (dev_drv->cur_screen->dsp_lut) { - for (i = 0; i < 256; i++) { - v = dev_drv->cur_screen->dsp_lut[i] = lut[i]; - c = lcdc_dev->dsp_lut_addr_base + (i << 2); - b = (v & 0xff) << 2; - g = (v & 0xff00) << 4; - r = (v & 0xff0000) << 6; - v = r + g + b; - for (j = 0; j < 4; j++) { - writel_relaxed(v, c); - v += (1 + (1 << 10) + (1 << 20)) ; - c++; - } - } - } else { - dev_err(dev_drv->dev, "no buffer to backup lut data!\n"); - ret = -1; - } - - do{ - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1)); - lcdc_cfg_done(lcdc_dev); - }while(!lcdc_read_bit(lcdc_dev,DSP_CTRL1,m_DSP_LUT_EN)); - return ret; -} - -static int rk3288_lcdc_config_done(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int i; - unsigned int mask, val; - struct rk_lcdc_win *win = NULL; - struct fb_info *fb0 = rk_get_fb(0); - - spin_lock(&lcdc_dev->reg_lock); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, - v_STANDBY_EN(lcdc_dev->standby)); - for (i=0;i<4;i++) { - win = dev_drv->win[i]; - if ((win->state == 0)&&(win->last_state == 1)) { - switch (win->id) { - case 0: - if (dev_drv->version == VOP_FULL_RK3288_V1_0) - lcdc_writel(lcdc_dev, WIN0_CTRL1, 0x0); - mask = m_WIN0_EN; - val = v_WIN0_EN(0); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask,val); - break; - case 1: - if (dev_drv->version == VOP_FULL_RK3288_V1_0) - lcdc_writel(lcdc_dev, WIN1_CTRL1, 0x0); - mask = m_WIN1_EN; - val = v_WIN1_EN(0); - lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask,val); - break; - case 2: - mask = m_WIN2_EN | m_WIN2_MST0_EN | m_WIN2_MST1_EN | - m_WIN2_MST2_EN | m_WIN2_MST3_EN; - val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) | v_WIN2_MST1_EN(0) | - v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask,val); - lcdc_writel(lcdc_dev,WIN2_DSP_INFO0,0); - lcdc_writel(lcdc_dev,WIN2_DSP_INFO1,0); - lcdc_writel(lcdc_dev,WIN2_DSP_INFO2,0); - lcdc_writel(lcdc_dev,WIN2_DSP_INFO3,0); - lcdc_writel(lcdc_dev,WIN2_MST0, fb0->fix.smem_start); - lcdc_writel(lcdc_dev,WIN2_MST1, fb0->fix.smem_start); - lcdc_writel(lcdc_dev,WIN2_MST2, fb0->fix.smem_start); - lcdc_writel(lcdc_dev,WIN2_MST3, fb0->fix.smem_start); - break; - case 3: - mask = m_WIN3_EN | m_WIN3_MST0_EN | m_WIN3_MST1_EN | - m_WIN3_MST2_EN | m_WIN3_MST3_EN; - val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) | v_WIN3_MST1_EN(0) | - v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0); - lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask,val); - lcdc_writel(lcdc_dev,WIN3_DSP_INFO0,0); - lcdc_writel(lcdc_dev,WIN3_DSP_INFO1,0); - lcdc_writel(lcdc_dev,WIN3_DSP_INFO2,0); - lcdc_writel(lcdc_dev,WIN3_DSP_INFO3,0); - lcdc_writel(lcdc_dev,WIN3_MST0, fb0->fix.smem_start); - lcdc_writel(lcdc_dev,WIN3_MST1, fb0->fix.smem_start); - lcdc_writel(lcdc_dev,WIN3_MST2, fb0->fix.smem_start); - lcdc_writel(lcdc_dev,WIN3_MST3, fb0->fix.smem_start); - break; - default: - break; - } - } - win->last_state = win->state; - } - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - - -static int rk3288_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - spin_lock(&lcdc_dev->reg_lock); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN, - v_DIRECT_PATH_EN(open)); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk3288_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - spin_lock(&lcdc_dev->reg_lock); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL, - v_DIRECT_PATCH_SEL(win_id)); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - return 0; - -} - -static int rk3288_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int ovl; - spin_lock(&lcdc_dev->reg_lock); - ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN); - spin_unlock(&lcdc_dev->reg_lock); - return ovl; -} -static int rk3288_lcdc_set_irq_to_cpu(struct rk_lcdc_driver * dev_drv,int enable) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv,struct lcdc_device,driver); - if (enable) - enable_irq(lcdc_dev->irq); - else - disable_irq(lcdc_dev->irq); - return 0; -} - -int rk3288_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 int_reg; - int ret; - - if (lcdc_dev->clk_on &&(!dev_drv->suspend_flag)){ - int_reg = lcdc_readl(lcdc_dev, INTR_CTRL0); - if (int_reg & m_LINE_FLAG_INTR_STS) { - lcdc_dev->driver.frame_time.last_framedone_t = - lcdc_dev->driver.frame_time.framedone_t; - lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0); - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR, - v_LINE_FLAG_INTR_CLR(1)); - ret = RK_LF_STATUS_FC; - } else - ret = RK_LF_STATUS_FR; - } else { - ret = RK_LF_STATUS_NC; - } - - return ret; -} - -static int rk3288_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv, - unsigned int dsp_addr[][4]) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - dsp_addr[0][0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST); - dsp_addr[1][0] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST); - dsp_addr[2][0] = lcdc_readl(lcdc_dev, WIN2_MST0); - dsp_addr[2][1] = lcdc_readl(lcdc_dev, WIN2_MST1); - dsp_addr[2][2] = lcdc_readl(lcdc_dev, WIN2_MST2); - dsp_addr[2][3] = lcdc_readl(lcdc_dev, WIN2_MST3); - dsp_addr[3][0] = lcdc_readl(lcdc_dev, WIN3_MST0); - dsp_addr[3][1] = lcdc_readl(lcdc_dev, WIN3_MST1); - dsp_addr[3][2] = lcdc_readl(lcdc_dev, WIN3_MST2); - dsp_addr[3][3] = lcdc_readl(lcdc_dev, WIN3_MST3); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk3288_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, - int mode, int calc, int up, - int down, int global) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u32 total_pixel, calc_pixel, stage_up, stage_down; - u32 pixel_num, global_dn; - u32 mask = 0, val = 0; - - if (dev_drv->version != VOP_FULL_RK3288_V1_1) { - pr_err("vop version:%x, not supoort cabc\n", dev_drv->version); - return 0; - } - if (!screen->cabc_lut) { - pr_err("screen cabc lut not config, so not open cabc\n"); - return 0; - } - dev_drv->cabc_mode = mode; - if (!dev_drv->cabc_mode) { - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - lcdc_msk_reg(lcdc_dev, CABC_CTRL0, - m_CABC_HANDLE_EN | m_CABC_EN, - v_CABC_EN(0) | v_CABC_HANDLE_EN(0)); - lcdc_cfg_done(lcdc_dev); - } - pr_info("mode = 0, close cabc\n"); - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - - total_pixel = screen->mode.xres * screen->mode.yres; - pixel_num = 1000 - calc; - calc_pixel = (total_pixel * pixel_num) / 1000; - stage_up = up; - stage_down = down; - global_dn = global; - pr_info("enable cabc:mode=%d, calc=%d, up=%d, down=%d, global=%d\n", - mode, calc, stage_up, stage_down, global_dn); - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - mask = m_CABC_EN | m_CABC_HANDLE_EN | m_PWM_CONFIG_MODE | - m_CABC_CALC_PIXEL_NUM; - val = v_CABC_EN(1) | v_CABC_HANDLE_EN(1) | - v_PWM_CONFIG_MODE(STAGE_BY_STAGE) | - v_CABC_CALC_PIXEL_NUM(calc_pixel); - lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val); - - mask = m_CABC_LUT_EN | m_CABC_TOTAL_PIXEL_NUM; - val = v_CABC_LUT_EN(1) | v_CABC_TOTAL_PIXEL_NUM(total_pixel); - lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val); - - mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_UP | - m_CABC_STAGE_MODE | m_MAX_SCALE_CFG_VALUE | - m_MAX_SCALE_CFG_ENABLE; - val = v_CABC_STAGE_DOWN(stage_down) | - v_CABC_STAGE_UP(stage_up) | - v_CABC_STAGE_MODE(0) | v_MAX_SCALE_CFG_VALUE(1) | - v_MAX_SCALE_CFG_ENABLE(0); - lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val); - - mask = m_CABC_GLOBAL_DN | m_CABC_GLOBAL_DN_LIMIT_EN; - val = v_CABC_GLOBAL_DN(global_dn) | - v_CABC_GLOBAL_DN_LIMIT_EN(1); - lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -/* - a:[-30~0]: - sin_hue = sin(a)*256 +0x100; - cos_hue = cos(a)*256; - a:[0~30] - sin_hue = sin(a)*256; - cos_hue = cos(a)*256; -*/ -static int rk3288_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode) -{ - - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 val; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - val = lcdc_readl(lcdc_dev, BCSH_H); - switch(mode){ - case H_SIN: - val &= m_BCSH_SIN_HUE; - break; - case H_COS: - val &= m_BCSH_COS_HUE; - val >>= 16; - break; - default: - break; - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return val; -} - - -static int rk3288_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue) -{ - - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE; - val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue); - lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int rk3288_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) { - switch (mode) { - case BRIGHTNESS: - /*from 0 to 255,typical is 128*/ - if (value < 0x80) - value += 0x80; - else if (value >= 0x80) - value = value - 0x80; - mask = m_BCSH_BRIGHTNESS; - val = v_BCSH_BRIGHTNESS(value); - break; - case CONTRAST: - /*from 0 to 510,typical is 256*/ - mask = m_BCSH_CONTRAST; - val = v_BCSH_CONTRAST(value); - break; - case SAT_CON: - /*from 0 to 1015,typical is 256*/ - mask = m_BCSH_SAT_CON; - val = v_BCSH_SAT_CON(value); - break; - default: - break; - } - lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - return val; -} - -static int rk3288_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 val; - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) { - val = lcdc_readl(lcdc_dev, BCSH_BCS); - switch (mode) { - case BRIGHTNESS: - val &= m_BCSH_BRIGHTNESS; - if(val > 0x80) - val -= 0x80; - else - val += 0x80; - break; - case CONTRAST: - val &= m_BCSH_CONTRAST; - val >>= 8; - break; - case SAT_CON: - val &= m_BCSH_SAT_CON; - val >>= 20; - break; - default: - break; - } - } - spin_unlock(&lcdc_dev->reg_lock); - return val; -} - - -static int rk3288_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - if (open) { - lcdc_writel(lcdc_dev,BCSH_COLOR_BAR,0x1); - lcdc_writel(lcdc_dev,BCSH_BCS,0xd0010000); - lcdc_writel(lcdc_dev,BCSH_H,0x01000000); - dev_drv->bcsh.enable = 1; - } else { - mask = m_BCSH_EN; - val = v_BCSH_EN(0); - lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val); - dev_drv->bcsh.enable = 0; - } - if (dev_drv->version == VOP_FULL_RK3288_V1_1) - rk3288_lcdc_bcsh_path_sel(dev_drv); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk3288_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, - bool enable) -{ - if (!enable || !dev_drv->bcsh.enable) { - rk3288_lcdc_open_bcsh(dev_drv, false); - return 0; - } - - if (dev_drv->bcsh.brightness <= 255 || - dev_drv->bcsh.contrast <= 510 || - dev_drv->bcsh.sat_con <= 1015 || - (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) { - rk3288_lcdc_open_bcsh(dev_drv, true); - if (dev_drv->bcsh.brightness <= 255) - rk3288_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS, - dev_drv->bcsh.brightness); - if (dev_drv->bcsh.contrast <= 510) - rk3288_lcdc_set_bcsh_bcs(dev_drv, CONTRAST, - dev_drv->bcsh.contrast); - if (dev_drv->bcsh.sat_con <= 1015) - rk3288_lcdc_set_bcsh_bcs(dev_drv, SAT_CON, - dev_drv->bcsh.sat_con); - if (dev_drv->bcsh.sin_hue <= 511 && - dev_drv->bcsh.cos_hue <= 511) - rk3288_lcdc_set_bcsh_hue(dev_drv, - dev_drv->bcsh.sin_hue, - dev_drv->bcsh.cos_hue); - } - return 0; -} - -static int rk3288_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv, - struct overscan *overscan) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if (unlikely(!lcdc_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on); - return 0; - } - rk3288_lcdc_post_cfg(dev_drv); - - return 0; -} - -static struct rk_lcdc_win lcdc_win[] = { - [0] = { - .name = "win0", - .id = 0, - .support_3d = false, - }, - [1] = { - .name = "win1", - .id = 1, - .support_3d = false, - }, - [2] = { - .name = "win2", - .id = 2, - .support_3d = false, - }, - [3] = { - .name = "win3", - .id = 3, - .support_3d = false, - }, -}; - -static int rk3288_lcdc_extern_func(struct rk_lcdc_driver *dev_drv, int cmd) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask, val; - - if (unlikely(!vop_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on); - return 0; - } - - switch (cmd) { - case SET_DSP_MIRROR: - mask = m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN; - val = v_DSP_X_MIR_EN(screen->x_mirror) | - v_DSP_Y_MIR_EN(screen->y_mirror); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - pr_info("%s: xmirror: %d, ymirror: %d\n", - __func__, dev_drv->cur_screen->x_mirror, - dev_drv->cur_screen->y_mirror); - break; - default: - break; - } - - return 0; -} - -static struct rk_lcdc_drv_ops lcdc_drv_ops = { - .open = rk3288_lcdc_open, - .win_direct_en = rk3288_lcdc_win_direct_en, - .load_screen = rk3288_load_screen, - .get_dspbuf_info = rk3288_get_dspbuf_info, - .post_dspbuf = rk3288_post_dspbuf, - .set_par = rk3288_lcdc_set_par, - .pan_display = rk3288_lcdc_pan_display, - .direct_set_addr = rk3288_lcdc_direct_set_win_addr, - .lcdc_reg_update = rk3288_lcdc_reg_update, - .blank = rk3288_lcdc_blank, - .ioctl = rk3288_lcdc_ioctl, - .suspend = rk3288_lcdc_early_suspend, - .resume = rk3288_lcdc_early_resume, - .get_win_state = rk3288_lcdc_get_win_state, - .area_support_num = rk3288_lcdc_get_area_num, - .ovl_mgr = rk3288_lcdc_ovl_mgr, - .get_disp_info = rk3288_lcdc_get_disp_info, - .fps_mgr = rk3288_lcdc_fps_mgr, - .fb_get_win_id = rk3288_lcdc_get_win_id, - .fb_win_remap = rk3288_fb_win_remap, - .set_dsp_lut = rk3288_set_dsp_lut, - .poll_vblank = rk3288_lcdc_poll_vblank, - .dpi_open = rk3288_lcdc_dpi_open, - .dpi_win_sel = rk3288_lcdc_dpi_win_sel, - .dpi_status = rk3288_lcdc_dpi_status, - .get_dsp_addr = rk3288_lcdc_get_dsp_addr, - .set_dsp_cabc = rk3288_lcdc_set_dsp_cabc, - .set_dsp_bcsh_hue = rk3288_lcdc_set_bcsh_hue, - .set_dsp_bcsh_bcs = rk3288_lcdc_set_bcsh_bcs, - .get_dsp_bcsh_hue = rk3288_lcdc_get_bcsh_hue, - .get_dsp_bcsh_bcs = rk3288_lcdc_get_bcsh_bcs, - .open_bcsh = rk3288_lcdc_open_bcsh, - .dump_reg = rk3288_lcdc_reg_dump, - .cfg_done = rk3288_lcdc_config_done, - .set_irq_to_cpu = rk3288_lcdc_set_irq_to_cpu, - .mmu_en = rk3288_lcdc_mmu_en, - .set_overscan = rk3288_lcdc_set_overscan, - -}; - -#ifdef LCDC_IRQ_DEBUG -static int rk3288_lcdc_parse_irq(struct lcdc_device *lcdc_dev,unsigned int reg_val) -{ - if (reg_val & m_WIN0_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN0_EMPTY_INTR_CLR, - v_WIN0_EMPTY_INTR_CLR(1)); - dev_warn(lcdc_dev->dev,"win0 empty irq!"); - }else if (reg_val & m_WIN1_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN1_EMPTY_INTR_CLR, - v_WIN1_EMPTY_INTR_CLR(1)); - dev_warn(lcdc_dev->dev,"win1 empty irq!"); - }else if (reg_val & m_WIN2_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN2_EMPTY_INTR_CLR, - v_WIN2_EMPTY_INTR_CLR(1)); - dev_warn(lcdc_dev->dev,"win2 empty irq!"); - }else if (reg_val & m_WIN3_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN3_EMPTY_INTR_CLR, - v_WIN3_EMPTY_INTR_CLR(1)); - dev_warn(lcdc_dev->dev,"win3 empty irq!"); - }else if (reg_val & m_HWC_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_HWC_EMPTY_INTR_CLR, - v_HWC_EMPTY_INTR_CLR(1)); - dev_warn(lcdc_dev->dev,"HWC empty irq!"); - }else if (reg_val & m_POST_BUF_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_POST_BUF_EMPTY_INTR_CLR, - v_POST_BUF_EMPTY_INTR_CLR(1)); - dev_warn(lcdc_dev->dev,"post buf empty irq!"); - }else if (reg_val & m_PWM_GEN_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_PWM_GEN_INTR_CLR, - v_PWM_GEN_INTR_CLR(1)); - dev_warn(lcdc_dev->dev,"PWM gen irq!"); - } - - return 0; -} -#endif - -static irqreturn_t rk3288_lcdc_isr(int irq, void *dev_id) -{ - struct lcdc_device *lcdc_dev = - (struct lcdc_device *)dev_id; - ktime_t timestamp = ktime_get(); - u32 intr0_reg; - - intr0_reg = lcdc_readl(lcdc_dev, INTR_CTRL0); - - if(intr0_reg & m_FS_INTR_STS){ - timestamp = ktime_get(); - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_FS_INTR_CLR, - v_FS_INTR_CLR(1)); - /*if(lcdc_dev->driver.wait_fs){ */ - if (0) { - spin_lock(&(lcdc_dev->driver.cpl_lock)); - complete(&(lcdc_dev->driver.frame_done)); - spin_unlock(&(lcdc_dev->driver.cpl_lock)); - } - lcdc_dev->driver.vsync_info.timestamp = timestamp; - wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait); - - }else if(intr0_reg & m_LINE_FLAG_INTR_STS){ - lcdc_dev->driver.frame_time.last_framedone_t = - lcdc_dev->driver.frame_time.framedone_t; - lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0); - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR, - v_LINE_FLAG_INTR_CLR(1)); - }else if(intr0_reg & m_BUS_ERROR_INTR_STS){ - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_BUS_ERROR_INTR_CLR, - v_BUS_ERROR_INTR_CLR(1)); - dev_warn(lcdc_dev->dev,"buf_error_int!"); - } - - /* for win empty debug */ -#ifdef LCDC_IRQ_EMPTY_DEBUG - intr1_reg = lcdc_readl(lcdc_dev, INTR_CTRL1); - if (intr1_reg != 0) { - rk3288_lcdc_parse_irq(lcdc_dev,intr1_reg); - } -#endif - return IRQ_HANDLED; -} - -#if defined(CONFIG_PM) -static int rk3288_lcdc_suspend(struct platform_device *pdev, pm_message_t state) -{ - return 0; -} - -static int rk3288_lcdc_resume(struct platform_device *pdev) -{ - return 0; -} -#else -#define rk3288_lcdc_suspend NULL -#define rk3288_lcdc_resume NULL -#endif - -static int rk3288_lcdc_parse_dt(struct lcdc_device *lcdc_dev) -{ - struct device_node *np = lcdc_dev->dev->of_node; - struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver; - int val; - - if (of_property_read_u32(np, "rockchip,prop", &val)) - lcdc_dev->prop = PRMRY; /*default set it as primary */ - else - lcdc_dev->prop = val; - - if (of_property_read_u32(np, "rockchip,mirror", &val)) - dev_drv->rotate_mode = NO_MIRROR; - else - dev_drv->rotate_mode = val; - - if (of_property_read_u32(np, "rockchip,cabc_mode", &val)) - dev_drv->cabc_mode = 0; /* default set close cabc */ - else - dev_drv->cabc_mode = val; - - if (of_property_read_u32(np, "rockchip,pwr18", &val)) - lcdc_dev->pwr18 = false; /*default set it as 3.xv power supply */ - else - lcdc_dev->pwr18 = (val ? true : false); - - if (of_property_read_u32(np, "rockchip,fb-win-map", &val)) - dev_drv->fb_win_map = FB_DEFAULT_ORDER; - else - dev_drv->fb_win_map = val; - - if (of_property_read_u32(np, "rockchip,bcsh-en", &val)) - dev_drv->bcsh.enable = false; - else - dev_drv->bcsh.enable = (val ? true : false); - - if (of_property_read_u32(np, "rockchip,brightness", &val)) - dev_drv->bcsh.brightness = 0xffff; - else - dev_drv->bcsh.brightness = val; - - if (of_property_read_u32(np, "rockchip,contrast", &val)) - dev_drv->bcsh.contrast = 0xffff; - else - dev_drv->bcsh.contrast = val; - - if (of_property_read_u32(np, "rockchip,sat-con", &val)) - dev_drv->bcsh.sat_con = 0xffff; - else - dev_drv->bcsh.sat_con = val; - - if (of_property_read_u32(np, "rockchip,hue", &val)) { - dev_drv->bcsh.sin_hue = 0xffff; - dev_drv->bcsh.cos_hue = 0xffff; - } else { - dev_drv->bcsh.sin_hue = val & 0xff; - dev_drv->bcsh.cos_hue = (val >> 8) & 0xff; - } - - if (of_property_read_u32(np, "rockchip,iommu-enabled", &val)) - dev_drv->iommu_enabled = 0; - else - dev_drv->iommu_enabled = val; - - if (of_property_read_u32(np, "rockchip,dsp_mode", &val)) - dev_drv->dsp_mode = DEFAULT_MODE; - else - dev_drv->dsp_mode = val; - - return 0; -} - -static int rk3288_lcdc_probe(struct platform_device *pdev) -{ - struct lcdc_device *lcdc_dev = NULL; - struct rk_lcdc_driver *dev_drv; - struct device *dev = &pdev->dev; - struct resource *res; - struct device_node *np = pdev->dev.of_node; - int prop; - int ret = 0; - - /*if the primary lcdc has not registered ,the extend - lcdc register later */ - of_property_read_u32(np, "rockchip,prop", &prop); - if (prop == EXTEND) { - if (!is_prmry_rk_lcdc_registered()) - return -EPROBE_DEFER; - } - lcdc_dev = devm_kzalloc(dev, - sizeof(struct lcdc_device), GFP_KERNEL); - if (!lcdc_dev) { - dev_err(&pdev->dev, "rk3288 lcdc device kmalloc fail!"); - return -ENOMEM; - } - platform_set_drvdata(pdev, lcdc_dev); - lcdc_dev->dev = dev; - rk3288_lcdc_parse_dt(lcdc_dev); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - lcdc_dev->reg_phy_base = res->start; - lcdc_dev->len = resource_size(res); - lcdc_dev->regs = devm_ioremap_resource(dev, res); - if (IS_ERR(lcdc_dev->regs)) - return PTR_ERR(lcdc_dev->regs); - - lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL); - if (IS_ERR(lcdc_dev->regsbak)) - return PTR_ERR(lcdc_dev->regsbak); - lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR); - lcdc_dev->id = rk3288_lcdc_get_id(lcdc_dev->reg_phy_base); - if (lcdc_dev->id < 0) { - dev_err(&pdev->dev, "no such lcdc device!\n"); - return -ENXIO; - } - dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id); - dev_drv = &lcdc_dev->driver; - dev_drv->dev = dev; - dev_drv->prop = prop; - dev_drv->id = lcdc_dev->id; - dev_drv->ops = &lcdc_drv_ops; - dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win); - spin_lock_init(&lcdc_dev->reg_lock); - - lcdc_dev->irq = platform_get_irq(pdev, 0); - if (lcdc_dev->irq < 0) { - dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n", - lcdc_dev->id); - return -ENXIO; - } - - ret = devm_request_irq(dev, lcdc_dev->irq, rk3288_lcdc_isr, - IRQF_DISABLED | IRQF_SHARED, dev_name(dev), lcdc_dev); - if (ret) { - dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", - lcdc_dev->irq, ret); - return ret; - } - - if (dev_drv->iommu_enabled) { - if(lcdc_dev->id == 0){ - strcpy(dev_drv->mmu_dts_name, VOPB_IOMMU_COMPATIBLE_NAME); - }else{ - strcpy(dev_drv->mmu_dts_name, VOPL_IOMMU_COMPATIBLE_NAME); - } - } - - ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id); - if (ret < 0) { - dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id); - return ret; - } - lcdc_dev->screen = dev_drv->screen0; - dev_info(dev, "lcdc%d probe ok, iommu %s\n", - lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled"); - - return 0; -} - -static int rk3288_lcdc_remove(struct platform_device *pdev) -{ - - return 0; -} - -static void rk3288_lcdc_shutdown(struct platform_device *pdev) -{ - struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - - rk3288_lcdc_deint(lcdc_dev); - rk_disp_pwr_disable(&lcdc_dev->driver); -} - -#if defined(CONFIG_OF) -static const struct of_device_id rk3288_lcdc_dt_ids[] = { - {.compatible = "rockchip,rk3288-lcdc",}, - {} -}; -#endif - -static struct platform_driver rk3288_lcdc_driver = { - .probe = rk3288_lcdc_probe, - .remove = rk3288_lcdc_remove, - .driver = { - .name = "rk3288-lcdc", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(rk3288_lcdc_dt_ids), - }, - .suspend = rk3288_lcdc_suspend, - .resume = rk3288_lcdc_resume, - .shutdown = rk3288_lcdc_shutdown, -}; - -static int __init rk3288_lcdc_module_init(void) -{ - return platform_driver_register(&rk3288_lcdc_driver); -} - -static void __exit rk3288_lcdc_module_exit(void) -{ - platform_driver_unregister(&rk3288_lcdc_driver); -} - -fs_initcall(rk3288_lcdc_module_init); -module_exit(rk3288_lcdc_module_exit); - - diff --git a/drivers/video/rockchip/lcdc/rk3288_lcdc.h b/drivers/video/rockchip/lcdc/rk3288_lcdc.h deleted file mode 100644 index 77218d2a6610..000000000000 --- a/drivers/video/rockchip/lcdc/rk3288_lcdc.h +++ /dev/null @@ -1,1474 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef RK3288_LCDC_H_ -#define RK3288_LCDC_H_ - -#include -#include -#include - - -/*******************register definition**********************/ - -#define REG_CFG_DONE (0x0000) -#define VERSION_INFO (0x0004) -#define m_RTL_VERSION (0xffff<<0) -#define m_FPGA_VERSION (0xffff<<16) -#define VOP_FULL_RK3288_V1_0 0x03007236 -#define VOP_FULL_RK3288_V1_1 0x0a050a01 -#define SYS_CTRL (0x0008) -#define v_DIRECT_PATH_EN(x) (((x)&1)<<0) -#define v_DIRECT_PATCH_SEL(x) (((x)&3)<<1) -#define v_DOUB_CHANNEL_EN(x) (((x)&1)<<3) -#define v_DOUB_CH_OVERLAP_NUM(x) (((x)&0xf)<<4) -#define v_EDPI_HALT_EN(x) (((x)&1)<<8) -#define v_EDPI_WMS_MODE(x) (((x)&1)<<9) -#define v_EDPI_WMS_FS(x) (((x)&1)<<10) -#define v_HDMI_DCLK_OUT_EN(x) (((x)&1)<<11) -#define v_RGB_OUT_EN(x) (((x)&1)<<12) -#define v_HDMI_OUT_EN(x) (((x)&1)<<13) -#define v_EDP_OUT_EN(x) (((x)&1)<<14) -#define v_MIPI_OUT_EN(x) (((x)&1)<<15) -#define v_DMA_BURST_LENGTH(x) (((x)&3)<<18) -#define v_MMU_EN(x) (((x)&1)<<20) -#define v_DMA_STOP(x) (((x)&1)<<21) -#define v_STANDBY_EN(x) (((x)&1)<<22) -#define v_AUTO_GATING_EN(x) (((x)&1)<<23) - -#define m_DIRECT_PATH_EN (1<<0) -#define m_DIRECT_PATCH_SEL (3<<1) -#define m_DOUB_CHANNEL_EN (1<<3) -#define m_DOUB_CH_OVERLAP_NUM (0xf<<4) -#define m_EDPI_HALT_EN (1<<8) -#define m_EDPI_WMS_MODE (1<<9) -#define m_EDPI_WMS_FS (1<<10) -#define m_HDMI_DCLK_OUT_EN (1<<11) -#define m_RGB_OUT_EN (1<<12) -#define m_HDMI_OUT_EN (1<<13) -#define m_EDP_OUT_EN (1<<14) -#define m_MIPI_OUT_EN (1<<15) -#define m_DMA_BURST_LENGTH (3<<18) -#define m_MMU_EN (1<<20) -#define m_DMA_STOP (1<<21) -#define m_STANDBY_EN (1<<22) -#define m_AUTO_GATING_EN (1<<23) -#define SYS_CTRL1 (0x000c) -#define v_NOC_HURRY_EN(x) (((x)&0x1 )<<0 ) -#define v_NOC_HURRY_VALUE(x) (((x)&0x3 )<<1 ) -#define v_NOC_HURRY_THRESHOLD(x) (((x)&0x3f)<<3 ) -#define v_NOC_QOS_EN(x) (((x)&0x1 )<<9 ) -#define v_NOC_WIN_QOS(x) (((x)&0x3 )<<10) -#define v_AXI_MAX_OUTSTANDING_EN(x) (((x)&0x1 )<<12) -#define v_AXI_OUTSTANDING_MAX_NUM(x) (((x)&0x1f)<<13) - -#define m_NOC_HURRY_EN (0x1 <<0 ) -#define m_NOC_HURRY_VALUE (0x3 <<1 ) -#define m_NOC_HURRY_THRESHOLD (0x3f<<3 ) -#define m_NOC_QOS_EN (0x1 <<9 ) -#define m_NOC_WIN_QOS (0x3 <<10) -#define m_AXI_MAX_OUTSTANDING_EN (0x1 <<12) -#define m_AXI_OUTSTANDING_MAX_NUM (0x1f<<13) - -#define DSP_CTRL0 (0x0010) -#define v_DSP_OUT_MODE(x) (((x)&0x0f)<<0) -#define v_DSP_HSYNC_POL(x) (((x)&1)<<4) -#define v_DSP_VSYNC_POL(x) (((x)&1)<<5) -#define v_DSP_DEN_POL(x) (((x)&1)<<6) -#define v_DSP_DCLK_POL(x) (((x)&1)<<7) -#define v_DSP_DCLK_DDR(x) (((x)&1)<<8) -#define v_DSP_DDR_PHASE(x) (((x)&1)<<9) -#define v_DSP_INTERLACE(x) (((x)&1)<<10) -#define v_DSP_FIELD_POL(x) (((x)&1)<<11) -#define v_DSP_BG_SWAP(x) (((x)&1)<<12) -#define v_DSP_RB_SWAP(x) (((x)&1)<<13) -#define v_DSP_RG_SWAP(x) (((x)&1)<<14) -#define v_DSP_DELTA_SWAP(x) (((x)&1)<<15) -#define v_DSP_DUMMY_SWAP(x) (((x)&1)<<16) -#define v_DSP_OUT_ZERO(x) (((x)&1)<<17) -#define v_DSP_BLANK_EN(x) (((x)&1)<<18) -#define v_DSP_BLACK_EN(x) (((x)&1)<<19) -#define v_DSP_CCIR656_AVG(x) (((x)&1)<<20) -#define v_DSP_YUV_CLIP(x) (((x)&1)<<21) -#define v_DSP_X_MIR_EN(x) (((x)&1)<<22) -#define v_DSP_Y_MIR_EN(x) (((x)&1)<<23) -#define m_DSP_OUT_MODE (0x0f<<0) -#define m_DSP_HSYNC_POL (1<<4) -#define m_DSP_VSYNC_POL (1<<5) -#define m_DSP_DEN_POL (1<<6) -#define m_DSP_DCLK_POL (1<<7) -#define m_DSP_DCLK_DDR (1<<8) -#define m_DSP_DDR_PHASE (1<<9) -#define m_DSP_INTERLACE (1<<10) -#define m_DSP_FIELD_POL (1<<11) -#define m_DSP_BG_SWAP (1<<12) -#define m_DSP_RB_SWAP (1<<13) -#define m_DSP_RG_SWAP (1<<14) -#define m_DSP_DELTA_SWAP (1<<15) -#define m_DSP_DUMMY_SWAP (1<<16) -#define m_DSP_OUT_ZERO (1<<17) -#define m_DSP_BLANK_EN (1<<18) -#define m_DSP_BLACK_EN (1<<19) -#define m_DSP_CCIR656_AVG (1<<20) -#define m_DSP_YUV_CLIP (1<<21) -#define m_DSP_X_MIR_EN (1<<22) -#define m_DSP_Y_MIR_EN (1<<23) - -#define DSP_CTRL1 (0x0014) -#define v_DSP_LUT_EN(x) (((x)&1)<<0) -#define v_PRE_DITHER_DOWN_EN(x) (((x)&1)<<1) -#define v_DITHER_DOWN_EN(x) (((x)&1)<<2) -#define v_DITHER_DOWN_MODE(x) (((x)&1)<<3) -#define v_DITHER_DOWN_SEL(x) (((x)&1)<<4) -#define v_DITHER_UP_EN(x) (((x)&1)<<6) -#define v_DSP_LAYER0_SEL(x) (((x)&3)<<8) -#define v_DSP_LAYER1_SEL(x) (((x)&3)<<10) -#define v_DSP_LAYER2_SEL(x) (((x)&3)<<12) -#define v_DSP_LAYER3_SEL(x) (((x)&3)<<14) -#define m_DSP_LUT_EN (1<<0) -#define m_PRE_DITHER_DOWN_EN (1<<1) -#define m_DITHER_DOWN_EN (1<<2) -#define m_DITHER_DOWN_MODE (1<<3) -#define m_DITHER_DOWN_SEL (1<<4) -#define m_DITHER_UP_EN (1<<6) -#define m_DSP_LAYER0_SEL (3<<8) -#define m_DSP_LAYER1_SEL (3<<10) -#define m_DSP_LAYER2_SEL (3<<12) -#define m_DSP_LAYER3_SEL (3<<14) - -#define DSP_BG (0x0018) -#define v_DSP_BG_BLUE(x) (((x<<2)&0x3ff)<<0) -#define v_DSP_BG_GREEN(x) (((x<<2)&0x3ff)<<10) -#define v_DSP_BG_RED(x) (((x<<2)&0x3ff)<<20) -#define m_DSP_BG_BLUE (0x3ff<<0) -#define m_DSP_BG_GREEN (0x3ff<<10) -#define m_DSP_BG_RED (0x3ff<<20) - -#define MCU_CTRL (0x001c) -#define v_MCU_PIX_TOTAL(x) (((x)&0x3f)<<0) -#define v_MCU_CS_PST(x) (((x)&0xf)<<6) -#define v_MCU_CS_PEND(x) (((x)&0x3f)<<10) -#define v_MCU_RW_PST(x) (((x)&0xf)<<16) -#define v_MCU_RW_PEND(x) (((x)&0x3f)<<20) -#define v_MCU_CLK_SEL(x) (((x)&1)<<26) -#define v_MCU_HOLD_MODE(x) (((x)&1)<<27) -#define v_MCU_FRAME_ST(x) (((x)&1)<<28) -#define v_MCU_RS(x) (((x)&1)<<29) -#define v_MCU_BYPASS(x) (((x)&1)<<30) -#define v_MCU_TYPE(x) (((x)&1)<<31) -#define m_MCU_PIX_TOTAL (0x3f<<0) -#define m_MCU_CS_PST (0xf<<6) -#define m_MCU_CS_PEND (0x3f<<10) -#define m_MCU_RW_PST (0xf<<16) -#define m_MCU_RW_PEND (0x3f<<20) -#define m_MCU_CLK_SEL (1<<26) -#define m_MCU_HOLD_MODE (1<<27) -#define m_MCU_FRAME_ST (1<<28) -#define m_MCU_RS (1<<29) -#define m_MCU_BYPASS (1<<30) -#define m_MCU_TYPE ((u32)1<<31) - -#define INTR_CTRL0 (0x0020) -#define v_DSP_HOLD_VALID_INTR_STS(x) (((x)&1)<<0) -#define v_FS_INTR_STS(x) (((x)&1)<<1) -#define v_LINE_FLAG_INTR_STS(x) (((x)&1)<<2) -#define v_BUS_ERROR_INTR_STS(x) (((x)&1)<<3) -#define v_DSP_HOLD_VALID_INTR_EN(x) (((x)&1)<<4) -#define v_FS_INTR_EN(x) (((x)&1)<<5) -#define v_LINE_FLAG_INTR_EN(x) (((x)&1)<<6) -#define v_BUS_ERROR_INTR_EN(x) (((x)&1)<<7) -#define v_DSP_HOLD_VALID_INTR_CLR(x) (((x)&1)<<8) -#define v_FS_INTR_CLR(x) (((x)&1)<<9) -#define v_LINE_FLAG_INTR_CLR(x) (((x)&1)<<10) -#define v_BUS_ERROR_INTR_CLR(x) (((x)&1)<<11) -#define v_DSP_LINE_FLAG_NUM(x) (((x)&0xfff)<<12) - -#define m_DSP_HOLD_VALID_INTR_STS (1<<0) -#define m_FS_INTR_STS (1<<1) -#define m_LINE_FLAG_INTR_STS (1<<2) -#define m_BUS_ERROR_INTR_STS (1<<3) -#define m_DSP_HOLD_VALID_INTR_EN (1<<4) -#define m_FS_INTR_EN (1<<5) -#define m_LINE_FLAG_INTR_EN (1<<6) -#define m_BUS_ERROR_INTR_EN (1<<7) -#define m_DSP_HOLD_VALID_INTR_CLR (1<<8) -#define m_FS_INTR_CLR (1<<9) -#define m_LINE_FLAG_INTR_CLR (1<<10) -#define m_BUS_ERROR_INTR_CLR (1<<11) -#define m_DSP_LINE_FLAG_NUM (0xfff<<12) - -#define INTR_CTRL1 (0x0024) -#define v_WIN0_EMPTY_INTR_STS(x) (((x)&1)<<0) -#define v_WIN1_EMPTY_INTR_STS(x) (((x)&1)<<1) -#define v_WIN2_EMPTY_INTR_STS(x) (((x)&1)<<2) -#define v_WIN3_EMPTY_INTR_STS(x) (((x)&1)<<3) -#define v_HWC_EMPTY_INTR_STS(x) (((x)&1)<<4) -#define v_POST_BUF_EMPTY_INTR_STS(x) (((x)&1)<<5) -#define v_PWM_GEN_INTR_STS(x) (((x)&1)<<6) -#define v_WIN0_EMPTY_INTR_EN(x) (((x)&1)<<8) -#define v_WIN1_EMPTY_INTR_EN(x) (((x)&1)<<9) -#define v_WIN2_EMPTY_INTR_EN(x) (((x)&1)<<10) -#define v_WIN3_EMPTY_INTR_EN(x) (((x)&1)<<11) -#define v_HWC_EMPTY_INTR_EN(x) (((x)&1)<<12) -#define v_POST_BUF_EMPTY_INTR_EN(x) (((x)&1)<<13) -#define v_PWM_GEN_INTR_EN(x) (((x)&1)<<14) -#define v_WIN0_EMPTY_INTR_CLR(x) (((x)&1)<<16) -#define v_WIN1_EMPTY_INTR_CLR(x) (((x)&1)<<17) -#define v_WIN2_EMPTY_INTR_CLR(x) (((x)&1)<<18) -#define v_WIN3_EMPTY_INTR_CLR(x) (((x)&1)<<19) -#define v_HWC_EMPTY_INTR_CLR(x) (((x)&1)<<20) -#define v_POST_BUF_EMPTY_INTR_CLR(x) (((x)&1)<<21) -#define v_PWM_GEN_INTR_CLR(x) (((x)&1)<<22) - -#define m_WIN0_EMPTY_INTR_STS (1<<0) -#define m_WIN1_EMPTY_INTR_STS (1<<1) -#define m_WIN2_EMPTY_INTR_STS (1<<2) -#define m_WIN3_EMPTY_INTR_STS (1<<3) -#define m_HWC_EMPTY_INTR_STS (1<<4) -#define m_POST_BUF_EMPTY_INTR_STS (1<<5) -#define m_PWM_GEN_INTR_STS (1<<6) -#define m_WIN0_EMPTY_INTR_EN (1<<8) -#define m_WIN1_EMPTY_INTR_EN (1<<9) -#define m_WIN2_EMPTY_INTR_EN (1<<10) -#define m_WIN3_EMPTY_INTR_EN (1<<11) -#define m_HWC_EMPTY_INTR_EN (1<<12) -#define m_POST_BUF_EMPTY_INTR_EN (1<<13) -#define m_PWM_GEN_INTR_EN (1<<14) -#define m_WIN0_EMPTY_INTR_CLR (1<<16) -#define m_WIN1_EMPTY_INTR_CLR (1<<17) -#define m_WIN2_EMPTY_INTR_CLR (1<<18) -#define m_WIN3_EMPTY_INTR_CLR (1<<19) -#define m_HWC_EMPTY_INTR_CLR (1<<20) -#define m_POST_BUF_EMPTY_INTR_CLR (1<<21) -#define m_PWM_GEN_INTR_CLR (1<<22) - -/*win0 register*/ -#define WIN0_CTRL0 (0x0030) -#define v_WIN0_EN(x) (((x)&1)<<0) -#define v_WIN0_DATA_FMT(x) (((x)&7)<<1) -#define v_WIN0_FMT_10(x) (((x)&1)<<4) -#define v_WIN0_LB_MODE(x) (((x)&7)<<5) -#define v_WIN0_INTERLACE_READ(x) (((x)&1)<<8) -#define v_WIN0_NO_OUTSTANDING(x) (((x)&1)<<9) -#define v_WIN0_CSC_MODE(x) (((x)&3)<<10) -#define v_WIN0_RB_SWAP(x) (((x)&1)<<12) -#define v_WIN0_ALPHA_SWAP(x) (((x)&1)<<13) -#define v_WIN0_MID_SWAP(x) (((x)&1)<<14) -#define v_WIN0_UV_SWAP(x) (((x)&1)<<15) -#define v_WIN0_PPAS_ZERO_EN(x) (((x)&1)<<16) -#define v_WIN0_YRGB_DEFLICK(x) (((x)&1)<<18) -#define v_WIN0_CBR_DEFLICK(x) (((x)&1)<<19) -#define v_WIN0_YUV_CLIP(x) (((x)&1)<<20) - -#define m_WIN0_EN (1<<0) -#define m_WIN0_DATA_FMT (7<<1) -#define m_WIN0_FMT_10 (1<<4) -#define m_WIN0_LB_MODE (7<<5) -#define m_WIN0_INTERLACE_READ (1<<8) -#define m_WIN0_NO_OUTSTANDING (1<<9) -#define m_WIN0_CSC_MODE (3<<10) -#define m_WIN0_RB_SWAP (1<<12) -#define m_WIN0_ALPHA_SWAP (1<<13) -#define m_WIN0_MID_SWAP (1<<14) -#define m_WIN0_UV_SWAP (1<<15) -#define m_WIN0_PPAS_ZERO_EN (1<<16) -#define m_WIN0_YRGB_DEFLICK (1<<18) -#define m_WIN0_CBR_DEFLICK (1<<19) -#define m_WIN0_YUV_CLIP (1<<20) - -#define WIN0_CTRL1 (0x0034) -#define v_WIN0_YRGB_AXI_GATHER_EN(x) (((x)&1)<<0) -#define v_WIN0_CBR_AXI_GATHER_EN(x) (((x)&1)<<1) -#define v_WIN0_BIC_COE_SEL(x) (((x)&3)<<2) -#define v_WIN0_VSD_YRGB_GT4(x) (((x)&1)<<4) -#define v_WIN0_VSD_YRGB_GT2(x) (((x)&1)<<5) -#define v_WIN0_VSD_CBR_GT4(x) (((x)&1)<<6) -#define v_WIN0_VSD_CBR_GT2(x) (((x)&1)<<7) -#define v_WIN0_YRGB_AXI_GATHER_NUM(x) (((x)&0xf)<<8) -#define v_WIN0_CBR_AXI_GATHER_NUM(x) (((x)&7)<<12) -#define v_WIN0_LINE_LOAD_MODE(x) (((x)&1)<<15) -#define v_WIN0_YRGB_HOR_SCL_MODE(x) (((x)&3)<<16) -#define v_WIN0_YRGB_VER_SCL_MODE(x) (((x)&3)<<18) -#define v_WIN0_YRGB_HSD_MODE(x) (((x)&3)<<20) -#define v_WIN0_YRGB_VSU_MODE(x) (((x)&1)<<22) -#define v_WIN0_YRGB_VSD_MODE(x) (((x)&1)<<23) -#define v_WIN0_CBR_HOR_SCL_MODE(x) (((x)&3)<<24) -#define v_WIN0_CBR_VER_SCL_MODE(x) (((x)&3)<<26) -#define v_WIN0_CBR_HSD_MODE(x) (((x)&3)<<28) -#define v_WIN0_CBR_VSU_MODE(x) (((x)&1)<<30) -#define v_WIN0_CBR_VSD_MODE(x) (((x)&1)<<31) - -#define m_WIN0_YRGB_AXI_GATHER_EN (1<<0) -#define m_WIN0_CBR_AXI_GATHER_EN (1<<1) -#define m_WIN0_BIC_COE_SEL (3<<2) -#define m_WIN0_VSD_YRGB_GT4 (1<<4) -#define m_WIN0_VSD_YRGB_GT2 (1<<5) -#define m_WIN0_VSD_CBR_GT4 (1<<6) -#define m_WIN0_VSD_CBR_GT2 (1<<7) -#define m_WIN0_YRGB_AXI_GATHER_NUM (0xf<<8) -#define m_WIN0_CBR_AXI_GATHER_NUM (7<<12) -#define m_WIN0_LINE_LOAD_MODE (1<<15) -#define m_WIN0_YRGB_HOR_SCL_MODE (3<<16) -#define m_WIN0_YRGB_VER_SCL_MODE (3<<18) -#define m_WIN0_YRGB_HSD_MODE (3<<20) -#define m_WIN0_YRGB_VSU_MODE (1<<22) -#define m_WIN0_YRGB_VSD_MODE (1<<23) -#define m_WIN0_CBR_HOR_SCL_MODE (3<<24) -#define m_WIN0_CBR_VER_SCL_MODE (3<<26) -#define m_WIN0_CBR_HSD_MODE (3<<28) -#define m_WIN0_CBR_VSU_MODE ((u32)1<<30) -#define m_WIN0_CBR_VSD_MODE ((u32)1<<31) - -#define WIN0_COLOR_KEY (0x0038) -#define v_WIN0_COLOR_KEY(x) (((x)&0x3fffffff)<<0) -#define v_WIN0_COLOR_KEY_EN(x) (((x)&1)<<31) -#define m_WIN0_COLOR_KEY (0x3fffffff<<0) -#define m_WIN0_COLOR_KEY_EN ((u32)1<<31) - -#define WIN0_VIR (0x003c) -#define v_WIN0_VIR_STRIDE(x) (((x)&0x3fff)<<0) -#define v_WIN0_VIR_STRIDE_UV(x) (((x)&0x3fff)<<16) -#define m_WIN0_VIR_STRIDE (0x3fff<<0) -#define m_WIN0_VIR_STRIDE_UV (0x3fff<<16) - -#define WIN0_YRGB_MST (0x0040) -#define WIN0_CBR_MST (0x0044) -#define WIN0_ACT_INFO (0x0048) -#define v_WIN0_ACT_WIDTH(x) (((x-1)&0x1fff)<<0) -#define v_WIN0_ACT_HEIGHT(x) (((x-1)&0x1fff)<<16) -#define m_WIN0_ACT_WIDTH (0x1fff<<0) -#define m_WIN0_ACT_HEIGHT (0x1fff<<16) - -#define WIN0_DSP_INFO (0x004c) -#define v_WIN0_DSP_WIDTH(x) (((x-1)&0xfff)<<0) -#define v_WIN0_DSP_HEIGHT(x) (((x-1)&0xfff)<<16) -#define m_WIN0_DSP_WIDTH (0xfff<<0) -#define m_WIN0_DSP_HEIGHT (0xfff<<16) - -#define WIN0_DSP_ST (0x0050) -#define v_WIN0_DSP_XST(x) (((x)&0x1fff)<<0) -#define v_WIN0_DSP_YST(x) (((x)&0x1fff)<<16) -#define m_WIN0_DSP_XST (0x1fff<<0) -#define m_WIN0_DSP_YST (0x1fff<<16) - -#define WIN0_SCL_FACTOR_YRGB (0x0054) -#define v_WIN0_HS_FACTOR_YRGB(x) (((x)&0xffff)<<0) -#define v_WIN0_VS_FACTOR_YRGB(x) (((x)&0xffff)<<16) -#define m_WIN0_HS_FACTOR_YRGB (0xffff<<0) -#define m_WIN0_VS_FACTOR_YRGB ((u32)0xffff<<16) - -#define WIN0_SCL_FACTOR_CBR (0x0058) -#define v_WIN0_HS_FACTOR_CBR(x) (((x)&0xffff)<<0) -#define v_WIN0_VS_FACTOR_CBR(x) (((x)&0xffff)<<16) -#define m_WIN0_HS_FACTOR_CBR (0xffff<<0) -#define m_WIN0_VS_FACTOR_CBR ((u32)0xffff<<16) - -#define WIN0_SCL_OFFSET (0x005c) -#define v_WIN0_HS_OFFSET_YRGB(x) (((x)&0xff)<<0) -#define v_WIN0_HS_OFFSET_CBR(x) (((x)&0xff)<<8) -#define v_WIN0_VS_OFFSET_YRGB(x) (((x)&0xff)<<16) -#define v_WIN0_VS_OFFSET_CBR(x) (((x)&0xff)<<24) - -#define m_WIN0_HS_OFFSET_YRGB (0xff<<0) -#define m_WIN0_HS_OFFSET_CBR (0xff<<8) -#define m_WIN0_VS_OFFSET_YRGB (0xff<<16) -#define m_WIN0_VS_OFFSET_CBR ((u32)0xff<<24) - -#define WIN0_SRC_ALPHA_CTRL (0x0060) -#define v_WIN0_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_WIN0_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_WIN0_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_WIN0_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_WIN0_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_WIN0_SRC_FACTOR_M0(x) (((x)&7)<<6) -#define v_WIN0_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_WIN0_FADING_VALUE(x) (((x)&0xff)<<24) - -#define m_WIN0_SRC_ALPHA_EN (1<<0) -#define m_WIN0_SRC_COLOR_M0 (1<<1) -#define m_WIN0_SRC_ALPHA_M0 (1<<2) -#define m_WIN0_SRC_BLEND_M0 (3<<3) -#define m_WIN0_SRC_ALPHA_CAL_M0 (1<<5) -#define m_WIN0_SRC_FACTOR_M0 (7<<6) -#define m_WIN0_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_WIN0_FADING_VALUE (0xff<<24) - -#define WIN0_DST_ALPHA_CTRL (0x0064) -#define v_WIN0_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_WIN0_DST_FACTOR_M0 (7<<6) - -#define WIN0_FADING_CTRL (0x0068) -#define v_WIN0_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_WIN0_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_WIN0_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_WIN0_FADING_EN(x) (((x)&1)<<24) - -#define m_WIN0_FADING_OFFSET_R (0xff<<0) -#define m_WIN0_FADING_OFFSET_G (0xff<<8) -#define m_WIN0_FADING_OFFSET_B (0xff<<16) -#define m_WIN0_FADING_EN (1<<24) - -/*win1 register*/ -#define WIN1_CTRL0 (0x0070) -#define v_WIN1_EN(x) (((x)&1)<<0) -#define v_WIN1_DATA_FMT(x) (((x)&7)<<1) -#define v_WIN1_FMT_10(x) (((x)&1)<<4) -#define v_WIN1_LB_MODE(x) (((x)&7)<<5) -#define v_WIN1_INTERLACE_READ_MODE(x) (((x)&1)<<8) -#define v_WIN1_NO_OUTSTANDING(x) (((x)&1)<<9) -#define v_WIN1_CSC_MODE(x) (((x)&3)<<10) -#define v_WIN1_RB_SWAP(x) (((x)&1)<<12) -#define v_WIN1_ALPHA_SWAP(x) (((x)&1)<<13) -#define v_WIN1_MID_SWAP(x) (((x)&1)<<14) -#define v_WIN1_UV_SWAP(x) (((x)&1)<<15) -#define v_WIN1_PPAS_ZERO_EN(x) (((x)&1)<<16) -#define v_WIN1_YRGB_DEFLICK(x) (((x)&1)<<18) -#define v_WIN1_CBR_DEFLICK(x) (((x)&1)<<19) -#define v_WIN1_YUV_CLIP(x) (((x)&1)<<20) - -#define m_WIN1_EN (1<<0) -#define m_WIN1_DATA_FMT (7<<1) -#define m_WIN1_FMT_10 (1<<4) -#define m_WIN1_LB_MODE (7<<5) -#define m_WIN1_INTERLACE_READ_MODE (1<<8) -#define m_WIN1_NO_OUTSTANDING (1<<9) -#define m_WIN1_CSC_MODE (3<<10) -#define m_WIN1_RB_SWAP (1<<12) -#define m_WIN1_ALPHA_SWAP (1<<13) -#define m_WIN1_MID_SWAP (1<<14) -#define m_WIN1_UV_SWAP (1<<15) -#define m_WIN1_PPAS_ZERO_EN (1<<16) -#define m_WIN1_YRGB_DEFLICK (1<<18) -#define m_WIN1_CBR_DEFLICK (1<<19) -#define m_WIN1_YUV_CLIP (1<<20) - -#define WIN1_CTRL1 (0x0074) -#define v_WIN1_YRGB_AXI_GATHER_EN(x) (((x)&1)<<0) -#define v_WIN1_CBR_AXI_GATHER_EN(x) (((x)&1)<<1) -#define v_WIN1_BIC_COE_SEL(x) (((x)&3)<<2) -#define v_WIN1_VSD_YRGB_GT4(x) (((x)&1)<<4) -#define v_WIN1_VSD_YRGB_GT2(x) (((x)&1)<<5) -#define v_WIN1_VSD_CBR_GT4(x) (((x)&1)<<6) -#define v_WIN1_VSD_CBR_GT2(x) (((x)&1)<<7) -#define v_WIN1_YRGB_AXI_GATHER_NUM(x) (((x)&0xf)<<8) -#define v_WIN1_CBR_AXI_GATHER_NUM(x) (((x)&7)<<12) -#define v_WIN1_LINE_LOAD_MODE(x) (((x)&1)<<15) -#define v_WIN1_YRGB_HOR_SCL_MODE(x) (((x)&3)<<16) -#define v_WIN1_YRGB_VER_SCL_MODE(x) (((x)&3)<<18) -#define v_WIN1_YRGB_HSD_MODE(x) (((x)&3)<<20) -#define v_WIN1_YRGB_VSU_MODE(x) (((x)&1)<<22) -#define v_WIN1_YRGB_VSD_MODE(x) (((x)&1)<<23) -#define v_WIN1_CBR_HOR_SCL_MODE(x) (((x)&3)<<24) -#define v_WIN1_CBR_VER_SCL_MODE(x) (((x)&3)<<26) -#define v_WIN1_CBR_HSD_MODE(x) (((x)&3)<<28) -#define v_WIN1_CBR_VSU_MODE(x) (((x)&1)<<30) -#define v_WIN1_CBR_VSD_MODE(x) (((x)&1)<<31) - -#define m_WIN1_YRGB_AXI_GATHER_EN (1<<0) -#define m_WIN1_CBR_AXI_GATHER_EN (1<<1) -#define m_WIN1_BIC_COE_SEL (3<<2) -#define m_WIN1_VSD_YRGB_GT4 (1<<4) -#define m_WIN1_VSD_YRGB_GT2 (1<<5) -#define m_WIN1_VSD_CBR_GT4 (1<<6) -#define m_WIN1_VSD_CBR_GT2 (1<<7) -#define m_WIN1_YRGB_AXI_GATHER_NUM (0xf<<8) -#define m_WIN1_CBR_AXI_GATHER_NUM (7<<12) -#define m_WIN1_LINE_LOAD_MODE (1<<15) -#define m_WIN1_YRGB_HOR_SCL_MODE (3<<16) -#define m_WIN1_YRGB_VER_SCL_MODE (3<<18) -#define m_WIN1_YRGB_HSD_MODE (3<<20) -#define m_WIN1_YRGB_VSU_MODE (1<<22) -#define m_WIN1_YRGB_VSD_MODE (1<<23) -#define m_WIN1_CBR_HOR_SCL_MODE (3<<24) -#define m_WIN1_CBR_VER_SCL_MODE (3<<26) -#define m_WIN1_CBR_HSD_MODE (3<<28) -#define m_WIN1_CBR_VSU_MODE (1<<30) -#define m_WIN1_CBR_VSD_MODE ((u32)1<<31) - -#define WIN1_COLOR_KEY (0x0078) -#define v_WIN1_COLOR_KEY(x) (((x)&0x3fffffff)<<0) -#define v_WIN1_COLOR_KEY_EN(x) (((x)&1)<<31) -#define m_WIN1_COLOR_KEY (0x3fffffff<<0) -#define m_WIN1_COLOR_KEY_EN ((u32)1<<31) - -#define WIN1_VIR (0x007c) -#define v_WIN1_VIR_STRIDE(x) (((x)&0x3fff)<<0) -#define v_WIN1_VIR_STRIDE_UV(x) (((x)&0x3fff)<<16) -#define m_WIN1_VIR_STRIDE (0x3fff<<0) -#define m_WIN1_VIR_STRIDE_UV (0x3fff<<16) - -#define WIN1_YRGB_MST (0x0080) -#define WIN1_CBR_MST (0x0084) -#define WIN1_ACT_INFO (0x0088) -#define v_WIN1_ACT_WIDTH(x) (((x-1)&0x1fff)<<0) -#define v_WIN1_ACT_HEIGHT(x) (((x-1)&0x1fff)<<16) -#define m_WIN1_ACT_WIDTH (0x1fff<<0) -#define m_WIN1_ACT_HEIGHT (0x1fff<<16) - -#define WIN1_DSP_INFO (0x008c) -#define v_WIN1_DSP_WIDTH(x) (((x-1)&0xfff)<<0) -#define v_WIN1_DSP_HEIGHT(x) (((x-1)&0xfff)<<16) -#define m_WIN1_DSP_WIDTH (0xfff<<0) -#define m_WIN1_DSP_HEIGHT (0xfff<<16) - -#define WIN1_DSP_ST (0x0090) -#define v_WIN1_DSP_XST(x) (((x)&0x1fff)<<0) -#define v_WIN1_DSP_YST(x) (((x)&0x1fff)<<16) -#define m_WIN1_DSP_XST (0x1fff<<0) -#define m_WIN1_DSP_YST (0x1fff<<16) - -#define WIN1_SCL_FACTOR_YRGB (0x0094) -#define v_WIN1_HS_FACTOR_YRGB(x) (((x)&0xffff)<<0) -#define v_WIN1_VS_FACTOR_YRGB(x) (((x)&0xffff)<<16) -#define m_WIN1_HS_FACTOR_YRGB (0xffff<<0) -#define m_WIN1_VS_FACTOR_YRGB ((u32)0xffff<<16) - -#define WIN1_SCL_FACTOR_CBR (0x0098) -#define v_WIN1_HS_FACTOR_CBR(x) (((x)&0xffff)<<0) -#define v_WIN1_VS_FACTOR_CBR(x) (((x)&0xffff)<<16) -#define m_WIN1_HS_FACTOR_CBR (0xffff<<0) -#define m_WIN1_VS_FACTOR_CBR ((u32)0xffff<<16) - -#define WIN1_SCL_OFFSET (0x009c) -#define v_WIN1_HS_OFFSET_YRGB(x) (((x)&0xff)<<0) -#define v_WIN1_HS_OFFSET_CBR(x) (((x)&0xff)<<8) -#define v_WIN1_VS_OFFSET_YRGB(x) (((x)&0xff)<<16) -#define v_WIN1_VS_OFFSET_CBR(x) (((x)&0xff)<<24) - -#define m_WIN1_HS_OFFSET_YRGB (0xff<<0) -#define m_WIN1_HS_OFFSET_CBR (0xff<<8) -#define m_WIN1_VS_OFFSET_YRGB (0xff<<16) -#define m_WIN1_VS_OFFSET_CBR ((u32)0xff<<24) - -#define WIN1_SRC_ALPHA_CTRL (0x00a0) -#define v_WIN1_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_WIN1_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_WIN1_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_WIN1_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_WIN1_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_WIN1_SRC_FACTOR_M0(x) (((x)&7)<<6) -#define v_WIN1_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_WIN1_FADING_VALUE(x) (((x)&0xff)<<24) - -#define m_WIN1_SRC_ALPHA_EN (1<<0) -#define m_WIN1_SRC_COLOR_M0 (1<<1) -#define m_WIN1_SRC_ALPHA_M0 (1<<2) -#define m_WIN1_SRC_BLEND_M0 (3<<3) -#define m_WIN1_SRC_ALPHA_CAL_M0 (1<<5) -#define m_WIN1_SRC_FACTOR_M0 (7<<6) -#define m_WIN1_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_WIN1_FADING_VALUE (0xff<<24) - -#define WIN1_DST_ALPHA_CTRL (0x00a4) -#define v_WIN1_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_WIN1_DST_FACTOR_M0 (7<<6) - -#define WIN1_FADING_CTRL (0x00a8) -#define v_WIN1_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_WIN1_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_WIN1_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_WIN1_FADING_EN(x) (((x)&1)<<24) - -#define m_WIN1_FADING_OFFSET_R (0xff<<0) -#define m_WIN1_FADING_OFFSET_G (0xff<<8) -#define m_WIN1_FADING_OFFSET_B (0xff<<16) -#define m_WIN1_FADING_EN (1<<24) - -/*win2 register*/ -#define WIN2_CTRL0 (0x00b0) -#define v_WIN2_EN(x) (((x)&1)<<0) -#define v_WIN2_DATA_FMT(x) (((x)&7)<<1) -#define v_WIN2_MST0_EN(x) (((x)&1)<<4) -#define v_WIN2_MST1_EN(x) (((x)&1)<<5) -#define v_WIN2_MST2_EN(x) (((x)&1)<<6) -#define v_WIN2_MST3_EN(x) (((x)&1)<<7) -#define v_WIN2_INTERLACE_READ(x) (((x)&1)<<8) -#define v_WIN2_NO_OUTSTANDING(x) (((x)&1)<<9) -#define v_WIN2_CSC_MODE(x) (((x)&1)<<10) -#define v_WIN2_RB_SWAP(x) (((x)&1)<<12) -#define v_WIN2_ALPHA_SWAP(x) (((x)&1)<<13) -#define v_WIN2_ENDIAN_MODE(x) (((x)&1)<<14) -#define v_WIN2_LUT_EN(x) (((x)&1)<<18) - -#define m_WIN2_EN (1<<0) -#define m_WIN2_DATA_FMT (7<<1) -#define m_WIN2_MST0_EN (1<<4) -#define m_WIN2_MST1_EN (1<<5) -#define m_WIN2_MST2_EN (1<<6) -#define m_WIN2_MST3_EN (1<<7) -#define m_WIN2_INTERLACE_READ (1<<8) -#define m_WIN2_NO_OUTSTANDING (1<<9) -#define m_WIN2_CSC_MODE (1<<10) -#define m_WIN2_RB_SWAP (1<<12) -#define m_WIN2_ALPHA_SWAP (1<<13) -#define m_WIN2_ENDIAN_MODE (1<<14) -#define m_WIN2_LUT_EN (1<<18) - -#define WIN2_CTRL1 (0x00b4) -#define v_WIN2_AXI_GATHER_EN(x) (((x)&1)<<0) -#define v_WIN2_AXI_GATHER_NUM(x) (((x)&0xf)<<4) -#define m_WIN2_AXI_GATHER_EN (1<<0) -#define m_WIN2_AXI_GATHER_NUM (0xf<<4) - -#define WIN2_VIR0_1 (0x00b8) -#define v_WIN2_VIR_STRIDE0(x) (((x)&0x1fff)<<0) -#define v_WIN2_VIR_STRIDE1(x) (((x)&0x1fff)<<16) -#define m_WIN2_VIR_STRIDE0 (0x1fff<<0) -#define m_WIN2_VIR_STRIDE1 (0x1fff<<16) - -#define WIN2_VIR2_3 (0x00bc) -#define v_WIN2_VIR_STRIDE2(x) (((x)&0x1fff)<<0) -#define v_WIN2_VIR_STRIDE3(x) (((x)&0x1fff)<<16) -#define m_WIN2_VIR_STRIDE2 (0x1fff<<0) -#define m_WIN2_VIR_STRIDE3 (0x1fff<<16) - -#define WIN2_MST0 (0x00c0) -#define WIN2_DSP_INFO0 (0x00c4) -#define v_WIN2_DSP_WIDTH0(x) (((x-1)&0xfff)<<0) -#define v_WIN2_DSP_HEIGHT0(x) (((x-1)&0xfff)<<16) -#define m_WIN2_DSP_WIDTH0 (0xfff<<0) -#define m_WIN2_DSP_HEIGHT0 (0xfff<<16) - -#define WIN2_DSP_ST0 (0x00c8) -#define v_WIN2_DSP_XST0(x) (((x)&0x1fff)<<0) -#define v_WIN2_DSP_YST0(x) (((x)&0x1fff)<<16) -#define m_WIN2_DSP_XST0 (0x1fff<<0) -#define m_WIN2_DSP_YST0 (0x1fff<<16) - -#define WIN2_COLOR_KEY (0x00cc) -#define v_WIN2_COLOR_KEY(x) (((x)&0xffffff)<<0) -#define v_WIN2_KEY_EN(x) (((x)&1)<<24) -#define m_WIN2_COLOR_KEY (0xffffff<<0) -#define m_WIN2_KEY_EN ((u32)1<<24) - - -#define WIN2_MST1 (0x00d0) -#define WIN2_DSP_INFO1 (0x00d4) -#define v_WIN2_DSP_WIDTH1(x) (((x-1)&0xfff)<<0) -#define v_WIN2_DSP_HEIGHT1(x) (((x-1)&0xfff)<<16) - -#define m_WIN2_DSP_WIDTH1 (0xfff<<0) -#define m_WIN2_DSP_HEIGHT1 (0xfff<<16) - -#define WIN2_DSP_ST1 (0x00d8) -#define v_WIN2_DSP_XST1(x) (((x)&0x1fff)<<0) -#define v_WIN2_DSP_YST1(x) (((x)&0x1fff)<<16) - -#define m_WIN2_DSP_XST1 (0x1fff<<0) -#define m_WIN2_DSP_YST1 (0x1fff<<16) - -#define WIN2_SRC_ALPHA_CTRL (0x00dc) -#define v_WIN2_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_WIN2_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_WIN2_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_WIN2_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_WIN2_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_WIN2_SRC_FACTOR_M0(x) (((x)&7)<<6) -#define v_WIN2_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_WIN2_FADING_VALUE(x) (((x)&0xff)<<24) - - -#define m_WIN2_SRC_ALPHA_EN (1<<0) -#define m_WIN2_SRC_COLOR_M0 (1<<1) -#define m_WIN2_SRC_ALPHA_M0 (1<<2) -#define m_WIN2_SRC_BLEND_M0 (3<<3) -#define m_WIN2_SRC_ALPHA_CAL_M0 (1<<5) -#define m_WIN2_SRC_FACTOR_M0 (7<<6) -#define m_WIN2_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_WIN2_FADING_VALUE (0xff<<24) - -#define WIN2_MST2 (0x00e0) -#define WIN2_DSP_INFO2 (0x00e4) -#define v_WIN2_DSP_WIDTH2(x) (((x-1)&0xfff)<<0) -#define v_WIN2_DSP_HEIGHT2(x) (((x-1)&0xfff)<<16) - -#define m_WIN2_DSP_WIDTH2 (0xfff<<0) -#define m_WIN2_DSP_HEIGHT2 (0xfff<<16) - - -#define WIN2_DSP_ST2 (0x00e8) -#define v_WIN2_DSP_XST2(x) (((x)&0x1fff)<<0) -#define v_WIN2_DSP_YST2(x) (((x)&0x1fff)<<16) -#define m_WIN2_DSP_XST2 (0x1fff<<0) -#define m_WIN2_DSP_YST2 (0x1fff<<16) - -#define WIN2_DST_ALPHA_CTRL (0x00ec) -#define v_WIN2_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_WIN2_DST_FACTOR_M0 (7<<6) - -#define WIN2_MST3 (0x00f0) -#define WIN2_DSP_INFO3 (0x00f4) -#define v_WIN2_DSP_WIDTH3(x) (((x-1)&0xfff)<<0) -#define v_WIN2_DSP_HEIGHT3(x) (((x-1)&0xfff)<<16) -#define m_WIN2_DSP_WIDTH3 (0xfff<<0) -#define m_WIN2_DSP_HEIGHT3 (0xfff<<16) - -#define WIN2_DSP_ST3 (0x00f8) -#define v_WIN2_DSP_XST3(x) (((x)&0x1fff)<<0) -#define v_WIN2_DSP_YST3(x) (((x)&0x1fff)<<16) -#define m_WIN2_DSP_XST3 (0x1fff<<0) -#define m_WIN2_DSP_YST3 (0x1fff<<16) - -#define WIN2_FADING_CTRL (0x00fc) -#define v_WIN2_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_WIN2_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_WIN2_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_WIN2_FADING_EN(x) (((x)&1)<<24) - -#define m_WIN2_FADING_OFFSET_R (0xff<<0) -#define m_WIN2_FADING_OFFSET_G (0xff<<8) -#define m_WIN2_FADING_OFFSET_B (0xff<<16) -#define m_WIN2_FADING_EN (1<<24) - -/*win3 register*/ -#define WIN3_CTRL0 (0x0100) -#define v_WIN3_EN(x) (((x)&1)<<0) -#define v_WIN3_DATA_FMT(x) (((x)&7)<<1) -#define v_WIN3_MST0_EN(x) (((x)&1)<<4) -#define v_WIN3_MST1_EN(x) (((x)&1)<<5) -#define v_WIN3_MST2_EN(x) (((x)&1)<<6) -#define v_WIN3_MST3_EN(x) (((x)&1)<<7) -#define v_WIN3_INTERLACE_READ(x) (((x)&1)<<8) -#define v_WIN3_NO_OUTSTANDING(x) (((x)&1)<<9) -#define v_WIN3_CSC_MODE(x) (((x)&1)<<10) -#define v_WIN3_RB_SWAP(x) (((x)&1)<<12) -#define v_WIN3_ALPHA_SWAP(x) (((x)&1)<<13) -#define v_WIN3_ENDIAN_MODE(x) (((x)&1)<<14) -#define v_WIN3_LUT_EN(x) (((x)&1)<<18) - -#define m_WIN3_EN (1<<0) -#define m_WIN3_DATA_FMT (7<<1) -#define m_WIN3_MST0_EN (1<<4) -#define m_WIN3_MST1_EN (1<<5) -#define m_WIN3_MST2_EN (1<<6) -#define m_WIN3_MST3_EN (1<<7) -#define m_WIN3_INTERLACE_READ (1<<8) -#define m_WIN3_NO_OUTSTANDING (1<<9) -#define m_WIN3_CSC_MODE (1<<10) -#define m_WIN3_RB_SWAP (1<<12) -#define m_WIN3_ALPHA_SWAP (1<<13) -#define m_WIN3_ENDIAN_MODE (1<<14) -#define m_WIN3_LUT_EN (1<<18) - - -#define WIN3_CTRL1 (0x0104) -#define v_WIN3_AXI_GATHER_EN(x) (((x)&1)<<0) -#define v_WIN3_AXI_GATHER_NUM(x) (((x)&0xf)<<4) -#define m_WIN3_AXI_GATHER_EN (1<<0) -#define m_WIN3_AXI_GATHER_NUM (0xf<<4) - -#define WIN3_VIR0_1 (0x0108) -#define v_WIN3_VIR_STRIDE0(x) (((x)&0x1fff)<<0) -#define v_WIN3_VIR_STRIDE1(x) (((x)&0x1fff)<<16) -#define m_WIN3_VIR_STRIDE0 (0x1fff<<0) -#define m_WIN3_VIR_STRIDE1 (0x1fff<<16) - -#define WIN3_VIR2_3 (0x010c) -#define v_WIN3_VIR_STRIDE2(x) (((x)&0x1fff)<<0) -#define v_WIN3_VIR_STRIDE3(x) (((x)&0x1fff)<<16) -#define m_WIN3_VIR_STRIDE2 (0x1fff<<0) -#define m_WIN3_VIR_STRIDE3 (0x1fff<<16) - -#define WIN3_MST0 (0x0110) -#define WIN3_DSP_INFO0 (0x0114) -#define v_WIN3_DSP_WIDTH0(x) (((x-1)&0xfff)<<0) -#define v_WIN3_DSP_HEIGHT0(x) (((x-1)&0xfff)<<16) -#define m_WIN3_DSP_WIDTH0 (0xfff<<0) -#define m_WIN3_DSP_HEIGHT0 (0xfff<<16) - -#define WIN3_DSP_ST0 (0x0118) -#define v_WIN3_DSP_XST0(x) (((x)&0x1fff)<<0) -#define v_WIN3_DSP_YST0(x) (((x)&0x1fff)<<16) -#define m_WIN3_DSP_XST0 (0x1fff<<0) -#define m_WIN3_DSP_YST0 (0x1fff<<16) - -#define WIN3_COLOR_KEY (0x011c) -#define v_WIN3_COLOR_KEY(x) (((x)&0xffffff)<<0) -#define v_WIN3_KEY_EN(x) (((x)&1)<<24) -#define m_WIN3_COLOR_KEY (0xffffff<<0) -#define m_WIN3_KEY_EN ((u32)1<<24) - -#define WIN3_MST1 (0x0120) -#define WIN3_DSP_INFO1 (0x0124) -#define v_WIN3_DSP_WIDTH1(x) (((x-1)&0xfff)<<0) -#define v_WIN3_DSP_HEIGHT1(x) (((x-1)&0xfff)<<16) -#define m_WIN3_DSP_WIDTH1 (0xfff<<0) -#define m_WIN3_DSP_HEIGHT1 (0xfff<<16) - -#define WIN3_DSP_ST1 (0x0128) -#define v_WIN3_DSP_XST1(x) (((x)&0x1fff)<<0) -#define v_WIN3_DSP_YST1(x) (((x)&0x1fff)<<16) -#define m_WIN3_DSP_XST1 (0x1fff<<0) -#define m_WIN3_DSP_YST1 (0x1fff<<16) - -#define WIN3_SRC_ALPHA_CTRL (0x012c) -#define v_WIN3_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_WIN3_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_WIN3_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_WIN3_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_WIN3_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_WIN3_SRC_FACTOR_M0(x) (((x)&7)<<6) -#define v_WIN3_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_WIN3_FADING_VALUE(x) (((x)&0xff)<<24) - -#define m_WIN3_SRC_ALPHA_EN (1<<0) -#define m_WIN3_SRC_COLOR_M0 (1<<1) -#define m_WIN3_SRC_ALPHA_M0 (1<<2) -#define m_WIN3_SRC_BLEND_M0 (3<<3) -#define m_WIN3_SRC_ALPHA_CAL_M0 (1<<5) -#define m_WIN3_SRC_FACTOR_M0 (7<<6) -#define m_WIN3_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_WIN3_FADING_VALUE (0xff<<24) - -#define WIN3_MST2 (0x0130) -#define WIN3_DSP_INFO2 (0x0134) -#define v_WIN3_DSP_WIDTH2(x) (((x-1)&0xfff)<<0) -#define v_WIN3_DSP_HEIGHT2(x) (((x-1)&0xfff)<<16) -#define m_WIN3_DSP_WIDTH2 (0xfff<<0) -#define m_WIN3_DSP_HEIGHT2 (0xfff<<16) - -#define WIN3_DSP_ST2 (0x0138) -#define v_WIN3_DSP_XST2(x) (((x)&0x1fff)<<0) -#define v_WIN3_DSP_YST2(x) (((x)&0x1fff)<<16) -#define m_WIN3_DSP_XST2 (0x1fff<<0) -#define m_WIN3_DSP_YST2 (0x1fff<<16) - -#define WIN3_DST_ALPHA_CTRL (0x013c) -#define v_WIN3_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_WIN3_DST_FACTOR_M0 (7<<6) - - -#define WIN3_MST3 (0x0140) -#define WIN3_DSP_INFO3 (0x0144) -#define v_WIN3_DSP_WIDTH3(x) (((x-1)&0xfff)<<0) -#define v_WIN3_DSP_HEIGHT3(x) (((x-1)&0xfff)<<16) -#define m_WIN3_DSP_WIDTH3 (0xfff<<0) -#define m_WIN3_DSP_HEIGHT3 (0xfff<<16) - -#define WIN3_DSP_ST3 (0x0148) -#define v_WIN3_DSP_XST3(x) (((x)&0x1fff)<<0) -#define v_WIN3_DSP_YST3(x) (((x)&0x1fff)<<16) -#define m_WIN3_DSP_XST3 (0x1fff<<0) -#define m_WIN3_DSP_YST3 (0x1fff<<16) - -#define WIN3_FADING_CTRL (0x014c) -#define v_WIN3_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_WIN3_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_WIN3_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_WIN3_FADING_EN(x) (((x)&1)<<24) - -#define m_WIN3_FADING_OFFSET_R (0xff<<0) -#define m_WIN3_FADING_OFFSET_G (0xff<<8) -#define m_WIN3_FADING_OFFSET_B (0xff<<16) -#define m_WIN3_FADING_EN (1<<24) - - -/*hwc register*/ -#define HWC_CTRL0 (0x0150) -#define v_HWC_EN(x) (((x)&1)<<0) -#define v_HWC_DATA_FMT(x) (((x)&7)<<1) -#define v_HWC_MODE(x) (((x)&1)<<4) -#define v_HWC_SIZE(x) (((x)&3)<<5) -#define v_HWC_INTERLACE_READ(x) (((x)&1)<<8) -#define v_HWC_NO_OUTSTANDING(x) (((x)&1)<<9) -#define v_HWC_CSC_MODE(x) (((x)&1)<<10) -#define v_HWC_RB_SWAP(x) (((x)&1)<<12) -#define v_HWC_ALPHA_SWAP(x) (((x)&1)<<13) -#define v_HWC_ENDIAN_MODE(x) (((x)&1)<<14) -#define v_HWC_LUT_EN(x) (((x)&1)<<18) - -#define m_HWC_EN (1<<0) -#define m_HWC_DATA_FMT (7<<1) -#define m_HWC_MODE (1<<4) -#define m_HWC_SIZE (3<<5) -#define m_HWC_INTERLACE_READ (1<<8) -#define m_HWC_NO_OUTSTANDING (1<<9) -#define m_HWC_CSC_MODE (1<<10) -#define m_HWC_RB_SWAP (1<<12) -#define m_HWC_ALPHA_SWAP (1<<13) -#define m_HWC_ENDIAN_MODE (1<<14) -#define m_HWC_LUT_EN (1<<18) - - -#define HWC_CTRL1 (0x0154) -#define v_HWC_AXI_GATHER_EN(x) (((x)&1)<<0) -#define v_HWC_AXI_GATHER_NUM(x) (((x)&7)<<4) -#define m_HWC_AXI_GATHER_EN (1<<0) -#define m_HWC_AXI_GATHER_NUM (7<<4) - -#define HWC_MST (0x0158) -#define HWC_DSP_ST (0x015c) -#define v_HWC_DSP_XST(x) (((x)&0x1fff)<<0) -#define v_HWC_DSP_YST(x) (((x)&0x1fff)<<16) -#define m_HWC_DSP_XST (0x1fff<<0) -#define m_HWC_DSP_YST (0x1fff<<16) - -#define HWC_SRC_ALPHA_CTRL (0x0160) -#define v_HWC_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_HWC_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_HWC_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_HWC_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_HWC_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_HWC_SRC_FACTOR_M0(x) (((x)&7)<<6) -#define v_HWC_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_HWC_FADING_VALUE(x) (((x)&0xff)<<24) - -#define m_HWC_SRC_ALPHA_EN (1<<0) -#define m_HWC_SRC_COLOR_M0 (1<<1) -#define m_HWC_SRC_ALPHA_M0 (1<<2) -#define m_HWC_SRC_BLEND_M0 (3<<3) -#define m_HWC_SRC_ALPHA_CAL_M0 (1<<5) -#define m_HWC_SRC_FACTOR_M0 (7<<6) -#define m_HWC_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_HWC_FADING_VALUE (0xff<<24) - -#define HWC_DST_ALPHA_CTRL (0x0164) -#define v_HWC_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_HWC_DST_FACTOR_M0 (7<<6) - - -#define HWC_FADING_CTRL (0x0168) -#define v_HWC_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_HWC_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_HWC_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_HWC_FADING_EN(x) (((x)&1)<<24) - -#define m_HWC_FADING_OFFSET_R (0xff<<0) -#define m_HWC_FADING_OFFSET_G (0xff<<8) -#define m_HWC_FADING_OFFSET_B (0xff<<16) -#define m_HWC_FADING_EN (1<<24) - -/*post process register*/ -#define POST_DSP_HACT_INFO (0x0170) -#define v_DSP_HACT_END_POST(x) (((x)&0x1fff)<<0) -#define v_DSP_HACT_ST_POST(x) (((x)&0x1fff)<<16) -#define m_DSP_HACT_END_POST (0x1fff<<0) -#define m_DSP_HACT_ST_POST (0x1fff<<16) - -#define POST_DSP_VACT_INFO (0x0174) -#define v_DSP_VACT_END_POST(x) (((x)&0x1fff)<<0) -#define v_DSP_VACT_ST_POST(x) (((x)&0x1fff)<<16) -#define m_DSP_VACT_END_POST (0x1fff<<0) -#define m_DSP_VACT_ST_POST (0x1fff<<16) - -#define POST_SCL_FACTOR_YRGB (0x0178) -#define v_POST_HS_FACTOR_YRGB(x) (((x)&0xffff)<<0) -#define v_POST_VS_FACTOR_YRGB(x) (((x)&0xffff)<<16) -#define m_POST_HS_FACTOR_YRGB (0xffff<<0) -#define m_POST_VS_FACTOR_YRGB (0xffff<<16) - -#define POST_SCL_CTRL (0x0180) -#define v_POST_HOR_SD_EN(x) (((x)&1)<<0) -#define v_POST_VER_SD_EN(x) (((x)&1)<<1) - -#define m_POST_HOR_SD_EN (0x1<<0) -#define m_POST_VER_SD_EN (0x1<<1) - -#define POST_DSP_VACT_INFO_F1 (0x0184) -#define v_DSP_VACT_END_POST_F1(x) (((x)&0x1fff)<<0) -#define v_DSP_VACT_ST_POST_F1(x) (((x)&0x1fff)<<16) - -#define m_DSP_VACT_END_POST_F1 (0x1fff<<0) -#define m_DSP_VACT_ST_POST_F1 (0x1fff<<16) - -#define DSP_HTOTAL_HS_END (0x0188) -#define v_DSP_HS_PW(x) (((x)&0x1fff)<<0) -#define v_DSP_HTOTAL(x) (((x)&0x1fff)<<16) -#define m_DSP_HS_PW (0x1fff<<0) -#define m_DSP_HTOTAL (0x1fff<<16) - -#define DSP_HACT_ST_END (0x018c) -#define v_DSP_HACT_END(x) (((x)&0x1fff)<<0) -#define v_DSP_HACT_ST(x) (((x)&0x1fff)<<16) -#define m_DSP_HACT_END (0x1fff<<0) -#define m_DSP_HACT_ST (0x1fff<<16) - -#define DSP_VTOTAL_VS_END (0x0190) -#define v_DSP_VS_PW(x) (((x)&0x1fff)<<0) -#define v_DSP_VTOTAL(x) (((x)&0x1fff)<<16) -#define m_DSP_VS_PW (0x1fff<<0) -#define m_DSP_VTOTAL (0x1fff<<16) - -#define DSP_VACT_ST_END (0x0194) -#define v_DSP_VACT_END(x) (((x)&0x1fff)<<0) -#define v_DSP_VACT_ST(x) (((x)&0x1fff)<<16) -#define m_DSP_VACT_END (0x1fff<<0) -#define m_DSP_VACT_ST (0x1fff<<16) - -#define DSP_VS_ST_END_F1 (0x0198) -#define v_DSP_VS_END_F1(x) (((x)&0x1fff)<<0) -#define v_DSP_VS_ST_F1(x) (((x)&0x1fff)<<16) -#define m_DSP_VS_END_F1 (0x1fff<<0) -#define m_DSP_VS_ST_F1 (0x1fff<<16) - -#define DSP_VACT_ST_END_F1 (0x019c) -#define v_DSP_VACT_END_F1(x) (((x)&0x1fff)<<0) -#define v_DSP_VAC_ST_F1(x) (((x)&0x1fff)<<16) -#define m_DSP_VACT_END_F1 (0x1fff<<0) -#define m_DSP_VAC_ST_F1 (0x1fff<<16) - - -/*pwm register*/ -#define PWM_CTRL (0x01a0) -#define v_PWM_EN(x) (((x)&1)<<0) -#define v_PWM_MODE(x) (((x)&3)<<1) - -#define v_DUTY_POL(x) (((x)&1)<<3) -#define v_INACTIVE_POL(x) (((x)&1)<<4) -#define v_OUTPUT_MODE(x) (((x)&1)<<5) -#define v_BL_EN(x) (((x)&1)<<8) -#define v_CLK_SEL(x) (((x)&1)<<9) -#define v_PRESCALE(x) (((x)&7)<<12) -#define v_SCALE(x) (((x)&0xff)<<16) -#define v_RPT(x) (((x)&0xff)<<24) - -#define m_PWM_EN (1<<0) -#define m_PWM_MODE (3<<1) - -#define m_DUTY_POL (1<<3) -#define m_INACTIVE_POL (1<<4) -#define m_OUTPUT_MODE (1<<5) -#define m_BL_EN (1<<8) -#define m_CLK_SEL (1<<9) -#define m_PRESCALE (7<<12) -#define m_SCALE (0xff<<16) -#define m_RPT ((u32)0xff<<24) - -#define PWM_PERIOD_HPR (0x01a4) -#define PWM_DUTY_LPR (0x01a8) -#define PWM_CNT (0x01ac) - -/*BCSH register*/ -#define BCSH_COLOR_BAR (0x01b0) -#define v_BCSH_EN(x) (((x)&1)<<0) -#define v_BCSH_COLOR_BAR_Y(x) (((x)&0x3ff)<<2) -#define v_BCSH_COLOR_BAR_U(x) (((x)&0x3ff)<<12) -#define v_BCSH_COLOR_BAR_V(x) (((x)&0x3ff)<<22) - -#define m_BCSH_EN (1<<0) -#define m_BCSH_COLOR_BAR_Y (0x3ff<<2) -#define m_BCSH_COLOR_BAR_U (0x3ff<<12) -#define m_BCSH_COLOR_BAR_V ((u32)0x3ff<<22) - -#define BCSH_BCS (0x01b4) -#define v_BCSH_BRIGHTNESS(x) (((x)&0xff)<<0) -#define v_BCSH_CONTRAST(x) (((x)&0x1ff)<<8) -#define v_BCSH_SAT_CON(x) (((x)&0x3ff)<<20) -#define v_BCSH_OUT_MODE(x) (((x)&0x3)<<30) - -#define m_BCSH_BRIGHTNESS (0xff<<0) -#define m_BCSH_CONTRAST (0x1ff<<8) -#define m_BCSH_SAT_CON (0x3ff<<20) -#define m_BCSH_OUT_MODE ((u32)0x3<<30) - - -#define BCSH_H (0x01b8) -#define v_BCSH_SIN_HUE(x) (((x)&0x1ff)<<0) -#define v_BCSH_COS_HUE(x) (((x)&0x1ff)<<16) - -#define m_BCSH_SIN_HUE (0x1ff<<0) -#define m_BCSH_COS_HUE (0x1ff<<16) - -#define BCSH_CTRL (0x01bc) -#define v_BCSH_Y2R_EN(x) (((x)&0x1)<<0) -#define v_BCSH_R2Y_EN(x) (((x)&0x1)<<4) -#define m_BCSH_Y2R_EN (0x1<<0) -#define m_BCSH_R2Y_EN (0x1<<4) - -#define CABC_CTRL0 (0x01c0) -#define v_CABC_EN(x) (((x)&1)<<0) -#define v_CABC_HANDLE_EN(x) (((x)&1)<<1) -#define v_PWM_CONFIG_MODE(x) (((x)&3)<<2) -#define v_CABC_CALC_PIXEL_NUM(x) (((x)&0x7fffff)<<4) -#define m_CABC_EN (1<<0) -#define m_CABC_HANDLE_EN (1<<1) -#define m_PWM_CONFIG_MODE (3<<2) -#define m_CABC_CALC_PIXEL_NUM (0x7fffff<<4) - -#define CABC_CTRL1 (0x01c4) -#define v_CABC_LUT_EN(x) (((x)&1)<<0) -#define v_CABC_TOTAL_PIXEL_NUM(x) (((x)&0x7fffff)<<4) -#define m_CABC_LUT_EN (1<<0) -#define m_CABC_TOTAL_PIXEL_NUM (0x7fffff<<4) - -#define CABC_GAUSS_LINE0_0 (0x01c8) -#define CABC_GAUSS_LINE0_1 (0x01cc) -#define CABC_GAUSS_LINE1_0 (0x01d0) -#define CABC_GAUSS_LINE1_1 (0x01d4) -#define CABC_GAUSS_LINE2_0 (0x01d8) -#define CABC_GAUSS_LINE2_1 (0x01dc) - -/*FRC register*/ -#define FRC_LOWER01_0 (0x01e0) -#define FRC_LOWER01_1 (0x01e4) -#define FRC_LOWER10_0 (0x01e8) -#define FRC_LOWER10_1 (0x01ec) -#define FRC_LOWER11_0 (0x01f0) -#define FRC_LOWER11_1 (0x01f4) - -#define CABC_CTRL2 (0x01f8) -#define v_CABC_STAGE_DOWN(x) (((x)&0xff)<<0) -#define v_CABC_STAGE_UP(x) (((x)&0x1ff)<<8) -#define v_CABC_STAGE_MODE(x) (((x)&1)<<19) -#define v_MAX_SCALE_CFG_VALUE(x) (((x)&0x1ff)<<20) -#define v_MAX_SCALE_CFG_ENABLE(x) (((x)&1)<<31) -#define m_CABC_STAGE_DOWN (0xff<<0) -#define m_CABC_STAGE_UP (0x1ff<<8) -#define m_CABC_STAGE_MODE (1<<19) -#define m_MAX_SCALE_CFG_VALUE (0x1ff<<20) -#define m_MAX_SCALE_CFG_ENABLE (1<<31) - -#define CABC_CTRL3 (0x01fc) -#define v_CABC_GLOBAL_DN(x) (((x)&0xff)<<0) -#define v_CABC_GLOBAL_DN_LIMIT_EN(x) (((x)&1)<<8) -#define m_CABC_GLOBAL_DN (0xff<<0) -#define m_CABC_GLOBAL_DN_LIMIT_EN (1<<8) - -#define MMU_DTE_ADDR (0x0300) -#define v_MMU_DTE_ADDR(x) (((x)&0xffffffff)<<0) -#define m_MMU_DTE_ADDR (0xffffffff<<0) - -#define MMU_STATUS (0x0304) -#define v_PAGING_ENABLED(x) (((x)&1)<<0) -#define v_PAGE_FAULT_ACTIVE(x) (((x)&1)<<1) -#define v_STAIL_ACTIVE(x) (((x)&1)<<2) -#define v_MMU_IDLE(x) (((x)&1)<<3) -#define v_REPLAY_BUFFER_EMPTY(x) (((x)&1)<<4) -#define v_PAGE_FAULT_IS_WRITE(x) (((x)&1)<<5) -#define v_PAGE_FAULT_BUS_ID(x) (((x)&0x1f)<<6) -#define m_PAGING_ENABLED (1<<0) -#define m_PAGE_FAULT_ACTIVE (1<<1) -#define m_STAIL_ACTIVE (1<<2) -#define m_MMU_IDLE (1<<3) -#define m_REPLAY_BUFFER_EMPTY (1<<4) -#define m_PAGE_FAULT_IS_WRITE (1<<5) -#define m_PAGE_FAULT_BUS_ID (0x1f<<6) - -#define MMU_COMMAND (0x0308) -#define v_MMU_CMD(x) (((x)&0x3)<<0) -#define m_MMU_CMD (0x3<<0) - -#define MMU_PAGE_FAULT_ADDR (0x030c) -#define v_PAGE_FAULT_ADDR(x) (((x)&0xffffffff)<<0) -#define m_PAGE_FAULT_ADDR (0xffffffff<<0) - -#define MMU_ZAP_ONE_LINE (0x0310) -#define v_MMU_ZAP_ONE_LINE(x) (((x)&0xffffffff)<<0) -#define m_MMU_ZAP_ONE_LINE (0xffffffff<<0) - -#define MMU_INT_RAWSTAT (0x0314) -#define v_PAGE_FAULT_RAWSTAT(x) (((x)&1)<<0) -#define v_READ_BUS_ERROR_RAWSTAT(x) (((x)&1)<<1) -#define m_PAGE_FAULT_RAWSTAT (1<<0) -#define m_READ_BUS_ERROR_RAWSTAT (1<<1) - -#define MMU_INT_CLEAR (0x0318) -#define v_PAGE_FAULT_CLEAR(x) (((x)&1)<<0) -#define v_READ_BUS_ERROR_CLEAR(x) (((x)&1)<<1) -#define m_PAGE_FAULT_CLEAR (1<<0) -#define m_READ_BUS_ERROR_CLEAR (1<<1) - -#define MMU_INT_MASK (0x031c) -#define v_PAGE_FAULT_MASK(x) (((x)&1)<<0) -#define v_READ_BUS_ERROR_MASK(x) (((x)&1)<<1) -#define m_PAGE_FAULT_MASK (1<<0) -#define m_READ_BUS_ERROR_MASK (1<<1) - -#define MMU_INT_STATUS (0x0320) -#define v_PAGE_FAULT_STATUS(x) (((x)&1)<<0) -#define v_READ_BUS_ERROR_STATUS(x) (((x)&1)<<1) -#define m_PAGE_FAULT_STATUS (1<<0) -#define m_READ_BUS_ERROR_STATUS (1<<1) - -#define MMU_AUTO_GATING (0x0324) -#define v_MMU_AUTO_GATING(x) (((x)&1)<<0) -#define m_MMU_AUTO_GATING (1<<0) - -#define WIN2_LUT_ADDR (0x0400) -#define WIN3_LUT_ADDR (0x0800) -#define HWC_LUT_ADDR (0x0c00) -#define GAMMA_LUT_ADDR (0x1000) -#define CABC_LUT_ADDR (0x2000) -#define MCU_BYPASS_WPORT (0x2200) -#define MCU_BYPASS_RPORT (0x2300) - -#define PWM_MODE_ONE_SHOT (0x0) -#define PWM_MODE_CONTINUOUS (0x1) -#define PWM_MODE_CAPTURE (0x2) -enum lb_mode { - LB_YUV_3840X5 = 0x0, - LB_YUV_2560X8 = 0x1, - LB_RGB_3840X2 = 0x2, - LB_RGB_2560X4 = 0x3, - LB_RGB_1920X5 = 0x4, - LB_RGB_1280X8 = 0x5 -}; - -enum sacle_up_mode { - SCALE_UP_BIL = 0x0, - SCALE_UP_BIC = 0x1 -}; - -enum scale_down_mode { - SCALE_DOWN_BIL = 0x0, - SCALE_DOWN_AVG = 0x1 -}; - -/*ALPHA BLENDING MODE*/ -enum alpha_mode { /* Fs Fd */ - AB_USER_DEFINE = 0x0, - AB_CLEAR = 0x1,/* 0 0*/ - AB_SRC = 0x2,/* 1 0*/ - AB_DST = 0x3,/* 0 1 */ - AB_SRC_OVER = 0x4,/* 1 1-As''*/ - AB_DST_OVER = 0x5,/* 1-Ad'' 1*/ - AB_SRC_IN = 0x6, - AB_DST_IN = 0x7, - AB_SRC_OUT = 0x8, - AB_DST_OUT = 0x9, - AB_SRC_ATOP = 0xa, - AB_DST_ATOP = 0xb, - XOR = 0xc, - AB_SRC_OVER_GLOBAL = 0xd -}; /*alpha_blending_mode*/ - -enum src_alpha_mode { - AA_STRAIGHT = 0x0, - AA_INVERSE = 0x1 -};/*src_alpha_mode*/ - -enum global_alpha_mode { - AA_GLOBAL = 0x0, - AA_PER_PIX = 0x1, - AA_PER_PIX_GLOBAL = 0x2 -};/*src_global_alpha_mode*/ - -enum src_alpha_sel { - AA_SAT = 0x0, - AA_NO_SAT = 0x1 -};/*src_alpha_sel*/ - -enum src_color_mode { - AA_SRC_PRE_MUL = 0x0, - AA_SRC_NO_PRE_MUL = 0x1 -};/*src_color_mode*/ - -enum factor_mode { - AA_ZERO = 0x0, - AA_ONE = 0x1, - AA_SRC = 0x2, - AA_SRC_INVERSE = 0x3, - AA_SRC_GLOBAL = 0x4 -};/*src_factor_mode && dst_factor_mode*/ - -enum cabc_stage_mode { - LAST_FRAME_PWM_VAL = 0x0, - CUR_FRAME_PWM_VAL = 0x1, - STAGE_BY_STAGE = 0x2 -}; - -struct lcdc_device{ - int id; - struct rk_lcdc_driver driver; - struct device *dev; - struct rk_screen *screen; - - void __iomem *regs; - void *regsbak; /*back up reg*/ - u32 reg_phy_base; /* physical basic address of lcdc register*/ - u32 len; /* physical map length of lcdc register*/ - spinlock_t reg_lock; /*one time only one process allowed to config the register*/ - - int __iomem *dsp_lut_addr_base; - - - int prop; /*used for primary or extended display device*/ - bool pre_init; - bool pwr18; /*if lcdc use 1.8v power supply*/ - bool clk_on; /*if aclk or hclk is closed ,acess to register is not allowed*/ - u8 atv_layer_cnt; /*active layer counter,when atv_layer_cnt = 0,disable lcdc*/ - - - unsigned int irq; - - struct clk *pd; /*lcdc power domain*/ - struct clk *hclk; /*lcdc AHP clk*/ - struct clk *dclk; /*lcdc dclk*/ - struct clk *aclk; /*lcdc share memory frequency*/ - u32 pixclock; - - u32 standby; /*1:standby,0:wrok*/ - u32 iommu_status; -}; - -struct alpha_config{ - enum src_alpha_mode src_alpha_mode; /*win0_src_alpha_m0*/ - u32 src_global_alpha_val; /*win0_src_global_alpha*/ - enum global_alpha_mode src_global_alpha_mode;/*win0_src_blend_m0*/ - enum src_alpha_sel src_alpha_cal_m0; /*win0_src_alpha_cal_m0*/ - enum src_color_mode src_color_mode; /*win0_src_color_m0*/ - enum factor_mode src_factor_mode; /*win0_src_factor_m0*/ - enum factor_mode dst_factor_mode; /*win0_dst_factor_m0*/ -}; - -struct lcdc_cabc_mode { - u32 pixel_num; /* pixel precent number */ - u16 stage_up; /* up stride */ - u16 stage_down; /* down stride */ -}; - -static inline void lcdc_writel(struct lcdc_device *lcdc_dev,u32 offset,u32 v) -{ - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - *_pv = v; - writel_relaxed(v,lcdc_dev->regs+offset); -} - -static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev,u32 offset) -{ - u32 v; - v = readl_relaxed(lcdc_dev->regs+offset); - return v; -} - -static inline u32 lcdc_read_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk) -{ - u32 *_pv = (u32*)lcdc_dev->regsbak; - u32 _v = readl_relaxed(lcdc_dev->regs+offset); - _pv += (offset >> 2); - *_pv = _v; - _v &= msk; - return (_v?1:0); -} - -static inline void lcdc_set_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk) -{ - u32* _pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) |= msk; - writel_relaxed(*_pv,lcdc_dev->regs + offset); -} - -static inline void lcdc_clr_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk) -{ - u32* _pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) &= (~msk); - writel_relaxed(*_pv,lcdc_dev->regs + offset); -} - -static inline void lcdc_msk_reg(struct lcdc_device *lcdc_dev,u32 offset,u32 msk,u32 v) -{ - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) &= (~msk); - (*_pv) |= v; - writel_relaxed(*_pv,lcdc_dev->regs+offset); -} - -static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev) -{ - writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE); - dsb(); -} - -#define CUBIC_PRECISE 0 -#define CUBIC_SPLINE 1 -#define CUBIC_CATROM 2 -#define CUBIC_MITCHELL 3 - -#define CUBIC_MODE_SELETION CUBIC_PRECISE - -/*****************************************************************************************************/ -#define SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT 12 /* 4.12*/ -#define SCALE_FACTOR_BILI_DN_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT))) - -#define SCALE_FACTOR_BILI_UP_FIXPOINT_SHIFT 16 /* 0.16*/ - -#define SCALE_FACTOR_AVRG_FIXPOINT_SHIFT 16 /*0.16*/ -#define SCALE_FACTOR_AVRG_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_FACTOR_AVRG_FIXPOINT_SHIFT))) - -#define SCALE_FACTOR_BIC_FIXPOINT_SHIFT 16 /* 0.16*/ -#define SCALE_FACTOR_BIC_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_FACTOR_BIC_FIXPOINT_SHIFT))) - -#define SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT 12 /*NONE SCALE,vsd_bil*/ -#define SCALE_FACTOR_VSDBIL_FIXPOINT_SHIFT 12 /*VER SCALE DOWN BIL*/ - -/*****************************************************************************************************/ - -/*#define GET_SCALE_FACTOR_BILI(src, dst) ((((src) - 1) << SCALE_FACTOR_BILI_FIXPOINT_SHIFT) / ((dst) - 1))*/ -/*#define GET_SCALE_FACTOR_BIC(src, dst) ((((src) - 1) << SCALE_FACTOR_BIC_FIXPOINT_SHIFT) / ((dst) - 1))*/ -/*modified by hpz*/ -#define GET_SCALE_FACTOR_BILI_DN(src, dst) ((((src)*2 - 3) << (SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT-1)) / ((dst) - 1)) -#define GET_SCALE_FACTOR_BILI_UP(src, dst) ((((src)*2 - 3) << (SCALE_FACTOR_BILI_UP_FIXPOINT_SHIFT-1)) / ((dst) - 1)) -#define GET_SCALE_FACTOR_BIC(src, dst) ((((src)*2 - 3) << (SCALE_FACTOR_BIC_FIXPOINT_SHIFT-1)) / ((dst) - 1)) - -/*****************************************************************/ -/*NOTE: hardwareΪ½ÚÊ¡¿ªÏú, srcHÏȳéÐеõ½ (srcH+vScaleDnMult-1)/vScaleDnMult; È»ºóËõ·Å*/ -#define GET_SCALE_DN_ACT_HEIGHT(srcH, vScaleDnMult) (((srcH)+(vScaleDnMult)-1)/(vScaleDnMult)) - -/*#define VSKIP_MORE_PRECISE*/ - -#ifdef VSKIP_MORE_PRECISE -#define MIN_SCALE_FACTOR_AFTER_VSKIP 1.5f -#define GET_SCALE_FACTOR_BILI_DN_VSKIP(srcH, dstH, vScaleDnMult) \ - (GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT((srcH), (vScaleDnMult)), (dstH))) -#else -#define MIN_SCALE_FACTOR_AFTER_VSKIP 1 -#define GET_SCALE_FACTOR_BILI_DN_VSKIP(srcH, dstH, vScaleDnMult) \ - ((GET_SCALE_DN_ACT_HEIGHT((srcH), (vScaleDnMult)) == (dstH))\ - ? (GET_SCALE_FACTOR_BILI_DN((srcH), (dstH))/(vScaleDnMult))\ - : GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT((srcH), (vScaleDnMult)), (dstH))) -#endif -/*****************************************************************/ - - -/*ScaleFactor must >= dst/src, or pixels at end of line may be unused*/ -/*ScaleFactor must < dst/(src-1), or dst buffer may overflow*/ -/*avrg old code: ((((dst) << SCALE_FACTOR_AVRG_FIXPOINT_SHIFT))/((src) - 1)) hxx_chgsrc*/ -/*modified by hpz:*/ -#define GET_SCALE_FACTOR_AVRG(src, dst) ((((dst) << (SCALE_FACTOR_AVRG_FIXPOINT_SHIFT+1)))/(2*(src) - 1)) - -/*****************************************************************************************************/ -/*Scale Coordinate Accumulate, x.16*/ -#define SCALE_COOR_ACC_FIXPOINT_SHIFT 16 -#define SCALE_COOR_ACC_FIXPOINT_ONE (1 << SCALE_COOR_ACC_FIXPOINT_SHIFT) -#define SCALE_COOR_ACC_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_COOR_ACC_FIXPOINT_SHIFT))) -#define SCALE_COOR_ACC_FIXPOINT_REVERT(x) ((((x) >> (SCALE_COOR_ACC_FIXPOINT_SHIFT-1)) + 1) >> 1) - -#define SCALE_GET_COOR_ACC_FIXPOINT(scaleFactor, factorFixpointShift) \ - ((scaleFactor) << (SCALE_COOR_ACC_FIXPOINT_SHIFT - (factorFixpointShift))) - - -/*****************************************************************************************************/ -/*CoarsePart of Scale Coordinate Accumulate, used for pixel mult-add factor, 0.8*/ -#define SCALE_FILTER_FACTOR_FIXPOINT_SHIFT 8 -#define SCALE_FILTER_FACTOR_FIXPOINT_ONE (1 << SCALE_FILTER_FACTOR_FIXPOINT_SHIFT) -#define SCALE_FILTER_FACTOR_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_FILTER_FACTOR_FIXPOINT_SHIFT))) -#define SCALE_FILTER_FACTOR_FIXPOINT_REVERT(x) ((((x) >> (SCALE_FILTER_FACTOR_FIXPOINT_SHIFT-1)) + 1) >> 1) - -#define SCALE_GET_FILTER_FACTOR_FIXPOINT(coorAccumulate, coorAccFixpointShift) \ - (((coorAccumulate)>>((coorAccFixpointShift)-SCALE_FILTER_FACTOR_FIXPOINT_SHIFT))&(SCALE_FILTER_FACTOR_FIXPOINT_ONE-1)) - -#define SCALE_OFFSET_FIXPOINT_SHIFT 8 -#define SCALE_OFFSET_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_OFFSET_FIXPOINT_SHIFT))) - -u32 getHardWareVSkipLines(u32 srcH, u32 dstH) -{ - u32 vScaleDnMult; - - if(srcH >= (u32)(4*dstH*MIN_SCALE_FACTOR_AFTER_VSKIP)) - { - vScaleDnMult = 4; - } - else if(srcH >= (u32)(2*dstH*MIN_SCALE_FACTOR_AFTER_VSKIP)) - { - vScaleDnMult = 2; - } - else - { - vScaleDnMult = 1; - } - - return vScaleDnMult; -} -#endif diff --git a/drivers/video/rockchip/lcdc/rk3368_lcdc.c b/drivers/video/rockchip/lcdc/rk3368_lcdc.c deleted file mode 100644 index 7ddd64da896f..000000000000 --- a/drivers/video/rockchip/lcdc/rk3368_lcdc.c +++ /dev/null @@ -1,5229 +0,0 @@ -/* - * drivers/video/rockchip/lcdc/rk3368_lcdc.c - * - * Copyright (C) 2014 ROCKCHIP, Inc. - *Author:hjc - *This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "rk3368_lcdc.h" - -#if defined(CONFIG_HAS_EARLYSUSPEND) -#include -#endif -/*#define CONFIG_RK_FPGA 1*/ - -static int dbg_thresd; -module_param(dbg_thresd, int, S_IRUGO | S_IWUSR); - -#define DBG(level, x...) do { \ - if (unlikely(dbg_thresd >= level)) \ - pr_info(x);\ - } while (0) - -#define EARLY_TIME 500 /*us*/ -static struct rk_lcdc_win lcdc_win[] = { - [0] = { - .name = "win0", - .id = 0, - .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_SCALE | - SUPPORT_YUV, - .property.max_input_x = 4096, - .property.max_input_y = 2304 - }, - [1] = { - .name = "win1", - .id = 1, - .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_SCALE | - SUPPORT_YUV, - .property.max_input_x = 4096, - .property.max_input_y = 2304 - }, - [2] = { - .name = "win2", - .id = 2, - .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_MULTI_AREA, - .property.max_input_x = 4096, - .property.max_input_y = 2304 - }, - [3] = { - .name = "win3", - .id = 3, - .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_MULTI_AREA, - .property.max_input_x = 4096, - .property.max_input_y = 2304 - }, - [4] = { - .name = "hwc", - .id = 4, - .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HWC_LAYER, - .property.max_input_x = 128, - .property.max_input_y = 128 - }, -}; - -static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable); - -/*#define WAIT_FOR_SYNC 1*/ -u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth) -{ - u32 vscalednmult; - - if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP)) - vscalednmult = 4; - else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP)) - vscalednmult = 2; - else - vscalednmult = 1; - - return vscalednmult; -} - - -static int rk3368_set_cabc_lut(struct rk_lcdc_driver *dev_drv, int *cabc_lut) -{ - int i; - int __iomem *c; - u32 v; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN, - v_CABC_LUT_EN(0)); - lcdc_cfg_done(lcdc_dev); - mdelay(25); - for (i = 0; i < 128; i++) { - v = cabc_lut[i]; - c = lcdc_dev->cabc_lut_addr_base + i; - writel_relaxed(v, c); - } - lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN, - v_CABC_LUT_EN(1)); - return 0; -} - - -static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut) -{ - int i; - int __iomem *c; - u32 v; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, - v_DSP_LUT_EN(0)); - lcdc_cfg_done(lcdc_dev); - mdelay(25); - for (i = 0; i < 256; i++) { - v = dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base + i; - writel_relaxed(v, c); - } - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, - v_DSP_LUT_EN(1)); - - return 0; -} - -static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev) -{ -#ifdef CONFIG_RK_FPGA - lcdc_dev->clk_on = 1; - return 0; -#endif - if (!lcdc_dev->clk_on) { - clk_prepare_enable(lcdc_dev->hclk); - clk_prepare_enable(lcdc_dev->dclk); - clk_prepare_enable(lcdc_dev->aclk); - if (lcdc_dev->pd) - clk_prepare_enable(lcdc_dev->pd); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) - pm_runtime_get_sync(lcdc_dev->dev); -#endif - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 1; - spin_unlock(&lcdc_dev->reg_lock); - } - - return 0; -} - -static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev) -{ -#ifdef CONFIG_RK_FPGA - lcdc_dev->clk_on = 0; - return 0; -#endif - if (lcdc_dev->clk_on) { - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 0; - spin_unlock(&lcdc_dev->reg_lock); - mdelay(25); - if (lcdc_dev->pd) - clk_disable_unprepare(lcdc_dev->pd); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) - pm_runtime_put(lcdc_dev->dev); -#endif - clk_disable_unprepare(lcdc_dev->dclk); - clk_disable_unprepare(lcdc_dev->hclk); - clk_disable_unprepare(lcdc_dev->aclk); - } - - return 0; -} - -static int __maybe_unused - rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev) -{ - u32 mask, val; - u32 intr_en_reg, intr_clr_reg; - - if (lcdc_dev->soc_type == VOP_FULL_RK3366) { - intr_clr_reg = INTR_CLEAR_RK3366; - intr_en_reg = INTR_EN_RK3366; - } else { - intr_clr_reg = INTR_CLEAR_RK3368; - intr_en_reg = INTR_EN_RK3368; - } - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN | - m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN | - m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN | - m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN | - m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN | - m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN | - m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN; - val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) | - v_ADDR_SAME_INTR_EN(0) | - v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) | - v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) | - v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) | - v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) | - v_POST_BUF_EMPTY_INTR_EN(0) | - v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0); - lcdc_msk_reg(lcdc_dev, intr_en_reg, mask, val); - - mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | - m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR | - m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR | - m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR | - m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR | - m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR | - m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR; - val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) | - v_ADDR_SAME_INTR_CLR(1) | - v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) | - v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) | - v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) | - v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) | - v_POST_BUF_EMPTY_INTR_CLR(1) | - v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1); - lcdc_msk_reg(lcdc_dev, intr_clr_reg, mask, val); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - } - mdelay(1); - return 0; -} - -static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int *cbase = (int *)lcdc_dev->regs; - int *regsbak = (int *)lcdc_dev->regsbak; - int i, j, val; - char dbg_message[30]; - char buf[10]; - - pr_info("lcd back up reg:\n"); - memset(dbg_message, 0, sizeof(dbg_message)); - memset(buf, 0, sizeof(buf)); - for (i = 0; i <= (0x200 >> 4); i++) { - val = sprintf(dbg_message, "0x%04x: ", i * 16); - for (j = 0; j < 4; j++) { - val = sprintf(buf, "%08x ", *(regsbak + i * 4 + j)); - strcat(dbg_message, buf); - } - pr_info("%s\n", dbg_message); - memset(dbg_message, 0, sizeof(dbg_message)); - memset(buf, 0, sizeof(buf)); - } - - pr_info("lcdc reg:\n"); - for (i = 0; i <= (0x200 >> 4); i++) { - val = sprintf(dbg_message, "0x%04x: ", i * 16); - for (j = 0; j < 4; j++) { - sprintf(buf, "%08x ", - readl_relaxed(cbase + i * 4 + j)); - strcat(dbg_message, buf); - } - pr_info("%s\n", dbg_message); - memset(dbg_message, 0, sizeof(dbg_message)); - memset(buf, 0, sizeof(buf)); - } - - return 0; -} - -#define WIN_EN(id) \ -static int win##id##_enable(struct lcdc_device *lcdc_dev, int en) \ -{ \ - u32 msk, val; \ - spin_lock(&lcdc_dev->reg_lock); \ - msk = m_WIN##id##_EN; \ - val = v_WIN##id##_EN(en); \ - lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val); \ - lcdc_cfg_done(lcdc_dev); \ - spin_unlock(&lcdc_dev->reg_lock); \ - return 0; \ -} - -WIN_EN(0); -WIN_EN(1); -WIN_EN(2); -WIN_EN(3); -/*enable/disable win directly*/ -static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv, - int win_id, int en) -{ - struct lcdc_device *lcdc_dev = - container_of(drv, struct lcdc_device, driver); - if (win_id == 0) - win0_enable(lcdc_dev, en); - else if (win_id == 1) - win1_enable(lcdc_dev, en); - else if (win_id == 2) - win2_enable(lcdc_dev, en); - else if (win_id == 3) - win3_enable(lcdc_dev, en); - else - dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id); - return 0; -} - -#define SET_WIN_ADDR(id) \ -static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \ -{ \ - u32 msk, val; \ - spin_lock(&lcdc_dev->reg_lock); \ - lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr); \ - msk = m_WIN##id##_EN; \ - val = v_WIN0_EN(1); \ - lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val); \ - lcdc_cfg_done(lcdc_dev); \ - spin_unlock(&lcdc_dev->reg_lock); \ - return 0; \ -} - -SET_WIN_ADDR(0); -SET_WIN_ADDR(1); -int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv, - int win_id, u32 addr) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - if (win_id == 0) - set_win0_addr(lcdc_dev, addr); - else - set_win1_addr(lcdc_dev, addr); - - return 0; -} - -static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev) -{ - int reg = 0; - u32 val = 0; - struct rk_screen *screen = lcdc_dev->driver.cur_screen; - u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin; - u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin; - u32 st_x = 0, st_y = 0; - struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0]; - - spin_lock(&lcdc_dev->reg_lock); - for (reg = 0; reg < SCAN_LINE_NUM; reg += 4) { - val = lcdc_readl_backup(lcdc_dev, reg); - switch (reg) { - case VERSION_INFO: - lcdc_dev->soc_type = val; - break; - case WIN0_ACT_INFO: - win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1; - win0->area[0].yact = - ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1; - break; - case WIN0_DSP_INFO: - win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1; - win0->area[0].ysize = - ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1; - break; - case WIN0_DSP_ST: - st_x = val & m_WIN0_DSP_XST; - st_y = (val & m_WIN0_DSP_YST) >> 16; - win0->area[0].xpos = st_x - h_pw_bp; - win0->area[0].ypos = st_y - v_pw_bp; - break; - case WIN0_CTRL0: - win0->state = val & m_WIN0_EN; - win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1; - win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4; - win0->area[0].format = win0->area[0].fmt_cfg; - break; - case WIN0_VIR: - win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE; - win0->area[0].uv_vir_stride = - (val & m_WIN0_VIR_STRIDE_UV) >> 16; - if (win0->area[0].format == ARGB888) - win0->area[0].xvir = win0->area[0].y_vir_stride; - else if (win0->area[0].format == RGB888) - win0->area[0].xvir = - win0->area[0].y_vir_stride * 4 / 3; - else if (win0->area[0].format == RGB565) - win0->area[0].xvir = - 2 * win0->area[0].y_vir_stride; - else /* YUV */ - win0->area[0].xvir = - 4 * win0->area[0].y_vir_stride; - break; - case WIN0_YRGB_MST: - win0->area[0].smem_start = val; - break; - case WIN0_CBR_MST: - win0->area[0].cbr_start = val; - break; - case DSP_VACT_ST_END: - if (support_uboot_display()) { - screen->mode.yres = - (val & 0x1fff) - ((val >> 16) & 0x1fff); - win0->area[0].ypos = - st_y - ((val >> 16) & 0x1fff); - } - break; - case DSP_HACT_ST_END: - if (support_uboot_display()) { - screen->mode.xres = - (val & 0x1fff) - ((val >> 16) & 0x1fff); - win0->area[0].xpos = - st_x - ((val >> 16) & 0x1fff); - } - break; - default: - break; - } - } - spin_unlock(&lcdc_dev->reg_lock); -} - -/********do basic init*********/ -static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv) -{ - u32 mask, val; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - if (lcdc_dev->pre_init) - return 0; - - lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc"); - lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc"); - lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc"); - if ((IS_ERR(lcdc_dev->aclk)) || (IS_ERR(lcdc_dev->dclk)) || - (IS_ERR(lcdc_dev->hclk))) { - dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n", - lcdc_dev->id); - } - - lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc"); - if (IS_ERR(lcdc_dev->pd)) { - dev_err(lcdc_dev->dev, "failed to get lcdc%d pdclk source\n", - lcdc_dev->id); - lcdc_dev->pd = NULL; - } - - if (!support_uboot_display()) - rk_disp_pwr_enable(dev_drv); - rk3368_lcdc_clk_enable(lcdc_dev); - - /*backup reg config at uboot */ - lcdc_read_reg_defalut_cfg(lcdc_dev); - if (lcdc_dev->soc_type == VOP_FULL_RK3366) - lcdc_grf_writel(lcdc_dev->grf_base, RK3366_GRF_IO_VSEL, - RK3366_GRF_VOP_IOVOL_SEL(lcdc_dev->pwr18)); - else - lcdc_grf_writel(lcdc_dev->pmugrf_base, - PMUGRF_SOC_CON0_VOP, - RK3368_GRF_VOP_IOVOL_SEL(lcdc_dev->pwr18)); - - lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_0,0x15110903); - lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_1,0x00030911); - lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_0,0x1a150b04); - lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_1,0x00040b15); - lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_0,0x15110903); - lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_1,0x00030911); - - lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821); - lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412); - lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696); - lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969); - lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb); - lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de); - - mask = m_AUTO_GATING_EN; - val = v_AUTO_GATING_EN(0); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - mask = m_DITHER_UP_EN; - val = v_DITHER_UP_EN(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - lcdc_cfg_done(lcdc_dev); - /*disable win0 to workaround iommu pagefault */ - /*if (dev_drv->iommu_enabled) */ - /* win0_enable(lcdc_dev, 0); */ - lcdc_dev->pre_init = true; - - return 0; -} - -static void rk3368_lcdc_deint(struct lcdc_device *lcdc_dev) -{ - u32 mask, val; - - if (lcdc_dev->clk_on) { - rk3368_lcdc_disable_irq(lcdc_dev); - spin_lock(&lcdc_dev->reg_lock); - mask = m_WIN0_EN; - val = v_WIN0_EN(0); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val); - lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val); - - mask = m_WIN2_EN | m_WIN2_MST0_EN | - m_WIN2_MST1_EN | - m_WIN2_MST2_EN | m_WIN2_MST3_EN; - val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) | - v_WIN2_MST1_EN(0) | - v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val); - lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - mdelay(50); - } -} - -static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u16 x_res = screen->mode.xres; - u16 y_res = screen->mode.yres; - u32 mask, val; - u16 h_total, v_total; - u16 post_hsd_en, post_vsd_en; - u16 post_dsp_hact_st, post_dsp_hact_end; - u16 post_dsp_vact_st, post_dsp_vact_end; - u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1; - u16 post_h_fac, post_v_fac; - - screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200; - screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200; - screen->post_xsize = x_res * - (dev_drv->overscan.left + dev_drv->overscan.right) / 200; - screen->post_ysize = y_res * - (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200; - - h_total = screen->mode.hsync_len + screen->mode.left_margin + - x_res + screen->mode.right_margin; - v_total = screen->mode.vsync_len + screen->mode.upper_margin + - y_res + screen->mode.lower_margin; - - if (screen->post_dsp_stx + screen->post_xsize > x_res) { - dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n", - screen->post_dsp_stx, screen->post_xsize, x_res); - screen->post_dsp_stx = x_res - screen->post_xsize; - } - if (screen->x_mirror == 0) { - post_dsp_hact_st = screen->post_dsp_stx + - screen->mode.hsync_len + screen->mode.left_margin; - post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize; - } else { - post_dsp_hact_end = h_total - screen->mode.right_margin - - screen->post_dsp_stx; - post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize; - } - if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) { - post_hsd_en = 1; - post_h_fac = - GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize); - } else { - post_hsd_en = 0; - post_h_fac = 0x1000; - } - - if (screen->post_dsp_sty + screen->post_ysize > y_res) { - dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n", - screen->post_dsp_sty, screen->post_ysize, y_res); - screen->post_dsp_sty = y_res - screen->post_ysize; - } - - if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) { - post_vsd_en = 1; - post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res, - screen->post_ysize); - } else { - post_vsd_en = 0; - post_v_fac = 0x1000; - } - - if (screen->mode.vmode & FB_VMODE_INTERLACED) { - post_dsp_vact_st = screen->post_dsp_sty / 2 + - screen->mode.vsync_len + - screen->mode.upper_margin; - post_dsp_vact_end = post_dsp_vact_st + - screen->post_ysize / 2; - - post_dsp_vact_st_f1 = screen->mode.vsync_len + - screen->mode.upper_margin + - y_res/2 + - screen->mode.lower_margin + - screen->mode.vsync_len + - screen->mode.upper_margin + - screen->post_dsp_sty / 2 + - 1; - post_dsp_vact_end_f1 = post_dsp_vact_st_f1 + - screen->post_ysize/2; - } else { - if (screen->y_mirror == 0) { - post_dsp_vact_st = screen->post_dsp_sty + - screen->mode.vsync_len + - screen->mode.upper_margin; - post_dsp_vact_end = post_dsp_vact_st + - screen->post_ysize; - } else { - post_dsp_vact_end = v_total - - screen->mode.lower_margin - - screen->post_dsp_sty; - post_dsp_vact_st = post_dsp_vact_end - - screen->post_ysize; - } - post_dsp_vact_st_f1 = 0; - post_dsp_vact_end_f1 = 0; - } - DBG(1, "post:xsize=%d,ysize=%d,xpos=%d", - screen->post_xsize, screen->post_ysize, screen->xpos); - DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n", - screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac); - mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST; - val = v_DSP_HACT_END_POST(post_dsp_hact_end) | - v_DSP_HACT_ST_POST(post_dsp_hact_st); - lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val); - - mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST; - val = v_DSP_VACT_END_POST(post_dsp_vact_end) | - v_DSP_VACT_ST_POST(post_dsp_vact_st); - lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val); - - mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB; - val = v_POST_HS_FACTOR_YRGB(post_h_fac) | - v_POST_VS_FACTOR_YRGB(post_v_fac); - lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val); - - mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1; - val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) | - v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1); - lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val); - - mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN; - val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en); - lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val); - return 0; -} - -static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win; - u32 colorkey_r, colorkey_g, colorkey_b; - int i, key_val; - - for (i = 0; i < 4; i++) { - win = dev_drv->win[i]; - key_val = win->color_key_val; - colorkey_r = (key_val & 0xff) << 2; - colorkey_g = ((key_val >> 8) & 0xff) << 12; - colorkey_b = ((key_val >> 16) & 0xff) << 22; - /*color key dither 565/888->aaa */ - key_val = colorkey_r | colorkey_g | colorkey_b; - switch (i) { - case 0: - lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val); - break; - case 1: - lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val); - break; - case 2: - lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val); - break; - case 3: - lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val); - break; - default: - pr_info("%s:un support win num:%d\n", - __func__, i); - break; - } - } - return 0; -} - -static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - struct alpha_config alpha_config; - u32 mask, val; - int ppixel_alpha = 0, global_alpha = 0, i; - u32 src_alpha_ctl = 0, dst_alpha_ctl = 0; - - memset(&alpha_config, 0, sizeof(struct alpha_config)); - for (i = 0; i < win->area_num; i++) { - ppixel_alpha |= ((win->area[i].format == ARGB888) || - (win->area[i].format == FBDC_ARGB_888) || - (win->area[i].format == FBDC_ABGR_888) || - (win->area[i].format == ABGR888)) ? 1 : 0; - } - global_alpha = (win->g_alpha_val == 0) ? 0 : 1; - alpha_config.src_global_alpha_val = win->g_alpha_val; - win->alpha_mode = AB_SRC_OVER; - switch (win->alpha_mode) { - case AB_USER_DEFINE: - break; - case AB_CLEAR: - alpha_config.src_factor_mode = AA_ZERO; - alpha_config.dst_factor_mode = AA_ZERO; - break; - case AB_SRC: - alpha_config.src_factor_mode = AA_ONE; - alpha_config.dst_factor_mode = AA_ZERO; - break; - case AB_DST: - alpha_config.src_factor_mode = AA_ZERO; - alpha_config.dst_factor_mode = AA_ONE; - break; - case AB_SRC_OVER: - alpha_config.src_color_mode = AA_SRC_PRE_MUL; - if (global_alpha) - alpha_config.src_factor_mode = AA_SRC_GLOBAL; - else - alpha_config.src_factor_mode = AA_ONE; - alpha_config.dst_factor_mode = AA_SRC_INVERSE; - break; - case AB_DST_OVER: - alpha_config.src_color_mode = AA_SRC_PRE_MUL; - alpha_config.src_factor_mode = AA_SRC_INVERSE; - alpha_config.dst_factor_mode = AA_ONE; - break; - case AB_SRC_IN: - alpha_config.src_color_mode = AA_SRC_PRE_MUL; - alpha_config.src_factor_mode = AA_SRC; - alpha_config.dst_factor_mode = AA_ZERO; - break; - case AB_DST_IN: - alpha_config.src_factor_mode = AA_ZERO; - alpha_config.dst_factor_mode = AA_SRC; - break; - case AB_SRC_OUT: - alpha_config.src_color_mode = AA_SRC_PRE_MUL; - alpha_config.src_factor_mode = AA_SRC_INVERSE; - alpha_config.dst_factor_mode = AA_ZERO; - break; - case AB_DST_OUT: - alpha_config.src_factor_mode = AA_ZERO; - alpha_config.dst_factor_mode = AA_SRC_INVERSE; - break; - case AB_SRC_ATOP: - alpha_config.src_color_mode = AA_SRC_PRE_MUL; - alpha_config.src_factor_mode = AA_SRC; - alpha_config.dst_factor_mode = AA_SRC_INVERSE; - break; - case AB_DST_ATOP: - alpha_config.src_color_mode = AA_SRC_PRE_MUL; - alpha_config.src_factor_mode = AA_SRC_INVERSE; - alpha_config.dst_factor_mode = AA_SRC; - break; - case XOR: - alpha_config.src_color_mode = AA_SRC_PRE_MUL; - alpha_config.src_factor_mode = AA_SRC_INVERSE; - alpha_config.dst_factor_mode = AA_SRC_INVERSE; - break; - case AB_SRC_OVER_GLOBAL: - alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL; - alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL; - alpha_config.src_factor_mode = AA_SRC_GLOBAL; - alpha_config.dst_factor_mode = AA_SRC_INVERSE; - break; - default: - pr_err("alpha mode error\n"); - break; - } - if ((ppixel_alpha == 1) && (global_alpha == 1)) - alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL; - else if (ppixel_alpha == 1) - alpha_config.src_global_alpha_mode = AA_PER_PIX; - else if (global_alpha == 1) - alpha_config.src_global_alpha_mode = AA_GLOBAL; - else - dev_warn(lcdc_dev->dev, "alpha_en should be 0\n"); - alpha_config.src_alpha_mode = AA_STRAIGHT; - alpha_config.src_alpha_cal_m0 = AA_NO_SAT; - - switch (win_id) { - case 0: - src_alpha_ctl = 0x60; - dst_alpha_ctl = 0x64; - break; - case 1: - src_alpha_ctl = 0xa0; - dst_alpha_ctl = 0xa4; - break; - case 2: - src_alpha_ctl = 0xdc; - dst_alpha_ctl = 0xec; - break; - case 3: - src_alpha_ctl = 0x12c; - dst_alpha_ctl = 0x13c; - break; - case 4: - src_alpha_ctl = 0x160; - dst_alpha_ctl = 0x164; - break; - } - mask = m_WIN0_DST_FACTOR_M0; - val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode); - lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val); - mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 | - m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 | - m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 | - m_WIN0_SRC_GLOBAL_ALPHA; - val = v_WIN0_SRC_ALPHA_EN(1) | - v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) | - v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) | - v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) | - v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) | - v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) | - v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val); - lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val); - - return 0; -} - -static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num) -{ - struct rk_lcdc_win_area area_temp; - int i, j; - - for (i = 0; i < area_num; i++) { - for (j = i + 1; j < area_num; j++) { - if (win->area[i].dsp_stx > win->area[j].dsp_stx) { - memcpy(&area_temp, &win->area[i], - sizeof(struct rk_lcdc_win_area)); - memcpy(&win->area[i], &win->area[j], - sizeof(struct rk_lcdc_win_area)); - memcpy(&win->area[j], &area_temp, - sizeof(struct rk_lcdc_win_area)); - } - } - } - - return 0; -} - -static int __maybe_unused - rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num) -{ - struct rk_lcdc_win_area area_temp; - - switch (area_num) { - case 2: - area_temp = win->area[0]; - win->area[0] = win->area[1]; - win->area[1] = area_temp; - break; - case 3: - area_temp = win->area[0]; - win->area[0] = win->area[2]; - win->area[2] = area_temp; - break; - case 4: - area_temp = win->area[0]; - win->area[0] = win->area[3]; - win->area[3] = area_temp; - - area_temp = win->area[1]; - win->area[1] = win->area[2]; - win->area[2] = area_temp; - break; - default: - pr_info("un supported area num!\n"); - break; - } - return 0; -} - -static int __maybe_unused -rk3368_win_area_check_var(int win_id, int area_num, - struct rk_lcdc_win_area *area_pre, - struct rk_lcdc_win_area *area_now) -{ - if ((area_pre->xpos > area_now->xpos) || - ((area_pre->xpos + area_pre->xsize > area_now->xpos) && - (area_pre->ypos + area_pre->ysize > area_now->ypos))) { - area_now->state = 0; - pr_err("win[%d]:\n" - "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n" - "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n", - win_id, - area_num - 1, area_pre->xpos, area_pre->xsize, - area_pre->ypos, area_pre->ysize, - area_num, area_now->xpos, area_now->xsize, - area_now->ypos, area_now->ysize); - return -EINVAL; - } - return 0; -} - -static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 val, i; - - for (i = 0; i < 100; i++) { - val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0); - val &= m_DBG_IFBDC_IDLE; - if (val) - continue; - else - mdelay(10); - }; - return val; -} - -static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - u32 mask, val; - - if (lcdc_dev->soc_type != VOP_FULL_RK3368) { - pr_err("soc: 0x%08x not support FBDC\n", lcdc_dev->soc_type); - return 0; - } - mask = m_IFBDC_CTRL_FBDC_COR_EN | - m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE | - m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO; - val = v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) | - v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) | - v_IFBDC_CTRL_FBDC_ROTATION_MODE((win->xmirror && - win->ymirror) << 1) | - v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) | - v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio); - lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val); - - mask = m_IFBDC_TILES_NUM; - val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles); - lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val); - - mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT; - val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) | - v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height); - lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val); - - mask = m_IFBDC_CMP_INDEX_INIT; - val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init); - lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val); - - mask = m_IFBDC_MB_VIR_WIDTH; - val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width); - lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val); - - return 0; -} - -static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - u8 fbdc_dsp_width_ratio = 0; - u16 fbdc_mb_vir_width = 0, fbdc_mb_vir_height = 0; - u16 fbdc_mb_width = 0, fbdc_mb_height = 0; - u16 fbdc_mb_xst = 0, fbdc_mb_yst = 0, fbdc_num_tiles = 0; - u16 fbdc_cmp_index_init = 0; - u8 mb_w_size = 0, mb_h_size = 0; - struct rk_screen *screen = dev_drv->cur_screen; - - if (screen->mode.flag & FB_VMODE_INTERLACED) { - dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n"); - return 0; - } - - if (lcdc_dev->soc_type != VOP_FULL_RK3368) { - pr_err("soc: 0x%08x not support FBDC\n", lcdc_dev->soc_type); - return 0; - } - switch (win->area[0].fmt_cfg) { - case VOP_FORMAT_ARGB888: - fbdc_dsp_width_ratio = 0; - mb_w_size = 16; - break; - case VOP_FORMAT_RGB888: - fbdc_dsp_width_ratio = 0; - mb_w_size = 16; - break; - case VOP_FORMAT_RGB565: - fbdc_dsp_width_ratio = 1; - mb_w_size = 32; - break; - default: - dev_err(lcdc_dev->dev, - "in fbdc mode,unsupport fmt:%d!\n", - win->area[0].fmt_cfg); - break; - } - mb_h_size = 4; - - /*macro block xvir and yvir */ - if ((win->area[0].xvir % mb_w_size == 0) && - (win->area[0].yvir % mb_h_size == 0)) { - fbdc_mb_vir_width = win->area[0].xvir / mb_w_size; - fbdc_mb_vir_height = win->area[0].yvir / mb_h_size; - } else { - pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg); - pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n", - win->area[0].xvir, win->area[0].yvir, - mb_w_size, mb_h_size); - } - /*macro block xact and yact */ - if ((win->area[0].xact % mb_w_size == 0) && - (win->area[0].yact % mb_h_size == 0)) { - fbdc_mb_width = win->area[0].xact / mb_w_size; - fbdc_mb_height = win->area[0].yact / mb_h_size; - } else { - pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg); - pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n", - win->area[0].xact, win->area[0].yact, - mb_w_size, mb_h_size); - } - /*macro block xoff and yoff */ - if ((win->area[0].xoff % mb_w_size == 0) && - (win->area[0].yoff % mb_h_size == 0)) { - fbdc_mb_xst = win->area[0].xoff / mb_w_size; - fbdc_mb_yst = win->area[0].yoff / mb_h_size; - } else { - pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg); - pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n", - win->area[0].xoff, win->area[0].yoff, - mb_w_size, mb_h_size); - } - - /*FBDC tiles */ - fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height; - - /* - switch (fbdc_rotation_mode) { - case FBDC_ROT_NONE: - fbdc_cmp_index_init = - (fbdc_mb_yst*fbdc_mb_vir_width) + fbdc_mb_xst; - break; - case FBDC_X_MIRROR: - fbdc_cmp_index_init = - (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+ - (fbdc_mb_width-1)); - break; - case FBDC_Y_MIRROR: - fbdc_cmp_index_init = - ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) + - fbdc_mb_xst; - break; - case FBDC_ROT_180: - fbdc_cmp_index_init = - ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) + - (fbdc_mb_xst+(fbdc_mb_width-1)); - break; - } - */ - if (win->xmirror && win->ymirror && ((win_id == 2) || (win_id == 3))) { - fbdc_cmp_index_init = - ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) + - (fbdc_mb_xst + (fbdc_mb_width - 1)); - } else { - fbdc_cmp_index_init = - (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst; - } - /*fbdc fmt maybe need to change*/ - win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio; - win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width; - win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height; - win->area[0].fbdc_mb_width = fbdc_mb_width; - win->area[0].fbdc_mb_height = fbdc_mb_height; - win->area[0].fbdc_mb_xst = fbdc_mb_xst; - win->area[0].fbdc_mb_yst = fbdc_mb_yst; - win->area[0].fbdc_num_tiles = fbdc_num_tiles; - win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init; - - return 0; -} - -static int rk3368_lcdc_axi_gather_cfg(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 mask, val; - u16 yrgb_gather_num = 3; - u16 cbcr_gather_num = 1; - - switch (win->area[0].format) { - case ARGB888: - case XBGR888: - case XRGB888: - case ABGR888: - case FBDC_ARGB_888: - case FBDC_RGBX_888: - case FBDC_ABGR_888: - yrgb_gather_num = 3; - break; - case RGB888: - case RGB565: - case BGR888: - case BGR565: - case FBDC_RGB_565: - yrgb_gather_num = 2; - break; - case YUV444: - case YUV422: - case YUV420: - case YUV420_NV21: - yrgb_gather_num = 1; - cbcr_gather_num = 2; - break; - default: - dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n", - __func__); - return -EINVAL; - } - - if ((win->id == 0) || (win->id == 1)) { - mask = m_WIN0_YRGB_AXI_GATHER_EN | m_WIN0_CBR_AXI_GATHER_EN | - m_WIN0_YRGB_AXI_GATHER_NUM | m_WIN0_CBR_AXI_GATHER_NUM; - val = v_WIN0_YRGB_AXI_GATHER_EN(1) | - v_WIN0_CBR_AXI_GATHER_EN(1) | - v_WIN0_YRGB_AXI_GATHER_NUM(yrgb_gather_num) | - v_WIN0_CBR_AXI_GATHER_NUM(cbcr_gather_num); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + (win->id * 0x40), - mask, val); - } else if ((win->id == 2) || (win->id == 3)) { - mask = m_WIN2_AXI_GATHER_EN | m_WIN2_AXI_GATHER_NUM; - val = v_WIN2_AXI_GATHER_EN(1) | - v_WIN2_AXI_GATHER_NUM(yrgb_gather_num); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL1 + ((win->id - 2) * 0x50), - mask, val); - } else if (win->id == 4) { - mask = m_HWC_AXI_GATHER_EN | m_HWC_AXI_GATHER_NUM; - val = v_HWC_AXI_GATHER_EN(1) | - v_HWC_AXI_GATHER_NUM(yrgb_gather_num); - lcdc_msk_reg(lcdc_dev, HWC_CTRL1, mask, val); - } - return 0; -} - -static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver; - struct rk_screen *screen = dev_drv->cur_screen; - - if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) { - switch (win->area[0].fmt_cfg) { - case VOP_FORMAT_ARGB888: - case VOP_FORMAT_RGB888: - case VOP_FORMAT_RGB565: - if ((screen->mode.xres < 1280) && - (screen->mode.yres < 720)) { - win->csc_mode = VOP_R2Y_CSC_BT601; - } else { - win->csc_mode = VOP_R2Y_CSC_BT709; - } - break; - default: - break; - } - } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) { - switch (win->area[0].fmt_cfg) { - case VOP_FORMAT_YCBCR420: - if ((win->id == 0) || (win->id == 1)) - win->csc_mode = VOP_Y2R_CSC_MPEG; - break; - default: - break; - } - } -} - -static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - unsigned int mask, val, off; - - off = win_id * 0x40; - /*if(win->win_lb_mode == 5) - win->win_lb_mode = 4; - for rk3288 to fix hw bug? */ - - if (win->state == 1) { - rk3368_lcdc_csc_mode(lcdc_dev, win); - rk3368_lcdc_axi_gather_cfg(lcdc_dev, win); - if (win->area[0].fbdc_en) - rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id); - mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 | - m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR | - m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE | m_WIN0_UV_SWAP; - val = v_WIN0_EN(win->state) | - v_WIN0_DATA_FMT(win->area[0].fmt_cfg) | - v_WIN0_FMT_10(win->fmt_10) | - v_WIN0_LB_MODE(win->win_lb_mode) | - v_WIN0_RB_SWAP(win->area[0].swap_rb) | - v_WIN0_X_MIRROR(win->xmirror) | - v_WIN0_Y_MIRROR(win->ymirror) | - v_WIN0_CSC_MODE(win->csc_mode) | - v_WIN0_UV_SWAP(win->area[0].swap_uv); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val); - - mask = m_WIN0_BIC_COE_SEL | - m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 | - m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 | - m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE | - m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE | - m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE | - m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE | - m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE; - val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) | - v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) | - v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) | - v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) | - v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) | - v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) | - v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) | - v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) | - v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) | - v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) | - v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) | - v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) | - v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) | - v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) | - v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val); - val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) | - v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride); - lcdc_writel(lcdc_dev, WIN0_VIR + off, val); - /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off, - win->area[0].y_addr); - lcdc_writel(lcdc_dev, WIN0_CBR_MST+off, - win->area[0].uv_addr); */ - val = v_WIN0_ACT_WIDTH(win->area[0].xact) | - v_WIN0_ACT_HEIGHT(win->area[0].yact); - lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val); - - val = v_WIN0_DSP_WIDTH(win->area[0].xsize) | - v_WIN0_DSP_HEIGHT(win->area[0].ysize); - lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val); - - val = v_WIN0_DSP_XST(win->area[0].dsp_stx) | - v_WIN0_DSP_YST(win->area[0].dsp_sty); - lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val); - - val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) | - v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y); - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val); - - val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) | - v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y); - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val); - if (win->alpha_en == 1) { - rk3368_lcdc_alpha_cfg(dev_drv, win_id); - } else { - mask = m_WIN0_SRC_ALPHA_EN; - val = v_WIN0_SRC_ALPHA_EN(0); - lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off, - mask, val); - } - - if (dev_drv->cur_screen->mode.vmode & FB_VMODE_INTERLACED) { - mask = m_WIN0_YRGB_DEFLICK | m_WIN0_CBR_DEFLICK; - if (win->area[0].yact == 2 * win->area[0].ysize) - val = v_WIN0_YRGB_DEFLICK(0) | - v_WIN0_CBR_DEFLICK(0); - else - val = v_WIN0_YRGB_DEFLICK(1) | - v_WIN0_CBR_DEFLICK(1); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val); - } - } else { - mask = m_WIN0_EN; - val = v_WIN0_EN(win->state); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val); - } - return 0; -} - -static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - unsigned int mask, val, off; - - off = (win_id - 2) * 0x50; - rk3368_lcdc_area_xst(win, win->area_num); - - if (win->state == 1) { - rk3368_lcdc_csc_mode(lcdc_dev, win); - rk3368_lcdc_axi_gather_cfg(lcdc_dev, win); - if (win->area[0].fbdc_en) - rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id); - - mask = m_WIN2_EN | m_WIN2_CSC_MODE; - val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val); - /*area 0 */ - if (win->area[0].state == 1) { - mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 | - m_WIN2_RB_SWAP0; - val = v_WIN2_MST0_EN(win->area[0].state) | - v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) | - v_WIN2_RB_SWAP0(win->area[0].swap_rb); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val); - - mask = m_WIN2_VIR_STRIDE0; - val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride); - lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val); - - /*lcdc_writel(lcdc_dev,WIN2_MST0+off, - win->area[0].y_addr); */ - val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) | - v_WIN2_DSP_HEIGHT0(win->area[0].ysize); - lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val); - val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) | - v_WIN2_DSP_YST0(win->area[0].dsp_sty); - lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val); - } else { - mask = m_WIN2_MST0_EN; - val = v_WIN2_MST0_EN(0); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val); - } - /*area 1 */ - if (win->area[1].state == 1) { - /*rk3368_win_area_check_var(win_id, 1, - &win->area[0], &win->area[1]); - */ - - mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 | - m_WIN2_RB_SWAP1; - val = v_WIN2_MST1_EN(win->area[1].state) | - v_WIN2_DATA_FMT1(win->area[1].fmt_cfg) | - v_WIN2_RB_SWAP1(win->area[1].swap_rb); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val); - - mask = m_WIN2_VIR_STRIDE1; - val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride); - lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val); - - /*lcdc_writel(lcdc_dev,WIN2_MST1+off, - win->area[1].y_addr); */ - val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) | - v_WIN2_DSP_HEIGHT1(win->area[1].ysize); - lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val); - val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) | - v_WIN2_DSP_YST1(win->area[1].dsp_sty); - lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val); - } else { - mask = m_WIN2_MST1_EN; - val = v_WIN2_MST1_EN(0); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val); - } - /*area 2 */ - if (win->area[2].state == 1) { - /*rk3368_win_area_check_var(win_id, 2, - &win->area[1], &win->area[2]); - */ - - mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 | - m_WIN2_RB_SWAP2; - val = v_WIN2_MST2_EN(win->area[2].state) | - v_WIN2_DATA_FMT2(win->area[2].fmt_cfg) | - v_WIN2_RB_SWAP2(win->area[2].swap_rb); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val); - - mask = m_WIN2_VIR_STRIDE2; - val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride); - lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val); - - /*lcdc_writel(lcdc_dev,WIN2_MST2+off, - win->area[2].y_addr); */ - val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) | - v_WIN2_DSP_HEIGHT2(win->area[2].ysize); - lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val); - val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) | - v_WIN2_DSP_YST2(win->area[2].dsp_sty); - lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val); - } else { - mask = m_WIN2_MST2_EN; - val = v_WIN2_MST2_EN(0); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val); - } - /*area 3 */ - if (win->area[3].state == 1) { - /*rk3368_win_area_check_var(win_id, 3, - &win->area[2], &win->area[3]); - */ - - mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 | - m_WIN2_RB_SWAP3; - val = v_WIN2_MST3_EN(win->area[3].state) | - v_WIN2_DATA_FMT3(win->area[3].fmt_cfg) | - v_WIN2_RB_SWAP3(win->area[3].swap_rb); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val); - - mask = m_WIN2_VIR_STRIDE3; - val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride); - lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val); - - /*lcdc_writel(lcdc_dev,WIN2_MST3+off, - win->area[3].y_addr); */ - val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) | - v_WIN2_DSP_HEIGHT3(win->area[3].ysize); - lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val); - val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) | - v_WIN2_DSP_YST3(win->area[3].dsp_sty); - lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val); - } else { - mask = m_WIN2_MST3_EN; - val = v_WIN2_MST3_EN(0); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val); - } - - if (win->alpha_en == 1) { - rk3368_lcdc_alpha_cfg(dev_drv, win_id); - } else { - mask = m_WIN2_SRC_ALPHA_EN; - val = v_WIN2_SRC_ALPHA_EN(0); - lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off, - mask, val); - } - } else { - mask = m_WIN2_EN | m_WIN2_MST0_EN | - m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN; - val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) | - v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val); - } - return 0; -} - -static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - unsigned int mask, val, hwc_size = 0; - - if (win->state == 1) { - rk3368_lcdc_csc_mode(lcdc_dev, win); - rk3368_lcdc_axi_gather_cfg(lcdc_dev, win); - mask = m_HWC_EN | m_HWC_DATA_FMT | - m_HWC_RB_SWAP | m_WIN0_CSC_MODE; - val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) | - v_HWC_RB_SWAP(win->area[0].swap_rb) | - v_WIN0_CSC_MODE(win->csc_mode); - lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val); - - if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32)) - hwc_size = 0; - else if ((win->area[0].xsize == 64) && - (win->area[0].ysize == 64)) - hwc_size = 1; - else if ((win->area[0].xsize == 96) && - (win->area[0].ysize == 96)) - hwc_size = 2; - else if ((win->area[0].xsize == 128) && - (win->area[0].ysize == 128)) - hwc_size = 3; - else - dev_err(lcdc_dev->dev, "un supported hwc size!\n"); - - mask = m_HWC_SIZE; - val = v_HWC_SIZE(hwc_size); - lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val); - - mask = m_HWC_DSP_XST | m_HWC_DSP_YST; - val = v_HWC_DSP_XST(win->area[0].dsp_stx) | - v_HWC_DSP_YST(win->area[0].dsp_sty); - lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val); - - if (win->alpha_en == 1) { - rk3368_lcdc_alpha_cfg(dev_drv, win_id); - } else { - mask = m_WIN2_SRC_ALPHA_EN; - val = v_WIN2_SRC_ALPHA_EN(0); - lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val); - } - } else { - mask = m_HWC_EN; - val = v_HWC_EN(win->state); - lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val); - } - return 0; -} - -static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver; - int timeout; - unsigned long flags; - - if (likely(lcdc_dev->clk_on)) { - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, - v_STANDBY_EN(lcdc_dev->standby)); - if ((win->id == 0) || (win->id == 1)) - rk3368_win_0_1_reg_update(dev_drv, win->id); - else if ((win->id == 2) || (win->id == 3)) - rk3368_win_2_3_reg_update(dev_drv, win->id); - else if (win->id == 4) - rk3368_hwc_reg_update(dev_drv, win->id); - /*rk3368_lcdc_post_cfg(dev_drv); */ - lcdc_cfg_done(lcdc_dev); - } - - /*if (dev_drv->wait_fs) { */ - if (0) { - spin_lock_irqsave(&dev_drv->cpl_lock, flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock, flags); - timeout = - wait_for_completion_timeout(&dev_drv->frame_done, - msecs_to_jiffies - (dev_drv->cur_screen->ft + 5)); - if (!timeout && (!dev_drv->frame_done.done)) { - dev_warn(lcdc_dev->dev, - "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } - } - DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id); - return 0; -} - -static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev) -{ - if (lcdc_dev->soc_type == VOP_FULL_RK3366) - memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x2a4); - else - memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x270); - - return 0; -} - -static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv) -{ - u32 mask, val; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if (unlikely(!lcdc_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on); - return 0; - } - if (dev_drv->iommu_enabled) { - if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) { - if (likely(lcdc_dev->clk_on)) { - mask = m_MMU_EN; - val = v_MMU_EN(1); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - mask = m_AXI_MAX_OUTSTANDING_EN | - m_AXI_OUTSTANDING_MAX_NUM; - val = v_AXI_OUTSTANDING_MAX_NUM(31) | - v_AXI_MAX_OUTSTANDING_EN(1); - lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val); - } - lcdc_dev->iommu_status = 1; - rockchip_iovmm_activate(dev_drv->dev); - } - } - return 0; -} - -static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate) -{ - int ret = 0, fps = 0; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; -#ifdef CONFIG_RK_FPGA - return 0; -#endif - if (reset_rate) - ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock); - if (ret) - dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id); - lcdc_dev->pixclock = - div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - lcdc_dev->driver.pixclock = lcdc_dev->pixclock; - - fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock); - screen->ft = 1000 / fps; - dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ", - lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps); - return 0; -} - -static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u16 hsync_len = screen->mode.hsync_len; - u16 left_margin = screen->mode.left_margin; - u16 right_margin = screen->mode.right_margin; - u16 vsync_len = screen->mode.vsync_len; - u16 upper_margin = screen->mode.upper_margin; - u16 lower_margin = screen->mode.lower_margin; - u16 x_res = screen->mode.xres; - u16 y_res = screen->mode.yres; - u32 mask, val; - u16 h_total, v_total; - u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1; - u32 frame_time; - u32 line_flag_reg; - - if (lcdc_dev->soc_type == VOP_FULL_RK3366) - line_flag_reg = LINE_FLAG_RK3366; - else - line_flag_reg = LINE_FLAG_RK3368; - - h_total = hsync_len + left_margin + x_res + right_margin; - v_total = vsync_len + upper_margin + y_res + lower_margin; - frame_time = 1000 * v_total * h_total / (screen->mode.pixclock / 1000); - mask = m_DSP_HS_PW | m_DSP_HTOTAL; - val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total); - lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val); - - mask = m_DSP_HACT_END | m_DSP_HACT_ST; - val = v_DSP_HACT_END(hsync_len + left_margin + x_res) | - v_DSP_HACT_ST(hsync_len + left_margin); - lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val); - - if (screen->mode.vmode & FB_VMODE_INTERLACED) { - /* First Field Timing */ - mask = m_DSP_VS_PW | m_DSP_VTOTAL; - val = v_DSP_VS_PW(vsync_len) | - v_DSP_VTOTAL(2 * (vsync_len + upper_margin + - lower_margin) + y_res + 1); - lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val); - - mask = m_DSP_VACT_END | m_DSP_VACT_ST; - val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) | - v_DSP_VACT_ST(vsync_len + upper_margin); - lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val); - - /* Second Field Timing */ - mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1; - vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin; - vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 + - lower_margin; - val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1); - lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val); - - mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1; - vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res + - lower_margin + 1; - vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 + - lower_margin + 1; - val = - v_DSP_VACT_END_F1(vact_end_f1) | - v_DSP_VAC_ST_F1(vact_st_f1); - lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val); - - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, - m_DSP_INTERLACE | m_DSP_FIELD_POL, - v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0)); - if (lcdc_dev->soc_type == VOP_FULL_RK3366) { - if (y_res <= 576) - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, - m_SW_CORE_DCLK_SEL, - v_SW_CORE_DCLK_SEL(1)); - else - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, - m_SW_CORE_DCLK_SEL, - v_SW_CORE_DCLK_SEL(0)); - } - mask = - m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK | - m_WIN0_CBR_DEFLICK; - val = - v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(0) | - v_WIN0_CBR_DEFLICK(0); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val); - - mask = - m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK | - m_WIN1_CBR_DEFLICK; - val = - v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(0) | - v_WIN1_CBR_DEFLICK(0); - lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val); - - mask = m_WIN2_INTERLACE_READ; - val = v_WIN2_INTERLACE_READ(1); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val); - - mask = m_WIN3_INTERLACE_READ; - val = v_WIN3_INTERLACE_READ(1); - lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val); - - mask = m_HWC_INTERLACE_READ; - val = v_HWC_INTERLACE_READ(1); - lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val); - - mask = m_DSP_LINE_FLAG0_NUM | m_DSP_LINE_FLAG1_NUM; - val = - v_DSP_LINE_FLAG0_NUM(vact_end_f1) | - v_DSP_LINE_FLAG1_NUM(vact_end_f1 - - EARLY_TIME * v_total / frame_time); - lcdc_msk_reg(lcdc_dev, line_flag_reg, mask, val); - } else { - mask = m_DSP_VS_PW | m_DSP_VTOTAL; - val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total); - lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val); - - mask = m_DSP_VACT_END | m_DSP_VACT_ST; - val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) | - v_DSP_VACT_ST(vsync_len + upper_margin); - lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val); - - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, - m_DSP_INTERLACE | m_DSP_FIELD_POL, - v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0)); - if (lcdc_dev->soc_type == VOP_FULL_RK3366) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, - m_SW_CORE_DCLK_SEL, - v_SW_CORE_DCLK_SEL(0)); - } - mask = - m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK | - m_WIN0_CBR_DEFLICK; - val = - v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) | - v_WIN0_CBR_DEFLICK(0); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val); - - mask = - m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK | - m_WIN1_CBR_DEFLICK; - val = - v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) | - v_WIN1_CBR_DEFLICK(0); - lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val); - - mask = m_WIN2_INTERLACE_READ; - val = v_WIN2_INTERLACE_READ(0); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val); - - mask = m_WIN3_INTERLACE_READ; - val = v_WIN3_INTERLACE_READ(0); - lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val); - - mask = m_HWC_INTERLACE_READ; - val = v_HWC_INTERLACE_READ(0); - lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val); - - mask = m_DSP_LINE_FLAG0_NUM | m_DSP_LINE_FLAG1_NUM; - val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res) | - v_DSP_LINE_FLAG1_NUM(vsync_len + upper_margin + y_res - - EARLY_TIME * v_total / frame_time); - lcdc_msk_reg(lcdc_dev, line_flag_reg, mask, val); - } - rk3368_lcdc_post_cfg(dev_drv); - return 0; -} - -static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 bcsh_ctrl; - - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_OVERLAY_MODE, - v_OVERLAY_MODE(dev_drv->overlay_mode)); - if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) { - if (IS_YUV_COLOR(dev_drv->output_color)) /* bypass */ - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, - m_BCSH_Y2R_EN | m_BCSH_R2Y_EN, - v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0)); - else /* YUV2RGB */ - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, - m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE | - m_BCSH_R2Y_EN, - v_BCSH_Y2R_EN(1) | - v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) | - v_BCSH_R2Y_EN(0)); - } else { /* overlay_mode=VOP_RGB_DOMAIN */ - /* bypass --need check,if bcsh close? */ - if (dev_drv->output_color == COLOR_RGB) { - bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL); - if (((bcsh_ctrl & m_BCSH_EN) == 1) || - (dev_drv->bcsh.enable == 1))/*bcsh enabled */ - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, - m_BCSH_R2Y_EN | - m_BCSH_Y2R_EN, - v_BCSH_R2Y_EN(1) | - v_BCSH_Y2R_EN(1)); - else - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, - m_BCSH_R2Y_EN | m_BCSH_Y2R_EN, - v_BCSH_R2Y_EN(0) | - v_BCSH_Y2R_EN(0)); - } else /* RGB2YUV */ - lcdc_msk_reg(lcdc_dev, BCSH_CTRL, - m_BCSH_R2Y_EN | - m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN, - v_BCSH_R2Y_EN(1) | - v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) | - v_BCSH_Y2R_EN(0)); - } -} - -static int rk3368_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact, - u16 *yact, int *format, u32 *dsp_addr, - int *ymirror) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - u32 val; - - spin_lock(&lcdc_dev->reg_lock); - - val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO); - *xact = (val & m_WIN0_ACT_WIDTH) + 1; - *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1; - - val = lcdc_readl(lcdc_dev, WIN0_CTRL0); - *format = (val & m_WIN0_DATA_FMT) >> 1; - *ymirror = (val & m_WIN0_Y_MIRROR) >> 22; - *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST); - - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int rk3368_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst, - int format, u16 xact, u16 yact, u16 xvir, - int ymirror) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - u32 val, mask; - struct rk_lcdc_win *win = dev_drv->win[0]; - int swap = (format == RGB888) ? 1 : 0; - - mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP | m_WIN0_Y_MIRROR; - val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap) | - v_WIN0_Y_MIRROR(ymirror); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val); - - lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE, - v_WIN0_VIR_STRIDE(xvir)); - lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) | - v_WIN0_ACT_HEIGHT(yact)); - - lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst); - - lcdc_cfg_done(lcdc_dev); - if (format == RGB888) - win->area[0].format = BGR888; - else - win->area[0].format = format; - - win->ymirror = ymirror; - win->state = 1; - win->last_state = 1; - - return 0; -} - -static int lcdc_reset(struct rk_lcdc_driver *dev_drv, bool initscreen) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask, val; - u32 __maybe_unused v; - if (!lcdc_dev->standby && initscreen && (dev_drv->first_frame != 1)) { - mdelay(150); - mask = m_WIN0_EN; - val = v_WIN0_EN(0); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val); - lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val); - - mask = m_WIN2_EN | m_WIN2_MST0_EN | - m_WIN2_MST1_EN | - m_WIN2_MST2_EN | m_WIN2_MST3_EN; - val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) | - v_WIN2_MST1_EN(0) | - v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val); - lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val); - mask = m_HDMI_OUT_EN; - val = v_HDMI_OUT_EN(0); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - lcdc_cfg_done(lcdc_dev); - mdelay(50); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1)); - writel_relaxed(0, lcdc_dev->regs + REG_CFG_DONE); - mdelay(50); -#ifdef VOP_RESET - if (dev_drv->iommu_enabled) { - if (dev_drv->mmu_dev) - rockchip_iovmm_deactivate(dev_drv->dev); - } - lcdc_cru_writel(lcdc_dev->cru_base, 0x0318, - (1 << 4) | (1 << 5) | (1 << 6) | - (1 << 20) | (1 << 21) | (1 << 22)); - udelay(100); - v = lcdc_cru_readl(lcdc_dev->cru_base, 0x0318); - pr_info("cru read = 0x%x\n", v); - lcdc_cru_writel(lcdc_dev->cru_base, 0x0318, - (0 << 4) | (0 << 5) | (0 << 6) | - (1 << 20) | (1 << 21) | (1 << 22)); - mdelay(100); - if (dev_drv->iommu_enabled) { - if (dev_drv->mmu_dev) - rockchip_iovmm_activate(dev_drv->dev); - } - mdelay(50); - rk3368_lcdc_reg_restore(lcdc_dev); - mdelay(50); -#endif - } - return 0; -} - -static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen) -{ - u16 face = 0; - u16 dclk_ddr = 0; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u32 mask = 0, val = 0; - - if (unlikely(!lcdc_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on); - return 0; - } - - if (!lcdc_dev->standby && initscreen && (dev_drv->first_frame != 1)) - flush_kthread_worker(&dev_drv->update_regs_worker); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - dev_drv->overlay_mode = VOP_RGB_DOMAIN; -#if 0 - if (!lcdc_dev->standby && !initscreen) { - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, - v_STANDBY_EN(1)); - lcdc_cfg_done(lcdc_dev); - mdelay(50); - } -#else - lcdc_reset(dev_drv, initscreen); -#endif - switch (screen->face) { - case OUT_P565: - face = OUT_P565; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_P666: - face = OUT_P666; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_D888_P565: - face = OUT_P888; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_D888_P666: - face = OUT_P888; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_P888: - face = OUT_P888; - mask = m_DITHER_DOWN_EN; - val = v_DITHER_DOWN_EN(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_YUV_420: - /*yuv420 output prefer yuv domain overlay */ - face = OUT_YUV_420; - dclk_ddr = 1; - mask = m_DITHER_DOWN_EN; - val = v_DITHER_DOWN_EN(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_S888: - face = OUT_S888; - mask = m_DITHER_DOWN_EN; - val = v_DITHER_DOWN_EN(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_S888DUMY: - face = OUT_S888DUMY; - mask = m_DITHER_DOWN_EN; - val = v_DITHER_DOWN_EN(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_CCIR656: - if (screen->color_mode == COLOR_RGB) - dev_drv->overlay_mode = VOP_RGB_DOMAIN; - else - dev_drv->overlay_mode = VOP_YUV_DOMAIN; - face = OUT_CCIR656_MODE_0; - mask = m_DITHER_DOWN_EN; - val = v_DITHER_DOWN_EN(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - default: - dev_err(lcdc_dev->dev, "un supported interface!\n"); - break; - } - switch (screen->type) { - case SCREEN_RGB: - mask = m_RGB_OUT_EN; - val = v_RGB_OUT_EN(1); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL | - m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL; - val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) | - v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) | - v_RGB_LVDS_DEN_POL(screen->pin_den) | - v_RGB_LVDS_DCLK_POL(screen->pin_dclk); - if (lcdc_dev->soc_type == VOP_FULL_RK3366) { - lcdc_grf_writel(lcdc_dev->grf_base, - RK3366_GRF_SOC_CON5, - RGB_SOURCE_SEL(dev_drv->id)); - lcdc_grf_writel(lcdc_dev->grf_base, - RK3366_GRF_SOC_CON0, - RGB_DATA_PLANA); - } - break; - case SCREEN_LVDS: - mask = m_RGB_OUT_EN; - val = v_RGB_OUT_EN(1); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL | - m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL; - val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) | - v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) | - v_RGB_LVDS_DEN_POL(screen->pin_den) | - v_RGB_LVDS_DCLK_POL(screen->pin_dclk); - if (lcdc_dev->soc_type == VOP_FULL_RK3366) - lcdc_grf_writel(lcdc_dev->grf_base, - RK3366_GRF_SOC_CON0, - LVDS_SOURCE_SEL(dev_drv->id)); - break; - case SCREEN_HDMI: - if (screen->color_mode == COLOR_RGB) - dev_drv->overlay_mode = VOP_RGB_DOMAIN; - else - dev_drv->overlay_mode = VOP_YUV_DOMAIN; - mask = m_HDMI_OUT_EN | m_RGB_OUT_EN; - val = v_HDMI_OUT_EN(1) | v_RGB_OUT_EN(0); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL | - m_HDMI_DEN_POL | m_HDMI_DCLK_POL; - val = v_HDMI_HSYNC_POL(screen->pin_hsync) | - v_HDMI_VSYNC_POL(screen->pin_vsync) | - v_HDMI_DEN_POL(screen->pin_den) | - v_HDMI_DCLK_POL(screen->pin_dclk); - if (lcdc_dev->soc_type == VOP_FULL_RK3366) { - lcdc_grf_writel(lcdc_dev->grf_base, - RK3366_GRF_SOC_CON0, - HDMI_SOURCE_SEL(dev_drv->id)); - } - break; - case SCREEN_MIPI: - mask = m_MIPI_OUT_EN | m_RGB_OUT_EN; - val = v_MIPI_OUT_EN(1) | v_RGB_OUT_EN(0); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL | - m_MIPI_DEN_POL | m_MIPI_DCLK_POL; - val = v_MIPI_HSYNC_POL(screen->pin_hsync) | - v_MIPI_VSYNC_POL(screen->pin_vsync) | - v_MIPI_DEN_POL(screen->pin_den) | - v_MIPI_DCLK_POL(screen->pin_dclk); - if (lcdc_dev->soc_type == VOP_FULL_RK3366) { - lcdc_grf_writel(lcdc_dev->grf_base, - RK3366_GRF_SOC_CON0, - MIPI_SOURCE_SEL(dev_drv->id)); - } - break; - case SCREEN_DUAL_MIPI: - mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN | - m_RGB_OUT_EN; - val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1) | - v_RGB_OUT_EN(0); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL | - m_MIPI_DEN_POL | m_MIPI_DCLK_POL; - val = v_MIPI_HSYNC_POL(screen->pin_hsync) | - v_MIPI_VSYNC_POL(screen->pin_vsync) | - v_MIPI_DEN_POL(screen->pin_den) | - v_MIPI_DCLK_POL(screen->pin_dclk); - break; - case SCREEN_EDP: - face = OUT_P888; /*RGB 888 output */ - - mask = m_EDP_OUT_EN | m_RGB_OUT_EN; - val = v_EDP_OUT_EN(1) | v_RGB_OUT_EN(0); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - - mask = m_EDP_HSYNC_POL | m_EDP_VSYNC_POL | - m_EDP_DEN_POL | m_EDP_DCLK_POL; - val = v_EDP_HSYNC_POL(screen->pin_hsync) | - v_EDP_VSYNC_POL(screen->pin_vsync) | - v_EDP_DEN_POL(screen->pin_den) | - v_EDP_DCLK_POL(screen->pin_dclk); - break; - } - /*hsync vsync den dclk polo,dither */ - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP | - m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP | - m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN | - m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN; - val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) | - v_DSP_BG_SWAP(screen->swap_gb) | - v_DSP_RB_SWAP(screen->swap_rb) | - v_DSP_RG_SWAP(screen->swap_rg) | - v_DSP_DELTA_SWAP(screen->swap_delta) | - v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) | - v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) | - v_DSP_X_MIR_EN(screen->x_mirror) | - v_DSP_Y_MIR_EN(screen->y_mirror); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - /*BG color */ - mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED; - if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) - val = v_DSP_BG_BLUE(0x80) | v_DSP_BG_GREEN(0x10) | - v_DSP_BG_RED(0x80); - else - val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) | - v_DSP_BG_RED(0); - lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val); - dev_drv->output_color = screen->color_mode; - if (screen->dsp_lut == NULL) - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, - v_DSP_LUT_EN(0)); - else - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, - v_DSP_LUT_EN(1)); - rk3368_lcdc_bcsh_path_sel(dev_drv); - rk3368_config_timing(dev_drv); - if (lcdc_dev->soc_type == VOP_FULL_RK3366) - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - rk3368_lcdc_set_dclk(dev_drv, 1); - if (screen->type != SCREEN_HDMI && - screen->type != SCREEN_TVOUT && - dev_drv->trsm_ops && - dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - if (screen->init) - screen->init(); - /*if (!lcdc_dev->standby) - lcdc_msk_reg(lcdc_dev, SYS_CTRL, - m_STANDBY_EN, v_STANDBY_EN(0));*/ - return 0; -} - - -/*enable layer,open:1,enable;0 disable*/ -static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev, - unsigned int win_id, bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on) && - lcdc_dev->driver.win[win_id]->state != open) { - if (open) { - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, - "wakeup from standby!\n"); - lcdc_dev->standby = 0; - } - lcdc_dev->atv_layer_cnt |= (1 << win_id); - } else { - if (lcdc_dev->atv_layer_cnt & (1 << win_id)) - lcdc_dev->atv_layer_cnt &= ~(1 << win_id); - } - lcdc_dev->driver.win[win_id]->state = open; - if (!open) { - /*rk3368_lcdc_reg_update(dev_drv);*/ - rk3368_lcdc_layer_update_regs - (lcdc_dev, lcdc_dev->driver.win[win_id]); - lcdc_cfg_done(lcdc_dev); - } - /*if no layer used,disable lcdc */ - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, - "no layer is used,go to standby!\n"); - lcdc_dev->standby = 1; - } - } - spin_unlock(&lcdc_dev->reg_lock); -} - -static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - u32 mask, val; - /*struct rk_screen *screen = dev_drv->cur_screen; */ - u32 intr_en_reg, intr_clr_reg; - - if (lcdc_dev->soc_type == VOP_FULL_RK3366) { - intr_clr_reg = INTR_CLEAR_RK3366; - intr_en_reg = INTR_EN_RK3366; - } else { - intr_clr_reg = INTR_CLEAR_RK3368; - intr_en_reg = INTR_EN_RK3368; - } - - mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR | - m_LINE_FLAG1_INTR_CLR; - val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) | - v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1); - lcdc_msk_reg(lcdc_dev, intr_clr_reg, mask, val); - - mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN | - m_BUS_ERROR_INTR_EN | m_LINE_FLAG1_INTR_EN; - val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) | - v_BUS_ERROR_INTR_EN(1) | v_LINE_FLAG1_INTR_EN(0); - lcdc_msk_reg(lcdc_dev, intr_en_reg, mask, val); -#ifdef LCDC_IRQ_EMPTY_DEBUG - mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN | - m_WIN2_EMPTY_INTR_EN | - m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN | - m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN; - val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) | - v_WIN2_EMPTY_INTR_EN(1) | - v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) | - v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1); - lcdc_msk_reg(lcdc_dev, intr_en_reg, mask, val); -#endif - return 0; -} - -static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id, - bool open) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - /*enable clk,when first layer open */ - if ((open) && (!lcdc_dev->atv_layer_cnt)) { - /*rockchip_set_system_status(sys_status);*/ - rk3368_lcdc_pre_init(dev_drv); - rk3368_lcdc_clk_enable(lcdc_dev); - rk3368_lcdc_enable_irq(dev_drv); - if (dev_drv->iommu_enabled) { - if (!dev_drv->mmu_dev) { - dev_drv->mmu_dev = - rk_fb_get_sysmmu_device_by_compatible - (dev_drv->mmu_dts_name); - if (dev_drv->mmu_dev) { - rk_fb_platform_set_sysmmu - (dev_drv->mmu_dev, dev_drv->dev); - } else { - dev_err(dev_drv->dev, - "fail get rk iommu device\n"); - return -1; - } - } - /*if (dev_drv->mmu_dev) - rockchip_iovmm_activate(dev_drv->dev); */ - } - rk3368_lcdc_reg_restore(lcdc_dev); - /*if (dev_drv->iommu_enabled) - rk3368_lcdc_mmu_en(dev_drv); */ - if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) { - rk3368_lcdc_set_dclk(dev_drv, 0); - /*rk3368_lcdc_enable_irq(dev_drv);*/ - } else { - rk3368_load_screen(dev_drv, 1); - } - if (dev_drv->bcsh.enable) - rk3368_lcdc_set_bcsh(dev_drv, 1); - spin_lock(&lcdc_dev->reg_lock); - if (dev_drv->cur_screen->dsp_lut) - rk3368_lcdc_set_lut(dev_drv, - dev_drv->cur_screen->dsp_lut); - spin_unlock(&lcdc_dev->reg_lock); - } - - if (win_id < ARRAY_SIZE(lcdc_win)) - rk3368_lcdc_layer_enable(lcdc_dev, win_id, open); - else - dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id); - - - /* when all layer closed,disable clk */ - /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) { - rk3368_lcdc_disable_irq(lcdc_dev); - rk3368_lcdc_reg_update(dev_drv); - if (dev_drv->iommu_enabled) { - if (dev_drv->mmu_dev) - rockchip_iovmm_deactivate(dev_drv->dev); - } - rk3368_lcdc_clk_disable(lcdc_dev); - #ifndef CONFIG_RK_FPGA - rockchip_clear_system_status(sys_status); - #endif - } */ - dev_drv->first_frame = 0; - return 0; -} - -static int win_0_1_display(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 y_addr; - u32 uv_addr; - unsigned int off; - - off = win->id * 0x40; - /*win->smem_start + win->y_offset; */ - y_addr = win->area[0].smem_start + win->area[0].y_offset; - uv_addr = win->area[0].cbr_start + win->area[0].c_offset; - DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x", - lcdc_dev->id, win->id, y_addr, uv_addr); - DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n", - win->area[0].y_offset, win->area[0].c_offset); - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - win->area[0].y_addr = y_addr; - win->area[0].uv_addr = uv_addr; - lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr); - lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr); - if (win->area[0].fbdc_en == 1) - lcdc_writel(lcdc_dev, IFBDC_BASE_ADDR, - win->area[0].y_addr); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win_2_3_display(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 i, y_addr; - unsigned int off; - - off = (win->id - 2) * 0x50; - y_addr = win->area[0].smem_start + win->area[0].y_offset; - DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - for (i = 0; i < win->area_num; i++) { - DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n", - i, win->area[i].y_addr, win->area[i].y_offset); - win->area[i].y_addr = - win->area[i].smem_start + win->area[i].y_offset; - } - lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr); - lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr); - lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr); - lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr); - if (win->area[0].fbdc_en == 1) - lcdc_writel(lcdc_dev, IFBDC_BASE_ADDR, - win->area[0].y_addr); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win) -{ - u32 y_addr; - - y_addr = win->area[0].smem_start + win->area[0].y_offset; - DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n", - lcdc_dev->id, __func__, y_addr); - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - win->area[0].y_addr = y_addr; - lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = NULL; - struct rk_screen *screen = dev_drv->cur_screen; - -#if defined(WAIT_FOR_SYNC) - int timeout; - unsigned long flags; -#endif - win = dev_drv->win[win_id]; - if (!screen) { - dev_err(dev_drv->dev, "screen is null!\n"); - return -ENOENT; - } - if (unlikely(!lcdc_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on); - return 0; - } - if (win_id == 0) { - win_0_1_display(lcdc_dev, win); - } else if (win_id == 1) { - win_0_1_display(lcdc_dev, win); - } else if (win_id == 2) { - win_2_3_display(lcdc_dev, win); - } else if (win_id == 3) { - win_2_3_display(lcdc_dev, win); - } else if (win_id == 4) { - hwc_display(lcdc_dev, win); - } else { - dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id); - return -EINVAL; - } - -#if defined(WAIT_FOR_SYNC) - spin_lock_irqsave(&dev_drv->cpl_lock, flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock, flags); - timeout = - wait_for_completion_timeout(&dev_drv->frame_done, - msecs_to_jiffies(dev_drv-> - cur_screen->ft + 5)); - if (!timeout && (!dev_drv->frame_done.done)) { - dev_info(dev_drv->dev, "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } -#endif - return 0; -} - -static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win, - struct rk_screen *screen) -{ - u16 srcW = 0; - u16 srcH = 0; - u16 dstW = 0; - u16 dstH = 0; - u16 yrgb_srcW = 0; - u16 yrgb_srcH = 0; - u16 yrgb_dstW = 0; - u16 yrgb_dstH = 0; - u32 yrgb_vscalednmult = 0; - u32 yrgb_xscl_factor = 0; - u32 yrgb_yscl_factor = 0; - u8 yrgb_vsd_bil_gt2 = 0; - u8 yrgb_vsd_bil_gt4 = 0; - - u16 cbcr_srcW = 0; - u16 cbcr_srcH = 0; - u16 cbcr_dstW = 0; - u16 cbcr_dstH = 0; - u32 cbcr_vscalednmult = 0; - u32 cbcr_xscl_factor = 0; - u32 cbcr_yscl_factor = 0; - u8 cbcr_vsd_bil_gt2 = 0; - u8 cbcr_vsd_bil_gt4 = 0; - u8 yuv_fmt = 0; - - srcW = win->area[0].xact; - if ((screen->mode.vmode & FB_VMODE_INTERLACED) && - (win->area[0].yact == 2 * win->area[0].ysize)) { - srcH = win->area[0].yact / 2; - yrgb_vsd_bil_gt2 = 1; - cbcr_vsd_bil_gt2 = 1; - } else { - srcH = win->area[0].yact; - } - dstW = win->area[0].xsize; - dstH = win->area[0].ysize; - - /*yrgb scl mode */ - yrgb_srcW = srcW; - yrgb_srcH = srcH; - yrgb_dstW = dstW; - yrgb_dstH = dstH; - if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) { - pr_err("ERROR: yrgb scale exceed 8,"); - pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", - yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH); - } - if (yrgb_srcW < yrgb_dstW) - win->yrgb_hor_scl_mode = SCALE_UP; - else if (yrgb_srcW > yrgb_dstW) - win->yrgb_hor_scl_mode = SCALE_DOWN; - else - win->yrgb_hor_scl_mode = SCALE_NONE; - - if (yrgb_srcH < yrgb_dstH) - win->yrgb_ver_scl_mode = SCALE_UP; - else if (yrgb_srcH > yrgb_dstH) - win->yrgb_ver_scl_mode = SCALE_DOWN; - else - win->yrgb_ver_scl_mode = SCALE_NONE; - - /*cbcr scl mode */ - switch (win->area[0].format) { - case YUV422: - case YUV422_A: - cbcr_srcW = srcW / 2; - cbcr_dstW = dstW; - cbcr_srcH = srcH; - cbcr_dstH = dstH; - yuv_fmt = 1; - break; - case YUV420: - case YUV420_A: - case YUV420_NV21: - cbcr_srcW = srcW / 2; - cbcr_dstW = dstW; - cbcr_srcH = srcH / 2; - cbcr_dstH = dstH; - yuv_fmt = 1; - break; - case YUV444: - case YUV444_A: - cbcr_srcW = srcW; - cbcr_dstW = dstW; - cbcr_srcH = srcH; - cbcr_dstH = dstH; - yuv_fmt = 1; - break; - default: - cbcr_srcW = 0; - cbcr_dstW = 0; - cbcr_srcH = 0; - cbcr_dstH = 0; - yuv_fmt = 0; - break; - } - if (yuv_fmt) { - if ((cbcr_dstW * 8 <= cbcr_srcW) || - (cbcr_dstH * 8 <= cbcr_srcH)) { - pr_err("ERROR: cbcr scale exceed 8,"); - pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW, - cbcr_srcH, cbcr_dstW, cbcr_dstH); - } - } - - if (cbcr_srcW < cbcr_dstW) - win->cbr_hor_scl_mode = SCALE_UP; - else if (cbcr_srcW > cbcr_dstW) - win->cbr_hor_scl_mode = SCALE_DOWN; - else - win->cbr_hor_scl_mode = SCALE_NONE; - - if (cbcr_srcH < cbcr_dstH) - win->cbr_ver_scl_mode = SCALE_UP; - else if (cbcr_srcH > cbcr_dstH) - win->cbr_ver_scl_mode = SCALE_DOWN; - else - win->cbr_ver_scl_mode = SCALE_NONE; - - /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n" - "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n" - "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW, - srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH, - win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW, - cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode, - win->cbr_ver_scl_mode);*/ - - /*line buffer mode */ - if ((win->area[0].format == YUV422) || - (win->area[0].format == YUV420) || - (win->area[0].format == YUV420_NV21) || - (win->area[0].format == YUV422_A) || - (win->area[0].format == YUV420_A)) { - if (win->cbr_hor_scl_mode == SCALE_DOWN) { - if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) || - (cbcr_dstW == 0)) - pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n", - cbcr_dstW); - else if (cbcr_dstW > 1280) - win->win_lb_mode = LB_YUV_3840X5; - else - win->win_lb_mode = LB_YUV_2560X8; - } else { /*SCALE_UP or SCALE_NONE */ - if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) || - (cbcr_srcW == 0)) - pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n", - cbcr_srcW); - else if (cbcr_srcW > 1280) - win->win_lb_mode = LB_YUV_3840X5; - else - win->win_lb_mode = LB_YUV_2560X8; - } - } else { - if (win->yrgb_hor_scl_mode == SCALE_DOWN) { - if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) || - (yrgb_dstW == 0)) - pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW); - else if (yrgb_dstW > 2560) - win->win_lb_mode = LB_RGB_3840X2; - else if (yrgb_dstW > 1920) - win->win_lb_mode = LB_RGB_2560X4; - else if (yrgb_dstW > 1280) - win->win_lb_mode = LB_RGB_1920X5; - else - win->win_lb_mode = LB_RGB_1280X8; - } else { /*SCALE_UP or SCALE_NONE */ - if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) || - (yrgb_srcW == 0)) - pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW); - else if (yrgb_srcW > 2560) - win->win_lb_mode = LB_RGB_3840X2; - else if (yrgb_srcW > 1920) - win->win_lb_mode = LB_RGB_2560X4; - else if (yrgb_srcW > 1280) - win->win_lb_mode = LB_RGB_1920X5; - else - win->win_lb_mode = LB_RGB_1280X8; - } - } - DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode); - - /*vsd/vsu scale ALGORITHM */ - win->yrgb_hsd_mode = SCALE_DOWN_BIL; /*not to specify */ - win->cbr_hsd_mode = SCALE_DOWN_BIL; /*not to specify */ - win->yrgb_vsd_mode = SCALE_DOWN_BIL; /*not to specify */ - win->cbr_vsd_mode = SCALE_DOWN_BIL; /*not to specify */ - switch (win->win_lb_mode) { - case LB_YUV_3840X5: - case LB_YUV_2560X8: - case LB_RGB_1920X5: - case LB_RGB_1280X8: - win->yrgb_vsu_mode = SCALE_UP_BIC; - win->cbr_vsu_mode = SCALE_UP_BIC; - break; - case LB_RGB_3840X2: - if (win->yrgb_ver_scl_mode != SCALE_NONE) - pr_err("ERROR : not allow yrgb ver scale\n"); - if (win->cbr_ver_scl_mode != SCALE_NONE) - pr_err("ERROR : not allow cbcr ver scale\n"); - break; - case LB_RGB_2560X4: - win->yrgb_vsu_mode = SCALE_UP_BIL; - win->cbr_vsu_mode = SCALE_UP_BIL; - break; - default: - pr_info("%s:un supported win_lb_mode:%d\n", - __func__, win->win_lb_mode); - break; - } - if (win->ymirror == 1) - win->yrgb_vsd_mode = SCALE_DOWN_BIL; - - if (screen->mode.vmode & FB_VMODE_INTERLACED) { - /*interlace mode must bill */ - win->yrgb_vsd_mode = SCALE_DOWN_BIL; - win->cbr_vsd_mode = SCALE_DOWN_BIL; - } - if ((win->yrgb_ver_scl_mode == SCALE_DOWN) && - (win->area[0].fbdc_en == 1)) { - /*in this pattern,use bil mode,not support souble scd, - use avg mode, support double scd, but aclk should be - bigger than dclk,aclk>>dclk */ - if (yrgb_srcH >= 2 * yrgb_dstH) { - pr_err("ERROR : fbdc mode,not support y scale down:"); - pr_err("srcH[%d] > 2 *dstH[%d]\n", - yrgb_srcH, yrgb_dstH); - } - } - DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n", - win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode, - win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode); - - /*SCALE FACTOR */ - - /*(1.1)YRGB HOR SCALE FACTOR */ - switch (win->yrgb_hor_scl_mode) { - case SCALE_NONE: - yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT); - break; - case SCALE_UP: - yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW); - break; - case SCALE_DOWN: - switch (win->yrgb_hsd_mode) { - case SCALE_DOWN_BIL: - yrgb_xscl_factor = - GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW); - break; - case SCALE_DOWN_AVG: - yrgb_xscl_factor = - GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW); - break; - default: - pr_info( - "%s:un supported yrgb_hsd_mode:%d\n", __func__, - win->yrgb_hsd_mode); - break; - } - break; - default: - pr_info("%s:un supported yrgb_hor_scl_mode:%d\n", - __func__, win->yrgb_hor_scl_mode); - break; - } /*win->yrgb_hor_scl_mode */ - - /*(1.2)YRGB VER SCALE FACTOR */ - switch (win->yrgb_ver_scl_mode) { - case SCALE_NONE: - yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT); - break; - case SCALE_UP: - switch (win->yrgb_vsu_mode) { - case SCALE_UP_BIL: - yrgb_yscl_factor = - GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH); - break; - case SCALE_UP_BIC: - if (yrgb_srcH < 3) { - pr_err("yrgb_srcH should be"); - pr_err(" greater than 3 !!!\n"); - } - yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH, - yrgb_dstH); - break; - default: - pr_info("%s:un support yrgb_vsu_mode:%d\n", - __func__, win->yrgb_vsu_mode); - break; - } - break; - case SCALE_DOWN: - switch (win->yrgb_vsd_mode) { - case SCALE_DOWN_BIL: - yrgb_vscalednmult = - rk3368_get_hard_ware_vskiplines(yrgb_srcH, - yrgb_dstH); - yrgb_yscl_factor = - GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH, - yrgb_vscalednmult); - if (yrgb_yscl_factor >= 0x2000) { - pr_err("yrgb_yscl_factor should be "); - pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n", - yrgb_yscl_factor); - } - if (yrgb_vscalednmult == 4) { - yrgb_vsd_bil_gt4 = 1; - yrgb_vsd_bil_gt2 = 0; - } else if (yrgb_vscalednmult == 2) { - yrgb_vsd_bil_gt4 = 0; - yrgb_vsd_bil_gt2 = 1; - } else { - yrgb_vsd_bil_gt4 = 0; - yrgb_vsd_bil_gt2 = 0; - } - break; - case SCALE_DOWN_AVG: - yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH, - yrgb_dstH); - break; - default: - pr_info("%s:un support yrgb_vsd_mode:%d\n", - __func__, win->yrgb_vsd_mode); - break; - } /*win->yrgb_vsd_mode */ - break; - default: - pr_info("%s:un supported yrgb_ver_scl_mode:%d\n", - __func__, win->yrgb_ver_scl_mode); - break; - } - win->scale_yrgb_x = yrgb_xscl_factor; - win->scale_yrgb_y = yrgb_yscl_factor; - win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4; - win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2; - DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor, - yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2); - - /*(2.1)CBCR HOR SCALE FACTOR */ - switch (win->cbr_hor_scl_mode) { - case SCALE_NONE: - cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT); - break; - case SCALE_UP: - cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW); - break; - case SCALE_DOWN: - switch (win->cbr_hsd_mode) { - case SCALE_DOWN_BIL: - cbcr_xscl_factor = - GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW); - break; - case SCALE_DOWN_AVG: - cbcr_xscl_factor = - GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW); - break; - default: - pr_info("%s:un support cbr_hsd_mode:%d\n", - __func__, win->cbr_hsd_mode); - break; - } - break; - default: - pr_info("%s:un supported cbr_hor_scl_mode:%d\n", - __func__, win->cbr_hor_scl_mode); - break; - } /*win->cbr_hor_scl_mode */ - - /*(2.2)CBCR VER SCALE FACTOR */ - switch (win->cbr_ver_scl_mode) { - case SCALE_NONE: - cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT); - break; - case SCALE_UP: - switch (win->cbr_vsu_mode) { - case SCALE_UP_BIL: - cbcr_yscl_factor = - GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH); - break; - case SCALE_UP_BIC: - if (cbcr_srcH < 3) { - pr_err("cbcr_srcH should be "); - pr_err("greater than 3 !!!\n"); - } - cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH, - cbcr_dstH); - break; - default: - pr_info("%s:un support cbr_vsu_mode:%d\n", - __func__, win->cbr_vsu_mode); - break; - } - break; - case SCALE_DOWN: - switch (win->cbr_vsd_mode) { - case SCALE_DOWN_BIL: - cbcr_vscalednmult = - rk3368_get_hard_ware_vskiplines(cbcr_srcH, - cbcr_dstH); - cbcr_yscl_factor = - GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH, - cbcr_vscalednmult); - if (cbcr_yscl_factor >= 0x2000) { - pr_err("cbcr_yscl_factor should be less "); - pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n", - cbcr_yscl_factor); - } - - if (cbcr_vscalednmult == 4) { - cbcr_vsd_bil_gt4 = 1; - cbcr_vsd_bil_gt2 = 0; - } else if (cbcr_vscalednmult == 2) { - cbcr_vsd_bil_gt4 = 0; - cbcr_vsd_bil_gt2 = 1; - } else { - cbcr_vsd_bil_gt4 = 0; - cbcr_vsd_bil_gt2 = 0; - } - break; - case SCALE_DOWN_AVG: - cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH, - cbcr_dstH); - break; - default: - pr_info("%s:un support cbr_vsd_mode:%d\n", - __func__, win->cbr_vsd_mode); - break; - } - break; - default: - pr_info("%s:un supported cbr_ver_scl_mode:%d\n", - __func__, win->cbr_ver_scl_mode); - break; - } - win->scale_cbcr_x = cbcr_xscl_factor; - win->scale_cbcr_y = cbcr_yscl_factor; - win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4; - win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2; - - DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor, - cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2); - return 0; -} - -static int dsp_x_pos(int mirror_en, struct rk_screen *screen, - struct rk_lcdc_win_area *area) -{ - int pos; - - if (screen->x_mirror && mirror_en) - pr_err("not support both win and global mirror\n"); - - if ((!mirror_en) && (!screen->x_mirror)) - pos = area->xpos + screen->mode.left_margin + - screen->mode.hsync_len; - else - pos = screen->mode.xres - area->xpos - - area->xsize + screen->mode.left_margin + - screen->mode.hsync_len; - - return pos; -} - -static int dsp_y_pos(int mirror_en, struct rk_screen *screen, - struct rk_lcdc_win_area *area) -{ - int pos; - - if (screen->y_mirror && mirror_en) - pr_err("not support both win and global mirror\n"); - if (!(screen->mode.vmode & FB_VMODE_INTERLACED)) { - if ((!mirror_en) && (!screen->y_mirror)) - pos = area->ypos + screen->mode.upper_margin + - screen->mode.vsync_len; - else - pos = screen->mode.yres - area->ypos - - area->ysize + screen->mode.upper_margin + - screen->mode.vsync_len; - } else { - pos = area->ypos / 2 + screen->mode.upper_margin + - screen->mode.vsync_len; - area->ysize /= 2; - } - - return pos; -} - -static int win_0_1_set_par(struct lcdc_device *lcdc_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - u32 xact = 0, yact = 0, xvir = 0, yvir = 0, xpos = 0, ypos = 0; - u8 fmt_cfg = 0, swap_rb = 0, swap_uv = 0; - char fmt[9] = "NULL"; - - xpos = dsp_x_pos(win->xmirror, screen, &win->area[0]); - ypos = dsp_y_pos(win->ymirror, screen, &win->area[0]); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - rk3368_lcdc_cal_scl_fac(win, screen); /*fac,lb,gt2,gt4 */ - switch (win->area[0].format) { - case FBDC_RGB_565: - fmt_cfg = 2; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = 0x05; - break; - case FBDC_ARGB_888: - fmt_cfg = 0; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = 0x0c; - break; - case FBDC_ABGR_888: - fmt_cfg = 0; - swap_rb = 1; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = 0x0c; - break; - case FBDC_RGBX_888: - fmt_cfg = 0; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = 0x3a; - break; - case ARGB888: - fmt_cfg = 0; - swap_rb = 0; - win->fmt_10 = 0; - break; - case XBGR888: - case ABGR888: - fmt_cfg = 0; - swap_rb = 1; - win->fmt_10 = 0; - break; - case BGR888: - fmt_cfg = 1; - swap_rb = 1; - win->fmt_10 = 0; - break; - case RGB888: - fmt_cfg = 1; - swap_rb = 0; - win->fmt_10 = 0; - break; - case RGB565: - fmt_cfg = 2; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV422: - fmt_cfg = 5; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV420: - fmt_cfg = 4; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV420_NV21: - fmt_cfg = 4; - swap_rb = 0; - swap_uv = 1; - win->fmt_10 = 0; - break; - case YUV444: - fmt_cfg = 6; - swap_rb = 0; - win->fmt_10 = 0; - break; - case YUV422_A: - fmt_cfg = 5; - swap_rb = 0; - win->fmt_10 = 1; - break; - case YUV420_A: - fmt_cfg = 4; - swap_rb = 0; - win->fmt_10 = 1; - break; - case YUV444_A: - fmt_cfg = 6; - swap_rb = 0; - win->fmt_10 = 1; - break; - default: - dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n", - __func__); - break; - } - win->area[0].fmt_cfg = fmt_cfg; - win->area[0].swap_rb = swap_rb; - win->area[0].swap_uv = swap_uv; - win->area[0].dsp_stx = xpos; - win->area[0].dsp_sty = ypos; - xact = win->area[0].xact; - yact = win->area[0].yact; - xvir = win->area[0].xvir; - yvir = win->area[0].yvir; - } - if (win->area[0].fbdc_en) - rk3368_init_fbdc_config(&lcdc_dev->driver, win->id); - rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id); - spin_unlock(&lcdc_dev->reg_lock); - - DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d", - lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt), - xact, yact, win->area[0].xsize); - DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - win->area[0].ysize, xvir, yvir, xpos, ypos); - - return 0; -} - - -static int win_2_3_set_par(struct lcdc_device *lcdc_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - int i; - u8 fmt_cfg = 0, swap_rb = 0; - char fmt[9] = "NULL"; - - if (win->ymirror) - pr_err("win[%d] not support y mirror\n", win->id); - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id); - for (i = 0; i < win->area_num; i++) { - switch (win->area[i].format) { - case FBDC_RGB_565: - fmt_cfg = 2; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = 0x05; - break; - case FBDC_ARGB_888: - fmt_cfg = 0; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = 0x0c; - break; - case FBDC_ABGR_888: - fmt_cfg = 0; - swap_rb = 1; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = 0x0c; - break; - case FBDC_RGBX_888: - fmt_cfg = 0; - swap_rb = 0; - win->fmt_10 = 0; - win->area[0].fbdc_fmt_cfg = 0x3a; - break; - case ARGB888: - fmt_cfg = 0; - swap_rb = 0; - break; - case XBGR888: - case ABGR888: - fmt_cfg = 0; - swap_rb = 1; - break; - case RGB888: - fmt_cfg = 1; - swap_rb = 0; - break; - case RGB565: - fmt_cfg = 2; - swap_rb = 0; - break; - default: - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", __func__); - break; - } - win->area[i].fmt_cfg = fmt_cfg; - win->area[i].swap_rb = swap_rb; - win->area[i].dsp_stx = - dsp_x_pos(win->xmirror, screen, - &win->area[i]); - win->area[i].dsp_sty = - dsp_y_pos(win->ymirror, screen, - &win->area[i]); - if (((win->area[i].xact != win->area[i].xsize) || - (win->area[i].yact != win->area[i].ysize)) && - !(screen->mode.vmode & FB_VMODE_INTERLACED)) { - pr_err("win[%d]->area[%d],not support scale\n", - win->id, i); - pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n", - win->area[i].xact, win->area[i].yact, - win->area[i].xsize, win->area[i].ysize); - win->area[i].xsize = win->area[i].xact; - win->area[i].ysize = win->area[i].yact; - } - DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n", - get_format_string(win->area[i].format, fmt), - win->area[i].xsize, win->area[i].ysize, - win->area[i].xpos, win->area[i].ypos); - } - } - if (win->area[0].fbdc_en) - rk3368_init_fbdc_config(&lcdc_dev->driver, win->id); - rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id); - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int hwc_set_par(struct lcdc_device *lcdc_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - u32 xact = 0, yact = 0, xvir = 0, yvir = 0, xpos = 0, ypos = 0; - u8 fmt_cfg = 0, swap_rb = 0; - char fmt[9] = "NULL"; - - xpos = win->area[0].xpos + screen->mode.left_margin + - screen->mode.hsync_len; - ypos = win->area[0].ypos + screen->mode.upper_margin + - screen->mode.vsync_len; - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */ - switch (win->area[0].format) { - case ARGB888: - fmt_cfg = 0; - swap_rb = 0; - break; - case XBGR888: - case ABGR888: - fmt_cfg = 0; - swap_rb = 1; - break; - case RGB888: - fmt_cfg = 1; - swap_rb = 0; - break; - case RGB565: - fmt_cfg = 2; - swap_rb = 0; - break; - default: - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", __func__); - break; - } - win->area[0].fmt_cfg = fmt_cfg; - win->area[0].swap_rb = swap_rb; - win->area[0].dsp_stx = xpos; - win->area[0].dsp_sty = ypos; - xact = win->area[0].xact; - yact = win->area[0].yact; - xvir = win->area[0].xvir; - yvir = win->area[0].yvir; - } - rk3368_hwc_reg_update(&lcdc_dev->driver, 4); - spin_unlock(&lcdc_dev->reg_lock); - - DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d", - lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt), - xact, yact, win->area[0].xsize); - DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - win->area[0].ysize, xvir, yvir, xpos, ypos); - return 0; -} - -static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = NULL; - struct rk_screen *screen = dev_drv->cur_screen; - - if (unlikely(!lcdc_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on); - return 0; - } - win = dev_drv->win[win_id]; - switch (win_id) { - case 0: - win_0_1_set_par(lcdc_dev, screen, win); - break; - case 1: - win_0_1_set_par(lcdc_dev, screen, win); - break; - case 2: - win_2_3_set_par(lcdc_dev, screen, win); - break; - case 3: - win_2_3_set_par(lcdc_dev, screen, win); - break; - case 4: - hwc_set_par(lcdc_dev, screen, win); - break; - default: - dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id); - break; - } - return 0; -} - -static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd, - unsigned long arg, int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 panel_size[2]; - void __user *argp = (void __user *)arg; - struct color_key_cfg clr_key_cfg; - - switch (cmd) { - case RK_FBIOGET_PANEL_SIZE: - panel_size[0] = lcdc_dev->screen->mode.xres; - panel_size[1] = lcdc_dev->screen->mode.yres; - if (copy_to_user(argp, panel_size, 8)) - return -EFAULT; - break; - case RK_FBIOPUT_COLOR_KEY_CFG: - if (copy_from_user(&clr_key_cfg, argp, - sizeof(struct color_key_cfg))) - return -EFAULT; - rk3368_lcdc_clr_key_cfg(dev_drv); - lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, - clr_key_cfg.win0_color_key_cfg); - lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, - clr_key_cfg.win1_color_key_cfg); - break; - - default: - break; - } - return 0; -} - -static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct device_node *backlight; - struct property *prop; - u32 brightness_levels[256]; - u32 length, max, last; - - if (lcdc_dev->backlight) - return 0; - backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0); - if (backlight) { - lcdc_dev->backlight = of_find_backlight_by_node(backlight); - if (!lcdc_dev->backlight) - dev_info(lcdc_dev->dev, "No find backlight device\n"); - } else { - dev_info(lcdc_dev->dev, "No find backlight device node\n"); - } - prop = of_find_property(backlight, "brightness-levels", &length); - if (!prop) - return -EINVAL; - max = length / sizeof(u32); - last = max - 1; - if (!of_property_read_u32_array(backlight, "brightness-levels", - brightness_levels, max)) { - if (brightness_levels[0] > brightness_levels[last]) - dev_drv->cabc_pwm_pol = 1;/*negative*/ - else - dev_drv->cabc_pwm_pol = 0;/*positive*/ - } else { - dev_info(lcdc_dev->dev, "Can not read brightness-levels value\n"); - } - return 0; -} - -static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 intr_clr_reg; - - if (lcdc_dev->soc_type == VOP_FULL_RK3366) - intr_clr_reg = INTR_CLEAR_RK3366; - else - intr_clr_reg = INTR_CLEAR_RK3368; - - if (dev_drv->suspend_flag) - return 0; - /* close the backlight */ - /*rk3368_lcdc_get_backlight_device(dev_drv); - if (lcdc_dev->backlight) { - lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN; - backlight_update_status(lcdc_dev->backlight); - }*/ - - dev_drv->suspend_flag = 1; - flush_kthread_worker(&dev_drv->update_regs_worker); - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable) - dev_drv->trsm_ops->disable(); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN, - v_DSP_BLANK_EN(1)); - lcdc_msk_reg(lcdc_dev, - intr_clr_reg, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR, - v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1)); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO, - v_DSP_OUT_ZERO(1)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1)); - lcdc_cfg_done(lcdc_dev); - - if (dev_drv->iommu_enabled) { - if (dev_drv->mmu_dev) - rockchip_iovmm_deactivate(dev_drv->dev); - } - - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - rk3368_lcdc_clk_disable(lcdc_dev); - rk_disp_pwr_disable(dev_drv); - return 0; -} - -static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if (!dev_drv->suspend_flag) - return 0; - rk_disp_pwr_enable(dev_drv); - - if (1/*lcdc_dev->atv_layer_cnt*/) { - rk3368_lcdc_clk_enable(lcdc_dev); - rk3368_lcdc_reg_restore(lcdc_dev); - - spin_lock(&lcdc_dev->reg_lock); - if (dev_drv->cur_screen->dsp_lut) - rk3368_lcdc_set_lut(dev_drv, - dev_drv->cur_screen->dsp_lut); - if (dev_drv->cur_screen->cabc_lut && dev_drv->cabc_mode) - rk3368_set_cabc_lut(dev_drv, - dev_drv->cur_screen->cabc_lut); - - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO, - v_DSP_OUT_ZERO(0)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0)); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN, - v_DSP_BLANK_EN(0)); - lcdc_cfg_done(lcdc_dev); - - if (dev_drv->iommu_enabled) { - /* win address maybe effect after next frame start, - * but mmu maybe effect right now, so we delay 50ms - */ - mdelay(50); - if (dev_drv->mmu_dev) - rockchip_iovmm_activate(dev_drv->dev); - } - - spin_unlock(&lcdc_dev->reg_lock); - } - dev_drv->suspend_flag = 0; - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - mdelay(100); - return 0; -} - -static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv, - int win_id, int blank_mode) -{ - switch (blank_mode) { - case FB_BLANK_UNBLANK: - rk3368_lcdc_early_resume(dev_drv); - break; - case FB_BLANK_NORMAL: - rk3368_lcdc_early_suspend(dev_drv); - break; - default: - rk3368_lcdc_early_suspend(dev_drv); - break; - } - - dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode); - - return 0; -} - -static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, - int win_id, int area_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 win_ctrl = 0; - u32 area_status = 0, state = 0; - - switch (win_id) { - case 0: - win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0); - area_status = win_ctrl & m_WIN0_EN; - break; - case 1: - win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0); - area_status = win_ctrl & m_WIN1_EN; - break; - case 2: - win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0); - if (area_id == 0) - area_status = win_ctrl & (m_WIN2_MST0_EN | m_WIN2_EN); - if (area_id == 1) - area_status = win_ctrl & m_WIN2_MST1_EN; - if (area_id == 2) - area_status = win_ctrl & m_WIN2_MST2_EN; - if (area_id == 3) - area_status = win_ctrl & m_WIN2_MST3_EN; - break; - case 3: - win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0); - if (area_id == 0) - area_status = win_ctrl & (m_WIN3_MST0_EN | m_WIN3_EN); - if (area_id == 1) - area_status = win_ctrl & m_WIN3_MST1_EN; - if (area_id == 2) - area_status = win_ctrl & m_WIN3_MST2_EN; - if (area_id == 3) - area_status = win_ctrl & m_WIN3_MST3_EN; - break; - case 4: - win_ctrl = lcdc_readl(lcdc_dev, HWC_CTRL0); - area_status = win_ctrl & m_HWC_EN; - break; - default: - pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n", - __func__, win_id, area_id); - break; - } - - state = (area_status > 0) ? 1 : 0; - return state; -} - -static int rk3368_lcdc_get_area_num(struct rk_lcdc_driver *dev_drv, - unsigned int *area_support) -{ - area_support[0] = 1; - area_support[1] = 1; - area_support[2] = 4; - area_support[3] = 4; - - return 0; -} - -/*overlay will be do at regupdate*/ -static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, - bool set) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = NULL; - int i, ovl = 0; - unsigned int mask, val; - int z_order_num = 0; - int layer0_sel = 0, layer1_sel = 1, layer2_sel = 2, layer3_sel = 3; - - if (swap == 0) { - for (i = 0; i < 4; i++) { - win = dev_drv->win[i]; - if (win->state == 1) - z_order_num++; - } - for (i = 0; i < 4; i++) { - win = dev_drv->win[i]; - if (win->state == 0) - win->z_order = z_order_num++; - switch (win->z_order) { - case 0: - layer0_sel = win->id; - break; - case 1: - layer1_sel = win->id; - break; - case 2: - layer2_sel = win->id; - break; - case 3: - layer3_sel = win->id; - break; - default: - break; - } - } - } else { - layer0_sel = swap % 10; - layer1_sel = swap / 10 % 10; - layer2_sel = swap / 100 % 10; - layer3_sel = swap / 1000; - } - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - if (set) { - mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL | - m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL; - val = v_DSP_LAYER0_SEL(layer0_sel) | - v_DSP_LAYER1_SEL(layer1_sel) | - v_DSP_LAYER2_SEL(layer2_sel) | - v_DSP_LAYER3_SEL(layer3_sel); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - } else { - layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, - m_DSP_LAYER0_SEL); - layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, - m_DSP_LAYER1_SEL); - layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, - m_DSP_LAYER2_SEL); - layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, - m_DSP_LAYER3_SEL); - ovl = layer3_sel * 1000 + layer2_sel * 100 + - layer1_sel * 10 + layer0_sel; - } - } else { - ovl = -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - - return ovl; -} - -static char *rk3368_lcdc_format_to_string(int format, char *fmt) -{ - if (!fmt) - return NULL; - - switch (format) { - case 0: - strcpy(fmt, "ARGB888"); - break; - case 1: - strcpy(fmt, "RGB888"); - break; - case 2: - strcpy(fmt, "RGB565"); - break; - case 4: - strcpy(fmt, "YCbCr420"); - break; - case 5: - strcpy(fmt, "YCbCr422"); - break; - case 6: - strcpy(fmt, "YCbCr444"); - break; - default: - strcpy(fmt, "invalid\n"); - break; - } - return fmt; -} -static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv, - char *buf, int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u16 hsync_len = screen->mode.hsync_len; - u16 left_margin = screen->mode.left_margin; - u16 vsync_len = screen->mode.vsync_len; - u16 upper_margin = screen->mode.upper_margin; - u32 h_pw_bp = hsync_len + left_margin; - u32 v_pw_bp = vsync_len + upper_margin; - u32 fmt_id; - char format_w0[9] = "NULL"; - char format_w1[9] = "NULL"; - char format_w2_0[9] = "NULL"; - char format_w2_1[9] = "NULL"; - char format_w2_2[9] = "NULL"; - char format_w2_3[9] = "NULL"; - char format_w3_0[9] = "NULL"; - char format_w3_1[9] = "NULL"; - char format_w3_2[9] = "NULL"; - char format_w3_3[9] = "NULL"; - char dsp_buf[100]; - u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st; - u32 y_factor, uv_factor; - u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel; - u8 w0_state, w1_state, w2_state, w3_state; - u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state; - u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state; - - u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y; - u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp; - u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y; - u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp; - u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac; - u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac; - - u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y; - u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x; - u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y; - u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp; - u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp; - u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp; - u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp; - - u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y; - u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x; - u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y; - u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp; - u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp; - u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp; - u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp; - u32 dclk_freq; - int size = 0; - - dclk_freq = screen->mode.pixclock; - /*rk3368_lcdc_reg_dump(dev_drv); */ - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - zorder = lcdc_readl(lcdc_dev, DSP_CTRL1); - layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8; - layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10; - layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12; - layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14; - /*WIN0 */ - win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0); - w0_state = win_ctrl & m_WIN0_EN; - fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1; - rk3368_lcdc_format_to_string(fmt_id, format_w0); - vir_info = lcdc_readl(lcdc_dev, WIN0_VIR); - act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO); - dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO); - dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST); - y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB); - uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR); - w0_vir_y = vir_info & m_WIN0_VIR_STRIDE; - w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16; - w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1; - w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1; - w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1; - w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1; - if (w0_state) { - w0_st_x = dsp_st & m_WIN0_DSP_XST; - w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16; - } - w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB; - w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16; - w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR; - w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16; - - /*WIN1 */ - win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0); - w1_state = win_ctrl & m_WIN1_EN; - fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1; - rk3368_lcdc_format_to_string(fmt_id, format_w1); - vir_info = lcdc_readl(lcdc_dev, WIN1_VIR); - act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO); - dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO); - dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST); - y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB); - uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR); - w1_vir_y = vir_info & m_WIN1_VIR_STRIDE; - w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16; - w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1; - w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1; - w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1; - w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1; - if (w1_state) { - w1_st_x = dsp_st & m_WIN1_DSP_XST; - w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16; - } - w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB; - w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16; - w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR; - w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16; - /*WIN2 */ - win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0); - w2_state = win_ctrl & m_WIN2_EN; - w2_0_state = (win_ctrl & 0x10) >> 4; - w2_1_state = (win_ctrl & 0x100) >> 8; - w2_2_state = (win_ctrl & 0x1000) >> 12; - w2_3_state = (win_ctrl & 0x10000) >> 16; - vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1); - w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0; - w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16; - vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3); - w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2; - w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16; - - fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1; - rk3368_lcdc_format_to_string(fmt_id, format_w2_0); - fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1; - rk3368_lcdc_format_to_string(fmt_id, format_w2_1); - fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1; - rk3368_lcdc_format_to_string(fmt_id, format_w2_2); - fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1; - rk3368_lcdc_format_to_string(fmt_id, format_w2_3); - - dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0); - dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0); - w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1; - w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1; - if (w2_0_state) { - w2_0_st_x = dsp_st & m_WIN2_DSP_XST0; - w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16; - } - dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1); - dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1); - w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1; - w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1; - if (w2_1_state) { - w2_1_st_x = dsp_st & m_WIN2_DSP_XST1; - w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16; - } - dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2); - dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2); - w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1; - w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1; - if (w2_2_state) { - w2_2_st_x = dsp_st & m_WIN2_DSP_XST2; - w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16; - } - dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3); - dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3); - w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1; - w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1; - if (w2_3_state) { - w2_3_st_x = dsp_st & m_WIN2_DSP_XST3; - w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16; - } - - /*WIN3 */ - win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0); - w3_state = win_ctrl & m_WIN3_EN; - w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4; - w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 8; - w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 12; - w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 16; - vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1); - w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0; - w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16; - vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3); - w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2; - w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16; - fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1; - rk3368_lcdc_format_to_string(fmt_id, format_w3_0); - fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1; - rk3368_lcdc_format_to_string(fmt_id, format_w3_1); - fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1; - rk3368_lcdc_format_to_string(fmt_id, format_w3_2); - fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1; - rk3368_lcdc_format_to_string(fmt_id, format_w3_3); - dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0); - dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0); - w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1; - w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1; - if (w3_0_state) { - w3_0_st_x = dsp_st & m_WIN3_DSP_XST0; - w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16; - } - - dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1); - dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1); - w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1; - w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1; - if (w3_1_state) { - w3_1_st_x = dsp_st & m_WIN3_DSP_XST1; - w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16; - } - - dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2); - dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2); - w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1; - w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1; - if (w3_2_state) { - w3_2_st_x = dsp_st & m_WIN3_DSP_XST2; - w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16; - } - - dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3); - dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3); - w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1; - w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1; - if (w3_3_state) { - w3_3_st_x = dsp_st & m_WIN3_DSP_XST3; - w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16; - } - - } else { - spin_unlock(&lcdc_dev->reg_lock); - return -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - size += snprintf(dsp_buf, 80, - "z-order:\n win[%d]\n win[%d]\n win[%d]\n win[%d]\n", - layer3_sel, layer2_sel, layer1_sel, layer0_sel); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - /*win0*/ - size += snprintf(dsp_buf, 80, - "win0:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,", - w0_state, format_w0, w0_vir_y, w0_vir_uv); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n", - w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ", - w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n", - w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST), - lcdc_readl(lcdc_dev, WIN0_CBR_MST)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*win1*/ - size += snprintf(dsp_buf, 80, - "win1:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,", - w1_state, format_w1, w1_vir_y, w1_vir_uv); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n", - w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ", - w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n", - w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST), - lcdc_readl(lcdc_dev, WIN1_CBR_MST)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*win2*/ - size += snprintf(dsp_buf, 80, - "win2:\n state:%d\n", - w2_state); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - /*area 0*/ - size += snprintf(dsp_buf, 80, - " area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp, - lcdc_readl(lcdc_dev, WIN2_MST0)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*area 1*/ - size += snprintf(dsp_buf, 80, - " area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp, - lcdc_readl(lcdc_dev, WIN2_MST1)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*area 2*/ - size += snprintf(dsp_buf, 80, - " area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp, - lcdc_readl(lcdc_dev, WIN2_MST2)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*area 3*/ - size += snprintf(dsp_buf, 80, - " area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp, - lcdc_readl(lcdc_dev, WIN2_MST3)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*win3*/ - size += snprintf(dsp_buf, 80, - "win3:\n state:%d\n", - w3_state); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - /*area 0*/ - size += snprintf(dsp_buf, 80, - " area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp, - lcdc_readl(lcdc_dev, WIN3_MST0)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*area 1*/ - size += snprintf(dsp_buf, 80, - " area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp, - lcdc_readl(lcdc_dev, WIN3_MST1)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*area 2*/ - size += snprintf(dsp_buf, 80, - " area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp, - lcdc_readl(lcdc_dev, WIN3_MST2)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /*area 3*/ - size += snprintf(dsp_buf, 80, - " area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,", - w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - size += snprintf(dsp_buf, 80, - " x_st:%4d, y_st:%4d, y_addr:0x%08x\n", - w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp, - lcdc_readl(lcdc_dev, WIN3_MST3)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - return size; -} - -static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, - bool set) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u64 ft = 0; - u32 dotclk; - int ret; - u32 pixclock; - u32 x_total, y_total; - - if (set) { - if (fps == 0) { - dev_info(dev_drv->dev, "unsupport set fps=0\n"); - return 0; - } - ft = div_u64(1000000000000llu, fps); - x_total = - screen->mode.upper_margin + screen->mode.lower_margin + - screen->mode.yres + screen->mode.vsync_len; - y_total = - screen->mode.left_margin + screen->mode.right_margin + - screen->mode.xres + screen->mode.hsync_len; - dev_drv->pixclock = div_u64(ft, x_total * y_total); - dotclk = div_u64(1000000000000llu, dev_drv->pixclock); - ret = clk_set_rate(lcdc_dev->dclk, dotclk); - } - - pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - lcdc_dev->pixclock = pixclock; - dev_drv->pixclock = lcdc_dev->pixclock; - fps = rk_fb_calc_fps(screen, pixclock); - screen->ft = 1000 / fps; /*one frame time in ms */ - - if (set) - dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__, - clk_get_rate(lcdc_dev->dclk), fps); - - return fps; -} - -static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order) -{ - mutex_lock(&dev_drv->fb_win_id_mutex); - if (order == FB_DEFAULT_ORDER) - order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC; - dev_drv->fb4_win_id = order / 10000; - dev_drv->fb3_win_id = (order / 1000) % 10; - dev_drv->fb2_win_id = (order / 100) % 10; - dev_drv->fb1_win_id = (order / 10) % 10; - dev_drv->fb0_win_id = order % 10; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return 0; -} - -static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv, - const char *id) -{ - int win_id = 0; - - mutex_lock(&dev_drv->fb_win_id_mutex); - if (!strcmp(id, "fb0") || !strcmp(id, "fb5")) - win_id = dev_drv->fb0_win_id; - else if (!strcmp(id, "fb1") || !strcmp(id, "fb6")) - win_id = dev_drv->fb1_win_id; - else if (!strcmp(id, "fb2") || !strcmp(id, "fb7")) - win_id = dev_drv->fb2_win_id; - else if (!strcmp(id, "fb3") || !strcmp(id, "fb8")) - win_id = dev_drv->fb3_win_id; - else if (!strcmp(id, "fb4") || !strcmp(id, "fb9")) - win_id = dev_drv->fb4_win_id; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return win_id; -} - -static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int i; - unsigned int mask, val, fbdc_en = 0; - struct rk_lcdc_win *win = NULL; - u32 line_scane_num, dsp_vs_st_f1; - - if (lcdc_dev->driver.cur_screen->mode.vmode & FB_VMODE_INTERLACED) { - dsp_vs_st_f1 = lcdc_readl(lcdc_dev, DSP_VS_ST_END_F1) >> 16; - for (i = 0; i < 1000; i++) { - line_scane_num = - lcdc_readl(lcdc_dev, SCAN_LINE_NUM) & 0x1fff; - if (line_scane_num > dsp_vs_st_f1 + 1) - udelay(50); - else - break; - } - } - - spin_lock(&lcdc_dev->reg_lock); - rk3368_lcdc_post_cfg(dev_drv); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, - v_STANDBY_EN(lcdc_dev->standby)); - for (i = 0; i < 4; i++) { - win = dev_drv->win[i]; - fbdc_en |= win->area[0].fbdc_en; - if ((win->state == 0) && (win->last_state == 1)) { - switch (win->id) { - case 0: - /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0); - for rk3288 to fix hw bug? */ - mask = m_WIN0_EN; - val = v_WIN0_EN(0); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val); - break; - case 1: - /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0); - for rk3288 to fix hw bug? */ - mask = m_WIN1_EN; - val = v_WIN1_EN(0); - lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val); - break; - case 2: - mask = m_WIN2_EN | m_WIN2_MST0_EN | - m_WIN2_MST1_EN | - m_WIN2_MST2_EN | m_WIN2_MST3_EN; - val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) | - v_WIN2_MST1_EN(0) | - v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val); - break; - case 3: - mask = m_WIN3_EN | m_WIN3_MST0_EN | - m_WIN3_MST1_EN | - m_WIN3_MST2_EN | m_WIN3_MST3_EN; - val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) | - v_WIN3_MST1_EN(0) | - v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0); - lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val); - break; - case 4: - mask = m_HWC_EN; - val = v_HWC_EN(0); - lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val); - break; - default: - break; - } - } - win->last_state = win->state; - } - if (lcdc_dev->soc_type == VOP_FULL_RK3368) { - mask = m_IFBDC_CTRL_FBDC_EN; - val = v_IFBDC_CTRL_FBDC_EN(fbdc_en); - lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val); - } - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv, - int enable) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - if (enable) - enable_irq(lcdc_dev->irq); - else - disable_irq(lcdc_dev->irq); - return 0; -} - -int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 int_reg_val; - int ret; - u32 intr_status_reg, intr_clear_reg; - - if (lcdc_dev->soc_type == VOP_FULL_RK3366) { - intr_status_reg = INTR_STATUS_RK3366; - intr_clear_reg = INTR_CLEAR_RK3366; - } else { - intr_status_reg = INTR_STATUS_RK3368; - intr_clear_reg = INTR_CLEAR_RK3368; - } - - if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) { - int_reg_val = lcdc_readl(lcdc_dev, intr_status_reg); - if (int_reg_val & m_LINE_FLAG0_INTR_STS) { - lcdc_dev->driver.frame_time.last_framedone_t = - lcdc_dev->driver.frame_time.framedone_t; - lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0); - lcdc_msk_reg(lcdc_dev, intr_clear_reg, - m_LINE_FLAG0_INTR_CLR, - v_LINE_FLAG0_INTR_CLR(1)); - ret = RK_LF_STATUS_FC; - } else { - ret = RK_LF_STATUS_FR; - } - } else { - ret = RK_LF_STATUS_NC; - } - - return ret; -} - -static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv, - unsigned int dsp_addr[][4]) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - dsp_addr[0][0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST); - dsp_addr[1][0] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST); - dsp_addr[2][0] = lcdc_readl(lcdc_dev, WIN2_MST0); - dsp_addr[2][1] = lcdc_readl(lcdc_dev, WIN2_MST1); - dsp_addr[2][2] = lcdc_readl(lcdc_dev, WIN2_MST2); - dsp_addr[2][3] = lcdc_readl(lcdc_dev, WIN2_MST3); - dsp_addr[3][0] = lcdc_readl(lcdc_dev, WIN3_MST0); - dsp_addr[3][1] = lcdc_readl(lcdc_dev, WIN3_MST1); - dsp_addr[3][2] = lcdc_readl(lcdc_dev, WIN3_MST2); - dsp_addr[3][3] = lcdc_readl(lcdc_dev, WIN3_MST3); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, - int mode, int calc, int up, - int down, int global) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u32 total_pixel, calc_pixel, stage_up, stage_down; - u32 pixel_num, global_dn; - u32 mask = 0, val = 0; - int *cabc_lut = NULL; - - if (screen->type == SCREEN_HDMI && screen->type == SCREEN_TVOUT) { - pr_err("screen type is %d, not support cabc\n", screen->type); - return 0; - } else if (!screen->cabc_lut) { - pr_err("screen cabc lut not config, so not open cabc\n"); - return 0; - } else { - cabc_lut = screen->cabc_lut; - } - - if (mode == 0) { - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - lcdc_msk_reg(lcdc_dev, CABC_CTRL0, - m_CABC_EN, v_CABC_EN(0)); - lcdc_cfg_done(lcdc_dev); - } - pr_info("mode = 0, close cabc\n"); - dev_drv->cabc_mode = mode; - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - if (dev_drv->cabc_mode == 0) - rk3368_set_cabc_lut(dev_drv, dev_drv->cur_screen->cabc_lut); - - total_pixel = screen->mode.xres * screen->mode.yres; - pixel_num = 1000 - calc; - calc_pixel = (total_pixel * pixel_num) / 1000; - stage_up = up; - stage_down = down; - global_dn = global; - pr_info("enable cabc:mode=%d, calc=%d, up=%d, down=%d, global=%d\n", - mode, calc, stage_up, stage_down, global_dn); - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - mask = m_CABC_EN | m_CABC_HANDLE_EN | m_PWM_CONFIG_MODE | - m_CABC_CALC_PIXEL_NUM; - val = v_CABC_EN(1) | v_CABC_HANDLE_EN(1) | - v_PWM_CONFIG_MODE(STAGE_BY_STAGE) | - v_CABC_CALC_PIXEL_NUM(calc_pixel); - lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val); - - mask = m_CABC_LUT_EN | m_CABC_TOTAL_PIXEL_NUM; - val = v_CABC_LUT_EN(1) | v_CABC_TOTAL_PIXEL_NUM(total_pixel); - lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val); - - mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_UP | - m_CABC_STAGE_MODE | m_MAX_SCALE_CFG_VALUE | - m_MAX_SCALE_CFG_ENABLE; - val = v_CABC_STAGE_DOWN(stage_down) | - v_CABC_STAGE_UP(stage_up) | - v_CABC_STAGE_MODE(0) | v_MAX_SCALE_CFG_VALUE(1) | - v_MAX_SCALE_CFG_ENABLE(0); - lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val); - - mask = m_CABC_GLOBAL_DN | m_CABC_GLOBAL_DN_LIMIT_EN; - val = v_CABC_GLOBAL_DN(global_dn) | - v_CABC_GLOBAL_DN_LIMIT_EN(1); - lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val); - lcdc_cfg_done(lcdc_dev); - dev_drv->cabc_mode = mode; - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -/* - a:[-30~0]: - sin_hue = sin(a)*256 +0x100; - cos_hue = cos(a)*256; - a:[0~30] - sin_hue = sin(a)*256; - cos_hue = cos(a)*256; -*/ -static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv, - bcsh_hue_mode mode) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 val = 0; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - val = lcdc_readl(lcdc_dev, BCSH_H); - switch (mode) { - case H_SIN: - val &= m_BCSH_SIN_HUE; - break; - case H_COS: - val &= m_BCSH_COS_HUE; - val >>= 16; - break; - default: - break; - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return val; -} - -static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv, - int sin_hue, int cos_hue) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE; - val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue); - lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv, - bcsh_bcs_mode mode, int value) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask = 0, val = 0; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - switch (mode) { - case BRIGHTNESS: - /*user: from 0 to 255,typical is 128, - *vop,6bit: from 0 to 64, typical is 32*/ - value /= 4; - if (value < 0x20) - value += 0x20; - else if (value >= 0x20) - value = value - 0x20; - mask = m_BCSH_BRIGHTNESS; - val = v_BCSH_BRIGHTNESS(value); - break; - case CONTRAST: - /*user: from 0 to 510,typical is 256 - *vop,9bit, from 0 to 511,typical is 256*/ - value = 512 - value; - mask = m_BCSH_CONTRAST; - val = v_BCSH_CONTRAST(value); - break; - case SAT_CON: - /*from 0 to 1024,typical is 512 - *vop,9bit, from 0 to 512, typical is 256*/ - value /= 2; - mask = m_BCSH_SAT_CON; - val = v_BCSH_SAT_CON(value); - break; - default: - break; - } - lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - return val; -} - -static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv, - bcsh_bcs_mode mode) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 val = 0; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - val = lcdc_readl(lcdc_dev, BCSH_BCS); - switch (mode) { - case BRIGHTNESS: - val &= m_BCSH_BRIGHTNESS; - if (val >= 0x20) - val -= 0x20; - else - val += 0x20; - val <<= 2; - break; - case CONTRAST: - val &= m_BCSH_CONTRAST; - val >>= 8; - break; - case SAT_CON: - val &= m_BCSH_SAT_CON; - val >>= 20; - val <<= 1; - break; - default: - break; - } - } - spin_unlock(&lcdc_dev->reg_lock); - return val; -} - -static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if (lcdc_dev->clk_on) { - if (open) { - lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1); - lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000); - lcdc_writel(lcdc_dev, BCSH_H, 0x01000000); - dev_drv->bcsh.enable = 1; - } else { - mask = m_BCSH_EN; - val = v_BCSH_EN(0); - lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val); - dev_drv->bcsh.enable = 0; - } - rk3368_lcdc_bcsh_path_sel(dev_drv); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable) -{ - if (!enable || !dev_drv->bcsh.enable) { - rk3368_lcdc_open_bcsh(dev_drv, false); - return 0; - } - - if (dev_drv->bcsh.brightness <= 255 || - dev_drv->bcsh.contrast <= 510 || - dev_drv->bcsh.sat_con <= 1015 || - (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) { - rk3368_lcdc_open_bcsh(dev_drv, true); - if (dev_drv->bcsh.brightness <= 255) - rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS, - dev_drv->bcsh.brightness); - if (dev_drv->bcsh.contrast <= 510) - rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST, - dev_drv->bcsh.contrast); - if (dev_drv->bcsh.sat_con <= 1015) - rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON, - dev_drv->bcsh.sat_con); - if (dev_drv->bcsh.sin_hue <= 511 && - dev_drv->bcsh.cos_hue <= 511) - rk3368_lcdc_set_bcsh_hue(dev_drv, - dev_drv->bcsh.sin_hue, - dev_drv->bcsh.cos_hue); - } - return 0; -} - -static int __maybe_unused -rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if (enable) { - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN, - v_DSP_BLACK_EN(1)); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN, - v_DSP_BLACK_EN(0)); - - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - } - - return 0; -} - - -static int rk3368_lcdc_wait_frame_start(struct rk_lcdc_driver *dev_drv, - int enable) -{ - u32 line_scane_num, vsync_end, vact_end; - u32 interlace_mode; - - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if (unlikely(!lcdc_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on); - return 0; - } - if (0 == enable) { - interlace_mode = lcdc_read_bit(lcdc_dev, DSP_CTRL0, - m_DSP_INTERLACE); - if (interlace_mode) { - vsync_end = lcdc_readl(lcdc_dev, DSP_VS_ST_END_F1) & - m_DSP_VS_END_F1; - vact_end = lcdc_readl(lcdc_dev, DSP_VACT_ST_END_F1) & - m_DSP_VACT_END_F1; - } else { - vsync_end = lcdc_readl(lcdc_dev, DSP_VTOTAL_VS_END) & - m_DSP_VS_PW; - vact_end = lcdc_readl(lcdc_dev, DSP_VACT_ST_END) & - m_DSP_VACT_END; - } - while (1) { - line_scane_num = lcdc_readl(lcdc_dev, SCAN_LINE_NUM) & - 0x1fff; - if ((line_scane_num > vsync_end) && - (line_scane_num <= vact_end - 100)) - break; - } - return 0; - } else if (1 == enable) { - line_scane_num = lcdc_readl(lcdc_dev, SCAN_LINE_NUM) & 0x1fff; - return line_scane_num; - } - - return 0; -} - -static int rk3368_lcdc_backlight_close(struct rk_lcdc_driver *dev_drv, - int enable) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if (unlikely(!lcdc_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on); - return 0; - } - rk3368_lcdc_get_backlight_device(dev_drv); - - if (enable) { - /* close the backlight */ - if (lcdc_dev->backlight) { - lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN; - backlight_update_status(lcdc_dev->backlight); - } - if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable) - dev_drv->trsm_ops->disable(); - } else { - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - msleep(100); - /* open the backlight */ - if (lcdc_dev->backlight) { - lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK; - backlight_update_status(lcdc_dev->backlight); - } - } - - return 0; -} - -static int rk3368_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv, - struct overscan *overscan) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if (unlikely(!lcdc_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on); - return 0; - } - /*rk3368_lcdc_post_cfg(dev_drv);*/ - - return 0; -} - -static int rk3368_lcdc_extern_func(struct rk_lcdc_driver *dev_drv, - int cmd) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 val; - - if (unlikely(!lcdc_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on); - return 0; - } - - switch (cmd) { - case GET_PAGE_FAULT: - val = lcdc_readl(lcdc_dev, MMU_INT_RAWSTAT); - if ((val & 0x1) == 1) { - if ((val & 0x2) == 1) - pr_info("val=0x%x,vop iommu bus error\n", val); - else - return 1; - } - break; - case CLR_PAGE_FAULT: - lcdc_writel(lcdc_dev, MMU_INT_CLEAR, 0x3); - break; - case UNMASK_PAGE_FAULT: - lcdc_writel(lcdc_dev, MMU_INT_MASK, 0x2); - break; - default: - break; - } - - return 0; -} - -static int rk3368_lcdc_set_wb(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_fb_reg_wb_data *wb_data; - u32 src_w, src_h, dst_w, dst_h, fmt_cfg; - u32 xscale_en = 0, x_scale_fac = 0, y_throw = 0; - u32 csc_mode = 0, rgb2yuv = 0, dither_en = 0; - - if (unlikely(!lcdc_dev->clk_on)) { - pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on); - return 0; - } - wb_data = &dev_drv->wb_data; - if ((wb_data->xsize == 0) || (wb_data->ysize == 0)) - return 0; - - src_w = dev_drv->cur_screen->mode.xres; - src_h = dev_drv->cur_screen->mode.yres; - dst_w = wb_data->xsize; - dst_h = wb_data->ysize; - if (!IS_ALIGNED(dst_w, RK3366_WB_ALIGN)) - pr_info("dst_w: %d not align 16 pixel\n", dst_w); - - if (src_w > dst_w) - xscale_en = 1; - else if (src_w < dst_w) - dst_w = src_w; - else - xscale_en = 0; - if (wb_data->state && xscale_en) - x_scale_fac = GET_SCALE_FACTOR_BILI_DN(src_w, dst_w); - if ((src_h >= 2 * dst_h) && (dst_h != 0)) - y_throw = 1; - else - y_throw = 0; - switch (wb_data->data_format) { - case XRGB888: - case XBGR888: - fmt_cfg = 0; - break; - case RGB888: - case BGR888: - fmt_cfg = 1; - break; - case RGB565: - case BGR565: - fmt_cfg = 2; - dither_en = 1; - break; - case YUV420: - fmt_cfg = 4; - if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) - rgb2yuv = 1; - if ((src_w < 1280) && (src_h < 720)) - csc_mode = VOP_R2Y_CSC_BT601; - else - csc_mode = VOP_R2Y_CSC_BT709; - break; - default: - fmt_cfg = 0; - pr_info("unsupport fmt: %d\n", wb_data->data_format); - break; - } - spin_lock(&lcdc_dev->reg_lock); - lcdc_msk_reg(lcdc_dev, WB_CTRL0, - m_WB_EN | m_WB_FMT | m_WB_XPSD_BIL_EN | - m_WB_YTHROW_EN | m_WB_RGB2YUV_EN | m_WB_RGB2YUV_MODE | - m_WB_DITHER_EN, - v_WB_EN(wb_data->state) | v_WB_FMT(fmt_cfg) | - v_WB_XPSD_BIL_EN(xscale_en) | - v_WB_YTHROW_EN(y_throw) | v_WB_RGB2YUV_EN(rgb2yuv) | - v_WB_RGB2YUV_MODE(csc_mode) | v_WB_DITHER_EN(dither_en)); - lcdc_msk_reg(lcdc_dev, WB_CTRL1, - m_WB_WIDTH | m_WB_XPSD_BIL_FACTOR, - v_WB_WIDTH(dst_w) | - v_WB_XPSD_BIL_FACTOR(x_scale_fac)); - lcdc_writel(lcdc_dev, WB_YRGB_MST, wb_data->smem_start); - lcdc_writel(lcdc_dev, WB_CBR_MST, wb_data->cbr_start); - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static struct rk_lcdc_drv_ops lcdc_drv_ops = { - .open = rk3368_lcdc_open, - .win_direct_en = rk3368_lcdc_win_direct_en, - .load_screen = rk3368_load_screen, - .get_dspbuf_info = rk3368_get_dspbuf_info, - .post_dspbuf = rk3368_post_dspbuf, - .set_par = rk3368_lcdc_set_par, - .pan_display = rk3368_lcdc_pan_display, - .direct_set_addr = rk3368_lcdc_direct_set_win_addr, - /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/ - .blank = rk3368_lcdc_blank, - .ioctl = rk3368_lcdc_ioctl, - .suspend = rk3368_lcdc_early_suspend, - .resume = rk3368_lcdc_early_resume, - .get_win_state = rk3368_lcdc_get_win_state, - .area_support_num = rk3368_lcdc_get_area_num, - .ovl_mgr = rk3368_lcdc_ovl_mgr, - .get_disp_info = rk3368_lcdc_get_disp_info, - .fps_mgr = rk3368_lcdc_fps_mgr, - .fb_get_win_id = rk3368_lcdc_get_win_id, - .fb_win_remap = rk3368_fb_win_remap, - .set_dsp_lut = rk3368_lcdc_set_lut, - .set_cabc_lut = rk3368_set_cabc_lut, - .poll_vblank = rk3368_lcdc_poll_vblank, - .get_dsp_addr = rk3368_lcdc_get_dsp_addr, - .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc, - .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue, - .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs, - .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue, - .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs, - .open_bcsh = rk3368_lcdc_open_bcsh, - .dump_reg = rk3368_lcdc_reg_dump, - .cfg_done = rk3368_lcdc_config_done, - .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu, - /*.dsp_black = rk3368_lcdc_dsp_black,*/ - .backlight_close = rk3368_lcdc_backlight_close, - .mmu_en = rk3368_lcdc_mmu_en, - .set_overscan = rk3368_lcdc_set_overscan, - .extern_func = rk3368_lcdc_extern_func, - .wait_frame_start = rk3368_lcdc_wait_frame_start, - .set_wb = rk3368_lcdc_set_wb, -}; - -#ifdef LCDC_IRQ_EMPTY_DEBUG -static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev, - unsigned int intr_status) -{ - u32 intr_clr_reg; - - if (lcdc_dev->soc_type == VOP_FULL_RK3366) - intr_clr_reg = INTR_CLEAR_RK3366; - else - intr_clr_reg = INTR_CLEAR_RK3368; - - if (intr_status & m_WIN0_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_WIN0_EMPTY_INTR_CLR, - v_WIN0_EMPTY_INTR_CLR(1)); - dev_warn(lcdc_dev->dev, "win0 empty irq!"); - } else if (intr_status & m_WIN1_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_WIN1_EMPTY_INTR_CLR, - v_WIN1_EMPTY_INTR_CLR(1)); - dev_warn(lcdc_dev->dev, "win1 empty irq!"); - } else if (intr_status & m_WIN2_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_WIN2_EMPTY_INTR_CLR, - v_WIN2_EMPTY_INTR_CLR(1)); - dev_warn(lcdc_dev->dev, "win2 empty irq!"); - } else if (intr_status & m_WIN3_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_WIN3_EMPTY_INTR_CLR, - v_WIN3_EMPTY_INTR_CLR(1)); - dev_warn(lcdc_dev->dev, "win3 empty irq!"); - } else if (intr_status & m_HWC_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_HWC_EMPTY_INTR_CLR, - v_HWC_EMPTY_INTR_CLR(1)); - dev_warn(lcdc_dev->dev, "HWC empty irq!"); - } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_POST_BUF_EMPTY_INTR_CLR, - v_POST_BUF_EMPTY_INTR_CLR(1)); - dev_warn(lcdc_dev->dev, "post buf empty irq!"); - } else if (intr_status & m_PWM_GEN_INTR_STS) { - lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_PWM_GEN_INTR_CLR, - v_PWM_GEN_INTR_CLR(1)); - dev_warn(lcdc_dev->dev, "PWM gen irq!"); - } - return 0; -} -#endif - -static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id) -{ - struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id; - ktime_t timestamp = ktime_get(); - u32 intr_status; - u32 line_scane_num, dsp_vs_st_f1; - struct rk_screen *screen = lcdc_dev->driver.cur_screen; - u32 intr_en_reg, intr_clr_reg, intr_status_reg; - - if (lcdc_dev->soc_type == VOP_FULL_RK3366) { - intr_status_reg = INTR_STATUS_RK3366; - intr_clr_reg = INTR_CLEAR_RK3366; - intr_en_reg = INTR_EN_RK3366; - } else { - intr_status_reg = INTR_STATUS_RK3368; - intr_clr_reg = INTR_CLEAR_RK3368; - intr_en_reg = INTR_EN_RK3368; - } - - intr_status = lcdc_readl(lcdc_dev, intr_status_reg); - if (intr_status & m_FS_INTR_STS) { - timestamp = ktime_get(); - lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_FS_INTR_CLR, - v_FS_INTR_CLR(1)); - line_scane_num = lcdc_readl(lcdc_dev, SCAN_LINE_NUM) & 0x1fff; - dsp_vs_st_f1 = lcdc_readl(lcdc_dev, DSP_VS_ST_END_F1) >> 16; - /*if(lcdc_dev->driver.wait_fs){ */ - if (0) { - spin_lock(&(lcdc_dev->driver.cpl_lock)); - complete(&(lcdc_dev->driver.frame_done)); - spin_unlock(&(lcdc_dev->driver.cpl_lock)); - } - lcdc_dev->driver.vsync_info.timestamp = timestamp; - if ((lcdc_dev->soc_type == VOP_FULL_RK3366) && - (lcdc_dev->driver.wb_data.state)) { - if (lcdc_read_bit(lcdc_dev, WB_CTRL0, m_WB_EN)) { - lcdc_msk_reg(lcdc_dev, WB_CTRL0, - m_WB_EN, v_WB_EN(0)); - lcdc_cfg_done(lcdc_dev); - lcdc_dev->driver.wb_data.state = 0; - } - } - wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait); - if (!(screen->mode.vmode & FB_VMODE_INTERLACED) || - (line_scane_num >= dsp_vs_st_f1)) { - lcdc_dev->driver.vsync_info.timestamp = timestamp; - wake_up_interruptible_all( - &lcdc_dev->driver.vsync_info.wait); - } - } else if (intr_status & m_LINE_FLAG0_INTR_STS) { - lcdc_dev->driver.frame_time.last_framedone_t = - lcdc_dev->driver.frame_time.framedone_t; - lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0); - lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_LINE_FLAG0_INTR_CLR, - v_LINE_FLAG0_INTR_CLR(1)); - } else if (intr_status & m_LINE_FLAG1_INTR_STS) { - /*line flag1 */ - lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_LINE_FLAG1_INTR_CLR, - v_LINE_FLAG1_INTR_CLR(1)); - } else if (intr_status & m_FS_NEW_INTR_STS) { - /*new frame start */ - lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_FS_NEW_INTR_CLR, - v_FS_NEW_INTR_CLR(1)); - } else if (intr_status & m_BUS_ERROR_INTR_STS) { - lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_BUS_ERROR_INTR_CLR, - v_BUS_ERROR_INTR_CLR(1)); - dev_warn(lcdc_dev->dev, "bus error!"); - } - - /* for win empty debug */ -#ifdef LCDC_IRQ_EMPTY_DEBUG - rk3368_lcdc_parse_irq(lcdc_dev, intr_status); -#endif - return IRQ_HANDLED; -} - -#if defined(CONFIG_PM) -static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state) -{ - return 0; -} - -static int rk3368_lcdc_resume(struct platform_device *pdev) -{ - return 0; -} -#else -#define rk3368_lcdc_suspend NULL -#define rk3368_lcdc_resume NULL -#endif - -static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev) -{ - struct device_node *np = lcdc_dev->dev->of_node; - struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver; - int val; - - if (of_property_read_u32(np, "rockchip,prop", &val)) - lcdc_dev->prop = PRMRY; /*default set it as primary */ - else - lcdc_dev->prop = val; - - if (of_property_read_u32(np, "rockchip,mirror", &val)) - dev_drv->rotate_mode = NO_MIRROR; - else - dev_drv->rotate_mode = val; - - if (of_property_read_u32(np, "rockchip,cabc_mode", &val)) - dev_drv->cabc_mode = 0; /* default set close cabc */ - else - dev_drv->cabc_mode = val; - - if (of_property_read_u32(np, "rockchip,pwr18", &val)) - /*default set it as 3.xv power supply */ - lcdc_dev->pwr18 = false; - else - lcdc_dev->pwr18 = (val ? true : false); - - if (of_property_read_u32(np, "rockchip,fb-win-map", &val)) - dev_drv->fb_win_map = FB_DEFAULT_ORDER; - else - dev_drv->fb_win_map = val; - - if (of_property_read_u32(np, "rockchip,bcsh-en", &val)) - dev_drv->bcsh.enable = false; - else - dev_drv->bcsh.enable = (val ? true : false); - - if (of_property_read_u32(np, "rockchip,brightness", &val)) - dev_drv->bcsh.brightness = 0xffff; - else - dev_drv->bcsh.brightness = val; - - if (of_property_read_u32(np, "rockchip,contrast", &val)) - dev_drv->bcsh.contrast = 0xffff; - else - dev_drv->bcsh.contrast = val; - - if (of_property_read_u32(np, "rockchip,sat-con", &val)) - dev_drv->bcsh.sat_con = 0xffff; - else - dev_drv->bcsh.sat_con = val; - - if (of_property_read_u32(np, "rockchip,hue", &val)) { - dev_drv->bcsh.sin_hue = 0xffff; - dev_drv->bcsh.cos_hue = 0xffff; - } else { - dev_drv->bcsh.sin_hue = val & 0xff; - dev_drv->bcsh.cos_hue = (val >> 8) & 0xff; - } - - if (of_property_read_u32(np, "rockchip,iommu-enabled", &val)) - dev_drv->iommu_enabled = 0; - else - dev_drv->iommu_enabled = val; - return 0; -} - -static int rk3368_lcdc_probe(struct platform_device *pdev) -{ - struct lcdc_device *lcdc_dev = NULL; - struct rk_lcdc_driver *dev_drv; - struct device *dev = &pdev->dev; - struct resource *res; - struct device_node *np = pdev->dev.of_node; - int prop; - int ret = 0; - - /*if the primary lcdc has not registered ,the extend - lcdc register later */ - of_property_read_u32(np, "rockchip,prop", &prop); - if (prop == EXTEND) { - if (!is_prmry_rk_lcdc_registered()) - return -EPROBE_DEFER; - } - lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL); - if (!lcdc_dev) { - dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!"); - return -ENOMEM; - } - platform_set_drvdata(pdev, lcdc_dev); - lcdc_dev->dev = dev; - rk3368_lcdc_parse_dt(lcdc_dev); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) - /* enable power domain */ - pm_runtime_enable(dev); -#endif - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - lcdc_dev->reg_phy_base = res->start; - lcdc_dev->len = resource_size(res); - - lcdc_dev->regs = devm_ioremap(&pdev->dev, res->start, - resource_size(res)); - if (IS_ERR(lcdc_dev->regs)) - return PTR_ERR(lcdc_dev->regs); - else - dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs); - - lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL); - if (IS_ERR(lcdc_dev->regsbak)) - return PTR_ERR(lcdc_dev->regsbak); - lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR); - lcdc_dev->cabc_lut_addr_base = (lcdc_dev->regs + CABC_GAMMA_LUT_ADDR); - lcdc_dev->grf_base = - syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); - if (IS_ERR(lcdc_dev->grf_base)) { - dev_err(&pdev->dev, "can't find lcdc grf property\n"); - lcdc_dev->grf_base = NULL; - } - lcdc_dev->pmugrf_base = - syscon_regmap_lookup_by_phandle(np, "rockchip,pmugrf"); - if (IS_ERR(lcdc_dev->pmugrf_base)) { - dev_err(&pdev->dev, "can't find lcdc pmu grf property\n"); - lcdc_dev->pmugrf_base = NULL; - } - - lcdc_dev->cru_base = - syscon_regmap_lookup_by_phandle(np, "rockchip,cru"); - if (IS_ERR(lcdc_dev->cru_base)) { - dev_err(&pdev->dev, "can't find lcdc cru_base property\n"); - lcdc_dev->cru_base = NULL; - } - - lcdc_dev->id = 0; - dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id); - dev_drv = &lcdc_dev->driver; - dev_drv->dev = dev; - dev_drv->prop = prop; - dev_drv->id = lcdc_dev->id; - dev_drv->ops = &lcdc_drv_ops; - dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win); - dev_drv->reserved_fb = 1;/*only need reserved 1 buffer*/ - spin_lock_init(&lcdc_dev->reg_lock); - - lcdc_dev->irq = platform_get_irq(pdev, 0); - if (lcdc_dev->irq < 0) { - dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n", - lcdc_dev->id); - return -ENXIO; - } - - ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr, - IRQF_SHARED, - dev_name(dev), lcdc_dev); - if (ret) { - dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", - lcdc_dev->irq, ret); - return ret; - } - - if (dev_drv->iommu_enabled) { - if (lcdc_dev->id == 0) { - strcpy(dev_drv->mmu_dts_name, - VOPB_IOMMU_COMPATIBLE_NAME); - } else { - strcpy(dev_drv->mmu_dts_name, - VOPL_IOMMU_COMPATIBLE_NAME); - } - } - - ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id); - if (ret < 0) { - dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id); - return ret; - } - if (lcdc_dev->soc_type == VOP_FULL_RK3366) - dev_drv->property.feature |= SUPPORT_WRITE_BACK; - else if (lcdc_dev->soc_type == VOP_FULL_RK3368) - dev_drv->property.feature |= SUPPORT_IFBDC; - dev_drv->property.feature |= SUPPORT_VOP_IDENTIFY | - SUPPORT_YUV420_OUTPUT; - dev_drv->property.max_output_x = 4096; - dev_drv->property.max_output_y = 2160; - lcdc_dev->screen = dev_drv->screen0; - dev_info(dev, "lcdc%d probe ok, iommu %s\n", - lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled"); - - return 0; -} - -static int rk3368_lcdc_remove(struct platform_device *pdev) -{ - return 0; -} - -static void rk3368_lcdc_shutdown(struct platform_device *pdev) -{ - struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver; -#if 1 - dev_drv->suspend_flag = 1; - mdelay(100); - flush_kthread_worker(&dev_drv->update_regs_worker); - kthread_stop(dev_drv->update_regs_thread); - rk3368_lcdc_deint(lcdc_dev); - /*if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable) - dev_drv->trsm_ops->disable();*/ - - rk3368_lcdc_clk_disable(lcdc_dev); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) - pm_runtime_disable(lcdc_dev->dev); -#endif - rk_disp_pwr_disable(dev_drv); -#else - rk3368_lcdc_early_suspend(&lcdc_dev->driver); - rk3368_lcdc_deint(lcdc_dev); -#endif -} - -#if defined(CONFIG_OF) -static const struct of_device_id rk3368_lcdc_dt_ids[] = { - {.compatible = "rockchip,rk3368-lcdc",}, - {.compatible = "rockchip,rk3366-lcdc-big",}, - {} -}; -#endif - -static struct platform_driver rk3368_lcdc_driver = { - .probe = rk3368_lcdc_probe, - .remove = rk3368_lcdc_remove, - .driver = { - .name = "rk3368-lcdc", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids), - }, - .suspend = rk3368_lcdc_suspend, - .resume = rk3368_lcdc_resume, - .shutdown = rk3368_lcdc_shutdown, -}; - -static int __init rk3368_lcdc_module_init(void) -{ - return platform_driver_register(&rk3368_lcdc_driver); -} - -static void __exit rk3368_lcdc_module_exit(void) -{ - platform_driver_unregister(&rk3368_lcdc_driver); -} - -fs_initcall(rk3368_lcdc_module_init); -module_exit(rk3368_lcdc_module_exit); diff --git a/drivers/video/rockchip/lcdc/rk3368_lcdc.h b/drivers/video/rockchip/lcdc/rk3368_lcdc.h deleted file mode 100644 index bcab60348233..000000000000 --- a/drivers/video/rockchip/lcdc/rk3368_lcdc.h +++ /dev/null @@ -1,2158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef RK3368_LCDC_H_ -#define RK3368_LCDC_H_ - -#include -#include -#include -#include -#include - -#define VOP_INPUT_MAX_WIDTH 4096 /*3840 for LINCOLN*/ - -#define REG_CFG_DONE (0x0000) -#define VOP_CFG_DONE(x) (((x)&1)<<0) -#define WIN0_CFG_DONE(x) (((x)&1)<<1) -#define WIN1_CFG_DONE(x) (((x)&1)<<2) -#define WIN2_CFG_DONE(x) (((x)&1)<<3) -#define WIN3_CFG_DONE(x) (((x)&1)<<4) -#define HWC_CFG_DONE(x) (((x)&1)<<5) -#define IEP_CFG_DONE(x) (((x)&1)<<6) -#define FBDC_CFG_DONE(x) (((x)&1)<<7) -#define SYS_CFG_DONE(x) (((x)&1)<<8) - -#define VOP_CFG_DONE_WMSK(x) (((x)&1)<<(0+16)) -#define WIN0_CFG_DONE_WMSK(x) (((x)&1)<<(1+16)) -#define WIN1_CFG_DONE_WMSK(x) (((x)&1)<<(2+16)) -#define WIN2_CFG_DONE_WMSK(x) (((x)&1)<<(3+16)) -#define WIN3_CFG_DONE_WMSK(x) (((x)&1)<<(4+16)) -#define HWC_CFG_DONE_WMSK(x) (((x)&1)<<(5+16)) -#define IEP_CFG_DONE_WMSK(x) (((x)&1)<<(6+16)) -#define FBDC_CFG_DONE_WMSK(x) (((x)&1)<<(7+16)) -#define SYS_CFG_DONE_WMSK(x) (((x)&1)<<(8+16)) - -#define VOP_REG_DONE (VOP_CFG_DONE(1) | VOP_CFG_DONE_WMSK(1)) -#define WIN0_REG_DONE (WIN0_CFG_DONE(1) | WIN0_CFG_DONE_WMSK(1)) -#define WIN1_REG_DONE (WIN1_CFG_DONE(1) | WIN1_CFG_DONE_WMSK(1)) -#define WIN2_REG_DONE (WIN2_CFG_DONE(1) | WIN2_CFG_DONE_WMSK(1)) -#define WIN3_REG_DONE (WIN3_CFG_DONE(1) | WIN3_CFG_DONE_WMSK(1)) -#define HWC_REG_DONE (HWC_CFG_DONE(1) | HWC_CFG_DONE_WMSK(1)) -#define IEP_REG_DONE (IEP_CFG_DONE(1) | IEP_CFG_DONE_WMSK(1)) -#define FBDC_REG_DONE (FBDC_CFG_DONE(1) | FBDC_CFG_DONE_WMSK(1)) -#define SYS_REG_DONE (SYS_CFG_DONE(1) | SYS_CFG_DONE_WMSK(1)) - -#define VERSION_INFO (0x0004) -#define m_RTL_VERSION (0xffff<<0) -#define m_FPGA_VERSION (0xffff<<16) -#define VOP_FULL_RK3368 0x03021223 -#define VOP_FULL_RK3366 0x03045635 - -#define SYS_CTRL (0x0008) -#define v_DIRECT_PATH_EN(x) (((x)&1)<<0) -#define v_DIRECT_PATCH_SEL(x) (((x)&3)<<1) -#define v_DOUB_CHANNEL_EN(x) (((x)&1)<<3) -#define v_DOUB_CH_OVERLAP_NUM(x) (((x)&0xf)<<4) -#define v_EDPI_HALT_EN(x) (((x)&1)<<8) -#define v_EDPI_WMS_MODE(x) (((x)&1)<<9) -#define v_EDPI_WMS_FS(x) (((x)&1)<<10) -#define v_GLOBAL_REGDONE_EN(x) (((x)&1)<<11) -#define v_RGB_OUT_EN(x) (((x)&1)<<12) -#define v_HDMI_OUT_EN(x) (((x)&1)<<13) -#define v_EDP_OUT_EN(x) (((x)&1)<<14) -#define v_MIPI_OUT_EN(x) (((x)&1)<<15) -#define v_OVERLAY_MODE(x) (((x)&1)<<16) -#define v_FS_SAME_ADDR_MASK_EN(x) (((x)&1)<<17) -#define v_POST_LB_MODE(x) (((x)&1)<<18) -#define v_WIN23_PRI_OPT_MODE(x) (((x)&1)<<19) -#define v_MMU_EN(x) (((x)&1)<<20) -#define v_DMA_STOP(x) (((x)&1)<<21) -#define v_STANDBY_EN(x) (((x)&1)<<22) -#define v_AUTO_GATING_EN(x) (((x)&1)<<23) - -#define m_DIRECT_PATH_EN (1<<0) -#define m_DIRECT_PATCH_SEL (3<<1) -#define m_DOUB_CHANNEL_EN (1<<3) -#define m_DOUB_CH_OVERLAP_NUM (0xf<<4) -#define m_EDPI_HALT_EN (1<<8) -#define m_EDPI_WMS_MODE (1<<9) -#define m_EDPI_WMS_FS (1<<10) -#define m_GLOBAL_REGDONE_EN (1<<11) -#define m_RGB_OUT_EN (1<<12) -#define m_HDMI_OUT_EN (1<<13) -#define m_EDP_OUT_EN (1<<14) -#define m_MIPI_OUT_EN (1<<15) -#define m_OVERLAY_MODE (1<<16) -#define m_FS_SAME_ADDR_MASK_EN (1<<17) -#define m_POST_LB_MODE (1<<18) -#define m_WIN23_PRI_OPT_MODE (1<<19) -#define m_MMU_EN (1<<20) -#define m_DMA_STOP (1<<21) -#define m_STANDBY_EN (1<<22) -#define m_AUTO_GATING_EN (1<<23) - -#define SYS_CTRL1 (0x000c) -#define v_NOC_HURRY_EN(x) (((x)&0x1)<<0) -#define v_NOC_HURRY_VALUE(x) (((x)&0x3)<<1) -#define v_NOC_HURRY_THRESHOLD(x) (((x)&0x3f)<<3) -#define v_NOC_QOS_EN(x) (((x)&0x1)<<9) -#define v_NOC_WIN_QOS(x) (((x)&0x3)<<10) -#define v_AXI_MAX_OUTSTANDING_EN(x) (((x)&0x1)<<12) -#define v_AXI_OUTSTANDING_MAX_NUM(x) (((x)&0x1f)<<13) -#define v_NOC_HURRY_W_MODE(x) (((x)&0x3)<<20) - -#define m_NOC_HURRY_EN (0x1<<0) -#define m_NOC_HURRY_VALUE (0x3<<1) -#define m_NOC_HURRY_THRESHOLD (0x3f<<3) -#define m_NOC_QOS_EN (0x1<<9) -#define m_NOC_WIN_QOS (0x3<<10) -#define m_AXI_MAX_OUTSTANDING_EN (0x1<<12) -#define m_AXI_OUTSTANDING_MAX_NUM (0x1f<<13) -#define m_NOC_HURRY_W_MODE (0x3<<20) - -#define DSP_CTRL0 (0x0010) -#define v_DSP_OUT_MODE(x) (((x)&0x0f)<<0) -#define v_SW_CORE_DCLK_SEL(x) (((x)&1)<<4) -#define v_DSP_DCLK_DDR(x) (((x)&1)<<8) -#define v_DSP_DDR_PHASE(x) (((x)&1)<<9) -#define v_DSP_INTERLACE(x) (((x)&1)<<10) -#define v_DSP_FIELD_POL(x) (((x)&1)<<11) -#define v_DSP_BG_SWAP(x) (((x)&1)<<12) -#define v_DSP_RB_SWAP(x) (((x)&1)<<13) -#define v_DSP_RG_SWAP(x) (((x)&1)<<14) -#define v_DSP_DELTA_SWAP(x) (((x)&1)<<15) -#define v_DSP_DUMMY_SWAP(x) (((x)&1)<<16) -#define v_DSP_OUT_ZERO(x) (((x)&1)<<17) -#define v_DSP_BLANK_EN(x) (((x)&1)<<18) -#define v_DSP_BLACK_EN(x) (((x)&1)<<19) -#define v_DSP_CCIR656_AVG(x) (((x)&1)<<20) -#define v_DSP_YUV_CLIP(x) (((x)&1)<<21) -#define v_DSP_X_MIR_EN(x) (((x)&1)<<22) -#define v_DSP_Y_MIR_EN(x) (((x)&1)<<23) -#define m_DSP_OUT_MODE (0x0f<<0) -#define m_SW_CORE_DCLK_SEL (1<<4) -#define m_DSP_DCLK_DDR (1<<8) -#define m_DSP_DDR_PHASE (1<<9) -#define m_DSP_INTERLACE (1<<10) -#define m_DSP_FIELD_POL (1<<11) -#define m_DSP_BG_SWAP (1<<12) -#define m_DSP_RB_SWAP (1<<13) -#define m_DSP_RG_SWAP (1<<14) -#define m_DSP_DELTA_SWAP (1<<15) -#define m_DSP_DUMMY_SWAP (1<<16) -#define m_DSP_OUT_ZERO (1<<17) -#define m_DSP_BLANK_EN (1<<18) -#define m_DSP_BLACK_EN (1<<19) -#define m_DSP_CCIR656_AVG (1<<20) -#define m_DSP_YUV_CLIP (1<<21) -#define m_DSP_X_MIR_EN (1<<22) -#define m_DSP_Y_MIR_EN (1<<23) - -#define DSP_CTRL1 (0x0014) -#define v_DSP_LUT_EN(x) (((x)&1)<<0) -#define v_PRE_DITHER_DOWN_EN(x) (((x)&1)<<1) -#define v_DITHER_DOWN_EN(x) (((x)&1)<<2) -#define v_DITHER_DOWN_MODE(x) (((x)&1)<<3) -#define v_DITHER_DOWN_SEL(x) (((x)&1)<<4) -#define v_DITHER_UP_EN(x) (((x)&1)<<6) -#define v_DSP_LAYER0_SEL(x) (((x)&3)<<8) -#define v_DSP_LAYER1_SEL(x) (((x)&3)<<10) -#define v_DSP_LAYER2_SEL(x) (((x)&3)<<12) -#define v_DSP_LAYER3_SEL(x) (((x)&3)<<14) - -#define v_RGB_LVDS_HSYNC_POL(x) (((x)&1)<<16) -#define v_RGB_LVDS_VSYNC_POL(x) (((x)&1)<<17) -#define v_RGB_LVDS_DEN_POL(x) (((x)&1)<<18) -#define v_RGB_LVDS_DCLK_POL(x) (((x)&1)<<19) - -#define v_HDMI_HSYNC_POL(x) (((x)&1)<<20) -#define v_HDMI_VSYNC_POL(x) (((x)&1)<<21) -#define v_HDMI_DEN_POL(x) (((x)&1)<<22) -#define v_HDMI_DCLK_POL(x) (((x)&1)<<23) - -#define v_EDP_HSYNC_POL(x) (((x)&1)<<24) -#define v_EDP_VSYNC_POL(x) (((x)&1)<<25) -#define v_EDP_DEN_POL(x) (((x)&1)<<26) -#define v_EDP_DCLK_POL(x) (((x)&1)<<27) - -#define v_MIPI_HSYNC_POL(x) (((x)&1)<<28) -#define v_MIPI_VSYNC_POL(x) (((x)&1)<<29) -#define v_MIPI_DEN_POL(x) (((x)&1)<<30) -#define v_MIPI_DCLK_POL(x) (((x)&1)<<31) - -#define m_DSP_LUT_EN (1<<0) -#define m_PRE_DITHER_DOWN_EN (1<<1) -#define m_DITHER_DOWN_EN (1<<2) -#define m_DITHER_DOWN_MODE (1<<3) -#define m_DITHER_DOWN_SEL (1<<4) -#define m_DITHER_UP_EN (1<<6) -#define m_DSP_LAYER0_SEL (3<<8) -#define m_DSP_LAYER1_SEL (3<<10) -#define m_DSP_LAYER2_SEL (3<<12) -#define m_DSP_LAYER3_SEL (3<<14) - -#define m_RGB_LVDS_HSYNC_POL (1<<16) -#define m_RGB_LVDS_VSYNC_POL (1<<17) -#define m_RGB_LVDS_DEN_POL (1<<18) -#define m_RGB_LVDS_DCLK_POL (1<<19) - -#define m_HDMI_HSYNC_POL (1<<20) -#define m_HDMI_VSYNC_POL (1<<21) -#define m_HDMI_DEN_POL (1<<22) -#define m_HDMI_DCLK_POL (1<<23) - -#define m_EDP_HSYNC_POL (1<<24) -#define m_EDP_VSYNC_POL (1<<25) -#define m_EDP_DEN_POL (1<<26) -#define m_EDP_DCLK_POL (1<<27) - -#define m_MIPI_HSYNC_POL (1<<28) -#define m_MIPI_VSYNC_POL (1<<29) -#define m_MIPI_DEN_POL (1<<30) -#define m_MIPI_DCLK_POL (1<<31) - -#define DSP_BG (0x0018) -#define v_DSP_BG_BLUE(x) (((x)&0xff) << 0) -#define v_DSP_BG_GREEN(x) (((x)&0xff) << 8) -#define v_DSP_BG_RED(x) (((x)&0xff) << 16) -#define m_DSP_BG_BLUE (0xff << 0) -#define m_DSP_BG_GREEN (0xff << 8) -#define m_DSP_BG_RED (0xff << 16) - -#define MCU_CTRL (0x001c) -#define v_MCU_PIX_TOTAL(x) (((x)&0x3f)<<0) -#define v_MCU_CS_PST(x) (((x)&0xf)<<6) -#define v_MCU_CS_PEND(x) (((x)&0x3f)<<10) -#define v_MCU_RW_PST(x) (((x)&0xf)<<16) -#define v_MCU_RW_PEND(x) (((x)&0x3f)<<20) -#define v_MCU_CLK_SEL(x) (((x)&1)<<26) -#define v_MCU_HOLD_MODE(x) (((x)&1)<<27) -#define v_MCU_FRAME_ST(x) (((x)&1)<<28) -#define v_MCU_RS(x) (((x)&1)<<29) -#define v_MCU_BYPASS(x) (((x)&1)<<30) -#define v_MCU_TYPE(x) (((x)&1)<<31) -#define m_MCU_PIX_TOTAL (0x3f<<0) -#define m_MCU_CS_PST (0xf<<6) -#define m_MCU_CS_PEND (0x3f<<10) -#define m_MCU_RW_PST (0xf<<16) -#define m_MCU_RW_PEND (0x3f<<20) -#define m_MCU_CLK_SEL (1<<26) -#define m_MCU_HOLD_MODE (1<<27) -#define m_MCU_FRAME_ST (1<<28) -#define m_MCU_RS (1<<29) -#define m_MCU_BYPASS (1<<30) -#define m_MCU_TYPE ((u32)1<<31) - -#define LINE_FLAG_RK3368 (0x0020)/*rk3368*/ -#define LINE_FLAG_RK3366 (0x02a0)/*rk3366*/ -#define m_DSP_LINE_FLAG0_NUM (0x1fff<<0) -#define m_DSP_LINE_FLAG1_NUM (0x1fff<<16) -#define v_DSP_LINE_FLAG0_NUM(x) (((x)&0x1fff)<<0) -#define v_DSP_LINE_FLAG1_NUM(x) (((x)&0x1fff)<<16) - -#define INTR_EN_RK3368 (0x0024)/*for rk3368*/ -#define INTR_EN_RK3366 (0x0280)/*for rk3366*/ -#define v_FS_INTR_EN(x) ((((x)&1)<<0) | ((1<<(0+16)))) -#define v_FS_NEW_INTR_EN(x) ((((x)&1)<<1) | ((1<<(1+16)))) -#define v_ADDR_SAME_INTR_EN(x) ((((x)&1)<<2) | ((1<<(2+16)))) -#define v_LINE_FLAG0_INTR_EN(x) ((((x)&1)<<3) | ((1<<(3+16)))) -#define v_LINE_FLAG1_INTR_EN(x) ((((x)&1)<<4) | ((1<<(4+16)))) -#define v_BUS_ERROR_INTR_EN(x) ((((x)&1)<<5) | ((1<<(5+16)))) -#define v_WIN0_EMPTY_INTR_EN(x) ((((x)&1)<<6) | ((1<<(6+16)))) -#define v_WIN1_EMPTY_INTR_EN(x) ((((x)&1)<<7) | ((1<<(7+16)))) -#define v_WIN2_EMPTY_INTR_EN(x) ((((x)&1)<<8) | ((1<<(8+16)))) -#define v_WIN3_EMPTY_INTR_EN(x) ((((x)&1)<<9) | ((1<<(9+16)))) -#define v_HWC_EMPTY_INTR_EN(x) ((((x)&1)<<10) | ((1<<(10+16)))) -#define v_POST_BUF_EMPTY_INTR_EN(x) ((((x)&1)<<11) | ((1<<(11+16)))) -#define v_PWM_GEN_INTR_EN(x) ((((x)&1)<<12) | ((1<<(12+16)))) -#define v_DSP_HOLD_VALID_INTR_EN(x) ((((x)&1)<<13) | ((1<<(13+16)))) -#define v_INTR_MMU_EN(x) ((((x)&1)<<14) | ((1<<(14+16))))/*rk3366*/ -#define v_INTR_DMA_FINISH_EN(x) ((((x)&1)<<15) | ((1<<(15+16))))/*rk3366*/ - -#define m_FS_INTR_EN ((1<<0) | ((1<<(0+16)))) -#define m_FS_NEW_INTR_EN ((1<<1) | ((1<<(1+16)))) -#define m_ADDR_SAME_INTR_EN ((1<<2) | ((1<<(2+16)))) -#define m_LINE_FLAG0_INTR_EN ((1<<3) | ((1<<(3+16)))) -#define m_LINE_FLAG1_INTR_EN ((1<<4) | ((1<<(4+16)))) -#define m_BUS_ERROR_INTR_EN ((1<<5) | ((1<<(5+16)))) -#define m_WIN0_EMPTY_INTR_EN ((1<<6) | ((1<<(6+16)))) -#define m_WIN1_EMPTY_INTR_EN ((1<<7) | ((1<<(7+16)))) -#define m_WIN2_EMPTY_INTR_EN ((1<<8) | ((1<<(8+16)))) -#define m_WIN3_EMPTY_INTR_EN ((1<<9) | ((1<<(9+16)))) -#define m_HWC_EMPTY_INTR_EN ((1<<10) | ((1<<(10+16)))) -#define m_POST_BUF_EMPTY_INTR_EN ((1<<11) | ((1<<(11+16)))) -#define m_PWM_GEN_INTR_EN ((1<<12) | ((1<<(12+16)))) -#define m_DSP_HOLD_VALID_INTR_EN ((1<<13) | ((1<<(13+16)))) -#define m_INTR_MMU_EN ((1<<14) | ((1<<(14+16))))/*rk3366*/ -#define m_INTR_DMA_FINISH_EN ((1<<15) | ((1<<(15+16))))/*rk3366*/ - -#define INTR_CLEAR_RK3368 (0x0028)/*rk3368*/ -#define INTR_CLEAR_RK3366 (0x0284)/*rk3366*/ -#define v_FS_INTR_CLR(x) ((((x)&1)<<0) | (1<<(0+16))) -#define v_FS_NEW_INTR_CLR(x) ((((x)&1)<<1) | (1<<(1+16))) -#define v_ADDR_SAME_INTR_CLR(x) ((((x)&1)<<2) | (1<<(2+16))) -#define v_LINE_FLAG0_INTR_CLR(x) ((((x)&1)<<3) | (1<<(3+16))) -#define v_LINE_FLAG1_INTR_CLR(x) ((((x)&1)<<4) | (1<<(4+16))) -#define v_BUS_ERROR_INTR_CLR(x) ((((x)&1)<<5) | (1<<(5+16))) -#define v_WIN0_EMPTY_INTR_CLR(x) ((((x)&1)<<6) | (1<<(6+16))) -#define v_WIN1_EMPTY_INTR_CLR(x) ((((x)&1)<<7) | (1<<(7+16))) -#define v_WIN2_EMPTY_INTR_CLR(x) ((((x)&1)<<8) | (1<<(8+16))) -#define v_WIN3_EMPTY_INTR_CLR(x) ((((x)&1)<<9) | (1<<(9+16))) -#define v_HWC_EMPTY_INTR_CLR(x) ((((x)&1)<<10) | (1<<(10+16))) -#define v_POST_BUF_EMPTY_INTR_CLR(x) ((((x)&1)<<11) | (1<<(11+16))) -#define v_PWM_GEN_INTR_CLR(x) ((((x)&1)<<12) | (1<<(12+16))) -#define v_DSP_HOLD_VALID_INTR_CLR(x) ((((x)&1)<<13) | (1<<(13+16))) -#define v_INTR_MMU_CLR(x) ((((x)&1)<<14) | ((1<<(14+16))))/*rk3366*/ -#define v_INTR_DMA_FINISH_CLR(x) ((((x)&1)<<15) | ((1<<(15+16))))/*rk3366*/ - -#define m_FS_INTR_CLR ((1<<0) | ((1<<(0+16)))) -#define m_FS_NEW_INTR_CLR ((1<<1) | ((1<<(1+16)))) -#define m_ADDR_SAME_INTR_CLR ((1<<2) | ((1<<(2+16)))) -#define m_LINE_FLAG0_INTR_CLR ((1<<3) | ((1<<(3+16)))) -#define m_LINE_FLAG1_INTR_CLR ((1<<4) | ((1<<(4+16)))) -#define m_BUS_ERROR_INTR_CLR ((1<<5) | ((1<<(5+16)))) -#define m_WIN0_EMPTY_INTR_CLR ((1<<6) | ((1<<(5+16)))) -#define m_WIN1_EMPTY_INTR_CLR ((1<<7) | ((1<<(7+16)))) -#define m_WIN2_EMPTY_INTR_CLR ((1<<8) | ((1<<(8+16)))) -#define m_WIN3_EMPTY_INTR_CLR ((1<<9) | ((1<<(9+16)))) -#define m_HWC_EMPTY_INTR_CLR ((1<<10) | ((1<<(10+16)))) -#define m_POST_BUF_EMPTY_INTR_CLR ((1<<11) | ((1<<(11+16)))) -#define m_PWM_GEN_INTR_CLR ((1<<12) | ((1<<(12+16)))) -#define m_DSP_HOLD_VALID_INTR_CLR ((1<<13) | ((1<<(13+16)))) -#define m_INTR_MMU_CLEAR ((1<<14) | ((1<<(14+16))))/*rk3366*/ -#define m_INTR_DMA_FINISH_CLEAR ((1<<15) | ((1<<(15+16))))/*rk3366*/ - -#define INTR_STATUS_RK3368 (0x002c)/*rk3366*/ -#define INTR_STATUS_RK3366 (0x0288)/*rk3366*/ -#define m_FS_INTR_STS (1<<0) -#define m_FS_NEW_INTR_STS (1<<1) -#define m_ADDR_SAME_INTR_STS (1<<2) -#define m_LINE_FLAG0_INTR_STS (1<<3) -#define m_LINE_FLAG1_INTR_STS (1<<4) -#define m_BUS_ERROR_INTR_STS (1<<5) -#define m_WIN0_EMPTY_INTR_STS (1<<6) -#define m_WIN1_EMPTY_INTR_STS (1<<7) -#define m_WIN2_EMPTY_INTR_STS (1<<8) -#define m_WIN3_EMPTY_INTR_STS (1<<9) -#define m_HWC_EMPTY_INTR_STS (1<<10) -#define m_POST_BUF_EMPTY_INTR_STS (1<<11) -#define m_PWM_GEN_INTR_STS (1<<12) -#define m_DSP_HOLD_VALID_INTR_STS (1<<13) -#define m_INTR_MMU_STS (1<<14)/*rk3366*/ -#define m_INTR_DMA_FINISH_STS (1<<15)/*rk3366*/ - -#define m_FS_INTR_RAWSTS (1<<(0+16)) -#define m_FS_NEW_INTR_RAWSTS (1<<(1+16)) -#define m_ADDR_SAME_INTR_RAWSTS (1<<(2+16)) -#define m_LINE_FLAG0_INTR_RAWSTS (1<<(3+16)) -#define m_LINE_FLAG1_INTR_RAWSTS (1<<(4+16)) -#define m_BUS_ERROR_INTR_RAWSTS (1<<(5+16)) -#define m_WIN0_EMPTY_INTR_RAWSTS (1<<(6+16)) -#define m_WIN1_EMPTY_INTR_RAWSTS (1<<(7+16)) -#define m_WIN2_EMPTY_INTR_RAWSTS (1<<(8+16)) -#define m_WIN3_EMPTY_INTR_RAWSTS (1<<(9+16)) -#define m_HWC_EMPTY_INTR_RAWSTS (1<<(10+16)) -#define m_POST_BUF_EMPTY_INTR_RAWSTS (1<<(11+16)) -#define m_PWM_GEN_INTR_RAWSTS (1<<(12+16)) -#define m_DSP_HOLD_VALID_INTR_RAWSTS (1<<(13+16)) - -#define INTR_RAW_STATUS_RK3366 (0x028c)/*rk3366*/ -#define m_FS_INTR_RAWSTS_RK3366 (1<<0)/*rk3366*/ -#define m_FS_NEW_INTR_RAWSTS_RK3366 (1<<1)/*rk3366*/ -#define m_ADDR_SAME_INTR_RAWSTS_RK3366 (1<<2)/*rk3366*/ -#define m_LINE_FLAG0_INTR_RAWSTS_RK3366 (1<<3)/*rk3366*/ -#define m_LINE_FLAG1_INTR_RAWSTS_RK3366 (1<<4)/*rk3366*/ -#define m_BUS_ERROR_INTR_RAWSTS_RK3366 (1<<5)/*rk3366*/ -#define m_WIN0_EMPTY_INTR_RAWSTS_RK3366 (1<<6)/*rk3366*/ -#define m_WIN1_EMPTY_INTR_RAWSTS_RK3366 (1<<7)/*rk3366*/ -#define m_WIN2_EMPTY_INTR_RAWSTS_RK3366 (1<<8)/*rk3366*/ -#define m_WIN3_EMPTY_INTR_RAWSTS_RK3366 (1<<9)/*rk3366*/ -#define m_HWC_EMPTY_INTR_RAWSTS_RK3366 (1<<10)/*rk3366*/ -#define m_POST_BUF_EMPTY_INTR_RAWSTS_RK3366 (1<<11)/*rk3366*/ -#define m_PWM_GEN_INTR_RAWSTS_RK3366 (1<<12)/*rk3366*/ -#define m_DSP_HOLD_VALID_INTR_RAWSTS_RK3366 (1<<13)/*rk3366*/ -#define m_INTR_MMU_RAWSTS_RK3366 (1<<14)/*rk3366*/ -#define m_INTR_DMA_FINISH_RAWSTS_RK3366 (1<<15)/*rk3366*/ - -/********************rk3366 write back register************************/ -#define WB_CTRL0 (0x0020) -#define v_WB_EN(x) (((x)&0x1)<<0) -#define v_WB_FMT(x) (((x)&0x7)<<1) -#define v_WB_DITHER_EN(x) (((x)&0x1)<<4) -#define v_WB_RGB2YUV_EN(x) (((x)&0x1)<<5) -#define v_WB_RGB2YUV_MODE(x) (((x)&0x1)<<6) -#define v_WB_XPSD_BIL_EN(x) (((x)&0x1)<<7) -#define v_WB_YTHROW_EN(x) (((x)&0x1)<<8) -#define v_WB_YTHROW_MODE(x) (((x)&0x1)<<9) -#define v_WB_HANDSHAKE_MODE(x) (((x)&0x1)<<11) -#define v_WB_YRGB_ID(x) (((x)&0xf)<<24) -#define v_WB_UI_ID(x) (((x)&0xf)<<28) -#define m_WB_EN (0x1<<0) -#define m_WB_FMT (0x7<<1) -#define m_WB_DITHER_EN (0x1<<4) -#define m_WB_RGB2YUV_EN (0x1<<5) -#define m_WB_RGB2YUV_MODE (0x1<<6) -#define m_WB_XPSD_BIL_EN (0x1<<7) -#define m_WB_YTHROW_EN (0x1<<8) -#define m_WB_YTHROW_MODE (0x1<<9) -#define m_WB_HANDSHAKE_MODE (0x1<<11) -#define m_WB_YRGB_ID (0xf<<24) -#define m_WB_UI_ID (0xf<<28) -#define WB_CTRL1 (0x0024) -#define v_WB_WIDTH(x) (((x)&0xfff)<<0) -#define v_WB_XPSD_BIL_FACTOR(x) (((x)&0x3fff)<<16) -#define m_WB_WIDTH (0xfff<<0) -#define m_WB_XPSD_BIL_FACTOR (0x3fff<<16) -#define WB_YRGB_MST (0x0028) -#define WB_CBR_MST (0x002c) -/********************rk3366 write back register************************/ - -/*win0 register*/ -#define WIN0_CTRL0 (0x0030) -#define v_WIN0_EN(x) (((x)&1)<<0) -#define v_WIN0_DATA_FMT(x) (((x)&7)<<1) -#define v_WIN0_FMT_10(x) (((x)&1)<<4) -#define v_WIN0_LB_MODE(x) (((x)&7)<<5) -#define v_WIN0_INTERLACE_READ(x) (((x)&1)<<8) -#define v_WIN0_NO_OUTSTANDING(x) (((x)&1)<<9) -#define v_WIN0_CSC_MODE(x) (((x)&3)<<10) -#define v_WIN0_RB_SWAP(x) (((x)&1)<<12) -#define v_WIN0_ALPHA_SWAP(x) (((x)&1)<<13) -#define v_WIN0_MID_SWAP(x) (((x)&1)<<14) -#define v_WIN0_UV_SWAP(x) (((x)&1)<<15) -#define v_WIN0_HW_PRE_MUL_EN(x) (((x)&1)<<16) -#define v_WIN0_YRGB_DEFLICK(x) (((x)&1)<<18) -#define v_WIN0_CBR_DEFLICK(x) (((x)&1)<<19) -#define v_WIN0_YUV_CLIP(x) (((x)&1)<<20) -#define v_WIN0_X_MIRROR(x) (((x)&1)<<21) -#define v_WIN0_Y_MIRROR(x) (((x)&1)<<22) -#define v_WIN0_AXI_MAX_OUTSTANDING_EN(x) (((x)&1)<<24) -#define v_WIN0_AXI_OUTSTANDING_MAX_NUM(x) (((x)&0x1f)<<25) -#define v_WIN0_DMA_BURST_LENGTH(x) (((x)&0x3)<<30) - -#define m_WIN0_EN (1<<0) -#define m_WIN0_DATA_FMT (7<<1) -#define m_WIN0_FMT_10 (1<<4) -#define m_WIN0_LB_MODE (7<<5) -#define m_WIN0_INTERLACE_READ (1<<8) -#define m_WIN0_NO_OUTSTANDING (1<<9) -#define m_WIN0_CSC_MODE (3<<10) -#define m_WIN0_RB_SWAP (1<<12) -#define m_WIN0_ALPHA_SWAP (1<<13) -#define m_WIN0_MID_SWAP (1<<14) -#define m_WIN0_UV_SWAP (1<<15) -#define m_WIN0_HW_PRE_MUL_EN (1<<16) -#define m_WIN0_YRGB_DEFLICK (1<<18) -#define m_WIN0_CBR_DEFLICK (1<<19) -#define m_WIN0_YUV_CLIP (1<<20) -#define m_WIN0_X_MIRROR (1<<21) -#define m_WIN0_Y_MIRROR (1<<22) -#define m_WIN0_AXI_MAX_OUTSTANDING_EN (1<<24) -#define m_WIN0_AXI_OUTSTANDING_MAX_NUM (0x1f<<25) -#define m_WIN0_DMA_BURST_LENGTH (0x3<<30) - -#define WIN0_CTRL1 (0x0034) -#define v_WIN0_YRGB_AXI_GATHER_EN(x) (((x)&1)<<0) -#define v_WIN0_CBR_AXI_GATHER_EN(x) (((x)&1)<<1) -#define v_WIN0_BIC_COE_SEL(x) (((x)&3)<<2) -#define v_WIN0_VSD_YRGB_GT4(x) (((x)&1)<<4) -#define v_WIN0_VSD_YRGB_GT2(x) (((x)&1)<<5) -#define v_WIN0_VSD_CBR_GT4(x) (((x)&1)<<6) -#define v_WIN0_VSD_CBR_GT2(x) (((x)&1)<<7) -#define v_WIN0_YRGB_AXI_GATHER_NUM(x) (((x)&0xf)<<8) -#define v_WIN0_CBR_AXI_GATHER_NUM(x) (((x)&7)<<12) -#define v_WIN0_LINE_LOAD_MODE(x) (((x)&1)<<15) -#define v_WIN0_YRGB_HOR_SCL_MODE(x) (((x)&3)<<16) -#define v_WIN0_YRGB_VER_SCL_MODE(x) (((x)&3)<<18) -#define v_WIN0_YRGB_HSD_MODE(x) (((x)&3)<<20) -#define v_WIN0_YRGB_VSU_MODE(x) (((x)&1)<<22) -#define v_WIN0_YRGB_VSD_MODE(x) (((x)&1)<<23) -#define v_WIN0_CBR_HOR_SCL_MODE(x) (((x)&3)<<24) -#define v_WIN0_CBR_VER_SCL_MODE(x) (((x)&3)<<26) -#define v_WIN0_CBR_HSD_MODE(x) (((x)&3)<<28) -#define v_WIN0_CBR_VSU_MODE(x) (((x)&1)<<30) -#define v_WIN0_CBR_VSD_MODE(x) (((x)&1)<<31) - -#define m_WIN0_YRGB_AXI_GATHER_EN (1<<0) -#define m_WIN0_CBR_AXI_GATHER_EN (1<<1) -#define m_WIN0_BIC_COE_SEL (3<<2) -#define m_WIN0_VSD_YRGB_GT4 (1<<4) -#define m_WIN0_VSD_YRGB_GT2 (1<<5) -#define m_WIN0_VSD_CBR_GT4 (1<<6) -#define m_WIN0_VSD_CBR_GT2 (1<<7) -#define m_WIN0_YRGB_AXI_GATHER_NUM (0xf<<8) -#define m_WIN0_CBR_AXI_GATHER_NUM (7<<12) -#define m_WIN0_LINE_LOAD_MODE (1<<15) -#define m_WIN0_YRGB_HOR_SCL_MODE (3<<16) -#define m_WIN0_YRGB_VER_SCL_MODE (3<<18) -#define m_WIN0_YRGB_HSD_MODE (3<<20) -#define m_WIN0_YRGB_VSU_MODE (1<<22) -#define m_WIN0_YRGB_VSD_MODE (1<<23) -#define m_WIN0_CBR_HOR_SCL_MODE (3<<24) -#define m_WIN0_CBR_VER_SCL_MODE (3<<26) -#define m_WIN0_CBR_HSD_MODE (3<<28) -#define m_WIN0_CBR_VSU_MODE ((u32)1<<30) -#define m_WIN0_CBR_VSD_MODE ((u32)1<<31) - -#define WIN0_COLOR_KEY (0x0038) -#define v_WIN0_COLOR_KEY(x) (((x)&0x3fffffff)<<0) -#define v_WIN0_COLOR_KEY_EN(x) (((x)&1)<<31) -#define m_WIN0_COLOR_KEY (0x3fffffff<<0) -#define m_WIN0_COLOR_KEY_EN ((u32)1<<31) - -#define WIN0_VIR (0x003c) -#define v_WIN0_VIR_STRIDE(x) (((x)&0xffff)<<0) -#define v_WIN0_VIR_STRIDE_UV(x) (((x)&0xffff)<<16) -#define m_WIN0_VIR_STRIDE (0xffff<<0) -#define m_WIN0_VIR_STRIDE_UV (0xffff<<16) - -#define WIN0_YRGB_MST (0x0040) -#define WIN0_CBR_MST (0x0044) -#define WIN0_ACT_INFO (0x0048) -#define v_WIN0_ACT_WIDTH(x) (((x-1)&0x1fff)<<0) -#define v_WIN0_ACT_HEIGHT(x) (((x-1)&0x1fff)<<16) -#define m_WIN0_ACT_WIDTH (0x1fff<<0) -#define m_WIN0_ACT_HEIGHT (0x1fff<<16) - -#define WIN0_DSP_INFO (0x004c) -#define v_WIN0_DSP_WIDTH(x) (((x-1)&0xfff)<<0) -#define v_WIN0_DSP_HEIGHT(x) (((x-1)&0xfff)<<16) -#define m_WIN0_DSP_WIDTH (0xfff<<0) -#define m_WIN0_DSP_HEIGHT (0xfff<<16) - -#define WIN0_DSP_ST (0x0050) -#define v_WIN0_DSP_XST(x) (((x)&0x1fff)<<0) -#define v_WIN0_DSP_YST(x) (((x)&0x1fff)<<16) -#define m_WIN0_DSP_XST (0x1fff<<0) -#define m_WIN0_DSP_YST (0x1fff<<16) - -#define WIN0_SCL_FACTOR_YRGB (0x0054) -#define v_WIN0_HS_FACTOR_YRGB(x) (((x)&0xffff)<<0) -#define v_WIN0_VS_FACTOR_YRGB(x) (((x)&0xffff)<<16) -#define m_WIN0_HS_FACTOR_YRGB (0xffff<<0) -#define m_WIN0_VS_FACTOR_YRGB ((u32)0xffff<<16) - -#define WIN0_SCL_FACTOR_CBR (0x0058) -#define v_WIN0_HS_FACTOR_CBR(x) (((x)&0xffff)<<0) -#define v_WIN0_VS_FACTOR_CBR(x) (((x)&0xffff)<<16) -#define m_WIN0_HS_FACTOR_CBR (0xffff<<0) -#define m_WIN0_VS_FACTOR_CBR ((u32)0xffff<<16) - -#define WIN0_SCL_OFFSET (0x005c) -#define v_WIN0_HS_OFFSET_YRGB(x) (((x)&0xff)<<0) -#define v_WIN0_HS_OFFSET_CBR(x) (((x)&0xff)<<8) -#define v_WIN0_VS_OFFSET_YRGB(x) (((x)&0xff)<<16) -#define v_WIN0_VS_OFFSET_CBR(x) (((x)&0xff)<<24) - -#define m_WIN0_HS_OFFSET_YRGB (0xff<<0) -#define m_WIN0_HS_OFFSET_CBR (0xff<<8) -#define m_WIN0_VS_OFFSET_YRGB (0xff<<16) -#define m_WIN0_VS_OFFSET_CBR ((u32)0xff<<24) - -#define WIN0_SRC_ALPHA_CTRL (0x0060) -#define v_WIN0_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_WIN0_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_WIN0_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_WIN0_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_WIN0_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_WIN0_SRC_FACTOR_M0(x) (((x)&7)<<6) -#define v_WIN0_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_WIN0_FADING_VALUE(x) (((x)&0xff)<<24) - -#define m_WIN0_SRC_ALPHA_EN (1<<0) -#define m_WIN0_SRC_COLOR_M0 (1<<1) -#define m_WIN0_SRC_ALPHA_M0 (1<<2) -#define m_WIN0_SRC_BLEND_M0 (3<<3) -#define m_WIN0_SRC_ALPHA_CAL_M0 (1<<5) -#define m_WIN0_SRC_FACTOR_M0 (7<<6) -#define m_WIN0_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_WIN0_FADING_VALUE (0xff<<24) - -#define WIN0_DST_ALPHA_CTRL (0x0064) -#define v_WIN0_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_WIN0_DST_FACTOR_M0 (7<<6) - -#define WIN0_FADING_CTRL (0x0068) -#define v_WIN0_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_WIN0_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_WIN0_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_WIN0_FADING_EN(x) (((x)&1)<<24) - -#define m_WIN0_FADING_OFFSET_R (0xff<<0) -#define m_WIN0_FADING_OFFSET_G (0xff<<8) -#define m_WIN0_FADING_OFFSET_B (0xff<<16) -#define m_WIN0_FADING_EN (1<<24) - -#define WIN0_CTRL2 (0x006c) -#define v_WIN_RID_WIN0_YRGB(x) (((x)&0xf)<<0) -#define v_WIN_RID_WIN0_CBR(x) (((x)&0xf)<<4) -#define m_WIN_RID_WIN0_YRGB ((0xf)<<0) -#define m_WIN_RID_WIN0_CBR ((0xf)<<4) -/*win1 register*/ -#define WIN1_CTRL0 (0x0070) -#define v_WIN1_EN(x) (((x)&1)<<0) -#define v_WIN1_DATA_FMT(x) (((x)&7)<<1) -#define v_WIN1_FMT_10(x) (((x)&1)<<4) -#define v_WIN1_LB_MODE(x) (((x)&7)<<5) -#define v_WIN1_INTERLACE_READ(x) (((x)&1)<<8) -#define v_WIN1_NO_OUTSTANDING(x) (((x)&1)<<9) -#define v_WIN1_CSC_MODE(x) (((x)&3)<<10) -#define v_WIN1_RB_SWAP(x) (((x)&1)<<12) -#define v_WIN1_ALPHA_SWAP(x) (((x)&1)<<13) -#define v_WIN1_MID_SWAP(x) (((x)&1)<<14) -#define v_WIN1_UV_SWAP(x) (((x)&1)<<15) -#define v_WIN1_HW_PRE_MUL_EN(x) (((x)&1)<<16) -#define v_WIN1_YRGB_DEFLICK(x) (((x)&1)<<18) -#define v_WIN1_CBR_DEFLICK(x) (((x)&1)<<19) -#define v_WIN1_YUV_CLIP(x) (((x)&1)<<20) -#define v_WIN1_X_MIRROR(x) (((x)&1)<<21) -#define v_WIN1_Y_MIRROR(x) (((x)&1)<<22) -#define v_WIN1_AXI_MAX_OUTSTANDING_EN(x) (((x)&1)<<24) -#define v_WIN1_AXI_OUTSTANDING_MAX_NUM(x) (((x)&0x1f)<<25) -#define v_WIN1_DMA_BURST_LENGTH(x) (((x)&0x3)<<30) -#define m_WIN1_EN (1<<0) -#define m_WIN1_DATA_FMT (7<<1) -#define m_WIN1_FMT_10 (1<<4) -#define m_WIN1_LB_MODE (7<<5) -#define m_WIN1_INTERLACE_READ (1<<8) -#define m_WIN1_NO_OUTSTANDING (1<<9) -#define m_WIN1_CSC_MODE (3<<10) -#define m_WIN1_RB_SWAP (1<<12) -#define m_WIN1_ALPHA_SWAP (1<<13) -#define m_WIN1_MID_SWAP (1<<14) -#define m_WIN1_UV_SWAP (1<<15) -#define m_WIN1_HW_PRE_MUL_EN (1<<16) -#define m_WIN1_YRGB_DEFLICK (1<<18) -#define m_WIN1_CBR_DEFLICK (1<<19) -#define m_WIN1_YUV_CLIP (1<<20) -#define m_WIN1_X_MIRROR (1<<21) -#define m_WIN1_Y_MIRROR (1<<22) -#define m_WIN1_AXI_MAX_OUTSTANDING_EN (1<<24) -#define m_WIN1_AXI_OUTSTANDING_MAX_NUM (0x1f<<25) -#define m_WIN1_DMA_BURST_LENGTH (0x3<<30) - -#define WIN1_CTRL1 (0x0074) -#define v_WIN1_YRGB_AXI_GATHER_EN(x) (((x)&1)<<0) -#define v_WIN1_CBR_AXI_GATHER_EN(x) (((x)&1)<<1) -#define v_WIN1_BIC_COE_SEL(x) (((x)&3)<<2) -#define v_WIN1_VSD_YRGB_GT4(x) (((x)&1)<<4) -#define v_WIN1_VSD_YRGB_GT2(x) (((x)&1)<<5) -#define v_WIN1_VSD_CBR_GT4(x) (((x)&1)<<6) -#define v_WIN1_VSD_CBR_GT2(x) (((x)&1)<<7) -#define v_WIN1_YRGB_AXI_GATHER_NUM(x) (((x)&0xf)<<8) -#define v_WIN1_CBR_AXI_GATHER_NUM(x) (((x)&7)<<12) -#define v_WIN1_LINE_LOAD_MODE(x) (((x)&1)<<15) -#define v_WIN1_YRGB_HOR_SCL_MODE(x) (((x)&3)<<16) -#define v_WIN1_YRGB_VER_SCL_MODE(x) (((x)&3)<<18) -#define v_WIN1_YRGB_HSD_MODE(x) (((x)&3)<<20) -#define v_WIN1_YRGB_VSU_MODE(x) (((x)&1)<<22) -#define v_WIN1_YRGB_VSD_MODE(x) (((x)&1)<<23) -#define v_WIN1_CBR_HOR_SCL_MODE(x) (((x)&3)<<24) -#define v_WIN1_CBR_VER_SCL_MODE(x) (((x)&3)<<26) -#define v_WIN1_CBR_HSD_MODE(x) (((x)&3)<<28) -#define v_WIN1_CBR_VSU_MODE(x) (((x)&1)<<30) -#define v_WIN1_CBR_VSD_MODE(x) (((x)&1)<<31) - -#define m_WIN1_YRGB_AXI_GATHER_EN (1<<0) -#define m_WIN1_CBR_AXI_GATHER_EN (1<<1) -#define m_WIN1_BIC_COE_SEL (3<<2) -#define m_WIN1_VSD_YRGB_GT4 (1<<4) -#define m_WIN1_VSD_YRGB_GT2 (1<<5) -#define m_WIN1_VSD_CBR_GT4 (1<<6) -#define m_WIN1_VSD_CBR_GT2 (1<<7) -#define m_WIN1_YRGB_AXI_GATHER_NUM (0xf<<8) -#define m_WIN1_CBR_AXI_GATHER_NUM (7<<12) -#define m_WIN1_LINE_LOAD_MODE (1<<15) -#define m_WIN1_YRGB_HOR_SCL_MODE (3<<16) -#define m_WIN1_YRGB_VER_SCL_MODE (3<<18) -#define m_WIN1_YRGB_HSD_MODE (3<<20) -#define m_WIN1_YRGB_VSU_MODE (1<<22) -#define m_WIN1_YRGB_VSD_MODE (1<<23) -#define m_WIN1_CBR_HOR_SCL_MODE (3<<24) -#define m_WIN1_CBR_VER_SCL_MODE (3<<26) -#define m_WIN1_CBR_HSD_MODE (3<<28) -#define m_WIN1_CBR_VSU_MODE (1<<30) -#define m_WIN1_CBR_VSD_MODE ((u32)1<<31) - -#define WIN1_COLOR_KEY (0x0078) -#define v_WIN1_COLOR_KEY(x) (((x)&0x3fffffff)<<0) -#define v_WIN1_COLOR_KEY_EN(x) (((x)&1)<<31) -#define m_WIN1_COLOR_KEY (0x3fffffff<<0) -#define m_WIN1_COLOR_KEY_EN ((u32)1<<31) - -#define WIN1_VIR (0x007c) -#define v_WIN1_VIR_STRIDE(x) (((x)&0xffff)<<0) -#define v_WIN1_VIR_STRIDE_UV(x) (((x)&0xffff)<<16) -#define m_WIN1_VIR_STRIDE (0xffff<<0) -#define m_WIN1_VIR_STRIDE_UV (0xffff<<16) - -#define WIN1_YRGB_MST (0x0080) -#define WIN1_CBR_MST (0x0084) -#define WIN1_ACT_INFO (0x0088) -#define v_WIN1_ACT_WIDTH(x) (((x-1)&0x1fff)<<0) -#define v_WIN1_ACT_HEIGHT(x) (((x-1)&0x1fff)<<16) -#define m_WIN1_ACT_WIDTH (0x1fff<<0) -#define m_WIN1_ACT_HEIGHT (0x1fff<<16) - -#define WIN1_DSP_INFO (0x008c) -#define v_WIN1_DSP_WIDTH(x) (((x-1)&0xfff)<<0) -#define v_WIN1_DSP_HEIGHT(x) (((x-1)&0xfff)<<16) -#define m_WIN1_DSP_WIDTH (0xfff<<0) -#define m_WIN1_DSP_HEIGHT (0xfff<<16) - -#define WIN1_DSP_ST (0x0090) -#define v_WIN1_DSP_XST(x) (((x)&0x1fff)<<0) -#define v_WIN1_DSP_YST(x) (((x)&0x1fff)<<16) -#define m_WIN1_DSP_XST (0x1fff<<0) -#define m_WIN1_DSP_YST (0x1fff<<16) - -#define WIN1_SCL_FACTOR_YRGB (0x0094) -#define v_WIN1_HS_FACTOR_YRGB(x) (((x)&0xffff)<<0) -#define v_WIN1_VS_FACTOR_YRGB(x) (((x)&0xffff)<<16) -#define m_WIN1_HS_FACTOR_YRGB (0xffff<<0) -#define m_WIN1_VS_FACTOR_YRGB ((u32)0xffff<<16) - -#define WIN1_SCL_FACTOR_CBR (0x0098) -#define v_WIN1_HS_FACTOR_CBR(x) (((x)&0xffff)<<0) -#define v_WIN1_VS_FACTOR_CBR(x) (((x)&0xffff)<<16) -#define m_WIN1_HS_FACTOR_CBR (0xffff<<0) -#define m_WIN1_VS_FACTOR_CBR ((u32)0xffff<<16) - -#define WIN1_SCL_OFFSET (0x009c) -#define v_WIN1_HS_OFFSET_YRGB(x) (((x)&0xff)<<0) -#define v_WIN1_HS_OFFSET_CBR(x) (((x)&0xff)<<8) -#define v_WIN1_VS_OFFSET_YRGB(x) (((x)&0xff)<<16) -#define v_WIN1_VS_OFFSET_CBR(x) (((x)&0xff)<<24) - -#define m_WIN1_HS_OFFSET_YRGB (0xff<<0) -#define m_WIN1_HS_OFFSET_CBR (0xff<<8) -#define m_WIN1_VS_OFFSET_YRGB (0xff<<16) -#define m_WIN1_VS_OFFSET_CBR ((u32)0xff<<24) - -#define WIN1_SRC_ALPHA_CTRL (0x00a0) -#define v_WIN1_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_WIN1_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_WIN1_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_WIN1_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_WIN1_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_WIN1_SRC_FACTOR_M0(x) (((x)&7)<<6) -#define v_WIN1_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_WIN1_FADING_VALUE(x) (((x)&0xff)<<24) - -#define m_WIN1_SRC_ALPHA_EN (1<<0) -#define m_WIN1_SRC_COLOR_M0 (1<<1) -#define m_WIN1_SRC_ALPHA_M0 (1<<2) -#define m_WIN1_SRC_BLEND_M0 (3<<3) -#define m_WIN1_SRC_ALPHA_CAL_M0 (1<<5) -#define m_WIN1_SRC_FACTOR_M0 (7<<6) -#define m_WIN1_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_WIN1_FADING_VALUE (0xff<<24) - -#define WIN1_DST_ALPHA_CTRL (0x00a4) -#define v_WIN1_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_WIN1_DST_FACTOR_M0 (7<<6) - -#define WIN1_FADING_CTRL (0x00a8) -#define v_WIN1_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_WIN1_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_WIN1_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_WIN1_FADING_EN(x) (((x)&1)<<24) - -#define m_WIN1_FADING_OFFSET_R (0xff<<0) -#define m_WIN1_FADING_OFFSET_G (0xff<<8) -#define m_WIN1_FADING_OFFSET_B (0xff<<16) -#define m_WIN1_FADING_EN (1<<24) - -#define WIN1_CTRL2 (0xac) -#define v_WIN_RID_WIN1_YRGB(x) (((x)&0xf)<<0) -#define v_WIN_RID_WIN1_CBR(x) (((x)&0xf)<<4) -#define m_WIN_RID_WIN1_YRGB ((0xf)<<0) -#define m_WIN_RID_WIN1_CBR ((0xf)<<4) -/*win2 register*/ -#define WIN2_CTRL0 (0x00b0) -#define v_WIN2_EN(x) (((x)&1)<<0) -#define v_WIN2_INTERLACE_READ(x) (((x)&1)<<1) -#define v_WIN2_CSC_MODE(x) (((x)&1)<<2) -#define v_WIN2_MST0_EN(x) (((x)&1)<<4) -#define v_WIN2_DATA_FMT0(x) (((x)&3)<<5) -#define v_WIN2_MST1_EN(x) (((x)&1)<<8) -#define v_WIN2_DATA_FMT1(x) (((x)&3)<<9) -#define v_WIN2_MST2_EN(x) (((x)&1)<<12) -#define v_WIN2_DATA_FMT2(x) (((x)&3)<<13) -#define v_WIN2_MST3_EN(x) (((x)&1)<<16) -#define v_WIN2_DATA_FMT3(x) (((x)&3)<<17) -#define v_WIN2_RB_SWAP0(x) (((x)&1)<<20) -#define v_WIN2_ALPHA_SWAP0(x) (((x)&1)<<21) -#define v_WIN2_ENDIAN_SWAP0(x) (((x)&1)<<22) -#define v_WIN2_RB_SWAP1(x) (((x)&1)<<23) -#define v_WIN2_ALPHA_SWAP1(x) (((x)&1)<<24) -#define v_WIN2_ENDIAN_SWAP1(x) (((x)&1)<<25) -#define v_WIN2_RB_SWAP2(x) (((x)&1)<<26) -#define v_WIN2_ALPHA_SWAP2(x) (((x)&1)<<27) -#define v_WIN2_ENDIAN_SWAP2(x) (((x)&1)<<28) -#define v_WIN2_RB_SWAP3(x) (((x)&1)<<29) -#define v_WIN2_ALPHA_SWAP3(x) (((x)&1)<<30) -#define v_WIN2_ENDIAN_SWAP3(x) (((x)&1)<<31) - -#define m_WIN2_EN (1<<0) -#define m_WIN2_INTERLACE_READ (1<<1) -#define m_WIN2_CSC_MODE (1<<2) -#define m_WIN2_MST0_EN (1<<4) -#define m_WIN2_DATA_FMT0 (3<<5) -#define m_WIN2_MST1_EN (1<<8) -#define m_WIN2_DATA_FMT1 (3<<9) -#define m_WIN2_MST2_EN (1<<12) -#define m_WIN2_DATA_FMT2 (3<<13) -#define m_WIN2_MST3_EN (1<<16) -#define m_WIN2_DATA_FMT3 (3<<17) -#define m_WIN2_RB_SWAP0 (1<<20) -#define m_WIN2_ALPHA_SWAP0 (1<<21) -#define m_WIN2_ENDIAN_SWAP0 (1<<22) -#define m_WIN2_RB_SWAP1 (1<<23) -#define m_WIN2_ALPHA_SWAP1 (1<<24) -#define m_WIN2_ENDIAN_SWAP1 (1<<25) -#define m_WIN2_RB_SWAP2 (1<<26) -#define m_WIN2_ALPHA_SWAP2 (1<<27) -#define m_WIN2_ENDIAN_SWAP2 (1<<28) -#define m_WIN2_RB_SWAP3 (1<<29) -#define m_WIN2_ALPHA_SWAP3 (1<<30) -#define m_WIN2_ENDIAN_SWAP3 (1<<31) - -#define WIN2_CTRL1 (0x00b4) -#define v_WIN2_AXI_GATHER_EN(x) (((x)&1)<<0) -#define v_WIN2_AXI_MAX_OUTSTANDING_EN(x) (((x)&1)<<1) -#define v_WIN2_DMA_BURST_LENGTH(x) (((x)&0x3)<<2) -#define v_WIN2_AXI_GATHER_NUM(x) (((x)&0xf)<<4) -#define v_WIN2_AXI_OUTSTANDING_MAX_NUM(x) (((x)&0x1f)<<8) -#define v_WIN2_RGB2YUV_EN(x) (((x)&1)<<13) -#define v_WIN2_NO_OUTSTANDING(x) (((x)&1)<<14) -#define v_WIN2_Y_MIR(x) (((x)&1)<<15) -#define v_WIN2_LUT_EN(x) (((x)&1)<<16) -#define v_WIN_RID_WIN2(x) (((x)&0xf)<<20) - -#define m_WIN2_AXI_GATHER_EN (1<<0) -#define m_WIN2_AXI_MAX_OUTSTANDING_EN (1<<1) -#define m_WIN2_DMA_BURST_LENGTH (0x3<<2) -#define m_WIN2_AXI_GATHER_NUM (0xf<<4) -#define m_WIN2_AXI_OUTSTANDING_MAX_NUM (0x1f<<8) -#define m_WIN2_RGB2YUV_EN (1<<13) -#define m_WIN2_NO_OUTSTANDING (1<<14) -#define m_WIN2_Y_MIR (1<<15) -#define m_WIN2_LUT_EN (1<<16) -#define m_WIN_RID_WIN2 (0xf<<20) - -#define WIN2_VIR0_1 (0x00b8) -#define v_WIN2_VIR_STRIDE0(x) (((x)&0xffff)<<0) -#define v_WIN2_VIR_STRIDE1(x) (((x)&0xffff)<<16) -#define m_WIN2_VIR_STRIDE0 (((u32)0xffff)<<0) -#define m_WIN2_VIR_STRIDE1 (((u32)0xffff)<<16) - -#define WIN2_VIR2_3 (0x00bc) -#define v_WIN2_VIR_STRIDE2(x) (((x)&0xffff)<<0) -#define v_WIN2_VIR_STRIDE3(x) (((x)&0xffff)<<16) -#define m_WIN2_VIR_STRIDE2 (((u32)0xffff)<<0) -#define m_WIN2_VIR_STRIDE3 (((u32)0xffff)<<16) - -#define WIN2_MST0 (0x00c0) -#define WIN2_DSP_INFO0 (0x00c4) -#define v_WIN2_DSP_WIDTH0(x) (((x-1)&0xfff)<<0) -#define v_WIN2_DSP_HEIGHT0(x) (((x-1)&0xfff)<<16) -#define m_WIN2_DSP_WIDTH0 (0xfff<<0) -#define m_WIN2_DSP_HEIGHT0 (0xfff<<16) - -#define WIN2_DSP_ST0 (0x00c8) -#define v_WIN2_DSP_XST0(x) (((x)&0x1fff)<<0) -#define v_WIN2_DSP_YST0(x) (((x)&0x1fff)<<16) -#define m_WIN2_DSP_XST0 (0x1fff<<0) -#define m_WIN2_DSP_YST0 (0x1fff<<16) - -#define WIN2_COLOR_KEY (0x00cc) -#define v_WIN2_COLOR_KEY(x) (((x)&0xffffff)<<0) -#define v_WIN2_KEY_EN(x) (((x)&1)<<24) -#define m_WIN2_COLOR_KEY (0xffffff<<0) -#define m_WIN2_KEY_EN ((u32)1<<24) - - -#define WIN2_MST1 (0x00d0) -#define WIN2_DSP_INFO1 (0x00d4) -#define v_WIN2_DSP_WIDTH1(x) (((x-1)&0xfff)<<0) -#define v_WIN2_DSP_HEIGHT1(x) (((x-1)&0xfff)<<16) - -#define m_WIN2_DSP_WIDTH1 (0xfff<<0) -#define m_WIN2_DSP_HEIGHT1 (0xfff<<16) - -#define WIN2_DSP_ST1 (0x00d8) -#define v_WIN2_DSP_XST1(x) (((x)&0x1fff)<<0) -#define v_WIN2_DSP_YST1(x) (((x)&0x1fff)<<16) -#define m_WIN2_DSP_XST1 (0x1fff<<0) -#define m_WIN2_DSP_YST1 (0x1fff<<16) - -#define WIN2_SRC_ALPHA_CTRL (0x00dc) -#define v_WIN2_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_WIN2_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_WIN2_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_WIN2_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_WIN2_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_WIN2_SRC_FACTOR_M0(x) (((x)&7)<<6) -#define v_WIN2_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_WIN2_FADING_VALUE(x) (((x)&0xff)<<24) -#define m_WIN2_SRC_ALPHA_EN (1<<0) -#define m_WIN2_SRC_COLOR_M0 (1<<1) -#define m_WIN2_SRC_ALPHA_M0 (1<<2) -#define m_WIN2_SRC_BLEND_M0 (3<<3) -#define m_WIN2_SRC_ALPHA_CAL_M0 (1<<5) -#define m_WIN2_SRC_FACTOR_M0 (7<<6) -#define m_WIN2_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_WIN2_FADING_VALUE (0xff<<24) - -#define WIN2_MST2 (0x00e0) -#define WIN2_DSP_INFO2 (0x00e4) -#define v_WIN2_DSP_WIDTH2(x) (((x-1)&0xfff)<<0) -#define v_WIN2_DSP_HEIGHT2(x) (((x-1)&0xfff)<<16) -#define m_WIN2_DSP_WIDTH2 (0xfff<<0) -#define m_WIN2_DSP_HEIGHT2 (0xfff<<16) - -#define WIN2_DSP_ST2 (0x00e8) -#define v_WIN2_DSP_XST2(x) (((x)&0x1fff)<<0) -#define v_WIN2_DSP_YST2(x) (((x)&0x1fff)<<16) -#define m_WIN2_DSP_XST2 (0x1fff<<0) -#define m_WIN2_DSP_YST2 (0x1fff<<16) - -#define WIN2_DST_ALPHA_CTRL (0x00ec) -#define v_WIN2_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_WIN2_DST_FACTOR_M0 (7<<6) - -#define WIN2_MST3 (0x00f0) -#define WIN2_DSP_INFO3 (0x00f4) -#define v_WIN2_DSP_WIDTH3(x) (((x-1)&0xfff)<<0) -#define v_WIN2_DSP_HEIGHT3(x) (((x-1)&0xfff)<<16) -#define m_WIN2_DSP_WIDTH3 (0xfff<<0) -#define m_WIN2_DSP_HEIGHT3 (0xfff<<16) - -#define WIN2_DSP_ST3 (0x00f8) -#define v_WIN2_DSP_XST3(x) (((x)&0x1fff)<<0) -#define v_WIN2_DSP_YST3(x) (((x)&0x1fff)<<16) -#define m_WIN2_DSP_XST3 (0x1fff<<0) -#define m_WIN2_DSP_YST3 (0x1fff<<16) - -#define WIN2_FADING_CTRL (0x00fc) -#define v_WIN2_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_WIN2_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_WIN2_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_WIN2_FADING_EN(x) (((x)&1)<<24) - -#define m_WIN2_FADING_OFFSET_R (0xff<<0) -#define m_WIN2_FADING_OFFSET_G (0xff<<8) -#define m_WIN2_FADING_OFFSET_B (0xff<<16) -#define m_WIN2_FADING_EN (1<<24) - -/*win3 register*/ -#define WIN3_CTRL0 (0x0100) -#define v_WIN3_EN(x) (((x)&1)<<0) -#define v_WIN3_INTERLACE_READ(x) (((x)&1)<<1) -#define v_WIN3_CSC_MODE(x) (((x)&1)<<2) -#define v_WIN3_MST0_EN(x) (((x)&1)<<4) -#define v_WIN3_DATA_FMT0(x) (((x)&3)<<5) -#define v_WIN3_MST1_EN(x) (((x)&1)<<8) -#define v_WIN3_DATA_FMT1(x) (((x)&3)<<9) -#define v_WIN3_MST2_EN(x) (((x)&1)<<12) -#define v_WIN3_DATA_FMT2(x) (((x)&3)<<13) -#define v_WIN3_MST3_EN(x) (((x)&1)<<16) -#define v_WIN3_DATA_FMT3(x) (((x)&3)<<17) -#define v_WIN3_RB_SWAP0(x) (((x)&1)<<20) -#define v_WIN3_ALPHA_SWAP0(x) (((x)&1)<<21) -#define v_WIN3_ENDIAN_SWAP0(x) (((x)&1)<<22) -#define v_WIN3_RB_SWAP1(x) (((x)&1)<<23) -#define v_WIN3_ALPHA_SWAP1(x) (((x)&1)<<24) -#define v_WIN3_ENDIAN_SWAP1(x) (((x)&1)<<25) -#define v_WIN3_RB_SWAP2(x) (((x)&1)<<26) -#define v_WIN3_ALPHA_SWAP2(x) (((x)&1)<<27) -#define v_WIN3_ENDIAN_SWAP2(x) (((x)&1)<<28) -#define v_WIN3_RB_SWAP3(x) (((x)&1)<<29) -#define v_WIN3_ALPHA_SWAP3(x) (((x)&1)<<30) -#define v_WIN3_ENDIAN_SWAP3(x) (((x)&1)<<31) - -#define m_WIN3_EN (1<<0) -#define m_WIN3_INTERLACE_READ (1<<1) -#define m_WIN3_CSC_MODE (1<<2) -#define m_WIN3_MST0_EN (1<<4) -#define m_WIN3_DATA_FMT0 (3<<5) -#define m_WIN3_MST1_EN (1<<8) -#define m_WIN3_DATA_FMT1 (3<<9) -#define m_WIN3_MST2_EN (1<<12) -#define m_WIN3_DATA_FMT2 (3<<13) -#define m_WIN3_MST3_EN (1<<16) -#define m_WIN3_DATA_FMT3 (3<<17) -#define m_WIN3_RB_SWAP0 (1<<20) -#define m_WIN3_ALPHA_SWAP0 (1<<21) -#define m_WIN3_ENDIAN_SWAP0 (1<<22) -#define m_WIN3_RB_SWAP1 (1<<23) -#define m_WIN3_ALPHA_SWAP1 (1<<24) -#define m_WIN3_ENDIAN_SWAP1 (1<<25) -#define m_WIN3_RB_SWAP2 (1<<26) -#define m_WIN3_ALPHA_SWAP2 (1<<27) -#define m_WIN3_ENDIAN_SWAP2 (1<<28) -#define m_WIN3_RB_SWAP3 (1<<29) -#define m_WIN3_ALPHA_SWAP3 (1<<30) -#define m_WIN3_ENDIAN_SWAP3 (1<<31) - -#define WIN3_CTRL1 (0x0104) -#define v_WIN3_AXI_GATHER_EN(x) (((x)&1)<<0) -#define v_WIN3_AXI_MAX_OUTSTANDING_EN(x) (((x)&1)<<1) -#define v_WIN3_DMA_BURST_LENGTH(x) (((x)&0x3)<<2) -#define v_WIN3_AXI_GATHER_NUM(x) (((x)&0xf)<<4) -#define v_WIN3_AXI_OUTSTANDING_MAX_NUM(x) (((x)&0x1f)<<8) -#define v_WIN3_NO_OUTSTANDING(x) (((x)&1)<<14) -#define v_WIN3_Y_MIR(x) (((x)&1)<<15) -#define v_WIN3_LUT_EN(x) (((x)&1)<<16) -#define v_WIN_RID_WIN3(x) (((x)&0xf)<<20) - -#define m_WIN3_AXI_GATHER_EN (1<<0) -#define m_WIN3_AXI_MAX_OUTSTANDING_EN (1<<1) -#define m_WIN3_DMA_BURST_LENGTH (0x3<<2) -#define m_WIN3_AXI_GATHER_NUM (0xf<<4) -#define m_WIN3_AXI_OUTSTANDING_MAX_NUM (0x1f<<8) -#define m_WIN3_NO_OUTSTANDING (1<<14) -#define m_WIN3_Y_MIR (1<<15) -#define m_WIN3_LUT_EN (1<<16) -#define m_WIN_RID_WIN3 (0xf<<20) - -#define WIN3_VIR0_1 (0x0108) -#define v_WIN3_VIR_STRIDE0(x) (((x)&0xffff)<<0) -#define v_WIN3_VIR_STRIDE1(x) (((x)&0xffff)<<16) -#define m_WIN3_VIR_STRIDE0 (0xffff<<0) -#define m_WIN3_VIR_STRIDE1 (0xffff<<16) - -#define WIN3_VIR2_3 (0x010c) -#define v_WIN3_VIR_STRIDE2(x) (((x)&0xffff)<<0) -#define v_WIN3_VIR_STRIDE3(x) (((x)&0xffff)<<16) -#define m_WIN3_VIR_STRIDE2 (0xffff<<0) -#define m_WIN3_VIR_STRIDE3 (0xffff<<16) - -#define WIN3_MST0 (0x0110) -#define WIN3_DSP_INFO0 (0x0114) -#define v_WIN3_DSP_WIDTH0(x) (((x-1)&0xfff)<<0) -#define v_WIN3_DSP_HEIGHT0(x) (((x-1)&0xfff)<<16) -#define m_WIN3_DSP_WIDTH0 (0xfff<<0) -#define m_WIN3_DSP_HEIGHT0 (0xfff<<16) - -#define WIN3_DSP_ST0 (0x0118) -#define v_WIN3_DSP_XST0(x) (((x)&0x1fff)<<0) -#define v_WIN3_DSP_YST0(x) (((x)&0x1fff)<<16) -#define m_WIN3_DSP_XST0 (0x1fff<<0) -#define m_WIN3_DSP_YST0 (0x1fff<<16) - -#define WIN3_COLOR_KEY (0x011c) -#define v_WIN3_COLOR_KEY(x) (((x)&0xffffff)<<0) -#define v_WIN3_KEY_EN(x) (((x)&1)<<24) -#define m_WIN3_COLOR_KEY (0xffffff<<0) -#define m_WIN3_KEY_EN ((u32)1<<24) - -#define WIN3_MST1 (0x0120) -#define WIN3_DSP_INFO1 (0x0124) -#define v_WIN3_DSP_WIDTH1(x) (((x-1)&0xfff)<<0) -#define v_WIN3_DSP_HEIGHT1(x) (((x-1)&0xfff)<<16) -#define m_WIN3_DSP_WIDTH1 (0xfff<<0) -#define m_WIN3_DSP_HEIGHT1 (0xfff<<16) - -#define WIN3_DSP_ST1 (0x0128) -#define v_WIN3_DSP_XST1(x) (((x)&0x1fff)<<0) -#define v_WIN3_DSP_YST1(x) (((x)&0x1fff)<<16) -#define m_WIN3_DSP_XST1 (0x1fff<<0) -#define m_WIN3_DSP_YST1 (0x1fff<<16) - -#define WIN3_SRC_ALPHA_CTRL (0x012c) -#define v_WIN3_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_WIN3_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_WIN3_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_WIN3_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_WIN3_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_WIN3_SRC_FACTOR_M0(x) (((x)&7)<<6) -#define v_WIN3_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_WIN3_FADING_VALUE(x) (((x)&0xff)<<24) - -#define m_WIN3_SRC_ALPHA_EN (1<<0) -#define m_WIN3_SRC_COLOR_M0 (1<<1) -#define m_WIN3_SRC_ALPHA_M0 (1<<2) -#define m_WIN3_SRC_BLEND_M0 (3<<3) -#define m_WIN3_SRC_ALPHA_CAL_M0 (1<<5) -#define m_WIN3_SRC_FACTOR_M0 (7<<6) -#define m_WIN3_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_WIN3_FADING_VALUE (0xff<<24) - -#define WIN3_MST2 (0x0130) -#define WIN3_DSP_INFO2 (0x0134) -#define v_WIN3_DSP_WIDTH2(x) (((x-1)&0xfff)<<0) -#define v_WIN3_DSP_HEIGHT2(x) (((x-1)&0xfff)<<16) -#define m_WIN3_DSP_WIDTH2 (0xfff<<0) -#define m_WIN3_DSP_HEIGHT2 (0xfff<<16) - -#define WIN3_DSP_ST2 (0x0138) -#define v_WIN3_DSP_XST2(x) (((x)&0x1fff)<<0) -#define v_WIN3_DSP_YST2(x) (((x)&0x1fff)<<16) -#define m_WIN3_DSP_XST2 (0x1fff<<0) -#define m_WIN3_DSP_YST2 (0x1fff<<16) - -#define WIN3_DST_ALPHA_CTRL (0x013c) -#define v_WIN3_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_WIN3_DST_FACTOR_M0 (7<<6) - - -#define WIN3_MST3 (0x0140) -#define WIN3_DSP_INFO3 (0x0144) -#define v_WIN3_DSP_WIDTH3(x) (((x-1)&0xfff)<<0) -#define v_WIN3_DSP_HEIGHT3(x) (((x-1)&0xfff)<<16) -#define m_WIN3_DSP_WIDTH3 (0xfff<<0) -#define m_WIN3_DSP_HEIGHT3 (0xfff<<16) - -#define WIN3_DSP_ST3 (0x0148) -#define v_WIN3_DSP_XST3(x) (((x)&0x1fff)<<0) -#define v_WIN3_DSP_YST3(x) (((x)&0x1fff)<<16) -#define m_WIN3_DSP_XST3 (0x1fff<<0) -#define m_WIN3_DSP_YST3 (0x1fff<<16) - -#define WIN3_FADING_CTRL (0x014c) -#define v_WIN3_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_WIN3_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_WIN3_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_WIN3_FADING_EN(x) (((x)&1)<<24) - -#define m_WIN3_FADING_OFFSET_R (0xff<<0) -#define m_WIN3_FADING_OFFSET_G (0xff<<8) -#define m_WIN3_FADING_OFFSET_B (0xff<<16) -#define m_WIN3_FADING_EN (1<<24) - - -/*hwc register*/ -#define HWC_CTRL0 (0x0150) -#define v_HWC_EN(x) (((x)&1)<<0) -#define v_HWC_DATA_FMT(x) (((x)&7)<<1) -#define v_HWC_MODE(x) (((x)&1)<<4) -#define v_HWC_SIZE(x) (((x)&3)<<5) -#define v_HWC_INTERLACE_READ(x) (((x)&1)<<8) -#define v_HWC_CSC_MODE(x) (((x)&1)<<10) -#define v_HWC_RB_SWAP(x) (((x)&1)<<12) -#define v_HWC_ALPHA_SWAP(x) (((x)&1)<<13) -#define v_HWC_ENDIAN_SWAP(x) (((x)&1)<<14) - -#define m_HWC_EN (1<<0) -#define m_HWC_DATA_FMT (7<<1) -#define m_HWC_MODE (1<<4) -#define m_HWC_SIZE (3<<5) -#define m_HWC_INTERLACE_READ (1<<8) -#define m_HWC_CSC_MODE (1<<10) -#define m_HWC_RB_SWAP (1<<12) -#define m_HWC_ALPHA_SWAP (1<<13) -#define m_HWC_ENDIAN_SWAP (1<<14) - - -#define HWC_CTRL1 (0x0154) -#define v_HWC_AXI_GATHER_EN(x) (((x)&1)<<0) -#define v_HWC_AXI_MAX_OUTSTANDING_EN(x) (((x)&1)<<1) -#define v_HWC_DMA_BURST_LENGTH(x) (((x)&0x3)<<2) -#define v_HWC_AXI_GATHER_NUM(x) (((x)&0x7)<<4) -#define v_HWC_AXI_OUTSTANDING_MAX_NUM(x) (((x)&0x1f)<<8) -#define v_HWC_RGB2YUV_EN(x) (((x)&1)<<13) -#define v_HWC_NO_OUTSTANDING(x) (((x)&1)<<14) -#define v_HWC_Y_MIR(x) (((x)&1)<<15) -#define v_HWC_LUT_EN(x) (((x)&1)<<16) -#define v_WIN_RID_HWC(x) (((x)&0xf)<<20) - -#define m_HWC_AXI_GATHER_EN (1<<0) -#define m_HWC_AXI_MAX_OUTSTANDING_EN (1<<1) -#define m_HWC_DMA_BURST_LENGTH (0x3<<2) -#define m_HWC_AXI_GATHER_NUM (0x7<<4) -#define m_HWC_AXI_OUTSTANDING_MAX_NUM (0x1f<<8) -#define m_HWC_RGB2YUV_EN (1<<13) -#define m_HWC_NO_OUTSTANDING (1<<14) -#define m_HWC_Y_MIR (1<<15) -#define m_HWC_LUT_EN (1<<16) -#define m_WIN_RID_HWC (0xf<<20) - -#define HWC_MST (0x0158) -#define HWC_DSP_ST (0x015c) -#define v_HWC_DSP_XST(x) (((x)&0x1fff)<<0) -#define v_HWC_DSP_YST(x) (((x)&0x1fff)<<16) -#define m_HWC_DSP_XST (0x1fff<<0) -#define m_HWC_DSP_YST (0x1fff<<16) - -#define HWC_SRC_ALPHA_CTRL (0x0160) -#define v_HWC_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_HWC_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_HWC_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_HWC_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_HWC_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_HWC_SRC_FACTOR_M0(x) (((x)&7)<<6) -#define v_HWC_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_HWC_FADING_VALUE(x) (((x)&0xff)<<24) - -#define m_HWC_SRC_ALPHA_EN (1<<0) -#define m_HWC_SRC_COLOR_M0 (1<<1) -#define m_HWC_SRC_ALPHA_M0 (1<<2) -#define m_HWC_SRC_BLEND_M0 (3<<3) -#define m_HWC_SRC_ALPHA_CAL_M0 (1<<5) -#define m_HWC_SRC_FACTOR_M0 (7<<6) -#define m_HWC_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_HWC_FADING_VALUE (0xff<<24) - -#define HWC_DST_ALPHA_CTRL (0x0164) -#define v_HWC_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_HWC_DST_FACTOR_M0 (7<<6) - - -#define HWC_FADING_CTRL (0x0168) -#define v_HWC_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_HWC_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_HWC_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_HWC_FADING_EN(x) (((x)&1)<<24) - -#define m_HWC_FADING_OFFSET_R (0xff<<0) -#define m_HWC_FADING_OFFSET_G (0xff<<8) -#define m_HWC_FADING_OFFSET_B (0xff<<16) -#define m_HWC_FADING_EN (1<<24) - -/*post process register*/ -#define POST_DSP_HACT_INFO (0x0170) -#define v_DSP_HACT_END_POST(x) (((x)&0x1fff)<<0) -#define v_DSP_HACT_ST_POST(x) (((x)&0x1fff)<<16) -#define m_DSP_HACT_END_POST (0x1fff<<0) -#define m_DSP_HACT_ST_POST (0x1fff<<16) - -#define POST_DSP_VACT_INFO (0x0174) -#define v_DSP_VACT_END_POST(x) (((x)&0x1fff)<<0) -#define v_DSP_VACT_ST_POST(x) (((x)&0x1fff)<<16) -#define m_DSP_VACT_END_POST (0x1fff<<0) -#define m_DSP_VACT_ST_POST (0x1fff<<16) - -#define POST_SCL_FACTOR_YRGB (0x0178) -#define v_POST_HS_FACTOR_YRGB(x) (((x)&0xffff)<<0) -#define v_POST_VS_FACTOR_YRGB(x) (((x)&0xffff)<<16) -#define m_POST_HS_FACTOR_YRGB (0xffff<<0) -#define m_POST_VS_FACTOR_YRGB (0xffff<<16) - -#define POST_SCL_CTRL (0x0180) -#define v_POST_HOR_SD_EN(x) (((x)&1)<<0) -#define v_POST_VER_SD_EN(x) (((x)&1)<<1) - -#define m_POST_HOR_SD_EN (0x1<<0) -#define m_POST_VER_SD_EN (0x1<<1) - -#define POST_DSP_VACT_INFO_F1 (0x0184) -#define v_DSP_VACT_END_POST_F1(x) (((x)&0x1fff)<<0) -#define v_DSP_VACT_ST_POST_F1(x) (((x)&0x1fff)<<16) - -#define m_DSP_VACT_END_POST_F1 (0x1fff<<0) -#define m_DSP_VACT_ST_POST_F1 (0x1fff<<16) - -#define DSP_HTOTAL_HS_END (0x0188) -#define v_DSP_HS_PW(x) (((x)&0x1fff)<<0) -#define v_DSP_HTOTAL(x) (((x)&0x1fff)<<16) -#define m_DSP_HS_PW (0x1fff<<0) -#define m_DSP_HTOTAL (0x1fff<<16) - -#define DSP_HACT_ST_END (0x018c) -#define v_DSP_HACT_END(x) (((x)&0x1fff)<<0) -#define v_DSP_HACT_ST(x) (((x)&0x1fff)<<16) -#define m_DSP_HACT_END (0x1fff<<0) -#define m_DSP_HACT_ST (0x1fff<<16) - -#define DSP_VTOTAL_VS_END (0x0190) -#define v_DSP_VS_PW(x) (((x)&0x1fff)<<0) -#define v_DSP_VTOTAL(x) (((x)&0x1fff)<<16) -#define m_DSP_VS_PW (0x1fff<<0) -#define m_DSP_VTOTAL (0x1fff<<16) - -#define DSP_VACT_ST_END (0x0194) -#define v_DSP_VACT_END(x) (((x)&0x1fff)<<0) -#define v_DSP_VACT_ST(x) (((x)&0x1fff)<<16) -#define m_DSP_VACT_END (0x1fff<<0) -#define m_DSP_VACT_ST (0x1fff<<16) - -#define DSP_VS_ST_END_F1 (0x0198) -#define v_DSP_VS_END_F1(x) (((x)&0x1fff)<<0) -#define v_DSP_VS_ST_F1(x) (((x)&0x1fff)<<16) -#define m_DSP_VS_END_F1 (0x1fff<<0) -#define m_DSP_VS_ST_F1 (0x1fff<<16) - -#define DSP_VACT_ST_END_F1 (0x019c) -#define v_DSP_VACT_END_F1(x) (((x)&0x1fff)<<0) -#define v_DSP_VAC_ST_F1(x) (((x)&0x1fff)<<16) -#define m_DSP_VACT_END_F1 (0x1fff<<0) -#define m_DSP_VAC_ST_F1 (0x1fff<<16) - - -/*pwm register*/ -#define PWM_CTRL (0x01a0) -#define v_PWM_EN(x) (((x)&1)<<0) -#define v_PWM_MODE(x) (((x)&3)<<1) - -#define v_DUTY_POL(x) (((x)&1)<<3) -#define v_INACTIVE_POL(x) (((x)&1)<<4) -#define v_OUTPUT_MODE(x) (((x)&1)<<5) -#define v_BL_EN(x) (((x)&1)<<8) -#define v_CLK_SEL(x) (((x)&1)<<9) -#define v_PRESCALE(x) (((x)&7)<<12) -#define v_CABC_PWM_OUT_POL(x) (((x)&1)<<15) -#define v_SCALE(x) (((x)&0xff)<<16) -#define v_RPT(x) (((x)&0xff)<<24) - -#define m_PWM_EN (1<<0) -#define m_PWM_MODE (3<<1) - -#define m_DUTY_POL (1<<3) -#define m_INACTIVE_POL (1<<4) -#define m_OUTPUT_MODE (1<<5) -#define m_BL_EN (1<<8) -#define m_CLK_SEL (1<<9) -#define m_CABC_PWM_OUT_POL (1<<15) - -#define m_PRESCALE (7<<12) -#define m_SCALE (0xff<<16) -#define m_RPT ((u32)0xff<<24) - -#define PWM_PERIOD_HPR (0x01a4) -#define PWM_DUTY_LPR (0x01a8) -#define PWM_CNT (0x01ac) - -/*BCSH register*/ -#define BCSH_COLOR_BAR (0x01b0) -#define v_BCSH_EN(x) (((x)&1)<<0) -#define v_BCSH_COLOR_BAR_Y(x) (((x)&0xff)<<8) -#define v_BCSH_COLOR_BAR_U(x) (((x)&0xff)<<16) -#define v_BCSH_COLOR_BAR_V(x) (((x)&0xff)<<24) -#define m_BCSH_EN (1<<0) -#define m_BCSH_COLOR_BAR_Y (0xff<<8) -#define m_BCSH_COLOR_BAR_U (0xff<<16) -#define m_BCSH_COLOR_BAR_V (0xff<<24) - -#define BCSH_BCS (0x01b4) -#define v_BCSH_BRIGHTNESS(x) (((x)&0x3f)<<0) -#define v_BCSH_CONTRAST(x) (((x)&0x1ff)<<8) -#define v_BCSH_SAT_CON(x) (((x)&0x3ff)<<20) -#define v_BCSH_OUT_MODE(x) (((x)&0x3)<<30) -#define m_BCSH_BRIGHTNESS (0x3f<<0) -#define m_BCSH_CONTRAST (0x1ff<<8) -#define m_BCSH_SAT_CON (0x3ff<<20) -#define m_BCSH_OUT_MODE ((u32)0x3<<30) - -#define BCSH_H (0x01b8) -#define v_BCSH_SIN_HUE(x) (((x)&0x1ff)<<0) -#define v_BCSH_COS_HUE(x) (((x)&0x1ff)<<16) - -#define m_BCSH_SIN_HUE (0x1ff<<0) -#define m_BCSH_COS_HUE (0x1ff<<16) - -#define BCSH_CTRL (0x01bc) -#define m_BCSH_Y2R_EN (0x1<<0) -#define m_BCSH_Y2R_CSC_MODE (0x3<<2) -#define m_BCSH_R2Y_EN (0x1<<4) -#define m_BCSH_R2Y_CSC_MODE (0x1<<6) -#define v_BCSH_Y2R_EN(x) (((x)&0x1)<<0) -#define v_BCSH_Y2R_CSC_MODE(x) (((x)&0x3)<<2) -#define v_BCSH_R2Y_EN(x) (((x)&0x1)<<4) -#define v_BCSH_R2Y_CSC_MODE(x) (((x)&0x1)<<6) - -#define CABC_CTRL0 (0x01c0) -#define v_CABC_EN(x) (((x)&1)<<0) -#define v_CABC_HANDLE_EN(x) (((x)&1)<<1) -#define v_PWM_CONFIG_MODE(x) (((x)&3)<<2) -#define v_CABC_CALC_PIXEL_NUM(x) (((x)&0x7fffff)<<4) -#define m_CABC_EN (1<<0) -#define m_CABC_HANDLE_EN (1<<1) -#define m_PWM_CONFIG_MODE (3<<2) -#define m_CABC_CALC_PIXEL_NUM (0x7fffff<<4) - -#define CABC_CTRL1 (0x01c4) -#define v_CABC_LUT_EN(x) (((x)&1)<<0) -#define v_CABC_TOTAL_PIXEL_NUM(x) (((x)&0x7fffff)<<4) -#define m_CABC_LUT_EN (1<<0) -#define m_CABC_TOTAL_PIXEL_NUM (0x7fffff<<4) - -#define CABC_CTRL2 (0x01c8) -#define v_CABC_STAGE_DOWN(x) (((x)&0xff)<<0) -#define v_CABC_STAGE_UP(x) (((x)&0x1ff)<<8) -#define v_CABC_STAGE_MODE(x) (((x)&1)<<19) -#define v_MAX_SCALE_CFG_VALUE(x) (((x)&0x1ff)<<20) -#define v_MAX_SCALE_CFG_ENABLE(x) (((x)&1)<<31) -#define m_CABC_STAGE_DOWN (0xff<<0) -#define m_CABC_STAGE_UP (0x1ff<<8) -#define m_CABC_STAGE_MODE (1<<19) -#define m_MAX_SCALE_CFG_VALUE (0x1ff<<20) -#define m_MAX_SCALE_CFG_ENABLE (1<<31) - -#define CABC_CTRL3 (0x01cc) -#define v_CABC_GLOBAL_DN(x) (((x)&0xff)<<0) -#define v_CABC_GLOBAL_DN_LIMIT_EN(x) (((x)&1)<<8) -#define m_CABC_GLOBAL_DN (0xff<<0) -#define m_CABC_GLOBAL_DN_LIMIT_EN (1<<8) - -#define CABC_GAUSS_LINE0_0 (0x01d0) -#define v_CABC_T_LINE0_0(x) (((x)&0xff)<<0) -#define v_CABC_T_LINE0_1(x) (((x)&0xff)<<8) -#define v_CABC_T_LINE0_2(x) (((x)&0xff)<<16) -#define v_CABC_T_LINE0_3(x) (((x)&0xff)<<24) -#define m_CABC_T_LINE0_0 (0xff<<0) -#define m_CABC_T_LINE0_1 (0xff<<8) -#define m_CABC_T_LINE0_2 (0xff<<16) -#define m_CABC_T_LINE0_3 ((u32)0xff<<24) - -#define CABC_GAUSS_LINE0_1 (0x01d4) -#define v_CABC_T_LINE0_4(x) (((x)&0xff)<<0) -#define v_CABC_T_LINE0_5(x) (((x)&0xff)<<8) -#define v_CABC_T_LINE0_6(x) (((x)&0xff)<<16) -#define m_CABC_T_LINE0_4 (0xff<<0) -#define m_CABC_T_LINE0_5 (0xff<<8) -#define m_CABC_T_LINE0_6 (0xff<<16) - - -#define CABC_GAUSS_LINE1_0 (0x01d8) -#define v_CABC_T_LINE1_0(x) (((x)&0xff)<<0) -#define v_CABC_T_LINE1_1(x) (((x)&0xff)<<8) -#define v_CABC_T_LINE1_2(x) (((x)&0xff)<<16) -#define v_CABC_T_LINE1_3(x) (((x)&0xff)<<24) -#define m_CABC_T_LINE1_0 (0xff<<0) -#define m_CABC_T_LINE1_1 (0xff<<8) -#define m_CABC_T_LINE1_2 (0xff<<16) -#define m_CABC_T_LINE1_3 ((u32)0xff<<24) - - -#define CABC_GAUSS_LINE1_1 (0x01dc) -#define v_CABC_T_LINE1_4(x) (((x)&0xff)<<0) -#define v_CABC_T_LINE1_5(x) (((x)&0xff)<<8) -#define v_CABC_T_LINE1_6(x) (((x)&0xff)<<16) -#define m_CABC_T_LINE1_4 (0xff<<0) -#define m_CABC_T_LINE1_5 (0xff<<8) -#define m_CABC_T_LINE1_6 (0xff<<16) - - -#define CABC_GAUSS_LINE2_0 (0x01e0) -#define v_CABC_T_LINE2_0(x) (((x)&0xff)<<0) -#define v_CABC_T_LINE2_1(x) (((x)&0xff)<<8) -#define v_CABC_T_LINE2_2(x) (((x)&0xff)<<16) -#define v_CABC_T_LINE2_3(x) (((x)&0xff)<<24) -#define m_CABC_T_LINE2_0 (0xff<<0) -#define m_CABC_T_LINE2_1 (0xff<<8) -#define m_CABC_T_LINE2_2 (0xff<<16) -#define m_CABC_T_LINE2_3 ((u32)0xff<<24) - - -#define CABC_GAUSS_LINE2_1 (0x01e4) -#define v_CABC_T_LINE2_4(x) (((x)&0xff)<<0) -#define v_CABC_T_LINE2_5(x) (((x)&0xff)<<8) -#define v_CABC_T_LINE2_6(x) (((x)&0xff)<<16) -#define m_CABC_T_LINE2_4 (0xff<<0) -#define m_CABC_T_LINE2_5 (0xff<<8) -#define m_CABC_T_LINE2_6 (0xff<<16) - -/*FRC register*/ -#define FRC_LOWER01_0 (0x01e8) -#define v_FRC_LOWER01_FRM0(x) (((x)&0xffff)<<0) -#define v_FRC_LOWER01_FRM1(x) (((x)&0xffff)<<16) -#define m_FRC_LOWER01_FRM0 (0xffff<<0) -#define m_FRC_LOWER01_FRM1 ((u32)0xffff<<16) - -#define FRC_LOWER01_1 (0x01ec) -#define v_FRC_LOWER01_FRM2(x) (((x)&0xffff)<<0) -#define v_FRC_LOWER01_FRM3(x) (((x)&0xffff)<<16) -#define m_FRC_LOWER01_FRM2 (0xffff<<0) -#define m_FRC_LOWER01_FRM3 ((u32)0xffff<<16) - - -#define FRC_LOWER10_0 (0x01f0) -#define v_FRC_LOWER10_FRM0(x) (((x)&0xffff)<<0) -#define v_FRC_LOWER10_FRM1(x) (((x)&0xffff)<<16) -#define m_FRC_LOWER10_FRM0 (0xffff<<0) -#define m_FRC_LOWER10_FRM1 ((u32)0xffff<<16) - - -#define FRC_LOWER10_1 (0x01f4) -#define v_FRC_LOWER10_FRM2(x) (((x)&0xffff)<<0) -#define v_FRC_LOWER10_FRM3(x) (((x)&0xffff)<<16) -#define m_FRC_LOWER10_FRM2 (0xffff<<0) -#define m_FRC_LOWER10_FRM3 ((u32)0xffff<<16) - - -#define FRC_LOWER11_0 (0x01f8) -#define v_FRC_LOWER11_FRM0(x) (((x)&0xffff)<<0) -#define v_FRC_LOWER11_FRM1(x) (((x)&0xffff)<<16) -#define m_FRC_LOWER11_FRM0 (0xffff<<0) -#define m_FRC_LOWER11_FRM1 ((u32)0xffff<<16) - - -#define FRC_LOWER11_1 (0x01fc) -#define v_FRC_LOWER11_FRM2(x) (((x)&0xffff)<<0) -#define v_FRC_LOWER11_FRM3(x) (((x)&0xffff)<<16) -#define m_FRC_LOWER11_FRM2 (0xffff<<0) -#define m_FRC_LOWER11_FRM3 ((u32)0xffff<<16) - -#define IFBDC_CTRL (0x0200) -#define v_IFBDC_CTRL_FBDC_EN(x) (((x)&0x1)<<0) -#define v_IFBDC_CTRL_FBDC_COR_EN(x) (((x)&0x1)<<1) -#define v_IFBDC_CTRL_FBDC_WIN_SEL(x) (((x)&0x3)<<2) -#define v_IFBDC_CTRL_FBDC_ROTATION_MODE(x) (((x)&0x7)<<4) -#define v_IFBDC_CTRL_FBDC_FMT(x) (((x)&0x7f)<<7) -#define v_IFBDC_AXI_MAX_OUTSTANDING_EN(x) (((x)&0x1)<<14) -#define v_IFBDC_AXI_OUTSTANDING_MAX_NUM(x) (((x)&0x1f)<<15) -#define v_IFBDC_CTRL_WIDTH_RATIO(x) (((x)&0x1)<<20) -#define v_IFBDC_FRAME_RST_EN(x) (((x)&0x1)<<21) -#define v_IFBDC_ICTRL_NOTIFY(x) (((x)&0x1)<<22) -#define v_IFBDC_INVALIDATE_PENDING_O(x) (((x)&0x1)<<23) -#define v_IFBDC_RID(x) (((x)&0xf)<<24) -#define v_IFBDC_RSTN(x) (((x)&0x1)<<28) - -#define m_IFBDC_CTRL_FBDC_EN (0x1<<0) -#define m_IFBDC_CTRL_FBDC_COR_EN (0x1<<1) -#define m_IFBDC_CTRL_FBDC_WIN_SEL (0x3<<2) -#define m_IFBDC_CTRL_FBDC_ROTATION_MODE (0x7<<4) -#define m_IFBDC_CTRL_FBDC_FMT (0x7f<<7) -#define m_IFBDC_AXI_MAX_OUTSTANDING_EN (0x1<<14) -#define m_IFBDC_AXI_OUTSTANDING_MAX_NUM (0x1f<<15) -#define m_IFBDC_CTRL_WIDTH_RATIO (0x1<<20) -#define m_IFBDC_FRAME_RST_EN (0x1<<21) -#define m_IFBDC_ICTRL_NOTIFY (0x1<<22) -#define m_IFBDC_INVALIDATE_PENDING_O (0x1<<23) -#define m_IFBDC_RID (0xf<<24) -#define m_IFBDC_RSTN (0x1<<28) - -#define IFBDC_TILES_NUM (0x0204) -#define v_IFBDC_TILES_NUM(x) (((x-1)&0x7fffff)<<0) -#define m_IFBDC_TILES_NUM (0x7fffff<<0) - -#define IFBDC_FRAME_RST_CYCLE (0x0208) -#define v_IFBDC_FRAME_RST_CYCLE(x) (((x)&0x3ff)<<0) -#define v_DMA_IFBDC_FRAME_RST_CYCLE(x) (((x)&0x3ff)<<16) -#define m_IFBDC_FRAME_RST_CYCLE ((0x3ff)<<0) -#define m_DMA_IFBDC_FRAME_RST_CYCLE ((0x3ff)<<16) - - - -#define IFBDC_BASE_ADDR (0x20c) -#define v_IFBDC_BASE_ADDR(x) (((x)&0xffffffff)<<0) -#define m_IFBDC_BASE_ADDR ((0xffffffff)<<0) - -#define IFBDC_MB_SIZE (0x210) -#define v_IFBDC_MB_SIZE_WIDTH(x) (((x-1)&0x7f)<<0) -#define v_IFBDC_MB_SIZE_HEIGHT(x) (((x-1)&0x1ff)<<16) -#define m_IFBDC_MB_SIZE_WIDTH ((0x7f)<<0) -#define m_IFBDC_MB_SIZE_HEIGHT ((0x1ff)<<16) - - -#define IFBDC_CMP_INDEX_INIT (0x0214) -#define v_IFBDC_CMP_INDEX_INIT(x) (((x)&0x7fffff) << 0) -#define m_IFBDC_CMP_INDEX_INIT (0x7fffff<<0) - -#define IFBDC_MB_VIR_WIDTH (0x220) -#define v_IFBDC_MB_VIR_WIDTH(x) (((x)&0xff)<<0) -#define m_IFBDC_MB_VIR_WIDTH ((0xff)<<0) - -#define IFBDC_DEBUG0 (0x230) -#define v_DBG_IFBDC_MB_Y_WCNT(x) (((x)&0x1ff)<<0) -#define v_DBG_IFBDC_IDLE(x) (((x)&0x1)<<12) -#define v_DBG_IFBDC_LB_RCNT(x) (((x)&0x7FF)<<16) -#define v_DBG_IFBDC_INVALIDATE_PENDING_I(x) (((x)&0x1)<<28) - -#define m_DBG_IFBDC_MB_Y_WCNT (0x1ff<<0) -#define m_DBG_IFBDC_IDLE (0x1<<12) -#define m_DBG_IFBDC_LB_RCNT (0x7FF<<16) -#define m_DBG_IFBDC_INVALIDATE_PENDING_I (0x1<<28) - -#define IFBDC_DEBUG1 (0x234) -#define V_DBG_FBDC_CMP_TILE_INDEX(x) (((x)&0x7fffff)<<0) -#define m_DBG_FBDC_CMP_TILE_INDEX (0x7fffff<<0) - -#define LATENCY_CTRL0 (0x250) -#define v_RD_LATENCY_EN(x) (((x)&0x1)<<0) -#define v_HAND_LATENCY_CLR(x) (((x)&0x1)<<1) -#define v_RD_LATENCY_MODE(x) (((x)&0x1)<<2) -#define v_RD_LATENCY_ID0(x) (((x)&0xf)<<4) -#define v_RD_LATENCY_THR(x) (((x)&0xfff)<<8) -#define v_RD_LATENCY_ST_NUM(x) (((x)&0x1f)<<20) -#define m_RD_LATENCY_EN (0x1<<0) -#define m_HAND_LATENCY_CLR (0x1<<1) -#define m_RD_LATENCY_MODE (0x1<<2) -#define m_RD_LATENCY_ID0 (0xf<<4) -#define m_RD_LATENCY_THR (0xfff<<8) -#define m_RD_LATENCY_ST_NUM (0x1f<<20) - -#define RD_MAX_LATENCY_NUM0 (0x254) -#define v_RD_MAX_LATENCY_NUM_CH0(x) (((x)&0xFFF)<<0) -#define v_RD_LATENCY_OVERFLOW_CH0(x) (((x)&0x1)<<16) -#define m_RD_MAX_LATENCY_NUM_CH0 (0xFFF<<0) -#define m_RD_LATENCY_OVERFLOW_CH0 (0x1<<16) - -#define RD_LATENCY_THR_NUM0 (0x258) -#define v_RD_LATENCY_THR_NUM_CH0(x) (((x)&0xFFFFFF)<<0) -#define m_RD_LATENCY_THR_NUM_CH0 (0xFFFFFF<<0) - -#define RD_LATENCY_SWAP_NUM0 (0x25c) -#define v_RD_LATENCY_SAMP_NUM_CH0(x) (((x)&0xFFFFFF)<<0) -#define m_RD_LATENCY_SAMP_NUM_CH0 (0xFFFFFF<<0) - -#define VOP_STATUS 0x000002a4 -#define v_VOP_DSP_VCNT(x) (((x)&0x1FFF)<<0) -#define v_VOP_MMU_IDLE(x) (((x)&0x1)<<16) -#define v_DMA_STOP_VALID(x) (((x)&0x1)<<17) -#define m_VOP_DSP_VCNT (0x1FFF<<0) -#define m_VOP_MMU_IDLE (0x1<<16) -#define m_DMA_STOP_VALID (0x1<<17) - -#define BLANKING_VALUE 0x02a8 -#define v_BLANKING_VALUE(x) (((x)&0xFFFFFF)<<0) -#define v_BLANKING_VALUE_CONFIG_EN(x) (((x)&0x1)<<24) -#define m_BLANKING_VALUE (0xFFFFFF<<0) -#define m_BLANKING_VALUE_CONFIG_EN (0x1<<24) - -#define WIN0_DSP_BG_RK3368 (0x260) -#define WIN0_DSP_BG_RK3366 (0x2b0)/*rk3366*/ -#define v_WIN0_DSP_BG_BLUE(x) (((x)&0xff)<<0) -#define v_WIN0_DSP_BG_GREEN(x) (((x)&0xff)<<8) -#define v_WIN0_DSP_BG_RED(x) (((x)&0xff)<<16) -#define v_WIN0_DSP_BG_EN(x) (((x)&1)<<31) -#define m_WIN0_DSP_BG_BLUE (0xff<<0) -#define m_WIN0_DSP_BG_GREEN (0xff<<8) -#define m_WIN0_DSP_BG_RED (0xff<<16) -#define m_WIN0_DSP_BG_EN (0x1<<31) - -#define WIN1_DSP_BG_RK3368 (0x264) -#define WIN1_DSP_BG_RK3366 (0x2b4)/*rk3366*/ -#define v_WIN1_DSP_BG_BLUE(x) (((x)&0xff)<<0) -#define v_WIN1_DSP_BG_GREEN(x) (((x)&0xff)<<8) -#define v_WIN1_DSP_BG_RED(x) (((x)&0xff)<<16) -#define v_WIN1_DSP_BG_EN(x) (((x)&1)<<31) -#define m_WIN1_DSP_BG_BLUE (0xff<<0) -#define m_WIN1_DSP_BG_GREEN (0xff<<8) -#define m_WIN1_DSP_BG_RED (0xff<<16) -#define m_WIN1_DSP_BG_EN (0x1<<31) - -#define WIN2_DSP_BG_RK3368 (0x268) -#define WIN2_DSP_BG_RK3366 (0x2b8)/*rk3366*/ -#define v_WIN2_DSP_BG_BLUE(x) (((x)&0xff)<<0) -#define v_WIN2_DSP_BG_GREEN(x) (((x)&0xff)<<8) -#define v_WIN2_DSP_BG_RED(x) (((x)&0xff)<<16) -#define v_WIN2_DSP_BG_EN(x) (((x)&1)<<31) -#define m_WIN2_DSP_BG_BLUE (0xff<<0) -#define m_WIN2_DSP_BG_GREEN (0xff<<8) -#define m_WIN2_DSP_BG_RED (0xff<<16) -#define m_WIN2_DSP_BG_EN (0x1<<31) - -#define WIN3_DSP_BG_RK3368 (0x26c) -#define WIN3_DSP_BG_RK3366 (0x2bC)/*rk3366*/ -#define v_WIN3_DSP_BG_BLUE(x) (((x)&0xff)<<0) -#define v_WIN3_DSP_BG_GREEN(x) (((x)&0xff)<<8) -#define v_WIN3_DSP_BG_RED(x) (((x)&0xff)<<16) -#define v_WIN3_DSP_BG_EN(x) (((x)&1)<<31) -#define m_WIN3_DSP_BG_BLUE (0xff<<0) -#define m_WIN3_DSP_BG_GREEN (0xff<<8) -#define m_WIN3_DSP_BG_RED (0xff<<16) -#define m_WIN3_DSP_BG_EN (0x1<<31) - -#define SCAN_LINE_NUM (0x270) -#define CABC_DEBUG0 (0x274) -#define CABC_DEBUG1 (0x278) -#define CABC_DEBUG2 (0x27c) -#define DBG_REG_000 (0x280) -#define DBG_REG_001 (0x284) -#define DBG_REG_002 (0x288) -#define DBG_REG_003 (0x28c) -#define DBG_REG_004 (0x290) -#define DBG_REG_005 (0x294) -#define DBG_REG_006 (0x298) -#define DBG_REG_007 (0x29c) -#define DBG_REG_008 (0x2a0) -#define DBG_REG_016 (0x2c0) -#define DBG_REG_017 (0x2c4) -#define DBG_REG_018 (0x2c8) -#define DBG_REG_019 (0x2cc) -#define DBG_REG_020 (0x2d0) -#define DBG_REG_021 (0x2d4) -#define DBG_REG_022 (0x2d8) -#define DBG_REG_023 (0x2dc) -#define DBG_REG_028 (0x2f0) - -#define MMU_DTE_ADDR (0x0300) -#define v_MMU_DTE_ADDR(x) (((x)&0xffffffff)<<0) -#define m_MMU_DTE_ADDR (0xffffffff<<0) - -#define MMU_STATUS (0x0304) -#define v_PAGING_ENABLED(x) (((x)&1)<<0) -#define v_PAGE_FAULT_ACTIVE(x) (((x)&1)<<1) -#define v_STAIL_ACTIVE(x) (((x)&1)<<2) -#define v_MMU_IDLE(x) (((x)&1)<<3) -#define v_REPLAY_BUFFER_EMPTY(x) (((x)&1)<<4) -#define v_PAGE_FAULT_IS_WRITE(x) (((x)&1)<<5) -#define v_PAGE_FAULT_BUS_ID(x) (((x)&0x1f)<<6) -#define m_PAGING_ENABLED (1<<0) -#define m_PAGE_FAULT_ACTIVE (1<<1) -#define m_STAIL_ACTIVE (1<<2) -#define m_MMU_IDLE (1<<3) -#define m_REPLAY_BUFFER_EMPTY (1<<4) -#define m_PAGE_FAULT_IS_WRITE (1<<5) -#define m_PAGE_FAULT_BUS_ID (0x1f<<6) - -#define MMU_COMMAND (0x0308) -#define v_MMU_CMD(x) (((x)&0x3)<<0) -#define m_MMU_CMD (0x3<<0) - -#define MMU_PAGE_FAULT_ADDR (0x030c) -#define v_PAGE_FAULT_ADDR(x) (((x)&0xffffffff)<<0) -#define m_PAGE_FAULT_ADDR (0xffffffff<<0) - -#define MMU_ZAP_ONE_LINE (0x0310) -#define v_MMU_ZAP_ONE_LINE(x) (((x)&0xffffffff)<<0) -#define m_MMU_ZAP_ONE_LINE (0xffffffff<<0) - -#define MMU_INT_RAWSTAT (0x0314) -#define v_PAGE_FAULT_RAWSTAT(x) (((x)&1)<<0) -#define v_READ_BUS_ERROR_RAWSTAT(x) (((x)&1)<<1) -#define m_PAGE_FAULT_RAWSTAT (1<<0) -#define m_READ_BUS_ERROR_RAWSTAT (1<<1) - -#define MMU_INT_CLEAR (0x0318) -#define v_PAGE_FAULT_CLEAR(x) (((x)&1)<<0) -#define v_READ_BUS_ERROR_CLEAR(x) (((x)&1)<<1) -#define m_PAGE_FAULT_CLEAR (1<<0) -#define m_READ_BUS_ERROR_CLEAR (1<<1) - -#define MMU_INT_MASK (0x031c) -#define v_PAGE_FAULT_MASK(x) (((x)&1)<<0) -#define v_READ_BUS_ERROR_MASK(x) (((x)&1)<<1) -#define m_PAGE_FAULT_MASK (1<<0) -#define m_READ_BUS_ERROR_MASK (1<<1) - -#define MMU_INT_STATUS (0x0320) -#define v_PAGE_FAULT_STATUS(x) (((x)&1)<<0) -#define v_READ_BUS_ERROR_STATUS(x) (((x)&1)<<1) -#define m_PAGE_FAULT_STATUS (1<<0) -#define m_READ_BUS_ERROR_STATUS (1<<1) - -#define MMU_AUTO_GATING (0x0324) -#define v_MMU_AUTO_GATING(x) (((x)&1)<<0) -#define m_MMU_AUTO_GATING (1<<0) - -#define WIN2_LUT_ADDR (0x0400) -#define WIN3_LUT_ADDR (0x0800) -#define HWC_LUT_ADDR (0x0c00) -#define GAMMA_LUT_ADDR (0x1000) -#define CABC_GAMMA_LUT_ADDR (0x1800) -#define MCU_BYPASS_WPORT (0x2200) -#define MCU_BYPASS_RPORT (0x2300) - -#define PMUGRF_SOC_CON0_VOP (0x0100) - -#define RK3366_GRF_SOC_CON0 (0x0400) -#define RK3366_GRF_SOC_CON5 (0x0414) - -#define OUT_CCIR656_MODE_0 5 -#define OUT_CCIR656_MODE_1 6 -#define OUT_CCIR656_MODE_2 7 - -#define VOP_SOURCE_SEL(id, shift) ((id << shift) | 1 << (shift + 16)) -#define RGB_SOURCE_SEL(id) VOP_SOURCE_SEL(id, 3) -#define LVDS_SOURCE_SEL(id) VOP_SOURCE_SEL(id, 0) -#define MIPI_SOURCE_SEL(id) VOP_SOURCE_SEL(id, 2) -#define HDMI_SOURCE_SEL(id) VOP_SOURCE_SEL(id, 1) - -#define RGB_DATA_PLANA ((2 << 6) | (3 << (6 + 16))) -#define RGB_DATA_PLANB ((3 << 6) | (3 << (6 + 16))) - -#define RK3366_GRF_IO_VSEL 0x0900 -#define RK3366_GRF_VOP_IOVOL_SEL(x) (((x) << 0) | (1 << (0 + 16))) -#define RK3368_GRF_VOP_IOVOL_SEL(x) (((x) << 5) | (1 << (5 + 16))) - -#define RK3366_WB_ALIGN 16 - -enum lb_mode { - LB_YUV_3840X5 = 0x0, - LB_YUV_2560X8 = 0x1, - LB_RGB_3840X2 = 0x2, - LB_RGB_2560X4 = 0x3, - LB_RGB_1920X5 = 0x4, - LB_RGB_1280X8 = 0x5 -}; - -enum sacle_up_mode { - SCALE_UP_BIL = 0x0, - SCALE_UP_BIC = 0x1 -}; - -enum scale_down_mode { - SCALE_DOWN_BIL = 0x0, - SCALE_DOWN_AVG = 0x1 -}; - -/*ALPHA BLENDING MODE*/ -enum alpha_mode { /* Fs Fd */ - AB_USER_DEFINE = 0x0, - AB_CLEAR = 0x1,/* 0 0*/ - AB_SRC = 0x2,/* 1 0*/ - AB_DST = 0x3,/* 0 1 */ - AB_SRC_OVER = 0x4,/* 1 1-As''*/ - AB_DST_OVER = 0x5,/* 1-Ad'' 1*/ - AB_SRC_IN = 0x6, - AB_DST_IN = 0x7, - AB_SRC_OUT = 0x8, - AB_DST_OUT = 0x9, - AB_SRC_ATOP = 0xa, - AB_DST_ATOP = 0xb, - XOR = 0xc, - AB_SRC_OVER_GLOBAL = 0xd -}; /*alpha_blending_mode*/ - -enum src_alpha_mode { - AA_STRAIGHT = 0x0, - AA_INVERSE = 0x1 -};/*src_alpha_mode*/ - -enum global_alpha_mode { - AA_GLOBAL = 0x0, - AA_PER_PIX = 0x1, - AA_PER_PIX_GLOBAL = 0x2 -};/*src_global_alpha_mode*/ - -enum src_alpha_sel { - AA_SAT = 0x0, - AA_NO_SAT = 0x1 -};/*src_alpha_sel*/ - -enum src_color_mode { - AA_SRC_PRE_MUL = 0x0, - AA_SRC_NO_PRE_MUL = 0x1 -};/*src_color_mode*/ - -enum factor_mode { - AA_ZERO = 0x0, - AA_ONE = 0x1, - AA_SRC = 0x2, - AA_SRC_INVERSE = 0x3, - AA_SRC_GLOBAL = 0x4 -};/*src_factor_mode && dst_factor_mode*/ - -enum _vop_r2y_csc_mode { - VOP_R2Y_CSC_BT601 = 0, - VOP_R2Y_CSC_BT709 -}; - -enum _vop_y2r_csc_mode { - VOP_Y2R_CSC_MPEG = 0, - VOP_Y2R_CSC_JPEG, - VOP_Y2R_CSC_HD, - VOP_Y2R_CSC_BYPASS -}; -enum _vop_format { - VOP_FORMAT_ARGB888 = 0, - VOP_FORMAT_RGB888, - VOP_FORMAT_RGB565, - VOP_FORMAT_YCBCR420 = 4, - VOP_FORMAT_YCBCR422, - VOP_FORMAT_YCBCR444 -}; - -enum _vop_overlay_mode { - VOP_RGB_DOMAIN, - VOP_YUV_DOMAIN -}; - -enum cabc_stage_mode { - LAST_FRAME_PWM_VAL = 0x0, - CUR_FRAME_PWM_VAL = 0x1, - STAGE_BY_STAGE = 0x2 -}; - -struct lcdc_device { - int id; - u32 soc_type; - struct rk_lcdc_driver driver; - struct device *dev; - struct rk_screen *screen; - - void __iomem *regs; - void *regsbak; /*back up reg*/ - u32 reg_phy_base; /* physical basic address of lcdc register*/ - struct regmap *grf_base; - struct regmap *pmugrf_base; - struct regmap *cru_base; - u32 len; /* physical map length of lcdc register*/ - /*one time only one process allowed to config the register*/ - spinlock_t reg_lock; - - int __iomem *dsp_lut_addr_base; - int __iomem *cabc_lut_addr_base; - - - int prop; /*used for primary or extended display device*/ - bool pre_init; - bool pwr18; /*if lcdc use 1.8v power supply*/ - /*if aclk or hclk is closed ,acess to register is not allowed*/ - bool clk_on; - /*active layer counter,when atv_layer_cnt = 0,disable lcdc*/ - u8 atv_layer_cnt; - - - unsigned int irq; - - struct clk *pd; /*lcdc power domain*/ - struct clk *hclk; /*lcdc AHP clk*/ - struct clk *dclk; /*lcdc dclk*/ - struct clk *aclk; /*lcdc share memory frequency*/ - u32 pixclock; - - u32 standby; /*1:standby,0:wrok*/ - u32 iommu_status; - struct backlight_device *backlight; - struct clk *pll_sclk; -}; - -struct alpha_config { - enum src_alpha_mode src_alpha_mode; /*win0_src_alpha_m0*/ - u32 src_global_alpha_val; /*win0_src_global_alpha*/ - enum global_alpha_mode src_global_alpha_mode;/*win0_src_blend_m0*/ - enum src_alpha_sel src_alpha_cal_m0; /*win0_src_alpha_cal_m0*/ - enum src_color_mode src_color_mode; /*win0_src_color_m0*/ - enum factor_mode src_factor_mode; /*win0_src_factor_m0*/ - enum factor_mode dst_factor_mode; /*win0_dst_factor_m0*/ -}; - -struct lcdc_cabc_mode { - u32 pixel_num; /* pixel precent number */ - u16 stage_up; /* up stride */ - u16 stage_down; /* down stride */ - u16 global_su; -}; - -static inline void lcdc_writel(struct lcdc_device *lcdc_dev, u32 offset, u32 v) -{ - u32 *_pv = (u32 *)lcdc_dev->regsbak; - - _pv += (offset >> 2); - *_pv = v; - writel_relaxed(v, lcdc_dev->regs + offset); -} - -static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev, u32 offset) -{ - u32 v; - - v = readl_relaxed(lcdc_dev->regs + offset); - return v; -} - -static inline u32 lcdc_readl_backup(struct lcdc_device *lcdc_dev, u32 offset) -{ - u32 v; - u32 *_pv = (u32 *)lcdc_dev->regsbak; - - _pv += (offset >> 2); - v = readl_relaxed(lcdc_dev->regs + offset); - *_pv = v; - return v; -} - -static inline u32 lcdc_read_bit(struct lcdc_device *lcdc_dev, - u32 offset, u32 msk) -{ - u32 v; - u32 _v = readl_relaxed(lcdc_dev->regs + offset); - - _v &= msk; - v = (_v ? 1 : 0); - return v; -} - -static inline void lcdc_set_bit(struct lcdc_device *lcdc_dev, - u32 offset, u32 msk) -{ - u32 *_pv = (u32 *)lcdc_dev->regsbak; - - _pv += (offset >> 2); - (*_pv) |= msk; - writel_relaxed(*_pv, lcdc_dev->regs + offset); -} - -static inline void lcdc_clr_bit(struct lcdc_device *lcdc_dev, - u32 offset, u32 msk) -{ - u32 *_pv = (u32 *)lcdc_dev->regsbak; - - _pv += (offset >> 2); - (*_pv) &= (~msk); - writel_relaxed(*_pv, lcdc_dev->regs + offset); -} - -static inline void lcdc_msk_reg(struct lcdc_device *lcdc_dev, - u32 offset, u32 msk, u32 v) -{ - u32 *_pv = (u32 *)lcdc_dev->regsbak; - - _pv += (offset >> 2); - (*_pv) &= (~msk); - (*_pv) |= v; - writel_relaxed(*_pv, lcdc_dev->regs + offset); - if (((lcdc_dev->soc_type == VOP_FULL_RK3366) && (offset == INTR_CLEAR_RK3366)) || - ((lcdc_dev->soc_type == VOP_FULL_RK3368) && (offset == INTR_CLEAR_RK3368))) - (*_pv) &= 0; -} - -static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev) -{ - writel_relaxed(0x01, lcdc_dev->regs + REG_CFG_DONE); - dsb(sy); -} - -static inline int lcdc_grf_writel(struct regmap *base, - u32 offset, u32 val) -{ - if (base) - regmap_write(base, offset, val); - dsb(sy); - - return 0; -} - -static inline int lcdc_cru_writel(struct regmap *base, - u32 offset, u32 val) -{ - if (base) - regmap_write(base, offset, val); - dsb(sy); - - return 0; -} - -static inline int lcdc_cru_readl(struct regmap *base, - u32 offset) -{ - u32 v; - regmap_read(base, offset, &v); - - return v; -} - -#define CUBIC_PRECISE 0 -#define CUBIC_SPLINE 1 -#define CUBIC_CATROM 2 -#define CUBIC_MITCHELL 3 - -#define FBDC_FMT_RGB565 0x5 -#define FBDC_FMT_U8U8U8U8 0xc /*ARGB888*/ -#define FBDC_FMT_U8U8U8 0x3a /*RGBP888*/ - -#define CUBIC_MODE_SELETION CUBIC_PRECISE - -/*************************************************************/ -#define SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT 12 /* 4.12*/ -#define SCALE_FACTOR_BILI_DN_FIXPOINT(x) \ - ((INT32)((x) * (1 << SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT))) - -#define SCALE_FACTOR_BILI_UP_FIXPOINT_SHIFT 16 /* 0.16*/ - -#define SCALE_FACTOR_AVRG_FIXPOINT_SHIFT 16 /*0.16*/ -#define SCALE_FACTOR_AVRG_FIXPOINT(x) \ - ((INT32)((x) * (1 << SCALE_FACTOR_AVRG_FIXPOINT_SHIFT))) - -#define SCALE_FACTOR_BIC_FIXPOINT_SHIFT 16 /* 0.16*/ -#define SCALE_FACTOR_BIC_FIXPOINT(x) \ - ((INT32)((x) * (1 << SCALE_FACTOR_BIC_FIXPOINT_SHIFT))) - -#define SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT 12 /*NONE SCALE,vsd_bil*/ -#define SCALE_FACTOR_VSDBIL_FIXPOINT_SHIFT 12 /*VER SCALE DOWN BIL*/ - -/*********************************************************/ - -/*#define GET_SCALE_FACTOR_BILI(src, dst) \ - ((((src) - 1) << SCALE_FACTOR_BILI_FIXPOINT_SHIFT) / ((dst) - 1))*/ -/*#define GET_SCALE_FACTOR_BIC(src, dst) \ - ((((src) - 1) << SCALE_FACTOR_BIC_FIXPOINT_SHIFT) / ((dst) - 1))*/ -/*modified by hpz*/ -#define GET_SCALE_FACTOR_BILI_DN(src, dst) \ - ((((src) * 2 - 3) << (SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT - 1)) \ - / ((dst) - 1)) -#define GET_SCALE_FACTOR_BILI_UP(src, dst) \ - ((((src) * 2 - 3) << (SCALE_FACTOR_BILI_UP_FIXPOINT_SHIFT - 1)) \ - / ((dst) - 1)) -#define GET_SCALE_FACTOR_BIC(src, dst) \ - ((((src) * 2 - 3) << (SCALE_FACTOR_BIC_FIXPOINT_SHIFT - 1)) \ - / ((dst) - 1)) - -/*********************************************************/ -/*NOTE: hardware in order to save resource , srch first to get interlace line -(srch+vscalednmult-1)/vscalednmult; and do scale*/ -#define GET_SCALE_DN_ACT_HEIGHT(srch, vscalednmult) \ - (((srch) + (vscalednmult) - 1) / (vscalednmult)) - -/*#define VSKIP_MORE_PRECISE*/ - -#ifdef VSKIP_MORE_PRECISE -#define MIN_SCALE_FACTOR_AFTER_VSKIP 1.5f -#define GET_SCALE_FACTOR_BILI_DN_VSKIP(srch, dsth, vscalednmult) \ - (GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT((srch),\ - (vscalednmult)), (dsth))) -#else -#define MIN_SCALE_FACTOR_AFTER_VSKIP 1 -#if 0/*rk3288*/ -#define GET_SCALE_FACTOR_BILI_DN_VSKIP(srch, dsth, vscalednmult) \ - ((GET_SCALE_DN_ACT_HEIGHT((srch), (vscalednmult)) == (dsth))\ - ? (GET_SCALE_FACTOR_BILI_DN((srch),\ - (dsth))/(vscalednmult))\ - : GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT((srch),\ - (vscalednmult)), (dsth))) -#else/*rk3368*/ -#define GET_SCALE_FACTOR_BILI_DN_VSKIP(srch, dsth, vscalednmult) \ - ((GET_SCALE_DN_ACT_HEIGHT((srch) , (vscalednmult)) == (dsth)) \ - ? (GET_SCALE_FACTOR_BILI_DN((srch) , (dsth)) / (vscalednmult)) \ - : (GET_SCALE_DN_ACT_HEIGHT((srch) , (vscalednmult)) == ((dsth) * 2)) \ - ? GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT(((srch) - 1),\ - (vscalednmult)) , (dsth)) : \ - GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT((srch),\ - (vscalednmult)) , (dsth))) -#endif - - -#endif -/*****************************************************************/ - - -/*scalefactor must >= dst/src, or pixels at end of line may be unused*/ -/*scalefactor must < dst/(src-1), or dst buffer may overflow*/ -/*avrg old code: ((((dst) << SCALE_FACTOR_AVRG_FIXPOINT_SHIFT))\ - /((src) - 1)) hxx_chgsrc*/ -/*modified by hpz:*/ -#define GET_SCALE_FACTOR_AVRG(src, dst) ((((dst) << \ - (SCALE_FACTOR_AVRG_FIXPOINT_SHIFT + 1))) / (2 * (src) - 1)) - -/*************************************************************************/ -/*Scale Coordinate Accumulate, x.16*/ -#define SCALE_COOR_ACC_FIXPOINT_SHIFT 16 -#define SCALE_COOR_ACC_FIXPOINT_ONE (1 << SCALE_COOR_ACC_FIXPOINT_SHIFT) -#define SCALE_COOR_ACC_FIXPOINT(x) \ - ((INT32)((x)*(1 << SCALE_COOR_ACC_FIXPOINT_SHIFT))) -#define SCALE_COOR_ACC_FIXPOINT_REVERT(x) \ - ((((x) >> (SCALE_COOR_ACC_FIXPOINT_SHIFT - 1)) + 1) >> 1) - -#define SCALE_GET_COOR_ACC_FIXPOINT(scalefactor, factorfixpointshift) \ - ((scalefactor) << \ - (SCALE_COOR_ACC_FIXPOINT_SHIFT - (factorfixpointshift))) - - -/************************************************************************/ -/*CoarsePart of Scale Coordinate Accumulate, used for pixel mult-add factor, 0.8*/ -#define SCALE_FILTER_FACTOR_FIXPOINT_SHIFT 8 -#define SCALE_FILTER_FACTOR_FIXPOINT_ONE \ - (1 << SCALE_FILTER_FACTOR_FIXPOINT_SHIFT) -#define SCALE_FILTER_FACTOR_FIXPOINT(x) \ - ((INT32)((x) * (1 << SCALE_FILTER_FACTOR_FIXPOINT_SHIFT))) -#define SCALE_FILTER_FACTOR_FIXPOINT_REVERT(x) \ - ((((x) >> (SCALE_FILTER_FACTOR_FIXPOINT_SHIFT-1)) + 1) >> 1) - -#define SCALE_GET_FILTER_FACTOR_FIXPOINT(cooraccumulate, \ - cooraccfixpointshift) \ - (((cooraccumulate) >> \ - ((cooraccfixpointshift) - SCALE_FILTER_FACTOR_FIXPOINT_SHIFT)) & \ - (SCALE_FILTER_FACTOR_FIXPOINT_ONE - 1)) - -#define SCALE_OFFSET_FIXPOINT_SHIFT 8 -#define SCALE_OFFSET_FIXPOINT(x) \ - ((INT32)((x) * (1 << SCALE_OFFSET_FIXPOINT_SHIFT))) - - -extern void rk_pwm_set(int bl_pwm_period, int bl_pwm_duty); -extern void rk_pwm_get(int *bl_pwm_period, int *bl_pwm_duty); -#endif diff --git a/drivers/video/rockchip/lcdc/rk_vop_lite.c b/drivers/video/rockchip/lcdc/rk_vop_lite.c deleted file mode 100644 index 7c1521ef64fc..000000000000 --- a/drivers/video/rockchip/lcdc/rk_vop_lite.c +++ /dev/null @@ -1,2643 +0,0 @@ -/* - * rockchip VOP(Video Output Processer) hardware driver. - * - * Copyright (C) 2016 Rockchip Electronics Co., Ltd. - * Author: WenLong Zhuang - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "rk_vop_lite.h" - -static int dbg_thresd; -module_param(dbg_thresd, int, S_IRUGO | S_IWUSR); - -#define DBG(level, x...) do { \ - if (unlikely(dbg_thresd >= level)) \ - pr_info(x);\ - } while (0) - -#define to_vop_dev(drv) container_of(drv, struct vop_device, driver) - -static struct rk_lcdc_win vop_win[] = { - { .name = "win0", .id = 0}, - { .name = "win1", .id = 1}, - { .name = "hwc", .id = 2} -}; - -static int vop_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable); - -static int vop_clk_enable(struct vop_device *vop_dev) -{ - if (!vop_dev->clk_on) { - pm_runtime_get_sync(vop_dev->dev); - - clk_enable(vop_dev->hclk); - clk_enable(vop_dev->aclk); - clk_enable(vop_dev->dclk); - spin_lock(&vop_dev->reg_lock); - vop_dev->clk_on = 1; - spin_unlock(&vop_dev->reg_lock); - } - - return 0; -} - -static int vop_clk_disable(struct vop_device *vop_dev) -{ - if (vop_dev->clk_on) { - spin_lock(&vop_dev->reg_lock); - vop_dev->clk_on = 0; - spin_unlock(&vop_dev->reg_lock); - clk_disable(vop_dev->dclk); - clk_disable(vop_dev->aclk); - clk_disable(vop_dev->hclk); - - pm_runtime_put(vop_dev->dev); - } - - return 0; -} - -static int vop_irq_enable(struct vop_device *vop_dev) -{ - u64 val; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - vop_mask_writel(vop_dev, INTR_CLEAR, INTR_MASK, INTR_MASK); - - val = INTR_FS0 | INTR_FS1 | INTR_LINE_FLAG0 | INTR_LINE_FLAG1 | - INTR_BUS_ERROR | INTR_WIN0_EMPTY | INTR_WIN1_EMPTY | - INTR_DSP_HOLD_VALID; - vop_mask_writel(vop_dev, INTR_EN, INTR_MASK, val); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_irq_disable(struct vop_device *vop_dev) -{ - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - vop_writel(vop_dev, INTR_EN, 0xffff0000); - vop_writel(vop_dev, INTR_CLEAR, 0xffffffff); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_standby_enable(struct vop_device *vop_dev) -{ - u64 val; - int ret; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - vop_dev->sync.stdbyfin.done = 0; - - vop_msk_reg(vop_dev, DSP_CTRL2, V_DSP_BLANK_EN(1)); - /*vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, INTR_MASK);*/ - val = V_IMD_VOP_STANDBY_EN(1) | V_IMD_VOP_DMA_STOP(1) | - V_IMD_DSP_OUT_ZERO(1); - vop_msk_reg(vop_dev, SYS_CTRL2, val); - vop_cfg_done(vop_dev); - spin_unlock(&vop_dev->reg_lock); - - /* wait for standby hold valid */ - ret = vop_completion_timeout_ms(&vop_dev->sync.stdbyfin, - vop_dev->sync.stdbyfin_to); - if (!ret) { - dev_err(vop_dev->dev, - "wait standby hold valid timeout %dms\n", - vop_dev->sync.stdbyfin_to); - return -ETIMEDOUT; - } - } else { - spin_unlock(&vop_dev->reg_lock); - } - - return 0; -} - -static int vop_standby_disable(struct vop_device *vop_dev) -{ - u64 val; - int ret; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - vop_dev->sync.frmst.done = 0; - val = V_IMD_VOP_STANDBY_EN(0) | V_IMD_VOP_DMA_STOP(0) | - V_IMD_DSP_OUT_ZERO(0); - vop_msk_reg(vop_dev, SYS_CTRL2, val); - vop_msk_reg(vop_dev, DSP_CTRL2, V_DSP_BLANK_EN(0)); - vop_cfg_done(vop_dev); - spin_unlock(&vop_dev->reg_lock); - - /* win address maybe effect after next frame start, - * but mmu maybe effect right now, so need wait frame start - */ - ret = vop_completion_timeout_ms(&vop_dev->sync.frmst, - vop_dev->sync.frmst_to); - if (!ret) { - dev_err(vop_dev->dev, "wait frame start timeout %dms\n", - vop_dev->sync.frmst_to); - return -ETIMEDOUT; - } - } else { - spin_unlock(&vop_dev->reg_lock); - } - - return 0; -} - -static int vop_mmu_enable(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - if (!dev_drv->iommu_enabled || !dev_drv->mmu_dev) { - pr_debug("%s: VOP iommu is disabled or not find mmu dev\n", - __func__); - return -ENODEV; - } - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - if (!vop_dev->iommu_status) { - vop_dev->iommu_status = 1; - rockchip_iovmm_activate(dev_drv->dev); - } - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_mmu_disable(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - if (!dev_drv->iommu_enabled || !dev_drv->mmu_dev) { - pr_debug("%s: VOP iommu is disabled or not find mmu dev\n", - __func__); - return -ENODEV; - } - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - if (vop_dev->iommu_status) { - vop_dev->iommu_status = 0; - rockchip_iovmm_deactivate(dev_drv->dev); - } - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_reg_dump(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - int *cbase = (int *)vop_dev->regs; - int *regsbak = (int *)vop_dev->regsbak; - int i, j, val; - char dbg_message[30]; - char buf[10]; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - pr_info("vop back up reg:\n"); - memset(dbg_message, 0, sizeof(dbg_message)); - memset(buf, 0, sizeof(buf)); - for (i = 0; i <= (0x200 >> 4); i++) { - val = sprintf(dbg_message, "0x%04x: ", i * 16); - for (j = 0; j < 4; j++) { - val = sprintf(buf, "%08x ", - *(regsbak + i * 4 + j)); - strcat(dbg_message, buf); - } - pr_info("%s\n", dbg_message); - memset(dbg_message, 0, sizeof(dbg_message)); - memset(buf, 0, sizeof(buf)); - } - - pr_info("vop reg:\n"); - for (i = 0; i <= (0x200 >> 4); i++) { - val = sprintf(dbg_message, "0x%04x: ", i * 16); - for (j = 0; j < 4; j++) { - sprintf(buf, "%08x ", - readl_relaxed(cbase + i * 4 + j)); - strcat(dbg_message, buf); - } - pr_info("%s\n", dbg_message); - memset(dbg_message, 0, sizeof(dbg_message)); - memset(buf, 0, sizeof(buf)); - } - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -#define WIN_EN(id) \ -static int win##id##_enable(struct vop_device *vop_dev, int en) \ -{ \ - spin_lock(&vop_dev->reg_lock); \ - vop_msk_reg(vop_dev, WIN##id##_CTRL0, V_WIN##id##_EN((u64)en)); \ - vop_cfg_done(vop_dev); \ - spin_unlock(&vop_dev->reg_lock); \ - return 0; \ -} - -WIN_EN(0); -WIN_EN(1); - -/* - * enable/disable win directly - */ -static int vop_win_direct_en(struct rk_lcdc_driver *drv, - int win_id, int en) -{ - struct vop_device *vop_dev = to_vop_dev(drv); - - if (win_id == 0) - win0_enable(vop_dev, en); - else if (win_id == 1) - win1_enable(vop_dev, en); - else - dev_err(vop_dev->dev, "invalid win number:%d\n", win_id); - return 0; -} - -#define SET_WIN_ADDR(id) \ -static int set_win##id##_addr(struct vop_device *vop_dev, u32 addr) \ -{ \ - spin_lock(&vop_dev->reg_lock); \ - vop_writel(vop_dev, WIN##id##_YRGB_MST, addr); \ - vop_msk_reg(vop_dev, WIN##id##_CTRL0, V_WIN##id##_EN(1)); \ - vop_cfg_done(vop_dev); \ - spin_unlock(&vop_dev->reg_lock); \ - return 0; \ -} - -SET_WIN_ADDR(0); -SET_WIN_ADDR(1); - -static int vop_direct_set_win_addr(struct rk_lcdc_driver *dev_drv, - int win_id, u32 addr) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - if (win_id == 0) - set_win0_addr(vop_dev, addr); - else - set_win1_addr(vop_dev, addr); - - return 0; -} - -static void vop_read_reg_default_cfg(struct vop_device *vop_dev) -{ - int reg = 0; - u32 val = 0; - struct rk_screen *screen = vop_dev->driver.cur_screen; - u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin; - u32 V_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin; - u32 st_x, st_y; - struct rk_lcdc_win *win0 = vop_dev->driver.win[0]; - - spin_lock(&vop_dev->reg_lock); - for (reg = 0; reg < vop_dev->len; reg += 4) { - val = vop_readl_backup(vop_dev, reg); - switch (reg) { - case WIN0_ACT_INFO: - win0->area[0].xact = (val & MASK(WIN0_ACT_WIDTH)) + 1; - win0->area[0].yact = - ((val & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1; - break; - case WIN0_DSP_INFO: - win0->area[0].xsize = (val & MASK(WIN0_DSP_WIDTH)) + 1; - win0->area[0].ysize = - ((val & MASK(WIN0_DSP_HEIGHT)) >> 16) + 1; - break; - case WIN0_DSP_ST: - st_x = val & MASK(WIN0_DSP_XST); - st_y = (val & MASK(WIN0_DSP_YST)) >> 16; - win0->area[0].xpos = st_x - h_pw_bp; - win0->area[0].ypos = st_y - V_pw_bp; - break; - case WIN0_CTRL0: - win0->state = val & MASK(WIN0_EN); - win0->area[0].fmt_cfg = - (val & MASK(WIN0_DATA_FMT)) >> 1; - win0->area[0].format = win0->area[0].fmt_cfg; - break; - case WIN0_VIR: - win0->area[0].y_vir_stride = - val & MASK(WIN0_YRGB_VIR_STRIDE); - win0->area[0].uv_vir_stride = - (val & MASK(WIN0_CBR_VIR_STRIDE)) >> 16; - if (win0->area[0].format == ARGB888) - win0->area[0].xvir = win0->area[0].y_vir_stride; - else if (win0->area[0].format == RGB888) - win0->area[0].xvir = - win0->area[0].y_vir_stride * 4 / 3; - else if ((win0->area[0].format == RGB565) || - (win0->area[0].format == BGR565)) - win0->area[0].xvir = - 2 * win0->area[0].y_vir_stride; - else - win0->area[0].xvir = - 4 * win0->area[0].y_vir_stride; - break; - case WIN0_YRGB_MST: - win0->area[0].smem_start = val; - break; - case WIN0_CBR_MST: - win0->area[0].cbr_start = val; - break; - default: - break; - } - } - spin_unlock(&vop_dev->reg_lock); -} - -static int vop_pre_init(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - if (vop_dev->pre_init) - return 0; - - if (dev_drv->iommu_enabled) { - dev_drv->mmu_dev = rk_fb_get_sysmmu_device_by_compatible( - dev_drv->mmu_dts_name); - if (dev_drv->mmu_dev) - rk_fb_platform_set_sysmmu( - dev_drv->mmu_dev, dev_drv->dev); - else - dev_err(dev_drv->dev, "fail get rk iommu device\n"); - } - - if (!support_uboot_display()) - rk_disp_pwr_enable(dev_drv); - - vop_clk_enable(vop_dev); - - /* backup reg config at uboot */ - vop_read_reg_default_cfg(vop_dev); - - /* vop io voltage select-->0: 3.3v; 1: 1.8v */ - if (vop_dev->pwr18 == 1) - vop_grf_writel(vop_dev->grf_base, GRF_IO_VSEL, - V_VOP_IOVOL_SEL(1)); - else - vop_grf_writel(vop_dev->grf_base, GRF_IO_VSEL, - V_VOP_IOVOL_SEL(0)); - - vop_msk_reg(vop_dev, SYS_CTRL1, V_SW_AXI_MAX_OUTSTAND_EN(1) | - V_SW_AXI_MAX_OUTSTAND_NUM(31)); - vop_msk_reg(vop_dev, SYS_CTRL2, V_IMD_AUTO_GATING_EN(0)); - vop_cfg_done(vop_dev); - vop_dev->pre_init = true; - - return 0; -} - -static void vop_deinit(struct vop_device *vop_dev) -{ - struct rk_lcdc_driver *dev_drv = &vop_dev->driver; - - vop_standby_enable(vop_dev); - vop_irq_disable(vop_dev); - vop_mmu_disable(dev_drv); - vop_clk_disable(vop_dev); - clk_unprepare(vop_dev->dclk); - clk_unprepare(vop_dev->aclk); - clk_unprepare(vop_dev->hclk); - pm_runtime_disable(vop_dev->dev); -} - -static void __maybe_unused -vop_win_csc_mode(struct vop_device *vop_dev, struct rk_lcdc_win *win, - int csc_mode) -{ - u64 val; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - if (win->id == 0) { - val = V_WIN0_CSC_MODE(csc_mode); - vop_msk_reg(vop_dev, WIN0_CTRL0, val); - } else if (win->id == 1) { - val = V_WIN1_CSC_MODE(csc_mode); - vop_msk_reg(vop_dev, WIN1_CTRL0, val); - } else { - dev_err(vop_dev->dev, "%s win%d unsupport csc mode", - __func__, win->id); - } - } - spin_unlock(&vop_dev->reg_lock); -} - -static int vop_clr_key_cfg(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct rk_lcdc_win *win; - int i; - - for (i = 0; i < dev_drv->lcdc_win_num; i++) { - win = dev_drv->win[i]; - switch (i) { - case 0: - vop_writel(vop_dev, WIN0_COLOR_KEY, win->color_key_val); - break; - case 1: - vop_writel(vop_dev, WIN1_COLOR_KEY, win->color_key_val); - break; - default: - pr_info("%s:un support win num:%d\n", - __func__, i); - break; - } - } - return 0; -} - -static int vop_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - u64 val; - int ppixel_alpha = 0; - int alpha_en = win->alpha_en; - int i; - - if (!alpha_en) { - if (win_id == 0) { - val = V_WIN0_ALPHA_EN(0); - vop_msk_reg(vop_dev, WIN0_ALPHA_CTRL, val); - } else { - val = V_WIN1_ALPHA_EN(0); - vop_msk_reg(vop_dev, WIN1_ALPHA_CTRL, val); - } - return 0; - } - - ppixel_alpha = ((win->area[0].format == ARGB888) || - (win->area[0].format == ABGR888)) ? 1 : 0; - - for (i = 0; i < dev_drv->lcdc_win_num; i++) { - if (!dev_drv->win[i]->state) - continue; - if (win->z_order > dev_drv->win[i]->z_order) - break; - } - - /* - * The bottom layer not support ppixel_alpha mode. - */ - if (i == dev_drv->lcdc_win_num) { - ppixel_alpha = 0; - alpha_en = 0; - } - - if (win_id == 0) { - val = V_WIN0_ALPHA_EN(alpha_en) | - V_WIN0_ALPHA_MODE(ppixel_alpha) | - V_WIN0_ALPHA_PRE_MUL(ppixel_alpha) | - V_WIN0_ALPHA_SAT_MODE(0); - vop_msk_reg(vop_dev, WIN0_ALPHA_CTRL, val); - } else if (win_id == 1) { - val = V_WIN1_ALPHA_EN(alpha_en) | - V_WIN1_ALPHA_MODE(ppixel_alpha) | - V_WIN1_ALPHA_PRE_MUL(ppixel_alpha) | - V_WIN1_ALPHA_SAT_MODE(0); - vop_msk_reg(vop_dev, WIN1_ALPHA_CTRL, val); - } else { - dev_err(vop_dev->dev, "%s: invalid win id=%d or unsupport\n", - __func__, win_id); - } - - return 0; -} - -static int vop_axi_gather_cfg(struct vop_device *vop_dev, - struct rk_lcdc_win *win) -{ - u64 val; - u16 yrgb_gather_num = 3; - u16 cbcr_gather_num = 1; - - switch (win->area[0].format) { - case ARGB888: - case XBGR888: - case ABGR888: - case XRGB888: - yrgb_gather_num = 3; - break; - case RGB888: - case RGB565: - case BGR888: - case BGR565: - yrgb_gather_num = 2; - break; - case YUV444: - case YUV422: - case YUV420: - case YUV420_A: - case YUV422_A: - case YUV444_A: - case YUV420_NV21: - yrgb_gather_num = 1; - cbcr_gather_num = 2; - break; - default: - dev_err(vop_dev->driver.dev, "%s:un supported format[%d]\n", - __func__, win->area[0].format); - return -EINVAL; - } - - if (win->id == 0) { - val = V_WIN0_YRGB_AXI_GATHER_EN(1) | - V_WIN0_CBR_AXI_GATHER_EN(1) | - V_WIN0_YRGB_AXI_GATHER_NUM(yrgb_gather_num) | - V_WIN0_CBR_AXI_GATHER_NUM(cbcr_gather_num); - vop_msk_reg(vop_dev, WIN0_CTRL1, val); - } else if (win->id == 1) { - val = V_WIN1_AXI_GATHER_EN(1) | - V_WIN1_AXI_GATHER_NUM(yrgb_gather_num); - vop_msk_reg(vop_dev, WIN1_CTRL1, val); - } - return 0; -} - -static int vop_win0_reg_update(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - u64 val; - - if (win->state == 1) { - vop_axi_gather_cfg(vop_dev, win); - val = V_WIN0_EN(win->state) | - V_WIN0_DATA_FMT(win->area[0].fmt_cfg) | - V_WIN0_RB_SWAP(win->area[0].swap_rb) | - V_WIN0_UV_SWAP(win->area[0].swap_uv); - if (dev_drv->cur_screen->mode.vmode & FB_VMODE_INTERLACED) - val |= V_WIN0_INTERLACE_READ(1); - else - val |= V_WIN0_INTERLACE_READ(0); - vop_msk_reg(vop_dev, WIN0_CTRL0, val); - - val = V_WIN0_YRGB_VIR_STRIDE(win->area[0].y_vir_stride) | - V_WIN0_CBR_VIR_STRIDE(win->area[0].uv_vir_stride); - vop_writel(vop_dev, WIN0_VIR, val); - - val = V_WIN0_DSP_WIDTH(win->area[0].xsize - 1) | - V_WIN0_DSP_HEIGHT(win->area[0].ysize - 1); - vop_writel(vop_dev, WIN0_DSP_INFO, val); - - val = V_WIN0_DSP_XST(win->area[0].dsp_stx) | - V_WIN0_DSP_YST(win->area[0].dsp_sty); - vop_writel(vop_dev, WIN0_DSP_ST, val); - - /* only win0 support scale and yuv */ - val = V_WIN0_ACT_WIDTH(win->area[0].xact - 1) | - V_WIN0_ACT_HEIGHT(win->area[0].yact - 1); - vop_writel(vop_dev, WIN0_ACT_INFO, val); - - val = V_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) | - V_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y); - vop_writel(vop_dev, WIN0_SCL_FACTOR_YRGB, val); - - val = V_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) | - V_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y); - vop_writel(vop_dev, WIN0_SCL_FACTOR_CBR, val); - - if (win->area[0].y_addr > 0) - vop_writel(vop_dev, WIN0_YRGB_MST, win->area[0].y_addr); - if (win->area[0].uv_addr > 0) - vop_writel(vop_dev, WIN0_CBR_MST, win->area[0].uv_addr); - - vop_alpha_cfg(dev_drv, win_id); - } else { - val = V_WIN0_EN(win->state); - vop_msk_reg(vop_dev, WIN0_CTRL0, val); - } - - return 0; -} - -static int vop_win1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - u64 val; - - if (win->state == 1) { - vop_axi_gather_cfg(vop_dev, win); - val = V_WIN1_EN(win->state) | - V_WIN1_DATA_FMT(win->area[0].fmt_cfg) | - V_WIN1_RB_SWAP(win->area[0].swap_rb); - if (dev_drv->cur_screen->mode.vmode & FB_VMODE_INTERLACED) - val |= V_WIN1_INTERLACE_READ(1); - vop_msk_reg(vop_dev, WIN1_CTRL0, val); - - val = V_WIN1_VIR_STRIDE(win->area[0].y_vir_stride); - vop_writel(vop_dev, WIN1_VIR, val); - - val = V_WIN1_DSP_WIDTH(win->area[0].xsize - 1) | - V_WIN1_DSP_HEIGHT(win->area[0].ysize - 1); - vop_writel(vop_dev, WIN1_DSP_INFO, val); - - val = V_WIN1_DSP_XST(win->area[0].dsp_stx) | - V_WIN1_DSP_YST(win->area[0].dsp_sty); - vop_writel(vop_dev, WIN1_DSP_ST, val); - - if (win->area[0].y_addr > 0) - vop_writel(vop_dev, WIN1_YRGB_MST, win->area[0].y_addr); - - vop_alpha_cfg(dev_drv, win_id); - } else { - val = V_WIN1_EN(win->state); - vop_msk_reg(vop_dev, WIN1_CTRL0, val); - } - - return 0; -} - -static int vop_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - unsigned int hwc_size = 0; - u64 val; - - if (win->state == 1) { - vop_axi_gather_cfg(vop_dev, win); - - if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32)) - hwc_size = 0; - else if ((win->area[0].xsize == 64) && - (win->area[0].ysize == 64)) - hwc_size = 1; - else - dev_err(vop_dev->dev, "unsupported hwc size[%dx%d]!\n", - win->area[0].xsize, win->area[0].ysize); - - val = V_HWC_EN(1) | V_HWC_SIZE(hwc_size); - vop_msk_reg(vop_dev, HWC_CTRL0, val); - - val = V_HWC_DSP_XST(win->area[0].dsp_stx) | - V_HWC_DSP_YST(win->area[0].dsp_sty); - vop_msk_reg(vop_dev, HWC_DSP_ST, val); - - if (win->area[0].y_addr > 0) - vop_writel(vop_dev, HWC_MST, win->area[0].y_addr); - } else { - val = V_HWC_EN(win->state); - vop_msk_reg(vop_dev, HWC_CTRL0, val); - } - - return 0; -} - -static int vop_layer_update_regs(struct vop_device *vop_dev, - struct rk_lcdc_win *win) -{ - struct rk_lcdc_driver *dev_drv = &vop_dev->driver; - - vop_msk_reg(vop_dev, SYS_CTRL2, - V_IMD_VOP_STANDBY_EN(vop_dev->standby)); - if (win->id == 0) - vop_win0_reg_update(dev_drv, win->id); - else if (win->id == 1) - vop_win1_reg_update(dev_drv, win->id); - else if (win->id == 2) - vop_hwc_reg_update(dev_drv, win->id); - vop_cfg_done(vop_dev); - - DBG(2, "%s for vop%d\n", __func__, vop_dev->id); - return 0; -} - -static int vop_set_hwc_lut(struct rk_lcdc_driver *dev_drv, - int *hwc_lut, int mode) -{ - int i = 0; - int __iomem *c; - int v; - int len = 256 * sizeof(u32); - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - if (!dev_drv->hwc_lut) - dev_drv->hwc_lut = devm_kzalloc(vop_dev->dev, len, GFP_KERNEL); - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - vop_msk_reg(vop_dev, HWC_CTRL0, V_HWC_LUT_EN(0)); - vop_cfg_done(vop_dev); - mdelay(25); - for (i = 0; i < 256; i++) { - if (mode == 1) - dev_drv->hwc_lut[i] = hwc_lut[i]; - - v = dev_drv->hwc_lut[i]; - c = vop_dev->hwc_lut_addr_base + (i << 2); - writel_relaxed(v, c); - } - vop_msk_reg(vop_dev, HWC_CTRL0, V_HWC_LUT_EN(1)); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut) -{ - int i = 0; - int __iomem *c; - int v; - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - if (!dsp_lut) - return 0; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - vop_msk_reg(vop_dev, DSP_CTRL2, V_DSP_LUT_EN(0)); - vop_cfg_done(vop_dev); - mdelay(25); - for (i = 0; i < 256; i++) { - v = dsp_lut[i]; - c = vop_dev->dsp_lut_addr_base + (i << 2); - writel_relaxed(v, c); - } - vop_msk_reg(vop_dev, DSP_CTRL2, V_DSP_LUT_EN(1)); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate) -{ - int ret = 0, fps = 0; - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct rk_screen *screen = dev_drv->cur_screen; - - if (reset_rate) - ret = clk_set_rate(vop_dev->dclk, screen->mode.pixclock); - if (ret) - dev_err(dev_drv->dev, "set lcdc%d dclk[%d] failed\n", - vop_dev->id, screen->mode.pixclock); - vop_dev->pixclock = - div_u64(1000000000000llu, clk_get_rate(vop_dev->dclk)); - vop_dev->driver.pixclock = vop_dev->pixclock; - - fps = rk_fb_calc_fps(screen, vop_dev->pixclock); - screen->ft = 1000 / fps; - dev_info(vop_dev->dev, "%s: dclk:%lu>>fps:%d ", - vop_dev->driver.name, clk_get_rate(vop_dev->dclk), fps); - return 0; -} - -static int vop_config_timing(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct rk_screen *screen = dev_drv->cur_screen; - u16 hsync_len = screen->mode.hsync_len; - u16 left_margin = screen->mode.left_margin; - u16 right_margin = screen->mode.right_margin; - u16 vsync_len = screen->mode.vsync_len; - u16 upper_margin = screen->mode.upper_margin; - u16 lower_margin = screen->mode.lower_margin; - u16 x_res = screen->mode.xres; - u16 y_res = screen->mode.yres; - u64 val; - u16 h_total, v_total; - u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1; - - /* config timing reg valid immediately or after frame start */ - if (screen->mode.vmode & FB_VMODE_INTERLACED) /* after frame start */ - vop_msk_reg(vop_dev, SYS_CTRL2, V_IMD_DSP_TIMING_IMD(1)); - else /* timing reg valid immediately */ - vop_msk_reg(vop_dev, SYS_CTRL2, V_IMD_DSP_TIMING_IMD(0)); - - h_total = hsync_len + left_margin + x_res + right_margin; - v_total = vsync_len + upper_margin + y_res + lower_margin; - - val = V_DSP_HS_END(hsync_len) | V_DSP_HTOTAL(h_total); - vop_msk_reg(vop_dev, DSP_HTOTAL_HS_END, val); - - val = V_DSP_HACT_END(hsync_len + left_margin + x_res) | - V_DSP_HACT_ST(hsync_len + left_margin); - vop_msk_reg(vop_dev, DSP_HACT_ST_END, val); - - if (screen->mode.vmode & FB_VMODE_INTERLACED) { - /* First Field Timing */ - val = V_DSP_VS_END(vsync_len) | - V_DSP_VTOTAL(2 * (vsync_len + upper_margin + - lower_margin) + y_res + 1); - vop_msk_reg(vop_dev, DSP_VTOTAL_VS_END, val); - - val = V_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) | - V_DSP_VACT_ST(vsync_len + upper_margin); - vop_msk_reg(vop_dev, DSP_VACT_ST_END, val); - - /* Second Field Timing */ - vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin; - vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 + - lower_margin; - val = V_DSP_VS_ST_F1(vs_st_f1) | V_DSP_VS_END_F1(vs_end_f1); - vop_msk_reg(vop_dev, DSP_VS_ST_END_F1, val); - - vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res + - lower_margin + 1; - vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 + - lower_margin + 1; - val = V_DSP_VACT_END_F1(vact_end_f1) | - V_DSP_VACT_ST_F1(vact_st_f1); - vop_msk_reg(vop_dev, DSP_VACT_ST_END_F1, val); - - val = V_DSP_LINE_FLAG0_NUM(lower_margin ? - vact_end_f1 : vact_end_f1 - 1); - - val |= V_DSP_LINE_FLAG1_NUM(lower_margin ? - vact_end_f1 : vact_end_f1 - 1); - vop_msk_reg(vop_dev, LINE_FLAG, val); - } else { - val = V_DSP_VS_END(vsync_len) | V_DSP_VTOTAL(v_total); - vop_msk_reg(vop_dev, DSP_VTOTAL_VS_END, val); - - val = V_DSP_VACT_END(vsync_len + upper_margin + y_res) | - V_DSP_VACT_ST(vsync_len + upper_margin); - vop_msk_reg(vop_dev, DSP_VACT_ST_END, val); - - val = V_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res) | - V_DSP_LINE_FLAG1_NUM(vsync_len + upper_margin + y_res); - vop_msk_reg(vop_dev, LINE_FLAG, val); - } - - return 0; -} - -static int vop_config_source(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct rk_screen *screen = dev_drv->cur_screen; - u64 val = 0; - - switch (screen->type) { - case SCREEN_RGB: - vop_grf_writel(vop_dev->grf_base, GRF_SOC_CON5, - V_RGB_VOP_SEL(dev_drv->id)); - val = V_RGB_DCLK_EN(1) | V_RGB_DCLK_POL(screen->pin_dclk) | - V_RGB_HSYNC_POL(screen->pin_hsync) | - V_RGB_VSYNC_POL(screen->pin_vsync) | - V_RGB_DEN_POL(screen->pin_den); - break; - case SCREEN_HDMI: - vop_grf_writel(vop_dev->grf_base, GRF_SOC_CON0, - V_HDMI_VOP_SEL(dev_drv->id)); - val = V_HDMI_DCLK_EN(1) | V_HDMI_DCLK_POL(screen->pin_dclk) | - V_HDMI_HSYNC_POL(screen->pin_hsync) | - V_HDMI_VSYNC_POL(screen->pin_vsync) | - V_HDMI_DEN_POL(screen->pin_den); - break; - case SCREEN_LVDS: - vop_grf_writel(vop_dev->grf_base, GRF_SOC_CON0, - V_LVDS_VOP_SEL(dev_drv->id)); - val = V_LVDS_DCLK_EN(1) | V_LVDS_DCLK_POL(screen->pin_dclk) | - V_LVDS_HSYNC_POL(screen->pin_hsync) | - V_LVDS_VSYNC_POL(screen->pin_vsync) | - V_LVDS_DEN_POL(screen->pin_den); - break; - case SCREEN_MIPI: - vop_grf_writel(vop_dev->grf_base, GRF_SOC_CON0, - V_DSI0_VOP_SEL(dev_drv->id)); - val = V_MIPI_DCLK_EN(1) | V_MIPI_DCLK_POL(screen->pin_dclk) | - V_MIPI_HSYNC_POL(screen->pin_hsync) | - V_MIPI_VSYNC_POL(screen->pin_vsync) | - V_MIPI_DEN_POL(screen->pin_den); - break; - default: - dev_err(vop_dev->dev, "un supported interface[%d]!\n", - screen->type); - break; - } - - val |= V_SW_CORE_CLK_SEL(!!screen->pixelrepeat); - if (screen->mode.vmode & FB_VMODE_INTERLACED) - val |= V_SW_HDMI_CLK_I_SEL(1); - else - val |= V_SW_HDMI_CLK_I_SEL(0); - vop_msk_reg(vop_dev, DSP_CTRL0, val); - - return 0; -} - -static int vop_config_interface(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct rk_screen *screen = dev_drv->cur_screen; - u64 val = 0; - - /* FRC dither down init */ - if (screen->face != OUT_P888) { - vop_writel(vop_dev, FRC_LOWER01_0, 0x12844821); - vop_writel(vop_dev, FRC_LOWER01_1, 0x21488412); - vop_writel(vop_dev, FRC_LOWER10_0, 0xa55a9696); - vop_writel(vop_dev, FRC_LOWER10_1, 0x5aa56969); - vop_writel(vop_dev, FRC_LOWER11_0, 0xdeb77deb); - vop_writel(vop_dev, FRC_LOWER11_1, 0xed7bb7de); - } - - switch (screen->face) { - case OUT_P888: - val = V_DSP_OUT_MODE(OUT_P888) | V_DITHER_DOWN(0); - break; - case OUT_P565: - val = V_DSP_OUT_MODE(OUT_P565) | V_DITHER_DOWN(1) | - V_DITHER_DOWN_MODE(DITHER_888_565) | - V_DITHER_DOWN_SEL(DITHER_SEL_FRC); - break; - case OUT_P666: - val = V_DSP_OUT_MODE(OUT_P666) | V_DITHER_DOWN(1) | - V_DITHER_DOWN_MODE(DITHER_888_666) | - V_DITHER_DOWN_SEL(DITHER_SEL_FRC); - break; - case OUT_D888_P565: - val = V_DSP_OUT_MODE(OUT_P888) | V_DITHER_DOWN(1) | - V_DITHER_DOWN_MODE(DITHER_888_565) | - V_DITHER_DOWN_SEL(DITHER_SEL_FRC); - break; - case OUT_D888_P666: - val = V_DSP_OUT_MODE(OUT_P888) | V_DITHER_DOWN(1) | - V_DITHER_DOWN_MODE(DITHER_888_666) | - V_DITHER_DOWN_SEL(DITHER_SEL_FRC); - break; - default: - dev_err(vop_dev->dev, "un supported screen face[%d]!\n", - screen->face); - break; - } - - if (screen->mode.vmode & FB_VMODE_INTERLACED) - val |= V_DSP_INTERLACE(1) | V_INTERLACE_FIELD_POL(0); - else - val |= V_DSP_INTERLACE(0) | V_INTERLACE_FIELD_POL(0); - - dev_drv->output_color = screen->color_mode; - if (screen->color_mode == COLOR_RGB) - dev_drv->overlay_mode = VOP_RGB_DOMAIN; - else - dev_drv->overlay_mode = VOP_YUV_DOMAIN; - - val |= V_SW_OVERLAY_MODE(dev_drv->overlay_mode) | - V_DSP_BG_SWAP(screen->swap_gb) | - V_DSP_RB_SWAP(screen->swap_rb) | - V_DSP_RG_SWAP(screen->swap_rg) | - V_DSP_DELTA_SWAP(screen->swap_delta) | - V_DSP_DUMMY_SWAP(screen->swap_dumy) | - V_DSP_BLANK_EN(0) | V_DSP_BLACK_EN(0); - vop_msk_reg(vop_dev, DSP_CTRL2, val); - - return 0; -} - -static void vop_config_background(struct rk_lcdc_driver *dev_drv, int rgb) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - u64 val; - int b = rgb & 0xff; - int g = (rgb >> 8) & 0xff; - int r = (rgb >> 16) & 0xff; - - val = V_DSP_BG_BLUE(b) | V_DSP_BG_GREEN(g) | V_DSP_BG_RED(r); - vop_msk_reg(vop_dev, DSP_BG, val); -} - -static void vop_bcsh_path_sel(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) { - if (IS_YUV_COLOR(dev_drv->output_color)) /* bypass */ - vop_msk_reg(vop_dev, BCSH_CTRL, - V_SW_BCSH_Y2R_EN(0) | V_SW_BCSH_R2Y_EN(0)); - else /* YUV2RGB */ - vop_msk_reg(vop_dev, BCSH_CTRL, V_SW_BCSH_Y2R_EN(1) | - V_SW_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) | - V_SW_BCSH_R2Y_EN(0)); - } else { - /* overlay_mode=VOP_RGB_DOMAIN */ - /* bypass --need check,if bcsh close? */ - if (dev_drv->output_color == COLOR_RGB) { - if (dev_drv->bcsh.enable == 1) - vop_msk_reg(vop_dev, BCSH_CTRL, - V_SW_BCSH_R2Y_EN(1) | - V_SW_BCSH_Y2R_EN(1)); - else - vop_msk_reg(vop_dev, BCSH_CTRL, - V_SW_BCSH_R2Y_EN(0) | - V_SW_BCSH_Y2R_EN(0)); - } else { - /* RGB2YUV */ - vop_msk_reg(vop_dev, BCSH_CTRL, - V_SW_BCSH_R2Y_EN(1) | - V_SW_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) | - V_SW_BCSH_Y2R_EN(0)); - } - } -} - -static int vop_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact, - u16 *yact, int *format, u32 *dsp_addr, - int *ymirror) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - u32 val; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - val = vop_readl(vop_dev, WIN0_ACT_INFO); - *xact = (val & MASK(WIN0_ACT_WIDTH)) + 1; - *yact = ((val & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1; - - val = vop_readl(vop_dev, WIN0_CTRL0); - *format = (val & MASK(WIN0_DATA_FMT)) >> 1; - *dsp_addr = vop_readl(vop_dev, WIN0_YRGB_MST); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst, - int format, u16 xact, u16 yact, u16 xvir, - int ymirror) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - int swap = (format == RGB888) ? 1 : 0; - u64 val; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - val = V_WIN0_DATA_FMT(format) | V_WIN0_RB_SWAP(swap); - vop_msk_reg(vop_dev, WIN0_CTRL0, val); - - vop_msk_reg(vop_dev, WIN0_VIR, V_WIN0_YRGB_VIR_STRIDE(xvir)); - vop_writel(vop_dev, WIN0_ACT_INFO, V_WIN0_ACT_WIDTH(xact - 1) | - V_WIN0_ACT_HEIGHT(yact - 1)); - - vop_writel(vop_dev, WIN0_YRGB_MST, rgb_mst); - - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static void vop_reg_restore(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - int len = FLAG_REG; - - spin_lock(&vop_dev->reg_lock); - - if (likely(vop_dev->clk_on)) - memcpy(vop_dev->regs, vop_dev->regsbak, len); - - spin_unlock(&vop_dev->reg_lock); - - /* set screen GAMMA lut */ - if (dev_drv->cur_screen && dev_drv->cur_screen->dsp_lut) - vop_set_lut(dev_drv, dev_drv->cur_screen->dsp_lut); - - /* set hwc lut */ - vop_set_hwc_lut(dev_drv, dev_drv->hwc_lut, 0); -} - -static int vop_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct rk_screen *screen = dev_drv->cur_screen; - - /*if (!vop_dev->standby && initscreen && (dev_drv->first_frame != 1))*/ - /* flush_kthread_worker(&dev_drv->update_regs_worker);*/ - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - vop_config_interface(dev_drv); - vop_config_source(dev_drv); - vop_config_timing(dev_drv); - if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) - vop_config_background(dev_drv, 0x801080); - else - vop_config_background(dev_drv, 0x000000); - - vop_bcsh_path_sel(dev_drv); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - vop_set_dclk(dev_drv, 1); - if (screen->init) - screen->init(); - - return 0; -} - -/* - * enable or disable layer according to win id - * @open: 1 enable; 0 disable - */ -static void vop_layer_enable(struct vop_device *vop_dev, - unsigned int win_id, bool open) -{ - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on) && - vop_dev->driver.win[win_id]->state != open) { - if (open) { - if (!vop_dev->atv_layer_cnt) { - dev_info(vop_dev->dev, - "wakeup from standby!\n"); - vop_dev->standby = 0; - } - vop_dev->atv_layer_cnt |= (1 << win_id); - } else { - if (vop_dev->atv_layer_cnt & (1 << win_id)) - vop_dev->atv_layer_cnt &= ~(1 << win_id); - } - vop_dev->driver.win[win_id]->state = open; - if (!open) { - vop_layer_update_regs(vop_dev, - vop_dev->driver.win[win_id]); - vop_cfg_done(vop_dev); - } - /* if no layer used,disable lcdc */ - if (!vop_dev->atv_layer_cnt) { - dev_info(vop_dev->dev, - "no layer is used,go to standby!\n"); - vop_dev->standby = 1; - } - } - spin_unlock(&vop_dev->reg_lock); -} - -static int vop_open(struct rk_lcdc_driver *dev_drv, int win_id, - bool open) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - /* enable clk,when first layer open */ - if ((open) && (!vop_dev->atv_layer_cnt)) { - /* rockchip_set_system_status(sys_status); */ - vop_pre_init(dev_drv); - vop_clk_enable(vop_dev); - vop_irq_enable(vop_dev); - - if (support_uboot_display() && (vop_dev->prop == PRMRY)) { - vop_set_dclk(dev_drv, 0); - } else { - vop_load_screen(dev_drv, 1); - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - } - if (dev_drv->bcsh.enable) - vop_set_bcsh(dev_drv, 1); - - /* set screen GAMMA lut */ - if (dev_drv->cur_screen && dev_drv->cur_screen->dsp_lut) - vop_set_lut(dev_drv, dev_drv->cur_screen->dsp_lut); - } - - if (win_id < ARRAY_SIZE(vop_win)) - vop_layer_enable(vop_dev, win_id, open); - else - dev_err(vop_dev->dev, "invalid win id:%d\n", win_id); - - dev_drv->first_frame = 0; - return 0; -} - -static int vop_pan_display(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct rk_lcdc_win *win = NULL; - struct rk_screen *screen = dev_drv->cur_screen; - - if (!screen) { - dev_err(dev_drv->dev, "screen is null!\n"); - return -ENOENT; - } - - if (win_id >= dev_drv->lcdc_win_num) { - dev_err(dev_drv->dev, "invalid win id:%d!\n", win_id); - return -EINVAL; - } - - win = dev_drv->win[win_id]; - win->area[0].y_addr = win->area[0].smem_start + win->area[0].y_offset; - /* only win0 support yuv format */ - if (win_id == 0) - win->area[0].uv_addr = - win->area[0].cbr_start + win->area[0].c_offset; - else - win->area[0].uv_addr = 0; - - DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x", - vop_dev->id, win->id, win->area[0].y_addr, win->area[0].uv_addr); - DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n", - win->area[0].y_offset, win->area[0].c_offset); - return 0; -} - -static int win_0_1_set_par(struct vop_device *vop_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - char fmt[9] = "NULL"; - - win->area[0].dsp_stx = win->area[0].xpos + screen->mode.left_margin + - screen->mode.hsync_len; - if (screen->mode.vmode & FB_VMODE_INTERLACED) { - win->area[0].ysize /= 2; - win->area[0].dsp_sty = win->area[0].ypos / 2 + - screen->mode.upper_margin + screen->mode.vsync_len; - } else { - win->area[0].dsp_sty = win->area[0].ypos + - screen->mode.upper_margin + screen->mode.vsync_len; - } - - win->scale_yrgb_x = CALSCALE(win->area[0].xact, win->area[0].xsize); - win->scale_yrgb_y = CALSCALE(win->area[0].yact, win->area[0].ysize); - - switch (win->area[0].format) { - case ARGB888: - win->area[0].fmt_cfg = VOP_FORMAT_ARGB888; - win->area[0].swap_rb = 0; - break; - case XBGR888: - case ABGR888: - win->area[0].fmt_cfg = VOP_FORMAT_ARGB888; - win->area[0].swap_rb = 1; - break; - case RGB888: - win->area[0].fmt_cfg = VOP_FORMAT_RGB888; - win->area[0].swap_rb = 0; - break; - case RGB565: - win->area[0].fmt_cfg = VOP_FORMAT_RGB565; - win->area[0].swap_rb = 0; - break; - case XRGB888: - win->area[0].fmt_cfg = VOP_FORMAT_ARGB888; - win->area[0].swap_rb = 0; - break; - case BGR888: - win->area[0].fmt_cfg = VOP_FORMAT_RGB888; - win->area[0].swap_rb = 1; - break; - case BGR565: - win->area[0].fmt_cfg = VOP_FORMAT_RGB565; - win->area[0].swap_rb = 1; - break; - case YUV422: - if (win->id == 0) { - win->area[0].fmt_cfg = VOP_FORMAT_YCBCR422; - win->area[0].swap_rb = 0; - win->area[0].swap_uv = 0; - win->scale_cbcr_x = CALSCALE(win->area[0].xact / 2, - win->area[0].xsize); - win->scale_cbcr_y = CALSCALE(win->area[0].yact, - win->area[0].ysize); - } else { - dev_err(vop_dev->dev, "%s:win%d unsupport YUV format\n", - __func__, win->id); - } - break; - case YUV420: - if (win->id == 0) { - win->area[0].fmt_cfg = VOP_FORMAT_YCBCR420; - win->area[0].swap_rb = 0; - win->area[0].swap_uv = 0; - win->scale_cbcr_x = CALSCALE(win->area[0].xact / 2, - win->area[0].xsize); - win->scale_cbcr_y = CALSCALE(win->area[0].yact / 2, - win->area[0].ysize); - } else { - dev_err(vop_dev->dev, "%s:win%d unsupport YUV format\n", - __func__, win->id); - } - - break; - case YUV420_NV21: - if (win->id == 0) { - win->area[0].fmt_cfg = VOP_FORMAT_YCBCR420; - win->area[0].swap_rb = 0; - win->area[0].swap_uv = 1; - win->scale_cbcr_x = CALSCALE(win->area[0].xact / 2, - win->area[0].xsize); - win->scale_cbcr_y = CALSCALE(win->area[0].yact / 2, - win->area[0].ysize); - } else { - dev_err(vop_dev->dev, "%s:win%d unsupport YUV format\n", - __func__, win->id); - } - break; - case YUV444: - if (win->id == 0) { - win->area[0].fmt_cfg = VOP_FORMAT_YCBCR444; - win->area[0].swap_rb = 0; - win->area[0].swap_uv = 0; - win->scale_cbcr_x = - CALSCALE(win->area[0].xact, win->area[0].xsize); - win->scale_cbcr_y = - CALSCALE(win->area[0].yact, win->area[0].ysize); - } else { - dev_err(vop_dev->dev, "%s:win%d unsupport YUV format\n", - __func__, win->id); - } - break; - default: - dev_err(vop_dev->dev, "%s:unsupport format[%d]!\n", - __func__, win->area[0].format); - break; - } - - DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d", - vop_dev->id, win->id, get_format_string(win->area[0].format, fmt), - win->area[0].xact, win->area[0].yact, win->area[0].xsize); - DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - win->area[0].ysize, win->area[0].xvir, win->area[0].yvir, - win->area[0].xpos, win->area[0].ypos); - - return 0; -} - -static int hwc_set_par(struct vop_device *vop_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - win->area[0].dsp_stx = win->area[0].xpos + screen->mode.left_margin + - screen->mode.hsync_len; - win->area[0].dsp_sty = win->area[0].ypos + screen->mode.upper_margin + - screen->mode.vsync_len; - - DBG(1, "lcdc[%d]:hwc>>%s\n>>xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d", - vop_dev->id, __func__, win->area[0].xsize, win->area[0].ysize, - win->area[0].xpos, win->area[0].ypos); - return 0; -} - -static int vop_set_par(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct rk_screen *screen = dev_drv->cur_screen; - - if (!screen) { - dev_err(dev_drv->dev, "screen is null!\n"); - return -ENOENT; - } - - switch (win_id) { - case 0: - win_0_1_set_par(vop_dev, screen, dev_drv->win[0]); - break; - case 1: - win_0_1_set_par(vop_dev, screen, dev_drv->win[1]); - break; - case 2: - hwc_set_par(vop_dev, screen, dev_drv->win[2]); - break; - default: - dev_err(dev_drv->dev, "%s: unsupported win id:%d\n", - __func__, win_id); - break; - } - return 0; -} - -static int vop_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd, - unsigned long arg, int win_id) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - u32 panel_size[2]; - void __user *argp = (void __user *)arg; - struct color_key_cfg clr_key_cfg; - - switch (cmd) { - case RK_FBIOGET_PANEL_SIZE: - panel_size[0] = vop_dev->screen->mode.xres; - panel_size[1] = vop_dev->screen->mode.yres; - if (copy_to_user(argp, panel_size, 8)) - return -EFAULT; - break; - case RK_FBIOPUT_COLOR_KEY_CFG: - if (copy_from_user(&clr_key_cfg, argp, - sizeof(struct color_key_cfg))) - return -EFAULT; - vop_clr_key_cfg(dev_drv); - vop_writel(vop_dev, WIN0_COLOR_KEY, - clr_key_cfg.win0_color_key_cfg); - vop_writel(vop_dev, WIN1_COLOR_KEY, - clr_key_cfg.win1_color_key_cfg); - break; - - default: - break; - } - return 0; -} - -static int vop_get_backlight_device(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct device_node *backlight; - struct property *prop; - u32 *brightness_levels; - u32 length, max, last; - - if (vop_dev->backlight) - return 0; - backlight = of_parse_phandle(vop_dev->dev->of_node, "backlight", 0); - if (backlight) { - vop_dev->backlight = of_find_backlight_by_node(backlight); - if (!vop_dev->backlight) - dev_info(vop_dev->dev, "No find backlight device\n"); - } else { - dev_info(vop_dev->dev, "No find backlight device node\n"); - } - prop = of_find_property(backlight, "brightness-levels", &length); - if (!prop) - return -EINVAL; - max = length / sizeof(u32); - last = max - 1; - brightness_levels = kmalloc(256, GFP_KERNEL); - if (brightness_levels) - return -ENOMEM; - - if (!of_property_read_u32_array(backlight, "brightness-levels", - brightness_levels, max)) { - if (brightness_levels[0] > brightness_levels[last]) - dev_drv->cabc_pwm_pol = 1;/*negative*/ - else - dev_drv->cabc_pwm_pol = 0;/*positive*/ - } else { - dev_info(vop_dev->dev, - "Can not read brightness-levels value\n"); - } - - kfree(brightness_levels); - - return 0; -} - -static int vop_backlight_close(struct rk_lcdc_driver *dev_drv, int enable) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - if (dev_drv->suspend_flag) - return 0; - - vop_get_backlight_device(dev_drv); - - if (enable) { - /* close the backlight */ - if (vop_dev->backlight) { - vop_dev->backlight->props.power = FB_BLANK_POWERDOWN; - backlight_update_status(vop_dev->backlight); - } - if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable) - dev_drv->trsm_ops->disable(); - } else { - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - msleep(100); - /* open the backlight */ - if (vop_dev->backlight) { - vop_dev->backlight->props.power = FB_BLANK_UNBLANK; - backlight_update_status(vop_dev->backlight); - } - } - - return 0; -} - -static int vop_early_suspend(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - if (dev_drv->suspend_flag) - return 0; - - dev_drv->suspend_flag = 1; - smp_wmb(); - flush_kthread_worker(&dev_drv->update_regs_worker); - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable) - dev_drv->trsm_ops->disable(); - - vop_standby_enable(vop_dev); - vop_mmu_disable(dev_drv); - vop_clk_disable(vop_dev); - rk_disp_pwr_disable(dev_drv); - - return 0; -} - -static int vop_early_resume(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - if (!dev_drv->suspend_flag) - return 0; - - rk_disp_pwr_enable(dev_drv); - vop_clk_enable(vop_dev); - vop_reg_restore(dev_drv); - vop_standby_disable(vop_dev); - vop_mmu_enable(dev_drv); - dev_drv->suspend_flag = 0; - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) - dev_drv->trsm_ops->enable(); - - return 0; -} - -static int vop_blank(struct rk_lcdc_driver *dev_drv, int win_id, int blank_mode) -{ - switch (blank_mode) { - case FB_BLANK_UNBLANK: - vop_early_resume(dev_drv); - break; - case FB_BLANK_NORMAL: - vop_early_suspend(dev_drv); - break; - default: - vop_early_suspend(dev_drv); - break; - } - - dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode); - - return 0; -} - -static int vop_get_win_state(struct rk_lcdc_driver *dev_drv, - int win_id, int area_id) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - u32 area_status = 0, state = 0; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - switch (win_id) { - case 0: - area_status = - vop_read_bit(vop_dev, WIN0_CTRL0, V_WIN0_EN(0)); - break; - case 1: - area_status = - vop_read_bit(vop_dev, WIN1_CTRL0, V_WIN1_EN(0)); - break; - case 2: - area_status = - vop_read_bit(vop_dev, HWC_CTRL0, V_HWC_EN(0)); - break; - default: - pr_err("%s: win[%d]area[%d],unsupport!!!\n", - __func__, win_id, area_id); - break; - } - } - spin_unlock(&vop_dev->reg_lock); - - state = (area_status > 0) ? 1 : 0; - return state; -} - -static int vop_get_area_num(struct rk_lcdc_driver *dev_drv, - unsigned int *area_support) -{ - area_support[0] = 1; - area_support[1] = 1; - - return 0; -} - -static int vop_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, bool set) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - int ovl; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - if (set) { - vop_msk_reg(vop_dev, DSP_CTRL2, V_DSP_WIN0_TOP(swap)); - ovl = swap; - } else { - ovl = - vop_read_bit(vop_dev, DSP_CTRL2, V_DSP_WIN0_TOP(0)); - } - } else { - ovl = -EPERM; - } - spin_unlock(&vop_dev->reg_lock); - - return ovl; -} - -static char *vop_format_to_string(int format, char *fmt) -{ - if (!fmt) - return NULL; - - switch (format) { - case 0: - strcpy(fmt, "ARGB888"); - break; - case 1: - strcpy(fmt, "RGB888"); - break; - case 2: - strcpy(fmt, "RGB565"); - break; - case 4: - strcpy(fmt, "YCbCr420"); - break; - case 5: - strcpy(fmt, "YCbCr422"); - break; - case 6: - strcpy(fmt, "YCbCr444"); - break; - default: - strcpy(fmt, "invalid\n"); - break; - } - return fmt; -} - -static ssize_t vop_get_disp_info(struct rk_lcdc_driver *dev_drv, - char *buf, int win_id) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct rk_screen *screen = dev_drv->cur_screen; - u16 hsync_len = screen->mode.hsync_len; - u16 left_margin = screen->mode.left_margin; - u16 vsync_len = screen->mode.vsync_len; - u16 upper_margin = screen->mode.upper_margin; - u32 h_pw_bp = hsync_len + left_margin; - u32 v_pw_bp = vsync_len + upper_margin; - u32 fmt_id; - char format_w0[9] = "NULL"; - char format_w1[9] = "NULL"; - char dsp_buf[100]; - u32 win_ctrl, ovl, vir_info, act_info, dsp_info, dsp_st; - u32 y_factor, uv_factor; - u8 w0_state, w1_state; - - u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y; - u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp; - u32 w1_vir_y, w1_dsp_x, w1_dsp_y; - u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp; - u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac; - - u32 dclk_freq; - int size = 0; - - dclk_freq = screen->mode.pixclock; - /*vop_reg_dump(dev_drv); */ - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - ovl = vop_read_bit(vop_dev, DSP_CTRL2, V_DSP_WIN0_TOP(0)); - /* WIN0 */ - win_ctrl = vop_readl(vop_dev, WIN0_CTRL0); - w0_state = win_ctrl & MASK(WIN0_EN); - fmt_id = (win_ctrl & MASK(WIN0_DATA_FMT)) >> 1; - vop_format_to_string(fmt_id, format_w0); - vir_info = vop_readl(vop_dev, WIN0_VIR); - act_info = vop_readl(vop_dev, WIN0_ACT_INFO); - dsp_info = vop_readl(vop_dev, WIN0_DSP_INFO); - dsp_st = vop_readl(vop_dev, WIN0_DSP_ST); - y_factor = vop_readl(vop_dev, WIN0_SCL_FACTOR_YRGB); - uv_factor = vop_readl(vop_dev, WIN0_SCL_FACTOR_CBR); - w0_vir_y = vir_info & MASK(WIN0_YRGB_VIR_STRIDE); - w0_vir_uv = (vir_info & MASK(WIN0_CBR_VIR_STRIDE)) >> 16; - w0_act_x = (act_info & MASK(WIN0_ACT_WIDTH)) + 1; - w0_act_y = ((act_info & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1; - w0_dsp_x = (dsp_info & MASK(WIN0_DSP_WIDTH)) + 1; - w0_dsp_y = ((dsp_info & MASK(WIN0_DSP_HEIGHT)) >> 16) + 1; - if (w0_state) { - w0_st_x = dsp_st & MASK(WIN0_DSP_XST); - w0_st_y = (dsp_st & MASK(WIN0_DSP_YST)) >> 16; - } - w0_y_h_fac = y_factor & MASK(WIN0_HS_FACTOR_YRGB); - w0_y_v_fac = (y_factor & MASK(WIN0_VS_FACTOR_YRGB)) >> 16; - w0_uv_h_fac = uv_factor & MASK(WIN0_HS_FACTOR_CBR); - w0_uv_v_fac = (uv_factor & MASK(WIN0_VS_FACTOR_CBR)) >> 16; - - /* WIN1 */ - win_ctrl = vop_readl(vop_dev, WIN1_CTRL0); - w1_state = win_ctrl & MASK(WIN1_EN); - fmt_id = (win_ctrl & MASK(WIN1_DATA_FMT)) >> 1; - vop_format_to_string(fmt_id, format_w1); - vir_info = vop_readl(vop_dev, WIN1_VIR); - dsp_info = vop_readl(vop_dev, WIN1_DSP_INFO); - dsp_st = vop_readl(vop_dev, WIN1_DSP_ST); - w1_vir_y = vir_info & MASK(WIN1_VIR_STRIDE); - w1_dsp_x = (dsp_info & MASK(WIN1_DSP_WIDTH)) + 1; - w1_dsp_y = ((dsp_info & MASK(WIN1_DSP_HEIGHT)) >> 16) + 1; - if (w1_state) { - w1_st_x = dsp_st & MASK(WIN1_DSP_XST); - w1_st_y = (dsp_st & MASK(WIN1_DSP_YST)) >> 16; - } - } else { - spin_unlock(&vop_dev->reg_lock); - return -EPERM; - } - spin_unlock(&vop_dev->reg_lock); - /* win0 */ - size += snprintf(dsp_buf, 80, - "win0:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,", - w0_state, format_w0, w0_vir_y, w0_vir_uv); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n", - w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ", - w0_st_x - h_pw_bp, w0_st_y - v_pw_bp, w0_y_h_fac, w0_y_v_fac); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n", - w0_uv_h_fac, w0_uv_v_fac, vop_readl(vop_dev, WIN0_YRGB_MST), - vop_readl(vop_dev, WIN0_CBR_MST)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /* win1 */ - size += snprintf(dsp_buf, 80, - "win1:\n state:%d, fmt:%7s\n y_vir:%4d,", - w1_state, format_w1, w1_vir_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - " dsp_x :%5d, dsp_y :%5d\n", - w1_dsp_x, w1_dsp_y); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - " x_st :%4d, y_st :%4d, ", - w1_st_x - h_pw_bp, w1_st_y - v_pw_bp); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - size += snprintf(dsp_buf, 80, - "y_addr:0x%08x\n", - vop_readl(vop_dev, WIN1_YRGB_MST)); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - /* zorder */ - size += snprintf(dsp_buf, 80, - ovl ? "win0 on the top of win1\n" : - "win1 on the top of win0\n"); - strcat(buf, dsp_buf); - memset(dsp_buf, 0, sizeof(dsp_buf)); - - return size; -} - -static int vop_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, bool set) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - struct rk_screen *screen = dev_drv->cur_screen; - u64 ft = 0; - u32 dotclk; - int ret; - u32 pixclock; - u32 x_total, y_total; - - if (set) { - if (fps == 0) { - dev_info(dev_drv->dev, "unsupport set fps=0\n"); - return 0; - } - ft = div_u64(1000000000000llu, fps); - x_total = - screen->mode.upper_margin + screen->mode.lower_margin + - screen->mode.yres + screen->mode.vsync_len; - y_total = - screen->mode.left_margin + screen->mode.right_margin + - screen->mode.xres + screen->mode.hsync_len; - dev_drv->pixclock = div_u64(ft, x_total * y_total); - dotclk = div_u64(1000000000000llu, dev_drv->pixclock); - ret = clk_set_rate(vop_dev->dclk, dotclk); - } - - pixclock = div_u64(1000000000000llu, clk_get_rate(vop_dev->dclk)); - vop_dev->pixclock = pixclock; - dev_drv->pixclock = vop_dev->pixclock; - fps = rk_fb_calc_fps(screen, pixclock); - screen->ft = 1000 / fps; /*one frame time in ms */ - - if (set) - dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__, - clk_get_rate(vop_dev->dclk), fps); - - return fps; -} - -static int vop_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order) -{ - mutex_lock(&dev_drv->fb_win_id_mutex); - if (order == FB_DEFAULT_ORDER) - order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC; - dev_drv->fb4_win_id = order / 10000; - dev_drv->fb3_win_id = (order / 1000) % 10; - dev_drv->fb2_win_id = (order / 100) % 10; - dev_drv->fb1_win_id = (order / 10) % 10; - dev_drv->fb0_win_id = order % 10; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return 0; -} - -static int vop_get_win_id(struct rk_lcdc_driver *dev_drv, const char *id) -{ - int win_id = 0; - - mutex_lock(&dev_drv->fb_win_id_mutex); - if (!strcmp(id, "fb0") || !strcmp(id, "fb5")) - win_id = dev_drv->fb0_win_id; - else if (!strcmp(id, "fb1") || !strcmp(id, "fb6")) - win_id = dev_drv->fb1_win_id; - else if (!strcmp(id, "fb2") || !strcmp(id, "fb7")) - win_id = dev_drv->fb2_win_id; - else if (!strcmp(id, "fb3") || !strcmp(id, "fb8")) - win_id = dev_drv->fb3_win_id; - else if (!strcmp(id, "fb4") || !strcmp(id, "fb9")) - win_id = dev_drv->fb4_win_id; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return win_id; -} - -static int vop_config_done(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - int i; - struct rk_lcdc_win *win = NULL; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - for (i = 0; i < dev_drv->lcdc_win_num; i++) { - win = dev_drv->win[i]; - vop_layer_update_regs(vop_dev, win); - } - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_dpi_open(struct rk_lcdc_driver *dev_drv, bool open) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - vop_msk_reg(vop_dev, SYS_CTRL0, V_DIRECT_PATH_EN(open)); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - vop_msk_reg(vop_dev, SYS_CTRL0, - V_DIRECT_PATH_LAYER_SEL(win_id)); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - return 0; -} - -static int vop_dpi_status(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - int status = 0; - - spin_lock(&vop_dev->reg_lock); - - if (likely(vop_dev->clk_on)) - status = vop_read_bit(vop_dev, SYS_CTRL0, V_DIRECT_PATH_EN(0)); - - spin_unlock(&vop_dev->reg_lock); - - return status; -} - -static int vop_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv, int enable) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - if (enable) - enable_irq(vop_dev->irq); - else - disable_irq(vop_dev->irq); - return 0; -} - -static int vop_poll_vblank(struct rk_lcdc_driver *dev_drv) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - u32 int_reg; - int ret; - - if (vop_dev->clk_on && (!dev_drv->suspend_flag)) { - int_reg = vop_readl(vop_dev, INTR_STATUS); - if (int_reg & INTR_LINE_FLAG0) { - vop_dev->driver.frame_time.last_framedone_t = - vop_dev->driver.frame_time.framedone_t; - vop_dev->driver.frame_time.framedone_t = cpu_clock(0); - vop_mask_writel(vop_dev, INTR_CLEAR, INTR_LINE_FLAG0, - INTR_LINE_FLAG0); - ret = RK_LF_STATUS_FC; - } else { - ret = RK_LF_STATUS_FR; - } - } else { - ret = RK_LF_STATUS_NC; - } - - return ret; -} - -static int vop_get_dsp_addr(struct rk_lcdc_driver *dev_drv, - unsigned int dsp_addr[][4]) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - dsp_addr[0][0] = vop_readl(vop_dev, WIN0_YRGB_MST); - dsp_addr[1][0] = vop_readl(vop_dev, WIN1_YRGB_MST); - dsp_addr[2][0] = vop_readl(vop_dev, HWC_MST); - } - spin_unlock(&vop_dev->reg_lock); - return 0; -} - -/* - * a:[-30~0]: - * sin_hue = sin(a)*256 +0x100; - * cos_hue = cos(a)*256; - * a:[0~30] - * sin_hue = sin(a)*256; - * cos_hue = cos(a)*256; - */ -static int vop_get_bcsh_hue(struct rk_lcdc_driver *dev_drv, bcsh_hue_mode mode) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - u32 val = 0; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - val = vop_readl(vop_dev, BCSH_H); - switch (mode) { - case H_SIN: - val &= MASK(SIN_HUE); - val <<= 1; - break; - case H_COS: - val &= MASK(COS_HUE); - val >>= 8; - val <<= 1; - break; - default: - break; - } - } - spin_unlock(&vop_dev->reg_lock); - - return val; -} - -static int vop_set_bcsh_hue(struct rk_lcdc_driver *dev_drv, - int sin_hue, int cos_hue) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - u64 val; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - /* - * config range is [0, 510), typical value is 256 - * register range is [0, 255], cos_hue typical value is 128 - * sin_hue typical value is 0 - */ - val = V_SIN_HUE(sin_hue >> 1) | V_COS_HUE(cos_hue >> 1); - vop_msk_reg(vop_dev, BCSH_H, val); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv, - bcsh_bcs_mode mode, int value) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - u64 val = 0; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - switch (mode) { - case BRIGHTNESS: - /* - * user range is [0, 255], typical value is 128 - * register range is [-32, 31], typical value is 0 - */ - value >>= 2; /* 0-->32-->63 for user, typical is 32 */ - if (value < 0x20) - value += 0x20; - else if (value >= 0x20) - value = value - 0x20; - val = V_BRIGHTNESS(value); - break; - case CONTRAST: - /* - * config range is [0, 510), typical value is 256 - * register range is [0, 255], typical value is 128 - */ - value >>= 1; - val = V_CONTRAST(value); - break; - case SAT_CON: - /* - * config range is [0, 1015], typical value is 512 - * register range is [0, 255], typical value is 128 - */ - value >>= 2; - val = V_SAT_CON(value); - break; - default: - break; - } - vop_msk_reg(vop_dev, BCSH_BCS, val); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - return val; -} - -static int vop_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv, bcsh_bcs_mode mode) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - u64 val = 0; - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - val = vop_readl(vop_dev, BCSH_BCS); - switch (mode) { - case BRIGHTNESS: - val &= MASK(BRIGHTNESS); - if (val >= 0x20) - val -= 0x20; - else - val += 0x20; - val <<= 2; - break; - case CONTRAST: - val &= MASK(CONTRAST); - val >>= 8; - val <<= 1; - break; - case SAT_CON: - val &= MASK(SAT_CON); - val >>= 16; - val <<= 2; - break; - default: - break; - } - } - spin_unlock(&vop_dev->reg_lock); - return val; -} - -static int vop_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - if (open) { - vop_writel(vop_dev, BCSH_BCS, - V_BRIGHTNESS(0x00) | V_CONTRAST(0x80) | - V_SAT_CON(0x80)); - vop_writel(vop_dev, BCSH_H, - V_SIN_HUE(0x00) | V_COS_HUE(0x80)); - vop_msk_reg(vop_dev, BCSH_CTRL, V_BCSH_EN(1) | - V_VIDEO_MODE(BCSH_MODE_VIDEO)); - dev_drv->bcsh.enable = 1; - } else { - vop_msk_reg(vop_dev, BCSH_CTRL, V_BCSH_EN(0)); - dev_drv->bcsh.enable = 0; - } - vop_bcsh_path_sel(dev_drv); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - - return 0; -} - -static int vop_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable) -{ - if (!enable || !dev_drv->bcsh.enable) { - vop_open_bcsh(dev_drv, false); - return 0; - } - - if (dev_drv->bcsh.brightness <= 255 || - dev_drv->bcsh.contrast < 510 || - dev_drv->bcsh.sat_con <= 1015 || - (dev_drv->bcsh.sin_hue < 510 && dev_drv->bcsh.cos_hue < 510)) { - vop_open_bcsh(dev_drv, true); - if (dev_drv->bcsh.brightness <= 255) - vop_set_bcsh_bcs(dev_drv, BRIGHTNESS, - dev_drv->bcsh.brightness); - if (dev_drv->bcsh.contrast < 510) - vop_set_bcsh_bcs(dev_drv, CONTRAST, - dev_drv->bcsh.contrast); - if (dev_drv->bcsh.sat_con <= 1015) - vop_set_bcsh_bcs(dev_drv, SAT_CON, - dev_drv->bcsh.sat_con); - if (dev_drv->bcsh.sin_hue < 510 && - dev_drv->bcsh.cos_hue < 510) - vop_set_bcsh_hue(dev_drv, dev_drv->bcsh.sin_hue, - dev_drv->bcsh.cos_hue); - } - - return 0; -} - -static int __maybe_unused -vop_dsp_black(struct rk_lcdc_driver *dev_drv, int enable) -{ - struct vop_device *vop_dev = to_vop_dev(dev_drv); - - if (enable) { - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLACK_EN(1)); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - } else { - spin_lock(&vop_dev->reg_lock); - if (likely(vop_dev->clk_on)) { - vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLACK_EN(0)); - vop_cfg_done(vop_dev); - } - spin_unlock(&vop_dev->reg_lock); - } - - return 0; -} - -static struct rk_lcdc_drv_ops lcdc_drv_ops = { - .open = vop_open, - .win_direct_en = vop_win_direct_en, - .load_screen = vop_load_screen, - .get_dspbuf_info = vop_get_dspbuf_info, - .post_dspbuf = vop_post_dspbuf, - .set_par = vop_set_par, - .pan_display = vop_pan_display, - .direct_set_addr = vop_direct_set_win_addr, - .blank = vop_blank, - .ioctl = vop_ioctl, - .suspend = vop_early_suspend, - .resume = vop_early_resume, - .get_win_state = vop_get_win_state, - .area_support_num = vop_get_area_num, - .ovl_mgr = vop_ovl_mgr, - .get_disp_info = vop_get_disp_info, - .fps_mgr = vop_fps_mgr, - .fb_get_win_id = vop_get_win_id, - .fb_win_remap = vop_fb_win_remap, - .poll_vblank = vop_poll_vblank, - .dpi_open = vop_dpi_open, - .dpi_win_sel = vop_dpi_win_sel, - .dpi_status = vop_dpi_status, - .get_dsp_addr = vop_get_dsp_addr, - .set_dsp_bcsh_hue = vop_set_bcsh_hue, - .set_dsp_bcsh_bcs = vop_set_bcsh_bcs, - .get_dsp_bcsh_hue = vop_get_bcsh_hue, - .get_dsp_bcsh_bcs = vop_get_bcsh_bcs, - .open_bcsh = vop_open_bcsh, - .set_dsp_lut = vop_set_lut, - .set_hwc_lut = vop_set_hwc_lut, - .dump_reg = vop_reg_dump, - .cfg_done = vop_config_done, - .set_irq_to_cpu = vop_set_irq_to_cpu, - /*.dsp_black = vop_dsp_black,*/ - .backlight_close = vop_backlight_close, - .mmu_en = vop_mmu_enable, -}; - -static irqreturn_t vop_isr(int irq, void *dev_id) -{ - struct vop_device *vop_dev = (struct vop_device *)dev_id; - ktime_t timestamp = ktime_get(); - u32 intr_status; - unsigned long flags; - - spin_lock_irqsave(&vop_dev->irq_lock, flags); - - intr_status = vop_readl(vop_dev, INTR_STATUS); - vop_mask_writel(vop_dev, INTR_CLEAR, INTR_MASK, intr_status); - - spin_unlock_irqrestore(&vop_dev->irq_lock, flags); - - intr_status &= 0xffff; /* ignore raw status at 16~32bit */ - /* This is expected for vop iommu irqs, since the irq is shared */ - if (!intr_status) - return IRQ_NONE; - - if (intr_status & INTR_FS0) { - timestamp = ktime_get(); - vop_dev->driver.vsync_info.timestamp = timestamp; - wake_up_interruptible_all(&vop_dev->driver.vsync_info.wait); - complete(&vop_dev->sync.frmst); - intr_status &= ~INTR_FS0; - } - - /* fs1 interrupt occur only when the address is different */ - if (intr_status & INTR_FS1) - intr_status &= ~INTR_FS1; - - if (intr_status & INTR_ADDR_SAME) - intr_status &= ~INTR_ADDR_SAME; - - if (intr_status & INTR_DSP_HOLD_VALID) { - complete(&vop_dev->sync.stdbyfin); - intr_status &= ~INTR_DSP_HOLD_VALID; - } - - if (intr_status & INTR_LINE_FLAG0) - intr_status &= ~INTR_LINE_FLAG0; - - if (intr_status & INTR_LINE_FLAG1) - intr_status &= ~INTR_LINE_FLAG1; - - if (intr_status & INTR_BUS_ERROR) { - intr_status &= ~INTR_BUS_ERROR; - dev_warn_ratelimited(vop_dev->dev, "bus error!"); - } - - if (intr_status & INTR_WIN0_EMPTY) { - intr_status &= ~INTR_WIN0_EMPTY; - dev_warn_ratelimited(vop_dev->dev, "intr win0 empty!"); - } - - if (intr_status & INTR_WIN1_EMPTY) { - intr_status &= ~INTR_WIN1_EMPTY; - dev_warn_ratelimited(vop_dev->dev, "intr win1 empty!"); - } - - if (intr_status & INTR_DMA_FINISH) - intr_status &= ~INTR_DMA_FINISH; - - if (intr_status & INTR_MMU_STATUS) - intr_status &= ~INTR_MMU_STATUS; - - if (intr_status) - dev_err(vop_dev->dev, "Unknown VOP IRQs: %#02x\n", intr_status); - - return IRQ_HANDLED; -} - -#if defined(CONFIG_PM) -static int vop_suspend(struct platform_device *pdev, pm_message_t state) -{ - return 0; -} - -static int vop_resume(struct platform_device *pdev) -{ - return 0; -} -#else -#define vop_suspend NULL -#define vop_resume NULL -#endif - -static int vop_parse_dt(struct vop_device *vop_dev) -{ - struct device_node *np = vop_dev->dev->of_node; - struct rk_lcdc_driver *dev_drv = &vop_dev->driver; - int val; - - if (of_property_read_u32(np, "rockchip,prop", &val)) - vop_dev->prop = PRMRY; /*default set it as primary */ - else - vop_dev->prop = val; - - if (of_property_read_u32(np, "rockchip,mirror", &val)) - dev_drv->rotate_mode = NO_MIRROR; - else - dev_drv->rotate_mode = val; - - if (of_property_read_u32(np, "rockchip,pwr18", &val)) - /*default set it as 3.xv power supply */ - vop_dev->pwr18 = false; - else - vop_dev->pwr18 = (val ? true : false); - - if (of_property_read_u32(np, "rockchip,fb-win-map", &val)) - dev_drv->fb_win_map = FB_DEFAULT_ORDER; - else - dev_drv->fb_win_map = val; - - if (of_property_read_u32(np, "rockchip,bcsh-en", &val)) - dev_drv->bcsh.enable = false; - else - dev_drv->bcsh.enable = (val ? true : false); - - if (of_property_read_u32(np, "rockchip,brightness", &val)) - dev_drv->bcsh.brightness = 0xffff; - else - dev_drv->bcsh.brightness = val; - - if (of_property_read_u32(np, "rockchip,contrast", &val)) - dev_drv->bcsh.contrast = 0xffff; - else - dev_drv->bcsh.contrast = val; - - if (of_property_read_u32(np, "rockchip,sat-con", &val)) - dev_drv->bcsh.sat_con = 0xffff; - else - dev_drv->bcsh.sat_con = val; - - if (of_property_read_u32(np, "rockchip,hue", &val)) { - dev_drv->bcsh.sin_hue = 0xffff; - dev_drv->bcsh.cos_hue = 0xffff; - } else { - dev_drv->bcsh.sin_hue = val & 0xff; - dev_drv->bcsh.cos_hue = (val >> 8) & 0xff; - } - - if (of_property_read_u32(np, "rockchip,iommu-enabled", &val)) - dev_drv->iommu_enabled = 0; - else - dev_drv->iommu_enabled = val; - - return 0; -} - -static int vop_probe(struct platform_device *pdev) -{ - struct vop_device *vop_dev = NULL; - struct rk_lcdc_driver *dev_drv; - struct device *dev = &pdev->dev; - struct resource *res; - struct device_node *np = pdev->dev.of_node; - int prop; - int ret = 0; - - /* - * if the primary lcdc has not registered ,the extend - * lcdc register later - */ - of_property_read_u32(np, "rockchip,prop", &prop); - if (prop == EXTEND) { - if (!is_prmry_rk_lcdc_registered()) - return -EPROBE_DEFER; - } - - vop_dev = devm_kzalloc(dev, sizeof(struct vop_device), GFP_KERNEL); - if (!vop_dev) - return -ENOMEM; - - platform_set_drvdata(pdev, vop_dev); - vop_dev->dev = dev; - vop_parse_dt(vop_dev); - - /* enable power domain */ - pm_runtime_enable(dev); - - vop_dev->hclk = devm_clk_get(vop_dev->dev, "hclk_lcdc"); - if (IS_ERR(vop_dev->hclk)) { - dev_err(vop_dev->dev, "failed to get hclk source\n"); - return PTR_ERR(vop_dev->hclk); - } - - vop_dev->aclk = devm_clk_get(vop_dev->dev, "aclk_lcdc"); - if (IS_ERR(vop_dev->aclk)) { - dev_err(vop_dev->dev, "failed to get aclk source\n"); - return PTR_ERR(vop_dev->aclk); - } - vop_dev->dclk = devm_clk_get(vop_dev->dev, "dclk_lcdc"); - if (IS_ERR(vop_dev->dclk)) { - dev_err(vop_dev->dev, "failed to get dclk source\n"); - return PTR_ERR(vop_dev->dclk); - } - - clk_prepare(vop_dev->hclk); - clk_prepare(vop_dev->aclk); - clk_prepare(vop_dev->dclk); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - vop_dev->regs = devm_ioremap_resource(dev, res); - if (IS_ERR(vop_dev->regs)) { - ret = PTR_ERR(vop_dev->regs); - goto err_exit; - } - - vop_dev->reg_phy_base = res->start; - vop_dev->len = resource_size(res); - vop_dev->regsbak = devm_kzalloc(dev, vop_dev->len, GFP_KERNEL); - if (!vop_dev->regsbak) { - ret = -ENOMEM; - goto err_exit; - } - - vop_dev->hwc_lut_addr_base = (vop_dev->regs + HWC_LUT_ADDR); - vop_dev->dsp_lut_addr_base = (vop_dev->regs + GAMMA_LUT_ADDR); - vop_dev->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); - if (IS_ERR(vop_dev->grf_base)) { - dev_err(vop_dev->dev, "ERROR!! can't find grf reg property\n"); - vop_dev->grf_base = NULL; - } - - vop_dev->id = 1; - dev_set_name(vop_dev->dev, "vop%d", vop_dev->id); - dev_drv = &vop_dev->driver; - dev_drv->dev = dev; - dev_drv->prop = prop; - dev_drv->id = vop_dev->id; - dev_drv->ops = &lcdc_drv_ops; - dev_drv->lcdc_win_num = ARRAY_SIZE(vop_win); - dev_drv->reserved_fb = 0; - spin_lock_init(&vop_dev->reg_lock); - spin_lock_init(&vop_dev->irq_lock); - init_completion(&vop_dev->sync.stdbyfin); - init_completion(&vop_dev->sync.frmst); - vop_dev->sync.stdbyfin_to = 50; /* timeout 50 ms */ - vop_dev->sync.frmst_to = 50; - - vop_dev->irq = platform_get_irq(pdev, 0); - if (vop_dev->irq < 0) { - dev_err(dev, "cannot find IRQ for lcdc%d\n", vop_dev->id); - ret = vop_dev->irq; - goto err_exit; - } - - ret = devm_request_irq(dev, vop_dev->irq, vop_isr, - IRQF_SHARED, - dev_name(dev), vop_dev); - if (ret) { - dev_err(dev, "cannot requeset irq %d - err %d\n", - vop_dev->irq, ret); - goto err_exit; - } - - if (dev_drv->iommu_enabled) - strcpy(dev_drv->mmu_dts_name, VOPL_IOMMU_COMPATIBLE_NAME); - - ret = rk_fb_register(dev_drv, vop_win, vop_dev->id); - if (ret < 0) { - dev_err(dev, "register fb for failed!\n"); - goto err_exit; - } - vop_dev->screen = dev_drv->screen0; - dev_info(dev, "lcdc%d probe ok, iommu %s\n", - vop_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled"); - - return 0; - -err_exit: - clk_unprepare(vop_dev->dclk); - clk_unprepare(vop_dev->aclk); - clk_unprepare(vop_dev->hclk); - pm_runtime_disable(dev); - - return ret; -} - -static int vop_remove(struct platform_device *pdev) -{ - return 0; -} - -static void vop_shutdown(struct platform_device *pdev) -{ - struct vop_device *vop_dev = platform_get_drvdata(pdev); - struct rk_lcdc_driver *dev_drv = &vop_dev->driver; - - dev_drv->suspend_flag = 1; - smp_wmb(); - flush_kthread_worker(&dev_drv->update_regs_worker); - kthread_stop(dev_drv->update_regs_thread); - - if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable) - dev_drv->trsm_ops->disable(); - - vop_deinit(vop_dev); - rk_disp_pwr_disable(dev_drv); -} - -#if defined(CONFIG_OF) -static const struct of_device_id vop_dt_ids[] = { - {.compatible = "rockchip,rk3366-lcdc-lite",}, - {} -}; -#endif - -static struct platform_driver vop_driver = { - .probe = vop_probe, - .remove = vop_remove, - .driver = { - .name = "rk-vop-lite", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(vop_dt_ids), - }, - .suspend = vop_suspend, - .resume = vop_resume, - .shutdown = vop_shutdown, -}; - -static int __init vop_module_init(void) -{ - return platform_driver_register(&vop_driver); -} - -static void __exit vop_module_exit(void) -{ - platform_driver_unregister(&vop_driver); -} - -fs_initcall(vop_module_init); -module_exit(vop_module_exit); diff --git a/drivers/video/rockchip/lcdc/rk_vop_lite.h b/drivers/video/rockchip/lcdc/rk_vop_lite.h deleted file mode 100644 index 4f8c096b2d4e..000000000000 --- a/drivers/video/rockchip/lcdc/rk_vop_lite.h +++ /dev/null @@ -1,649 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef RK_VOPLITE_H_ -#define RK_VOPLITE_H_ - -#include -#include -#include -#include -#include - -#define VOP_INPUT_MAX_WIDTH 2048 - -/* - * Registers in this file - * REG_CFG_DONE: Register config done flag - * VERSION_INFO: Version for vop - * DSP_BG: Background color - * MCU_RESERVED: Reversed - * SYS_CTRL0: System control register0 - * SYS_CTRL1: Axi Bus interface control register - * SYS_CTRL2: System control register for immediate reg - * DSP_CTRL0: Display control register0 - * DSP_CTRL2: Display control register2 - * VOP_STATUS: Some vop module status - * LINE_FLAG: Line flag config register - * INTR_EN: Interrupt enable register - * INTR_CLEAR: Interrupt clear register - * INTR_STATUS: Interrupt raw status and interrupt status - * WIN0_CTRL0: Win0 ctrl register0 - * WIN0_CTRL1: Win0 ctrl register1 - * WIN0_COLOR_KEY: Win0 color key register - * WIN0_VIR: Win0 virtual stride - * WIN0_YRGB_MST: Win0 YRGB memory start address - * WIN0_CBR_MST: Win0 Cbr memory start address - * WIN0_ACT_INFO: Win0 active window width/height - * WIN0_DSP_INFO: Win0 display width/height on panel - * WIN0_DSP_ST: Win0 display start point on panel - * WIN0_SCL_FACTOR_YRGB: Win0 YRGB scaling factor - * WIN0_SCL_FACTOR_CBR: Win0 Cbr scaling factor - * WIN0_SCL_OFFSET: Win0 scaling start point offset - * WIN0_ALPHA_CTRL: Win0 Blending control register - * WIN1_CTRL0: Win1 ctrl register0 - * WIN1_CTRL1: Win1 ctrl register1 - * WIN1_VIR: win1 virtual stride - * WIN1_YRGB_MST: Win1 frame buffer memory start address - * WIN1_DSP_INFO: Win1 display width/height on panel - * WIN1_DSP_ST: Win1 display start point on panel - * WIN1_COLOR_KEY: Win1 color key register - * WIN1_ALPHA_CTRL: Win1 Blending control register - * HWC_CTRL0: Hwc ctrl register0 - * HWC_CTRL1: Hwc ctrl register1 - * HWC_MST: Hwc memory start address - * HWC_DSP_ST: Hwc display start point on panel - * HWC_ALPHA_CTRL: Hwc blending control register - * DSP_HTOTAL_HS_END: Panel scanning horizontal width and hsync pulse end point - * DSP_HACT_ST_END: Panel active horizontal scanning start point and end point - * DSP_VTOTAL_VS_END: Panel scanning vertical height and vsync pulse end point - * DSP_VACT_ST_END: Panel active vertical scanning start point and end point - * DSP_VS_ST_END_F1: Vertical scanning start point and vsync pulse end point - * of even filed in interlace mode - * DSP_VACT_ST_END_F1: Vertical scanning active start point and end point of - * even filed in interlace mode - * BCSH_CTRL: BCSH contrl register - * BCSH_COLOR_BAR: Color bar config register - * BCSH_BCS: Brightness contrast saturation*contrast config register - * BCSH_H: Sin hue and cos hue config register - * FRC_LOWER01_0: FRC lookup table config register010 - * FRC_LOWER01_1: FRC lookup table config register011 - * FRC_LOWER10_0: FRC lookup table config register100 - * FRC_LOWER10_1: FRC lookup table config register101 - * FRC_LOWER11_0: FRC lookup table config register110 - * FRC_LOWER11_1: FRC lookup table config register111 - * DBG_REG_00: Current line number of dsp timing - * BLANKING_VALUE: The value of vsync blanking - * FLAG_REG_FRM_VALID: Flag reg value after frame valid - * FLAG_REG: Flag reg value before frame valid - * HWC_LUT_ADDR: Hwc lut base address - * GAMMA_LUT_ADDR: GAMMA lut base address - */ - -static inline u64 val_mask(int val, u64 msk, int shift) -{ - return (msk << (shift + 32)) | ((msk & val) << shift); -} - -#define VAL_MASK(x, width, shift) val_mask(x, (1 << width) - 1, shift) - -#define MASK(x) (V_##x(0) >> 32) - -#define REG_CFG_DONE 0x00000000 -#define V_REG_LOAD_GLOBAL_EN(x) VAL_MASK(x, 1, 0) -#define V_REG_LOAD_WIN0_EN(x) VAL_MASK(x, 1, 1) -#define V_REG_LOAD_WIN1_EN(x) VAL_MASK(x, 1, 2) -#define V_REG_LOAD_HWC_EN(x) VAL_MASK(x, 1, 3) -#define V_REG_LOAD_IEP_EN(x) VAL_MASK(x, 1, 4) -#define V_REG_LOAD_SYS_EN(x) VAL_MASK(x, 1, 5) -#define VERSION 0x00000004 -#define V_BUILD(x) VAL_MASK(x, 16, 0) -#define V_MINOR(x) VAL_MASK(x, 8, 16) -#define V_MAJOR(x) VAL_MASK(x, 8, 24) -#define DSP_BG 0x00000008 -#define V_DSP_BG_BLUE(x) VAL_MASK(x, 8, 0) -#define V_DSP_BG_GREEN(x) VAL_MASK(x, 8, 8) -#define V_DSP_BG_RED(x) VAL_MASK(x, 8, 16) -#define MCU_RESERVED 0x0000000c -#define SYS_CTRL0 0x00000010 -#define V_DIRECT_PATH_EN(x) VAL_MASK(x, 1, 0) -#define V_DIRECT_PATH_LAYER_SEL(x) VAL_MASK(x, 1, 1) -#define SYS_CTRL1 0x00000014 -#define V_SW_NOC_QOS_EN(x) VAL_MASK(x, 1, 0) -#define V_SW_NOC_QOS_VALUE(x) VAL_MASK(x, 2, 1) -#define V_SW_NOC_HURRY_EN(x) VAL_MASK(x, 1, 4) -#define V_SW_NOC_HURRY_VALUE(x) VAL_MASK(x, 2, 5) -#define V_SW_NOC_HURRY_THRESHOLD(x) VAL_MASK(x, 4, 8) -#define V_SW_AXI_MAX_OUTSTAND_EN(x) VAL_MASK(x, 1, 12) -#define V_SW_AXI_MAX_OUTSTAND_NUM(x) VAL_MASK(x, 5, 16) -#define SYS_CTRL2 0x00000018 -#define V_IMD_AUTO_GATING_EN(x) VAL_MASK(x, 1, 0) -#define V_IMD_VOP_STANDBY_EN(x) VAL_MASK(x, 1, 1) -#define V_IMD_VOP_DMA_STOP(x) VAL_MASK(x, 1, 2) -#define V_IMD_DSP_OUT_ZERO(x) VAL_MASK(x, 1, 3) -#define V_IMD_YUV_CLIP(x) VAL_MASK(x, 1, 4) -#define V_IMD_DSP_DATA_OUT_MODE(x) VAL_MASK(x, 1, 6) -#define V_SW_IO_PAD_CLK_SEL(x) VAL_MASK(x, 1, 7) -#define V_IMD_DSP_TIMING_IMD(x) VAL_MASK(x, 1, 12) -#define V_IMD_GLOBAL_REGDONE_EN(x) VAL_MASK(x, 1, 13) -#define V_FS_ADDR_MASK_EN(x) VAL_MASK(x, 1, 14) -#define DSP_CTRL0 0x00000020 -#define V_RGB_DCLK_EN(x) VAL_MASK(x, 1, 0) -#define V_RGB_DCLK_POL(x) VAL_MASK(x, 1, 1) -#define V_RGB_HSYNC_POL(x) VAL_MASK(x, 1, 2) -#define V_RGB_VSYNC_POL(x) VAL_MASK(x, 1, 3) -#define V_RGB_DEN_POL(x) VAL_MASK(x, 1, 4) -#define V_HDMI_DCLK_EN(x) VAL_MASK(x, 1, 8) -#define V_HDMI_DCLK_POL(x) VAL_MASK(x, 1, 9) -#define V_HDMI_HSYNC_POL(x) VAL_MASK(x, 1, 10) -#define V_HDMI_VSYNC_POL(x) VAL_MASK(x, 1, 11) -#define V_HDMI_DEN_POL(x) VAL_MASK(x, 1, 12) -#define V_SW_CORE_CLK_SEL(x) VAL_MASK(x, 1, 13) -#define V_SW_HDMI_CLK_I_SEL(x) VAL_MASK(x, 1, 14) -#define V_LVDS_DCLK_EN(x) VAL_MASK(x, 1, 16) -#define V_LVDS_DCLK_POL(x) VAL_MASK(x, 1, 17) -#define V_LVDS_HSYNC_POL(x) VAL_MASK(x, 1, 18) -#define V_LVDS_VSYNC_POL(x) VAL_MASK(x, 1, 19) -#define V_LVDS_DEN_POL(x) VAL_MASK(x, 1, 20) -#define V_MIPI_DCLK_EN(x) VAL_MASK(x, 1, 24) -#define V_MIPI_DCLK_POL(x) VAL_MASK(x, 1, 25) -#define V_MIPI_HSYNC_POL(x) VAL_MASK(x, 1, 26) -#define V_MIPI_VSYNC_POL(x) VAL_MASK(x, 1, 27) -#define V_MIPI_DEN_POL(x) VAL_MASK(x, 1, 28) -#define DSP_CTRL2 0x00000028 -#define V_DSP_INTERLACE(x) VAL_MASK(x, 1, 0) -#define V_INTERLACE_FIELD_POL(x) VAL_MASK(x, 1, 1) -#define V_DITHER_UP(x) VAL_MASK(x, 1, 2) -#define V_DSP_WIN0_TOP(x) VAL_MASK(x, 1, 3) -#define V_SW_OVERLAY_MODE(x) VAL_MASK(x, 1, 4) -#define V_DSP_LUT_EN(x) VAL_MASK(x, 1, 5) -#define V_DITHER_DOWN_MODE(x) VAL_MASK(x, 1, 6) -#define V_DITHER_DOWN_SEL(x) VAL_MASK(x, 1, 7) -#define V_DITHER_DOWN(x) VAL_MASK(x, 1, 8) -#define V_DSP_BG_SWAP(x) VAL_MASK(x, 1, 9) -#define V_DSP_DELTA_SWAP(x) VAL_MASK(x, 1, 10) -#define V_DSP_RB_SWAP(x) VAL_MASK(x, 1, 11) -#define V_DSP_RG_SWAP(x) VAL_MASK(x, 1, 12) -#define V_DSP_DUMMY_SWAP(x) VAL_MASK(x, 1, 13) -#define V_DSP_BLANK_EN(x) VAL_MASK(x, 1, 14) -#define V_DSP_BLACK_EN(x) VAL_MASK(x, 1, 15) -#define V_DSP_OUT_MODE(x) VAL_MASK(x, 4, 16) -#define VOP_STATUS 0x0000002c -#define V_DSP_BLANKING_EN_ASYNC_AFF2(x) VAL_MASK(x, 1, 0) -#define V_IDLE_MMU_FF1(x) VAL_MASK(x, 1, 1) -#define V_INT_RAW_DMA_FINISH(x) VAL_MASK(x, 1, 2) -#define V_DMA_STOP_VALID(x) VAL_MASK(x, 1, 4) -#define LINE_FLAG 0x00000030 -#define V_DSP_LINE_FLAG0_NUM(x) VAL_MASK(x, 12, 0) -#define V_DSP_LINE_FLAG1_NUM(x) VAL_MASK(x, 12, 16) -#define INTR_EN 0x00000034 -#define V_FS0_INTR_EN(x) VAL_MASK(x, 1, 0) -#define V_FS1_INTR_EN(x) VAL_MASK(x, 1, 1) -#define V_ADDR_SAME_INTR_EN(x) VAL_MASK(x, 1, 2) -#define V_LINE_FLAG0_INTR_EN(x) VAL_MASK(x, 1, 3) -#define V_LINE_FLAG1_INTR_EN(x) VAL_MASK(x, 1, 4) -#define V_BUS_ERROR_INTR_EN(x) VAL_MASK(x, 1, 5) -#define V_WIN0_EMPTY_INTR_EN(x) VAL_MASK(x, 1, 6) -#define V_WIN1_EMPTY_INTR_EN(x) VAL_MASK(x, 1, 7) -#define V_DSP_HOLD_VALID_INTR_EN(x) VAL_MASK(x, 1, 8) -#define V_DMA_FRM_FSH_INTR_EN(x) VAL_MASK(x, 1, 9) -#define INTR_CLEAR 0x00000038 -#define V_FS0_INTR_CLR(x) VAL_MASK(x, 1, 0) -#define V_FS1_INTR_CLR(x) VAL_MASK(x, 1, 1) -#define V_ADDR_SAME_INTR_CLR(x) VAL_MASK(x, 1, 2) -#define V_LINE_FLAG0_INTR_CLR(x) VAL_MASK(x, 1, 3) -#define V_LINE_FLAG1_INTR_CLR(x) VAL_MASK(x, 1, 4) -#define V_BUS_ERROR_INTR_CLR(x) VAL_MASK(x, 1, 5) -#define V_WIN0_EMPTY_INTR_CLR(x) VAL_MASK(x, 1, 6) -#define V_WIN1_EMPTY_INTR_CLR(x) VAL_MASK(x, 1, 7) -#define V_DSP_HOLD_VALID_INTR_CLR(x) VAL_MASK(x, 1, 8) -#define V_DMA_FRM_FSH_INTR_CLR(x) VAL_MASK(x, 1, 9) -#define INTR_STATUS 0x0000003c -#define V_FS0_INTR_STS(x) VAL_MASK(x, 1, 0) -#define V_FS1_INTR_STS(x) VAL_MASK(x, 1, 1) -#define V_ADDR_SAME_INTR_STS(x) VAL_MASK(x, 1, 2) -#define V_LINE_FLAG0_INTR_STS(x) VAL_MASK(x, 1, 3) -#define V_LINE_FLAG1_INTR_STS(x) VAL_MASK(x, 1, 4) -#define V_BUS_ERROR_INTR_STS(x) VAL_MASK(x, 1, 5) -#define V_WIN0_EMPTY_INTR_STS(x) VAL_MASK(x, 1, 6) -#define V_WIN1_EMPTY_INTR_STS(x) VAL_MASK(x, 1, 7) -#define V_DSP_HOLD_VALID_INTR_STS(x) VAL_MASK(x, 1, 8) -#define V_DMA_FRM_FSH_INTR_STS(x) VAL_MASK(x, 1, 9) -#define V_MMU_INTR_STATUS(x) VAL_MASK(x, 1, 15) -#define V_FS0_INTR_RAW_STS(x) VAL_MASK(x, 1, 16) -#define V_FS1_INTR_RAW_STS(x) VAL_MASK(x, 1, 17) -#define V_ADDR_SAME_INTR_RAW_STS(x) VAL_MASK(x, 1, 18) -#define V_LINE_FLAG0_INTR_RAW_STS(x) VAL_MASK(x, 1, 19) -#define V_LINE_FLAG1_INTR_RAW_STS(x) VAL_MASK(x, 1, 20) -#define V_BUS_ERROR_INTR_RAW_STS(x) VAL_MASK(x, 1, 21) -#define V_WIN0_EMPTY_INTR_RAW_STS(x) VAL_MASK(x, 1, 22) -#define V_WIN1_EMPTY_INTR_RAW_STS(x) VAL_MASK(x, 1, 23) -#define V_DSP_HOLD_VALID_INTR_RAW_STS(x) VAL_MASK(x, 1, 24) -#define V_DMA_FRM_FSH_INTR_RAW_STS(x) VAL_MASK(x, 1, 25) -#define WIN0_CTRL0 0x00000050 -#define V_WIN0_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN0_DATA_FMT(x) VAL_MASK(x, 3, 1) -#define V_WIN0_INTERLACE_READ(x) VAL_MASK(x, 1, 8) -#define V_WIN0_NO_OUTSTANDING(x) VAL_MASK(x, 1, 9) -#define V_WIN0_CSC_MODE(x) VAL_MASK(x, 2, 10) -#define V_WIN0_RB_SWAP(x) VAL_MASK(x, 1, 12) -#define V_WIN0_ALPHA_SWAP(x) VAL_MASK(x, 1, 13) -#define V_WIN0_MID_SWAP(x) VAL_MASK(x, 1, 14) -#define V_WIN0_UV_SWAP(x) VAL_MASK(x, 1, 15) -#define V_WIN0_YRGB_DEFLICK(x) VAL_MASK(x, 1, 18) -#define V_WIN0_CBR_DEFLICK(x) VAL_MASK(x, 1, 19) -#define WIN0_CTRL1 0x00000054 -#define V_WIN0_YRGB_AXI_GATHER_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN0_CBR_AXI_GATHER_EN(x) VAL_MASK(x, 1, 1) -#define V_WIN0_DMA_BURST_LENGTH(x) VAL_MASK(x, 2, 2) -#define V_WIN0_YRGB_AXI_GATHER_NUM(x) VAL_MASK(x, 4, 4) -#define V_WIN0_CBR_AXI_GATHER_NUM(x) VAL_MASK(x, 3, 8) -#define V_SW_WIN0_YRGB0_RID(x) VAL_MASK(x, 4, 12) -#define V_SW_WIN0_CBR0_RID(x) VAL_MASK(x, 4, 16) -#define WIN0_COLOR_KEY 0x00000058 -#define V_WIN0_KEY_COLOR(x) VAL_MASK(x, 24, 0) -#define V_WIN0_KEY_EN(x) VAL_MASK(x, 1, 24) -#define WIN0_VIR 0x0000005c -#define V_WIN0_YRGB_VIR_STRIDE(x) VAL_MASK(x, 13, 0) -#define V_WIN0_CBR_VIR_STRIDE(x) VAL_MASK(x, 13, 16) -#define WIN0_YRGB_MST 0x00000060 -#define WIN0_CBR_MST 0x00000064 -#define WIN0_ACT_INFO 0x00000068 -#define V_WIN0_ACT_WIDTH(x) VAL_MASK(x, 13, 0) -#define V_WIN0_ACT_HEIGHT(x) VAL_MASK(x, 13, 16) -#define WIN0_DSP_INFO 0x0000006c -#define V_WIN0_DSP_WIDTH(x) VAL_MASK(x, 11, 0) -#define V_WIN0_DSP_HEIGHT(x) VAL_MASK(x, 11, 16) -#define WIN0_DSP_ST 0x00000070 -#define V_WIN0_DSP_XST(x) VAL_MASK(x, 12, 0) -#define V_WIN0_DSP_YST(x) VAL_MASK(x, 12, 16) -#define WIN0_SCL_FACTOR_YRGB 0x00000074 -#define V_WIN0_HS_FACTOR_YRGB(x) VAL_MASK(x, 16, 0) -#define V_WIN0_VS_FACTOR_YRGB(x) VAL_MASK(x, 16, 16) -#define WIN0_SCL_FACTOR_CBR 0x00000078 -#define V_WIN0_HS_FACTOR_CBR(x) VAL_MASK(x, 16, 0) -#define V_WIN0_VS_FACTOR_CBR(x) VAL_MASK(x, 16, 16) -#define WIN0_SCL_OFFSET 0x0000007c -#define V_WIN0_HS_OFFSET_YRGB(x) VAL_MASK(x, 8, 0) -#define V_WIN0_HS_OFFSET_CBR(x) VAL_MASK(x, 8, 8) -#define V_WIN0_VS_OFFSET_YRGB(x) VAL_MASK(x, 8, 16) -#define V_WIN0_VS_OFFSET_CBR(x) VAL_MASK(x, 8, 24) -#define WIN0_ALPHA_CTRL 0x00000080 -#define V_WIN0_ALPHA_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN0_ALPHA_MODE(x) VAL_MASK(x, 1, 1) -#define V_WIN0_ALPHA_PRE_MUL(x) VAL_MASK(x, 1, 2) -#define V_WIN0_ALPHA_SAT_MODE(x) VAL_MASK(x, 1, 3) -#define V_WIN0_ALPHA_VALUE(x) VAL_MASK(x, 8, 4) -#define WIN1_CTRL0 0x00000090 -#define V_WIN1_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN1_CSC_MODE(x) VAL_MASK(x, 1, 2) -#define V_WIN1_DATA_FMT(x) VAL_MASK(x, 3, 4) -#define V_WIN1_INTERLACE_READ(x) VAL_MASK(x, 1, 8) -#define V_WIN1_NO_OUTSTANDING(x) VAL_MASK(x, 1, 9) -#define V_WIN1_RB_SWAP(x) VAL_MASK(x, 1, 12) -#define V_WIN1_ALPHA_SWAP(x) VAL_MASK(x, 1, 13) -#define V_WIN1_ENDIAN_SWAP(x) VAL_MASK(x, 1, 14) -#define WIN1_CTRL1 0x00000094 -#define V_WIN1_AXI_GATHER_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN1_DMA_BURST_LENGTH(x) VAL_MASK(x, 2, 2) -#define V_WIN1_AXI_GATHER_NUM(x) VAL_MASK(x, 4, 4) -#define V_SW_WIN1_RID(x) VAL_MASK(x, 4, 8) -#define WIN1_VIR 0x00000098 -#define V_WIN1_VIR_STRIDE(x) VAL_MASK(x, 13, 0) -#define WIN1_YRGB_MST 0x000000a0 -#define WIN1_DSP_INFO 0x000000a4 -#define V_WIN1_DSP_WIDTH(x) VAL_MASK(x, 11, 0) -#define V_WIN1_DSP_HEIGHT(x) VAL_MASK(x, 11, 16) -#define WIN1_DSP_ST 0x000000a8 -#define V_WIN1_DSP_XST(x) VAL_MASK(x, 12, 0) -#define V_WIN1_DSP_YST(x) VAL_MASK(x, 12, 16) -#define WIN1_COLOR_KEY 0x000000ac -#define V_WIN1_KEY_COLOR(x) VAL_MASK(x, 24, 0) -#define V_WIN1_KEY_EN(x) VAL_MASK(x, 1, 24) -#define WIN1_ALPHA_CTRL 0x000000bc -#define V_WIN1_ALPHA_EN(x) VAL_MASK(x, 1, 0) -#define V_WIN1_ALPHA_MODE(x) VAL_MASK(x, 1, 1) -#define V_WIN1_ALPHA_PRE_MUL(x) VAL_MASK(x, 1, 2) -#define V_WIN1_ALPHA_SAT_MODE(x) VAL_MASK(x, 1, 3) -#define V_WIN1_ALPHA_VALUE(x) VAL_MASK(x, 8, 4) -#define HWC_CTRL0 0x000000e0 -#define V_HWC_EN(x) VAL_MASK(x, 1, 0) -#define V_HWC_SIZE(x) VAL_MASK(x, 1, 1) -#define V_HWC_LOAD_EN(x) VAL_MASK(x, 1, 2) -#define V_HWC_LUT_EN(x) VAL_MASK(x, 1, 3) -#define V_SW_HWC_RID(x) VAL_MASK(x, 4, 4) -#define HWC_CTRL1 0x000000e4 -#define HWC_MST 0x000000e8 -#define HWC_DSP_ST 0x000000ec -#define V_HWC_DSP_XST(x) VAL_MASK(x, 12, 0) -#define V_HWC_DSP_YST(x) VAL_MASK(x, 12, 16) -#define HWC_ALPHA_CTRL 0x000000f0 -#define V_HWC_ALPHA_EN(x) VAL_MASK(x, 1, 0) -#define V_HWC_ALPHA_MODE(x) VAL_MASK(x, 1, 1) -#define V_HWC_ALPHA_PRE_MUL(x) VAL_MASK(x, 1, 2) -#define V_HWC_ALPHA_SAT_MODE(x) VAL_MASK(x, 1, 3) -#define V_HWC_ALPHA_VALUE(x) VAL_MASK(x, 8, 4) -#define DSP_HTOTAL_HS_END 0x00000100 -#define V_DSP_HS_END(x) VAL_MASK(x, 12, 0) -#define V_DSP_HTOTAL(x) VAL_MASK(x, 12, 16) -#define DSP_HACT_ST_END 0x00000104 -#define V_DSP_HACT_END(x) VAL_MASK(x, 12, 0) -#define V_DSP_HACT_ST(x) VAL_MASK(x, 12, 16) -#define DSP_VTOTAL_VS_END 0x00000108 -#define V_DSP_VS_END(x) VAL_MASK(x, 12, 0) -#define V_DSP_VTOTAL(x) VAL_MASK(x, 12, 16) -#define DSP_VACT_ST_END 0x0000010c -#define V_DSP_VACT_END(x) VAL_MASK(x, 12, 0) -#define V_DSP_VACT_ST(x) VAL_MASK(x, 12, 16) -#define DSP_VS_ST_END_F1 0x00000110 -#define V_DSP_VS_END_F1(x) VAL_MASK(x, 12, 0) -#define V_DSP_VS_ST_F1(x) VAL_MASK(x, 12, 16) -#define DSP_VACT_ST_END_F1 0x00000114 -#define V_DSP_VACT_END_F1(x) VAL_MASK(x, 12, 0) -#define V_DSP_VACT_ST_F1(x) VAL_MASK(x, 12, 16) -#define BCSH_CTRL 0x00000160 -#define V_BCSH_EN(x) VAL_MASK(x, 1, 0) -#define V_SW_BCSH_R2Y_CSC_MODE(x) VAL_MASK(x, 1, 1) -#define V_VIDEO_MODE(x) VAL_MASK(x, 2, 2) -#define V_SW_BCSH_Y2R_CSC_MODE(x) VAL_MASK(x, 2, 4) -#define V_SW_BCSH_Y2R_EN(x) VAL_MASK(x, 1, 6) -#define V_SW_BCSH_R2Y_EN(x) VAL_MASK(x, 1, 7) -#define BCSH_COL_BAR 0x00000164 -#define V_COLOR_BAR_Y(x) VAL_MASK(x, 8, 0) -#define V_COLOR_BAR_U(x) VAL_MASK(x, 8, 8) -#define V_COLOR_BAR_V(x) VAL_MASK(x, 8, 16) -#define BCSH_BCS 0x00000168 -#define V_BRIGHTNESS(x) VAL_MASK(x, 6, 0) -#define V_CONTRAST(x) VAL_MASK(x, 8, 8) -#define V_SAT_CON(x) VAL_MASK(x, 9, 16) -#define BCSH_H 0x0000016c -#define V_SIN_HUE(x) VAL_MASK(x, 8, 0) -#define V_COS_HUE(x) VAL_MASK(x, 8, 8) -#define FRC_LOWER01_0 0x00000170 -#define V_LOWER01_FRM0(x) VAL_MASK(x, 16, 0) -#define V_LOWER01_FRM1(x) VAL_MASK(x, 16, 16) -#define FRC_LOWER01_1 0x00000174 -#define V_LOWER01_FRM2(x) VAL_MASK(x, 16, 0) -#define V_LOWER01_FRM3(x) VAL_MASK(x, 16, 16) -#define FRC_LOWER10_0 0x00000178 -#define V_LOWER10_FRM0(x) VAL_MASK(x, 16, 0) -#define V_LOWER10_FRM1(x) VAL_MASK(x, 16, 16) -#define FRC_LOWER10_1 0x0000017c -#define V_LOWER10_FRM2(x) VAL_MASK(x, 16, 0) -#define V_LOWER10_FRM3(x) VAL_MASK(x, 16, 16) -#define FRC_LOWER11_0 0x00000180 -#define V_LOWER11_FRM0(x) VAL_MASK(x, 16, 0) -#define V_LOWER11_FRM1(x) VAL_MASK(x, 16, 16) -#define FRC_LOWER11_1 0x00000184 -#define V_LOWER11_FRM2(x) VAL_MASK(x, 16, 0) -#define V_LOWER11_FRM3(x) VAL_MASK(x, 16, 16) -#define DBG_REG_000 0x00000190 -#define BLANKING_VALUE 0x000001f4 -#define V_SW_BLANKING_VALUE(x) VAL_MASK(x, 24, 0) -#define V_BLANKING_VALUE_CONFIG_EN(x) VAL_MASK(x, 1, 24) -#define FLAG_REG_FRM_VALID 0x000001f8 -#define FLAG_REG 0x000001fc -#define HWC_LUT_ADDR 0x00000600 -#define GAMMA_LUT_ADDR 0x00000a00 -#define MMU_DTE_ADDR 0x00000f00 -#define MMU_STATUS 0x00000f04 -#define V_PAGING_ENABLED(x) VAL_MASK(x, 1, 0) -#define V_PAGE_FAULT_ACTIVE(x) VAL_MASK(x, 1, 1) -#define V_STAIL_ACTIVE(x) VAL_MASK(x, 1, 2) -#define V_MMU_IDLE(x) VAL_MASK(x, 1, 3) -#define V_REPLAY_BUFFER_EMPTY(x) VAL_MASK(x, 1, 4) -#define V_PAGE_FAULT_IS_WRITE(x) VAL_MASK(x, 1, 5) -#define MMU_COMMAND 0x00000f08 -#define MMU_PAGE_FAULT_ADDR 0x00000f0c -#define MMU_ZAP_ONE_LINE 0x00000f10 -#define MMU_INT_RAWSTAT 0x00000f14 -#define V_PAGE_FAULT(x) VAL_MASK(x, 1, 0) -#define MMU_INT_CLEAR 0x00000f18 -#define V_PAGE_FAULT(x) VAL_MASK(x, 1, 0) -#define MMU_INT_MASK 0x00000f1c -#define V_PAGE_FAULT(x) VAL_MASK(x, 1, 0) -#define MMU_INT_STATUS 0x00000f20 -#define V_PAGE_FAULT(x) VAL_MASK(x, 1, 0) -#define MMU_AUTO_GATING 0x00000f24 -#define V_MMU_AUTO_GATING(x) VAL_MASK(x, 1, 0) -#define MMU_CFG_DONE 0x00000f28 - -#define INTR_FS0 BIT(0) -#define INTR_FS1 BIT(1) -#define INTR_ADDR_SAME BIT(2) -#define INTR_LINE_FLAG0 BIT(3) -#define INTR_LINE_FLAG1 BIT(4) -#define INTR_BUS_ERROR BIT(5) -#define INTR_WIN0_EMPTY BIT(6) -#define INTR_WIN1_EMPTY BIT(7) -#define INTR_DSP_HOLD_VALID BIT(8) -#define INTR_DMA_FINISH BIT(9) -#define INTR_MMU_STATUS BIT(15) - -#define INTR_MASK (INTR_FS0 | INTR_FS1 | INTR_ADDR_SAME | INTR_LINE_FLAG0 | \ - INTR_LINE_FLAG1 | INTR_BUS_ERROR | INTR_WIN0_EMPTY | \ - INTR_WIN1_EMPTY | INTR_DSP_HOLD_VALID | INTR_DMA_FINISH) - -/* GRF register for VOP source select */ -#define GRF_WEN_SHIFT(x) (BIT(x) << 16) - -#define GRF_SOC_CON0 0x0400 -#define V_LVDS_VOP_SEL(x) (((x) << 0) | GRF_WEN_SHIFT(0)) -#define V_HDMI_VOP_SEL(x) (((x) << 1) | GRF_WEN_SHIFT(1)) -#define V_DSI0_VOP_SEL(x) (((x) << 2) | GRF_WEN_SHIFT(2)) - -#define GRF_SOC_CON5 0x0414 -#define V_RGB_VOP_SEL(x) (((x) << 4) | GRF_WEN_SHIFT(4)) - -#define GRF_IO_VSEL 0x0900 -#define V_VOP_IOVOL_SEL(x) (((x) << 0) | GRF_WEN_SHIFT(0)) - -struct vop_sync_obj_s { - struct completion stdbyfin; /* standby finish */ - int stdbyfin_to; - struct completion frmst; /* frame start */ - int frmst_to; -}; - -struct vop_device { - int id; - struct rk_lcdc_driver driver; - struct device *dev; - struct rk_screen *screen; - - void __iomem *regs; - void *regsbak; - u32 reg_phy_base; - u32 len; - void __iomem *hwc_lut_addr_base; - void __iomem *dsp_lut_addr_base; - struct regmap *grf_base; - - /* one time only one process allowed to config the register */ - spinlock_t reg_lock; - - int prop; /* used for primary or extended display device */ - bool pre_init; - bool pwr18; /* if lcdc use 1.8v power supply */ - /* if aclk or hclk is closed, access to register is not allowed */ - bool clk_on; - /* active layer counter,when atv_layer_cnt = 0,disable lcdc */ - u8 atv_layer_cnt; - - unsigned int irq; - - struct clk *hclk; /* lcdc AHP clk */ - struct clk *dclk; /* lcdc dclk */ - struct clk *aclk; /* lcdc share memory frequency */ - u32 pixclock; - - u32 standby; /* 1:standby,0:wrok */ - u32 iommu_status; - struct backlight_device *backlight; - - /* lock vop irq reg */ - spinlock_t irq_lock; - struct vop_sync_obj_s sync; -}; - -static inline int vop_completion_timeout_ms(struct completion *comp, int to) -{ - long jiffies = msecs_to_jiffies(to); - - return wait_for_completion_timeout(comp, jiffies); -} - -static inline void vop_writel(struct vop_device *vop_dev, u32 offset, u32 v) -{ - u32 *_pv = (u32 *)vop_dev->regsbak; - - _pv += (offset >> 2); - *_pv = v; - writel_relaxed(v, vop_dev->regs + offset); -} - -static inline u32 vop_readl(struct vop_device *vop_dev, u32 offset) -{ - u32 v; - - v = readl_relaxed(vop_dev->regs + offset); - return v; -} - -static inline u32 vop_readl_backup(struct vop_device *vop_dev, u32 offset) -{ - u32 v; - u32 *_pv = (u32 *)vop_dev->regsbak; - - _pv += (offset >> 2); - v = readl_relaxed(vop_dev->regs + offset); - *_pv = v; - return v; -} - -static inline u32 vop_read_bit(struct vop_device *vop_dev, u32 offset, u64 v) -{ - u32 _v = readl_relaxed(vop_dev->regs + offset); - - _v &= v >> 32; - v = (_v ? 1 : 0); - return v; -} - -static inline void vop_set_bit(struct vop_device *vop_dev, u32 offset, u64 v) -{ - u32 *_pv = (u32 *)vop_dev->regsbak; - - _pv += (offset >> 2); - (*_pv) |= v >> 32; - writel_relaxed(*_pv, vop_dev->regs + offset); -} - -static inline void vop_clr_bit(struct vop_device *vop_dev, u32 offset, u64 v) -{ - u32 *_pv = (u32 *)vop_dev->regsbak; - - _pv += (offset >> 2); - (*_pv) &= (~(v >> 32)); - writel_relaxed(*_pv, vop_dev->regs + offset); -} - -static inline void vop_msk_reg(struct vop_device *vop_dev, u32 offset, u64 v) -{ - u32 *_pv = (u32 *)vop_dev->regsbak; - - _pv += (offset >> 2); - (*_pv) &= (~(v >> 32)); - (*_pv) |= (u32)v; - writel_relaxed(*_pv, vop_dev->regs + offset); -} - -static inline void vop_mask_writel(struct vop_device *vop_dev, u32 offset, - u32 mask, u32 v) -{ - v = mask << 16 | v; - writel_relaxed(v, vop_dev->regs + offset); -} - -static inline void vop_cfg_done(struct vop_device *vop_dev) -{ - writel_relaxed(0x001f001f, vop_dev->regs + REG_CFG_DONE); - dsb(sy); -} - -static inline int vop_grf_writel(struct regmap *base, u32 offset, u32 val) -{ - if (base) - regmap_write(base, offset, val); - dsb(sy); - - return 0; -} - -static inline int vop_cru_writel(struct regmap *base, u32 offset, u32 val) -{ - if (base) - regmap_write(base, offset, val); - dsb(sy); - - return 0; -} - -static inline int vop_cru_readl(struct regmap *base, u32 offset) -{ - u32 v; - - if (base) - regmap_read(base, offset, &v); - - return v; -} - -enum dither_down_mode { - DITHER_888_565 = 0x0, - DITHER_888_666 = 0x1, -}; - -enum dither_down_sel { - DITHER_SEL_ALLEGRO = 0x0, - DITHER_SEL_FRC = 0x1, -}; - -enum _vop_r2y_csc_mode { - VOP_R2Y_CSC_BT601 = 0, - VOP_R2Y_CSC_BT709 -}; - -enum _vop_y2r_csc_mode { - VOP_Y2R_CSC_MPEG = 0, - VOP_Y2R_CSC_HD, - VOP_Y2R_CSC_JPEG, - VOP_Y2R_CSC_BYPASS -}; - -enum _vop_format { - VOP_FORMAT_ARGB888 = 0, - VOP_FORMAT_RGB888, - VOP_FORMAT_RGB565, - VOP_FORMAT_YCBCR420 = 4, - VOP_FORMAT_YCBCR422, - VOP_FORMAT_YCBCR444 -}; - -enum _bcsh_video_mode { - BCSH_MODE_BLACK = 0, - BCSH_MODE_BLUE, - BCSH_MODE_COLORBAR, - BCSH_MODE_VIDEO, -}; - -#define IS_YUV(x) ((x) >= VOP_FORMAT_YCBCR420) - -enum _vop_overlay_mode { - VOP_RGB_DOMAIN, - VOP_YUV_DOMAIN -}; - -/*************************************************************/ -#define CALSCALE(x, y) \ - (1 == (y) ? 0x1000 : ((((u32)((x) - 1)) * 0x1000) / ((y) - 1))) - -#endif diff --git a/drivers/video/rockchip/rk_fb.c b/drivers/video/rockchip/rk_fb.c deleted file mode 100644 index 45b9569d7ed7..000000000000 --- a/drivers/video/rockchip/rk_fb.c +++ /dev/null @@ -1,4723 +0,0 @@ -/* - * drivers/video/rockchip/rk_fb.c - * - * Copyright (C) ROCKCHIP, Inc. - * Author:yxj - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "bmp_helper.h" - -#if defined(CONFIG_RK_HDMI) -#include "hdmi/rockchip-hdmi.h" -#endif - -#if defined(CONFIG_ROCKCHIP_RGA) || defined(CONFIG_ROCKCHIP_RGA2) -#include "rga/rga.h" -#endif - -#ifdef CONFIG_OF -#include -#include -#include -#include