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mtd: spi-nor: winbond: Add support for W25Q64PW-M

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There is an ID collision with chips of same density from the JW family
(which it self conflicted with yet another family). Chips are very
similar in practice, it is mostly a matter of electrical differences
(mostly power consumption being lower) as well as the addition of inline
ECC capability.

16 bytes chunks are protected against single errors. In case a
non-aligned write happens, ECC is locally disabled until the next erase.

Another significant difference is that PW chips identify themselves as
supporting the new SFDP (rev F) QER field which forces an alternate
write SR2 opcode (0x31).

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Michael Walle <mwalle@kernel.org>
This commit is contained in:
Miquel Raynal 2026-09-21 08:43:54 +02:00 committed by Michael Walle
parent 03613e40f1
commit d96b00b230
1 changed files with 1 additions and 1 deletions
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2
drivers/mtd/spi-nor/winbond.c
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@ -475,7 +475,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.otp = SNOR_OTP(256, 3, 0x1000, 0x1000),
}, {
/* W25Q64JW-M */
/* W25Q64JW-M, W25Q64PW-M */
.id = SNOR_ID(0xef, 0x80, 0x17),
.name = "w25q64jwm",
.size = SZ_8M,