From d96b00b230d0512844d0e9c9bc391cdc30ab653b Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 21 Sep 2026 08:43:54 +0200 Subject: [PATCH] mtd: spi-nor: winbond: Add support for W25Q64PW-M There is an ID collision with chips of same density from the JW family (which it self conflicted with yet another family). Chips are very similar in practice, it is mostly a matter of electrical differences (mostly power consumption being lower) as well as the addition of inline ECC capability. 16 bytes chunks are protected against single errors. In case a non-aligned write happens, ECC is locally disabled until the next erase. Another significant difference is that PW chips identify themselves as supporting the new SFDP (rev F) QER field which forces an alternate write SR2 opcode (0x31). Signed-off-by: Miquel Raynal Signed-off-by: Michael Walle --- drivers/mtd/spi-nor/winbond.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index c56bb01c197b..6bb0f2bda14c 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -475,7 +475,7 @@ static const struct flash_info winbond_nor_parts[] = { .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, .otp = SNOR_OTP(256, 3, 0x1000, 0x1000), }, { - /* W25Q64JW-M */ + /* W25Q64JW-M, W25Q64PW-M */ .id = SNOR_ID(0xef, 0x80, 0x17), .name = "w25q64jwm", .size = SZ_8M,