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arm64: dts: mediatek: mt8195: Add and use UART AP_DMA controller

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This SoC has a DMA controller (AP_DMA) that provides one channel
for each data direction (transmit and receive) for all of the
UART controllers in the SoC.

In order to increase the efficiency of data TX/RX over the UART
controllers, add the UART DMA controller and assign the right
channels to each uart controller.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
AngeloGioacchino Del Regno 2026-07-09 11:09:24 +02:00
parent f0c918fe24
commit d8461fe07c
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GPG Key ID: 9A3604CFAD978478
1 changed files with 37 additions and 0 deletions
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37
arch/arm64/boot/dts/mediatek/mt8195.dtsi
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@ -904,6 +904,31 @@ spmi: spmi@10027000 {
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
};
apdma: dma-controller@10220880 {
compatible = "mediatek,mt8195-uart-dma", "mediatek,mt6835-uart-dma";
reg = <0 0x10220880 0 0x80>, <0 0x10220900 0 0x80>,
<0 0x10220980 0 0x80>, <0 0x10220a00 0 0x80>,
<0 0x10220a80 0 0x80>, <0 0x10220b00 0 0x80>,
<0 0x10220b80 0 0x80>, <0 0x10220c00 0 0x80>,
<0 0x10220c80 0 0x80>, <0 0x10220d00 0 0x80>,
<0 0x10220d80 0 0x80>, <0 0x10220e00 0 0x80>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
#dma-cells = <1>;
dma-requests = <12>;
};
iommu_infra: infra-iommu@10315000 {
compatible = "mediatek,mt8195-iommu-infra";
reg = <0 0x10315000 0 0x5000>;
@ -1040,6 +1065,8 @@ uart0: serial@11001100 {
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
clock-names = "baud", "bus";
dmas = <&apdma 0>, <&apdma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1050,6 +1077,8 @@ uart1: serial@11001200 {
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
clock-names = "baud", "bus";
dmas = <&apdma 2>, <&apdma 3>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1060,6 +1089,8 @@ uart2: serial@11001300 {
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
clock-names = "baud", "bus";
dmas = <&apdma 4>, <&apdma 5>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1070,6 +1101,8 @@ uart3: serial@11001400 {
interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
clock-names = "baud", "bus";
dmas = <&apdma 6>, <&apdma 7>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1080,6 +1113,8 @@ uart4: serial@11001500 {
interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
clock-names = "baud", "bus";
dmas = <&apdma 8>, <&apdma 9>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1090,6 +1125,8 @@ uart5: serial@11001600 {
interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
clock-names = "baud", "bus";
dmas = <&apdma 10>, <&apdma 11>;
dma-names = "tx", "rx";
status = "disabled";
};