github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-09-25 17:42:03 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm64: dts: mediatek: mt8192: Add and use UART AP_DMA controller

Browse Source 
This SoC has a DMA controller (AP_DMA) that provides one channel
for each data direction (transmit and receive) for all of the
UART controllers in the SoC.

In order to increase the efficiency of data TX/RX over the UART
controllers, add the UART DMA controller and assign the right
channels to its two uart controllers.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
AngeloGioacchino Del Regno 2026-07-09 11:09:23 +02:00
parent f58f969218
commit f0c918fe24
No known key found for this signature in database
GPG Key ID: 9A3604CFAD978478
1 changed files with 17 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
arch/arm64/boot/dts/mediatek/mt8192.dtsi
View File

@ -741,6 +741,19 @@ spmi: spmi@10027000 {
assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
};
apdma: dma-controller@10217a80 {
compatible = "mediatek,mt8192-uart-dma", "mediatek,mt6835-uart-dma";
reg = <0 0x10217a80 0 0x80>, <0 0x10217b00 0 0x80>,
<0 0x10217b80 0 0x80>, <0 0x10217c00 0 0x80>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg CLK_INFRA_AP_DMA>;
#dma-cells = <1>;
dma-requests = <4>;
};
gce: mailbox@10228000 {
compatible = "mediatek,mt8192-gce";
reg = <0 0x10228000 0 0x4000>;
@ -765,6 +778,8 @@ uart0: serial@11002000 {
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
dmas = <&apdma 0>, <&apdma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -775,6 +790,8 @@ uart1: serial@11003000 {
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
clock-names = "baud", "bus";
dmas = <&apdma 2>, <&apdma 3>;
dma-names = "tx", "rx";
status = "disabled";
};