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TI K3 device tree updates for v6.13
Generic Fixups/Cleanups: - Cleanup bootph-* tags to limit to leaf nodes only - clock IDs for MCSPI instances fixed up across J7xx family - Misc indentation and whitespace cleanup across dts New SoC - J742s2 which is a cutdown of existing J784s4 and uses same EVM SoC Specific features and Fixes: - eQEP (counter) support across AM64/AM62/AM62A AM64 - M4F Remoteproc support - stats collection support for ICSSGs via ti,pa-stats - Add PCIe EP overlays AM65 - stats collection support for ICSSGs via ti,pa-stats AM62: - M4F Remoteproc support - eMMC/SD TAP value updates - dtbs_check fixes for opp_efuse_table AM62A - 1.4GHz opp entry AM62P - 1.4GHz opp entry J7200 - Add PCIe EP overlays - Pinmux node reg range fixes Board Specific AM62 - am62 verdin ivy carrier board support - am625-verdin TPM device support - am62 verdin ivy board support - Beagleplay Mikrobus PWM header support - am62-verdin increase SD regulator startup delay AM64 - am642-phyboard-electra-rdk trickle charger support - am64-phy* drop buswidth from sdhci nodes -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEEyRC2zAhGcGjrhiNExEYeRXyRFuMFAmcp9KAQHHZpZ25lc2hy QHRpLmNvbQAKCRDERh5FfJEW40WlCAClaeiGzfL3a9da/KtAeee7H7Q+XWbjZod9 rysiexvCisp+aG9XUnHgS+zuiyYXHBRwpXVnOF5tKxrcOvmxloqOLr/5ZjWCtJKT efCrgAmZfpwnBXlNQzUwYVmJ5j1hOTVowa01uMVZd5vGwMa+GUjaZe+jakbI+EOn 4F7dlNW6YTnwFvpyIiFCkVd3vXLNYNmpsbOT+ax6+uuRzDJ7z4QFQuWNvHLy/c9r HG6AUXLR8EB2+MhJVSp41mrh8N4Tdwledtbs+VbzMMvMzlErMpx9AEeqOqp9cmo7 vNGXu5K/Abaozp1PryaxH1r0OPpKxL1nyUZ5xT9FpuXI0NpTxAuk =E9iT -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmczzh8ACgkQYKtH/8kJ Uid1jg//YlvVspOI+zVkGezhyToEvTxefDWs7pMmceo62Xu++i7XxIvZ/C9yUz7O gPJ4rp/pXGMkQuwZSkTH21DwGpXJC2xTbZ10meuSwiiDXys25VnYcQO3/PxqcY5j JEib8S0FVLqPBYwn6WCjKtznD+RKUNLiMbN/6vWvZfJMbpCVysJDP2LYTYWAmsm8 0gvyJU45xxYN+lhMWqjQXdtbycjTCidT5ZRIedvvV3sp5XwLOzNZLXgnezqdrCIV EHCYZjai70atPAcUeBOjpr6RFN2NqKXx610vKdBNxjvltBYGCxk5vovYXJOjoxBl uWZz/uq4LIxUfRIov31vEE1BtOeP1/xorowSL6PTrYLT863D3kQ+OyqIBr/LJlsk S6OubK5dVJBJnuwohvpb/Vsqg3GuiHVRoRUAWGvfO27b7K1J752Zo7wJW4So/d+v 39N0k240xjqunfcDL/A/08FPliCUfx1qma3PQQc7brPDVyOo9o94yrbZxpbJpjsn uRoIVnty9Zi2JAL+aYAAy3t0LFxQ2hDlCDIvcz9NhHQzpmc4FWzdRKbqptgnGaLf 2ifDZPfNqYK/TTQT6QwGDI4EfQNTTqLIEJUo6FigyVaS3tyvKcUYyP0m/5zAk6GD Jo3F519d/mDCPTtJAtm5O0HPsXXvO4Z3NnIfVeoDPeU+zDk6wNw= =ngkz -----END PGP SIGNATURE----- Merge tag 'ti-k3-dt-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt TI K3 device tree updates for v6.13 Generic Fixups/Cleanups: - Cleanup bootph-* tags to limit to leaf nodes only - clock IDs for MCSPI instances fixed up across J7xx family - Misc indentation and whitespace cleanup across dts New SoC - J742s2 which is a cutdown of existing J784s4 and uses same EVM SoC Specific features and Fixes: - eQEP (counter) support across AM64/AM62/AM62A AM64 - M4F Remoteproc support - stats collection support for ICSSGs via ti,pa-stats - Add PCIe EP overlays AM65 - stats collection support for ICSSGs via ti,pa-stats AM62: - M4F Remoteproc support - eMMC/SD TAP value updates - dtbs_check fixes for opp_efuse_table AM62A - 1.4GHz opp entry AM62P - 1.4GHz opp entry J7200 - Add PCIe EP overlays - Pinmux node reg range fixes Board Specific AM62 - am62 verdin ivy carrier board support - am625-verdin TPM device support - am62 verdin ivy board support - Beagleplay Mikrobus PWM header support - am62-verdin increase SD regulator startup delay AM64 - am642-phyboard-electra-rdk trickle charger support - am64-phy* drop buswidth from sdhci nodes * tag 'ti-k3-dt-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (61 commits) arm64: dts: ti: k3-am62: use opp_efuse_table for opp-table syscon arm64: dts: ti: k3-am62p5-sk: add 1.4ghz opp entry arm64: dts: ti: k3-am62p: add opp frequencies arm64: dts: ti: k3-am62a7-sk: add 1.4ghz opp entry arm64: dts: ti: k3-am62a: add opp frequencies arm64: dts: ti: k3-am62-verdin: Add Ivy carrier board arm64: dts: ti: k3-am62-verdin: add label to som adc node dt-bindings: arm: ti: Add verdin am62 ivy board arm64: dts: ti: k3-am642-phyboard-electra-rdk: Enable trickle charger arm64: dts: ti: k3-am64-phycore-som: Add M4F remoteproc nodes arm64: dts: ti: k3-am62-phycore-som: Add M4F remoteproc nodes arm64: dts: ti: minor whitespace cleanup arm64: dts: ti: k3-am62x-phyboard-lyra: Fix indentation in audio-card arm64: dts: ti: k3-am642-phyboard-electra-rdk: Fix bus-width property in MMC nodes arm64: dts: ti: k3-am64-phycore-som: Fix bus-width property in MMC nodes arm64: dts: ti: k3-am642-evm: Add overlay for PCIe0 EP mode arm64: dts: ti: k3-j7200-evm: Add overlay for PCIE1 Endpoint Mode arm64: dts: ti: k3-am62-main: Update otap/itap values arm64: dts: ti: k3-am625-beagleplay: Enable MikroBUS PWM arm64: dts: ti: k3-am62-verdin: Fix SD regulator startup delay ... Link: https://lore.kernel.org/r/3ded4795-2186-4e06-bda6-9c9a65a3fdb9@ti.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
d745bdcb7a
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@ -56,6 +56,7 @@ properties:
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- enum:
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- toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia
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- toradex,verdin-am62-nonwifi-dev # Verdin AM62 Module on Verdin Development Board
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- toradex,verdin-am62-nonwifi-ivy # Verdin AM62 Module on Ivy
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- toradex,verdin-am62-nonwifi-mallow # Verdin AM62 Module on Mallow
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- toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia
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- const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT
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@ -67,6 +68,7 @@ properties:
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- enum:
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- toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia
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- toradex,verdin-am62-wifi-dev # Verdin AM62 Wi-Fi / BT M. on Verdin Development B.
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- toradex,verdin-am62-wifi-ivy # Verdin AM62 Wi-Fi / BT Module on Ivy
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- toradex,verdin-am62-wifi-mallow # Verdin AM62 Wi-Fi / BT Module on Mallow
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- toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia
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- const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module
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@ -144,6 +146,12 @@ properties:
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- ti,j722s-evm
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- const: ti,j722s
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- description: K3 J742S2 SoC
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items:
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- enum:
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- ti,j742s2-evm
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- const: ti,j742s2
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- description: K3 J784s4 SoC
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items:
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- enum:
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@ -16,13 +16,14 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-ivy.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-mallow.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-ivy.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-mallow.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-1-4-ghz-opp.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am62x-phyboard-lyra-gpio-fan.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo
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@ -48,6 +49,7 @@ k3-am642-hummingboard-t-usb3-dtbs := \
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dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac-mii.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-pcie0-ep.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-pcie.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-usb3.dtb
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@ -96,6 +98,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-pcie-usb3.dtbo
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# Boards with J7200 SoC
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k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm-pcie1-ep.dtbo
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# Boards with J721e SoC
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k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo
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@ -126,13 +129,14 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-pcie0-pcie1-ep.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
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# Boards with J742S2 SoC
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dtb-$(CONFIG_ARCH_K3) += k3-j742s2-evm.dtb
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# Build time test only, enabled by CONFIG_OF_ALL_DTBS
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k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
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k3-am625-beagleplay-csi2-ov5640.dtbo
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k3-am625-beagleplay-csi2-tevi-ov5640-dtbs := k3-am625-beagleplay.dtb \
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k3-am625-beagleplay-csi2-tevi-ov5640.dtbo
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k3-am625-phyboard-lyra-1-4-ghz-opp.dtbs := k3-am625-phyboard-lyra-rdk.dtb \
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k3-am625-phyboard-lyra-1-4-ghz-opp.dtbo
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k3-am625-phyboard-lyra-disable-eth-phy-dtbs := k3-am625-phyboard-lyra-rdk.dtb \
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k3-am6xx-phycore-disable-eth-phy.dtbo
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k3-am625-phyboard-lyra-disable-rtc-dtbs := k3-am625-phyboard-lyra-rdk.dtb \
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@ -168,6 +172,8 @@ k3-am642-evm-icssg1-dualemac-dtbs := \
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k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo
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k3-am642-evm-icssg1-dualemac-mii-dtbs := \
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k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac-mii.dtbo
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k3-am642-evm-pcie0-ep-dtbs := \
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k3-am642-evm.dtb k3-am642-evm-pcie0-ep.dtbo
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k3-am642-phyboard-electra-disable-eth-phy-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-disable-eth-phy.dtbo
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k3-am642-phyboard-electra-disable-rtc-dtbs := \
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@ -188,6 +194,8 @@ k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \
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k3-j721e-sk-csi2-dual-imx219.dtbo
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k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \
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k3-j721e-sk-csi2-dual-imx219.dtbo
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k3-j7200-evm-pcie1-ep-dtbs := k3-j7200-common-proc-board.dtb \
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k3-j7200-evm-pcie1-ep.dtbo
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k3-j721e-common-proc-board-infotainment-dtbs := k3-j721e-common-proc-board.dtb \
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k3-j721e-common-proc-board-infotainment.dtbo
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k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \
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@ -217,10 +225,12 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
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k3-am62p5-sk-csi2-tevi-ov5640.dtb \
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k3-am642-evm-icssg1-dualemac.dtb \
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k3-am642-evm-icssg1-dualemac-mii.dtb \
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k3-am642-evm-pcie0-ep.dtb \
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k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \
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k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \
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k3-am68-sk-base-board-csi2-dual-imx219.dtb \
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k3-am69-sk-csi2-dual-imx219.dtb \
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k3-j7200-evm-pcie1-ep.dtbo \
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k3-j721e-common-proc-board-infotainment.dtb \
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k3-j721e-evm-pcie0-ep.dtb \
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k3-j721e-sk-csi2-dual-imx219.dtb \
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@ -243,7 +253,9 @@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl += -@
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DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
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DTC_FLAGS_k3-am68-sk-base-board += -@
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DTC_FLAGS_k3-am69-sk += -@
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DTC_FLAGS_k3-j7200-common-proc-board += -@
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DTC_FLAGS_k3-j721e-common-proc-board += -@
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DTC_FLAGS_k3-j721e-sk += -@
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DTC_FLAGS_k3-j721s2-common-proc-board += -@
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DTC_FLAGS_k3-j784s4-evm += -@
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DTC_FLAGS_k3-j742s2-evm += -@
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@ -561,10 +561,9 @@ sdhci0: mmc@fa10000 {
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ti,clkbuf-sel = <0x7>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-mmc-hs = <0x0>;
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ti,otap-del-sel-ddr52 = <0x5>;
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ti,otap-del-sel-hs200 = <0x5>;
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ti,itap-del-sel-legacy = <0xa>;
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ti,itap-del-sel-mmc-hs = <0x1>;
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ti,otap-del-sel-hs200 = <0x6>;
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ti,itap-del-sel-legacy = <0x0>;
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ti,itap-del-sel-mmc-hs = <0x0>;
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status = "disabled";
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};
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@ -577,17 +576,17 @@ sdhci1: mmc@fa00000 {
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clock-names = "clk_ahb", "clk_xin";
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bus-width = <4>;
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ti,clkbuf-sel = <0x7>;
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ti,otap-del-sel-legacy = <0x8>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-sd-hs = <0x0>;
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ti,otap-del-sel-sdr12 = <0x0>;
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ti,otap-del-sel-sdr25 = <0x0>;
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ti,otap-del-sel-sdr50 = <0x8>;
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ti,otap-del-sel-sdr104 = <0x7>;
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ti,otap-del-sel-ddr50 = <0x4>;
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ti,itap-del-sel-legacy = <0xa>;
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ti,itap-del-sel-sd-hs = <0x1>;
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ti,itap-del-sel-sdr12 = <0xa>;
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ti,itap-del-sel-sdr25 = <0x1>;
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ti,otap-del-sel-sdr12 = <0xf>;
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ti,otap-del-sel-sdr25 = <0xf>;
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ti,otap-del-sel-sdr50 = <0xc>;
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ti,otap-del-sel-sdr104 = <0x6>;
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ti,otap-del-sel-ddr50 = <0x9>;
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ti,itap-del-sel-legacy = <0x0>;
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ti,itap-del-sel-sd-hs = <0x0>;
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ti,itap-del-sel-sdr12 = <0x0>;
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ti,itap-del-sel-sdr25 = <0x0>;
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status = "disabled";
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};
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@ -600,17 +599,17 @@ sdhci2: mmc@fa20000 {
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clock-names = "clk_ahb", "clk_xin";
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bus-width = <4>;
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ti,clkbuf-sel = <0x7>;
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ti,otap-del-sel-legacy = <0x8>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-sd-hs = <0x0>;
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ti,otap-del-sel-sdr12 = <0x0>;
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ti,otap-del-sel-sdr25 = <0x0>;
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ti,otap-del-sel-sdr50 = <0x8>;
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ti,otap-del-sel-sdr104 = <0x7>;
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ti,otap-del-sel-ddr50 = <0x8>;
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ti,itap-del-sel-legacy = <0xa>;
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ti,itap-del-sel-sd-hs = <0xa>;
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ti,itap-del-sel-sdr12 = <0xa>;
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ti,itap-del-sel-sdr25 = <0x1>;
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ti,otap-del-sel-sdr12 = <0xf>;
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ti,otap-del-sel-sdr25 = <0xf>;
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ti,otap-del-sel-sdr50 = <0xc>;
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ti,otap-del-sel-sdr104 = <0x6>;
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ti,otap-del-sel-ddr50 = <0x9>;
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ti,itap-del-sel-legacy = <0x0>;
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ti,itap-del-sel-sd-hs = <0x0>;
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ti,itap-del-sel-sdr12 = <0x0>;
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ti,itap-del-sel-sdr25 = <0x0>;
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status = "disabled";
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};
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@ -843,6 +842,33 @@ ecap2: pwm@23120000 {
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status = "disabled";
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};
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eqep0: counter@23200000 {
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compatible = "ti,am62-eqep";
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reg = <0x00 0x23200000 0x00 0x100>;
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power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 59 0>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
|
||||
};
|
||||
|
||||
eqep1: counter@23210000 {
|
||||
compatible = "ti,am62-eqep";
|
||||
reg = <0x00 0x23210000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 60 0>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eqep2: counter@23220000 {
|
||||
compatible = "ti,am62-eqep";
|
||||
reg = <0x00 0x23220000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 62 0>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_mcan0: can@20701000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x00 0x20701000 0x00 0x200>,
|
||||
|
|
|
|||
|
|
@ -174,4 +174,17 @@ mcu_mcan1: can@4e18000 {
|
|||
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_m4fss: m4fss@5000000 {
|
||||
compatible = "ti,am64-m4fss";
|
||||
reg = <0x00 0x5000000 0x00 0x30000>,
|
||||
<0x00 0x5040000 0x00 0x10000>;
|
||||
reg-names = "iram", "dram";
|
||||
resets = <&k3_reset 9 1>;
|
||||
firmware-name = "am62-mcu-m4f0_0-fw";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <9>;
|
||||
ti,sci-proc-ids = <0x18 0xff>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -45,6 +45,18 @@ ramoops@9ca00000 {
|
|||
pmsg-size = <0x8000>;
|
||||
};
|
||||
|
||||
mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9cb00000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_memory_region: m4f-memory@9cc00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9cc00000 0x00 0xe00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
secure_tfa_ddr: tfa@9e780000 {
|
||||
reg = <0x00 0x9e780000 0x00 0x80000>;
|
||||
alignment = <0x1000>;
|
||||
|
|
@ -173,6 +185,13 @@ AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */
|
|||
};
|
||||
};
|
||||
|
||||
&a53_opp_table {
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-supported-hw = <0x01 0x0004>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_rgmii1_pins_default>;
|
||||
|
|
@ -196,6 +215,13 @@ cpsw3g_phy1: ethernet-phy@1 {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
|
|
@ -226,8 +252,8 @@ pmic@30 {
|
|||
regulators {
|
||||
vdd_core: buck1 {
|
||||
regulator-name = "VDD_CORE";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
|
@ -295,6 +321,13 @@ i2c_som_rtc: rtc@52 {
|
|||
};
|
||||
};
|
||||
|
||||
&mcu_m4fss {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_m4_0>;
|
||||
memory-region = <&mcu_m4fss_dma_memory_region>,
|
||||
<&mcu_m4fss_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
|
|
|||
655
arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi
Normal file
655
arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi
Normal file
|
|
@ -0,0 +1,655 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2024 Toradex
|
||||
*
|
||||
* Common dtsi for Verdin AM62 SoM on Ivy carrier board
|
||||
*
|
||||
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
|
||||
* https://www.toradex.com/products/carrier-board/ivy-carrier-board
|
||||
*/
|
||||
|
||||
#include <dt-bindings/mux/mux.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
|
||||
/ {
|
||||
/* AIN1 Voltage w/o AIN1_MODE gpio control */
|
||||
ain1_voltage_unmanaged: voltage-divider-ain1 {
|
||||
compatible = "voltage-divider";
|
||||
#io-channel-cells = <1>;
|
||||
io-channels = <&ivy_adc1 0>;
|
||||
full-ohms = <19>;
|
||||
output-ohms = <1>;
|
||||
};
|
||||
|
||||
/* AIN1 Current w/o AIN1_MODE gpio control */
|
||||
ain1_current_unmanaged: current-sense-shunt-ain1 {
|
||||
compatible = "current-sense-shunt";
|
||||
#io-channel-cells = <0>;
|
||||
io-channels = <&ivy_adc1 1>;
|
||||
shunt-resistor-micro-ohms = <100000000>;
|
||||
};
|
||||
|
||||
/* AIN1_MODE - SODIMM 216 */
|
||||
ain1_mode_mux_ctrl: mux-controller-0 {
|
||||
compatible = "gpio-mux";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_5>;
|
||||
#mux-control-cells = <0>;
|
||||
mux-gpios = <&main_gpio0 40 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
ain1-voltage {
|
||||
compatible = "io-channel-mux";
|
||||
channels = "ain1_voltage", "";
|
||||
io-channels = <&ain1_voltage_unmanaged 0>;
|
||||
io-channel-names = "parent";
|
||||
mux-controls = <&ain1_mode_mux_ctrl>;
|
||||
settle-time-us = <1000>;
|
||||
};
|
||||
|
||||
ain1-current {
|
||||
compatible = "io-channel-mux";
|
||||
channels = "", "ain1_current";
|
||||
io-channels = <&ain1_current_unmanaged>;
|
||||
io-channel-names = "parent";
|
||||
mux-controls = <&ain1_mode_mux_ctrl>;
|
||||
settle-time-us = <1000>;
|
||||
};
|
||||
|
||||
/* AIN2 Voltage w/o AIN2_MODE gpio control */
|
||||
ain2_voltage_unmanaged: voltage-divider-ain2 {
|
||||
compatible = "voltage-divider";
|
||||
#io-channel-cells = <1>;
|
||||
io-channels = <&ivy_adc2 0>;
|
||||
full-ohms = <19>;
|
||||
output-ohms = <1>;
|
||||
};
|
||||
|
||||
/* AIN2 Current w/o AIN2_MODE gpio control */
|
||||
ain2_current_unmanaged: current-sense-shunt-ain2 {
|
||||
compatible = "current-sense-shunt";
|
||||
#io-channel-cells = <0>;
|
||||
io-channels = <&ivy_adc2 1>;
|
||||
shunt-resistor-micro-ohms = <100000000>;
|
||||
};
|
||||
|
||||
/* AIN2_MODE - SODIMM 218 */
|
||||
ain2_mode_mux_ctrl: mux-controller-1 {
|
||||
compatible = "gpio-mux";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_6>;
|
||||
#mux-control-cells = <0>;
|
||||
mux-gpios = <&main_gpio0 36 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
ain2-voltage {
|
||||
compatible = "io-channel-mux";
|
||||
channels = "ain2_voltage", "";
|
||||
io-channels = <&ain2_voltage_unmanaged 0>;
|
||||
io-channel-names = "parent";
|
||||
mux-controls = <&ain2_mode_mux_ctrl>;
|
||||
settle-time-us = <1000>;
|
||||
};
|
||||
|
||||
ain2-current {
|
||||
compatible = "io-channel-mux";
|
||||
channels = "", "ain2_current";
|
||||
io-channels = <&ain2_current_unmanaged>;
|
||||
io-channel-names = "parent";
|
||||
mux-controls = <&ain2_mode_mux_ctrl>;
|
||||
settle-time-us = <1000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ivy_leds>;
|
||||
|
||||
/* D7 Blue - SODIMM 30 - LEDs.GPIO1 */
|
||||
led-0 {
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
default-state = "off";
|
||||
function = LED_FUNCTION_STATUS;
|
||||
function-enumerator = <1>;
|
||||
gpios = <&main_gpio1 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* D7 Green - SODIMM 32 - LEDs.GPIO2 */
|
||||
led-1 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "off";
|
||||
function = LED_FUNCTION_STATUS;
|
||||
function-enumerator = <1>;
|
||||
gpios = <&main_gpio1 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* D7 Red - SODIMM 34 - LEDs.GPIO3 */
|
||||
led-2 {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
default-state = "off";
|
||||
function = LED_FUNCTION_STATUS;
|
||||
function-enumerator = <1>;
|
||||
gpios = <&main_gpio1 10 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* D8 Blue - SODIMM 36 - LEDs.GPIO4 */
|
||||
led-3 {
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
default-state = "off";
|
||||
function = LED_FUNCTION_STATUS;
|
||||
function-enumerator = <2>;
|
||||
gpios = <&main_gpio1 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* D8 Green - SODIMM 54 - LEDs.GPIO5 */
|
||||
led-4 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "off";
|
||||
function = LED_FUNCTION_STATUS;
|
||||
function-enumerator = <2>;
|
||||
gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* D8 Red - SODIMM 44 - LEDs.GPIO6 */
|
||||
led-5 {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
default-state = "off";
|
||||
function = LED_FUNCTION_STATUS;
|
||||
function-enumerator = <2>;
|
||||
gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* D9 Blue - SODIMM 46 - LEDs.GPIO7 */
|
||||
led-6 {
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
default-state = "off";
|
||||
function = LED_FUNCTION_STATUS;
|
||||
function-enumerator = <3>;
|
||||
gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* D9 Red - SODIMM 48 - LEDs.GPIO8 */
|
||||
led-7 {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
default-state = "off";
|
||||
function = LED_FUNCTION_STATUS;
|
||||
function-enumerator = <3>;
|
||||
gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
reg_3v2_ain1: regulator-3v2-ain1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-name = "+3V2_AIN1";
|
||||
};
|
||||
|
||||
reg_3v2_ain2: regulator-3v2-ain2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-name = "+3V2_AIN2";
|
||||
};
|
||||
|
||||
/* Ivy Power Supply Input Voltage */
|
||||
ivy-input-voltage {
|
||||
compatible = "voltage-divider";
|
||||
/* Verdin ADC_1 */
|
||||
io-channels = <&verdin_som_adc 7>;
|
||||
full-ohms = <204700>; /* 200K + 4.7K */
|
||||
output-ohms = <4700>;
|
||||
};
|
||||
|
||||
ivy-5v-voltage {
|
||||
compatible = "voltage-divider";
|
||||
/* Verdin ADC_2 */
|
||||
io-channels = <&verdin_som_adc 6>;
|
||||
full-ohms = <39000>; /* 27K + 12K */
|
||||
output-ohms = <12000>;
|
||||
};
|
||||
|
||||
ivy-3v3-voltage {
|
||||
compatible = "voltage-divider";
|
||||
/* Verdin ADC_3 */
|
||||
io-channels = <&verdin_som_adc 5>;
|
||||
full-ohms = <54000>; /* 27K + 27K */
|
||||
output-ohms = <27000>;
|
||||
};
|
||||
|
||||
ivy-1v8-voltage {
|
||||
compatible = "voltage-divider";
|
||||
/* Verdin ADC_4 */
|
||||
io-channels = <&verdin_som_adc 4>;
|
||||
full-ohms = <39000>; /* 12K + 27K */
|
||||
output-ohms = <27000>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
pinctrl_ivy_leds: ivy-leds-default-pins {
|
||||
pinctrl-single,pins =
|
||||
<AM62X_IOPAD(0x019c, PIN_INPUT, 7)>, /* (B18) MCASP0_AXR1.GPIO1_9 */ /* SODIMM 36 */
|
||||
<AM62X_IOPAD(0x01a0, PIN_INPUT, 7)>, /* (B20) MCASP0_AXR0.GPIO1_10 */ /* SODIMM 34 */
|
||||
<AM62X_IOPAD(0x01a4, PIN_INPUT, 7)>, /* (A19) MCASP0_ACLKX.GPIO1_11 */ /* SODIMM 30 */
|
||||
<AM62X_IOPAD(0x01a8, PIN_INPUT, 7)>, /* (A20) MCASP0_AFSX.GPIO1_12 */ /* SODIMM 32 */
|
||||
<AM62X_IOPAD(0x0088, PIN_INPUT, 7)>, /* (L17) GPMC0_OEn_REn.GPIO0_33 */ /* SODIMM 48 */
|
||||
<AM62X_IOPAD(0x0098, PIN_INPUT, 7)>, /* (R18) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */
|
||||
<AM62X_IOPAD(0x008c, PIN_INPUT, 7)>, /* (L25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */
|
||||
<AM62X_IOPAD(0x002c, PIN_INPUT, 7)>; /* (F23) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */
|
||||
};
|
||||
};
|
||||
|
||||
/* Verdin ETH */
|
||||
&cpsw3g {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
|
||||
&cpsw3g_mdio {
|
||||
status = "okay";
|
||||
|
||||
cpsw3g_phy1: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
|
||||
interrupt-parent = <&main_gpio0>;
|
||||
interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Verdin ETH_1*/
|
||||
&cpsw_port1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin ETH_2_RGMII */
|
||||
&cpsw_port2 {
|
||||
phy-handle = <&cpsw3g_phy1>;
|
||||
phy-mode = "rgmii-rxid";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>,
|
||||
<&pinctrl_qspi1_cs2_gpio>,
|
||||
<&pinctrl_qspi1_io0_gpio>,
|
||||
<&pinctrl_qspi1_io1_gpio>,
|
||||
<&pinctrl_qspi1_io2_gpio>,
|
||||
<&pinctrl_qspi1_io3_gpio>;
|
||||
gpio-line-names =
|
||||
"", /* 0 */
|
||||
"",
|
||||
"",
|
||||
"DIGI_1", /* SODIMM 56 */
|
||||
"DIGI_2", /* SODIMM 58 */
|
||||
"REL1", /* SODIMM 60 */
|
||||
"REL2", /* SODIMM 62 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 10 */
|
||||
"",
|
||||
"REL3", /* SODIMM 64 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 20 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 30 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 40 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 50 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 60 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 70 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 80 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"";
|
||||
};
|
||||
|
||||
&main_gpio1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>;
|
||||
gpio-line-names =
|
||||
"", /* 0 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 10 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"REL4", /* SODIMM 66 */
|
||||
"",
|
||||
"", /* 20 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 30 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 40 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 50 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 60 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 70 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"", /* 80 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"";
|
||||
};
|
||||
|
||||
/* Verdin I2C_1 */
|
||||
&main_i2c1 {
|
||||
status = "okay";
|
||||
|
||||
temperature-sensor@4f {
|
||||
compatible = "ti,tmp1075";
|
||||
reg = <0x4f>;
|
||||
};
|
||||
|
||||
eeprom@57 {
|
||||
compatible = "st,24c02", "atmel,24c02";
|
||||
reg = <0x57>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Verdin I2C_4 CSI */
|
||||
&main_i2c3 {
|
||||
status = "okay";
|
||||
|
||||
ivy_adc1: adc@40 {
|
||||
compatible = "ti,ads1119";
|
||||
reg = <0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_7>;
|
||||
interrupt-parent = <&main_gpio0>;
|
||||
interrupts = <41 IRQ_TYPE_EDGE_FALLING>;
|
||||
avdd-supply = <®_3v2_ain1>;
|
||||
dvdd-supply = <®_3v2_ain1>;
|
||||
vref-supply = <®_3v2_ain1>;
|
||||
#address-cells = <1>;
|
||||
#io-channel-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* AIN1 0-33V Voltage Input */
|
||||
channel@0 {
|
||||
reg = <0>;
|
||||
diff-channels = <0 1>;
|
||||
};
|
||||
|
||||
/* AIN1 0-20mA Current Input */
|
||||
channel@1 {
|
||||
reg = <1>;
|
||||
diff-channels = <2 3>;
|
||||
};
|
||||
};
|
||||
|
||||
ivy_adc2: adc@41 {
|
||||
compatible = "ti,ads1119";
|
||||
reg = <0x41>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_8>;
|
||||
interrupt-parent = <&main_gpio0>;
|
||||
interrupts = <42 IRQ_TYPE_EDGE_FALLING>;
|
||||
avdd-supply = <®_3v2_ain2>;
|
||||
dvdd-supply = <®_3v2_ain2>;
|
||||
vref-supply = <®_3v2_ain2>;
|
||||
#address-cells = <1>;
|
||||
#io-channel-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* AIN2 0-33V Voltage Input */
|
||||
channel@0 {
|
||||
reg = <0>;
|
||||
diff-channels = <0 1>;
|
||||
};
|
||||
|
||||
/* AIN2 0-20mA Current Input */
|
||||
channel@1 {
|
||||
reg = <1>;
|
||||
diff-channels = <2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Verdin CAN_1 */
|
||||
&main_mcan0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin SPI_1 */
|
||||
&main_spi1 {
|
||||
pinctrl-0 = <&pinctrl_spi1>,
|
||||
<&pinctrl_spi1_cs0>,
|
||||
<&pinctrl_gpio_1>,
|
||||
<&pinctrl_gpio_4>;
|
||||
cs-gpios = <0>,
|
||||
<&mcu_gpio0 1 GPIO_ACTIVE_LOW>,
|
||||
<&mcu_gpio0 4 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
tpm@1 {
|
||||
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <18500000>;
|
||||
};
|
||||
|
||||
fram@2 {
|
||||
compatible = "fujitsu,mb85rs256", "atmel,at25";
|
||||
reg = <2>;
|
||||
address-width = <16>;
|
||||
size = <32768>;
|
||||
spi-max-frequency = <33000000>;
|
||||
pagesize = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Verdin UART_3 */
|
||||
&main_uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin UART_1 */
|
||||
&main_uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_gpio0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_2>,
|
||||
<&pinctrl_gpio_3>,
|
||||
<&pinctrl_pcie_1_reset>;
|
||||
gpio-line-names =
|
||||
"",
|
||||
"",
|
||||
"GPIO2", /* Verdin GPIO_2 - SODIMM 208 */
|
||||
"GPIO3", /* Verdin GPIO_3 - SODIMM 210 */
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"";
|
||||
};
|
||||
|
||||
/* Verdin CAN_2 */
|
||||
&mcu_mcan0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin SD_1 */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin USB_1*/
|
||||
&usbss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin USB_2 */
|
||||
&usbss1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin PCIE_1_RESET# */
|
||||
&verdin_pcie_1_reset_hog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin UART_2 */
|
||||
&wkup_uart0 {
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
rs485-rts-active-low;
|
||||
rs485-rx-during-tx;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -160,7 +160,7 @@ reg_sdhc1_vmmc: regulator-sdhci1 {
|
|||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-name = "+V3.3_SD";
|
||||
startup-delay-us = <2000>;
|
||||
startup-delay-us = <20000>;
|
||||
};
|
||||
|
||||
reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc {
|
||||
|
|
@ -1131,6 +1131,11 @@ port@1 {
|
|||
};
|
||||
};
|
||||
|
||||
tpm@2e {
|
||||
compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
|
||||
reg = <0x2e>;
|
||||
};
|
||||
|
||||
pmic@30 {
|
||||
compatible = "ti,tps65219";
|
||||
reg = <0x30>;
|
||||
|
|
@ -1219,11 +1224,12 @@ sensor@48 {
|
|||
reg = <0x48>;
|
||||
};
|
||||
|
||||
adc@49 {
|
||||
compatible = "ti,ads1015";
|
||||
verdin_som_adc: adc@49 {
|
||||
compatible = "ti,tla2024";
|
||||
reg = <0x49>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#io-channel-cells = <1>;
|
||||
|
||||
/* Verdin PMIC_I2C (ADC_4 - ADC_3) */
|
||||
channel@0 {
|
||||
|
|
|
|||
|
|
@ -8,9 +8,9 @@
|
|||
#include <dt-bindings/bus/ti-sysc.h>
|
||||
|
||||
&cbass_wakeup {
|
||||
wkup_conf: syscon@43000000 {
|
||||
wkup_conf: bus@43000000 {
|
||||
bootph-all;
|
||||
compatible = "syscon", "simple-mfd";
|
||||
compatible = "simple-bus";
|
||||
reg = <0x00 0x43000000 0x00 0x20000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -22,6 +22,11 @@ chipid: chipid@14 {
|
|||
reg = <0x14 0x4>;
|
||||
};
|
||||
|
||||
opp_efuse_table: syscon@18 {
|
||||
compatible = "ti,am62-opp-efuse-table", "syscon";
|
||||
reg = <0x18 0x4>;
|
||||
};
|
||||
|
||||
cpsw_mac_syscon: ethernet-mac-syscon@200 {
|
||||
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
|
||||
reg = <0x200 0x8>;
|
||||
|
|
|
|||
|
|
@ -419,6 +419,12 @@ AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */
|
|||
>;
|
||||
};
|
||||
|
||||
mikrobus_pwm_pins_default: mikrobus-pwm-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x01a4, PIN_INPUT, 2) /* (B20) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart0_pins_default: main-uart0-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
|
|
@ -926,3 +932,9 @@ &mcasp1 {
|
|||
0 0 0 0
|
||||
>;
|
||||
};
|
||||
|
||||
&ecap2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mikrobus_pwm_pins_default>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,20 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 PHYTEC America LLC
|
||||
* Author: Nathan Morrisson <nmorrisson@phytec.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&vdd_core {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
};
|
||||
|
||||
&a53_opp_table {
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-supported-hw = <0x01 0x0004>;
|
||||
};
|
||||
};
|
||||
22
arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-ivy.dts
Normal file
22
arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-ivy.dts
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2024 Toradex
|
||||
*
|
||||
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
|
||||
* https://www.toradex.com/products/carrier-board/ivy-carrier-board
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am625.dtsi"
|
||||
#include "k3-am62-verdin.dtsi"
|
||||
#include "k3-am62-verdin-nonwifi.dtsi"
|
||||
#include "k3-am62-verdin-ivy.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Verdin AM62 on Ivy Board";
|
||||
compatible = "toradex,verdin-am62-nonwifi-ivy",
|
||||
"toradex,verdin-am62-nonwifi",
|
||||
"toradex,verdin-am62",
|
||||
"ti,am625";
|
||||
};
|
||||
22
arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-ivy.dts
Normal file
22
arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-ivy.dts
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2024 Toradex
|
||||
*
|
||||
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
|
||||
* https://www.toradex.com/products/carrier-board/ivy-carrier-board
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am625.dtsi"
|
||||
#include "k3-am62-verdin.dtsi"
|
||||
#include "k3-am62-verdin-wifi.dtsi"
|
||||
#include "k3-am62-verdin-ivy.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Verdin AM62 WB on Ivy Board";
|
||||
compatible = "toradex,verdin-am62-wifi-ivy",
|
||||
"toradex,verdin-am62-wifi",
|
||||
"toradex,verdin-am62",
|
||||
"ti,am625";
|
||||
};
|
||||
|
|
@ -108,7 +108,7 @@ cpu3: cpu@3 {
|
|||
a53_opp_table: opp-table {
|
||||
compatible = "operating-points-v2-ti-cpu";
|
||||
opp-shared;
|
||||
syscon = <&wkup_conf>;
|
||||
syscon = <&opp_efuse_table>;
|
||||
|
||||
opp-200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
|
|
|
|||
|
|
@ -943,6 +943,33 @@ ecap2: pwm@23120000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
eqep0: counter@23200000 {
|
||||
compatible = "ti,am62-eqep";
|
||||
reg = <0x00 0x23200000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 59 0>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eqep1: counter@23210000 {
|
||||
compatible = "ti,am62-eqep";
|
||||
reg = <0x00 0x23210000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 60 0>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eqep2: counter@23220000 {
|
||||
compatible = "ti,am62-eqep";
|
||||
reg = <0x00 0x23220000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 62 0>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp0: audio-controller@2b00000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x00 0x02b00000 0x00 0x2000>,
|
||||
|
|
|
|||
|
|
@ -17,6 +17,11 @@ chipid: chipid@14 {
|
|||
reg = <0x14 0x4>;
|
||||
};
|
||||
|
||||
opp_efuse_table: syscon@18 {
|
||||
compatible = "ti,am62-opp-efuse-table", "syscon";
|
||||
reg = <0x18 0x4>;
|
||||
};
|
||||
|
||||
cpsw_mac_syscon: ethernet-mac-syscon@200 {
|
||||
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
|
||||
reg = <0x200 0x8>;
|
||||
|
|
|
|||
|
|
@ -16,3 +16,7 @@ / {
|
|||
"phytec,am62a-phycore-som", "ti,am62a7";
|
||||
model = "PHYTEC phyBOARD-Lyra AM62A7";
|
||||
};
|
||||
|
||||
&cpsw3g_phy3 {
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -68,6 +68,15 @@ wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
|
|||
};
|
||||
};
|
||||
|
||||
opp-table {
|
||||
/* Requires VDD_CORE at 0v85 */
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-supported-hw = <0x01 0x0004>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vmain_pd: regulator-0 {
|
||||
/* TPS25750 PD CONTROLLER OUTPUT */
|
||||
compatible = "regulator-fixed";
|
||||
|
|
|
|||
|
|
@ -48,6 +48,8 @@ cpu0: cpu@0 {
|
|||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
clocks = <&k3_clks 135 0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
|
|
@ -62,6 +64,8 @@ cpu1: cpu@1 {
|
|||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
clocks = <&k3_clks 136 0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
|
|
@ -76,6 +80,8 @@ cpu2: cpu@2 {
|
|||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
clocks = <&k3_clks 137 0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
|
|
@ -90,6 +96,51 @@ cpu3: cpu@3 {
|
|||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
clocks = <&k3_clks 138 0>;
|
||||
};
|
||||
};
|
||||
|
||||
a53_opp_table: opp-table {
|
||||
compatible = "operating-points-v2-ti-cpu";
|
||||
opp-shared;
|
||||
syscon = <&opp_efuse_table>;
|
||||
|
||||
opp-200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
opp-supported-hw = <0x01 0x0007>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-supported-hw = <0x01 0x0007>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-supported-hw = <0x01 0x0007>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-supported-hw = <0x01 0x0007>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-supported-hw = <0x01 0x0006>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-1250000000 {
|
||||
opp-hz = /bits/ 64 <1250000000>;
|
||||
opp-supported-hw = <0x01 0x0004>;
|
||||
clock-latency-ns = <6000000>;
|
||||
opp-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -827,6 +827,33 @@ ecap2: pwm@23120000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
eqep0: counter@23200000 {
|
||||
compatible = "ti,am62-eqep";
|
||||
reg = <0x00 0x23200000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 59 0>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eqep1: counter@23210000 {
|
||||
compatible = "ti,am62-eqep";
|
||||
reg = <0x00 0x23210000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 60 0>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eqep2: counter@23220000 {
|
||||
compatible = "ti,am62-eqep";
|
||||
reg = <0x00 0x23220000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 62 0>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_mcan0: can@20701000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x00 0x20701000 0x00 0x200>,
|
||||
|
|
|
|||
|
|
@ -20,6 +20,11 @@ chipid: chipid@14 {
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
opp_efuse_table: syscon@18 {
|
||||
compatible = "ti,am62-opp-efuse-table", "syscon";
|
||||
reg = <0x18 0x4>;
|
||||
};
|
||||
|
||||
cpsw_mac_syscon: ethernet-mac-syscon@200 {
|
||||
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
|
||||
reg = <0x200 0x8>;
|
||||
|
|
|
|||
|
|
@ -128,6 +128,15 @@ led-0 {
|
|||
};
|
||||
};
|
||||
|
||||
opp-table {
|
||||
/* Requires VDD_CORE at 0v85 */
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-supported-hw = <0x01 0x0004>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
};
|
||||
|
||||
tlv320_mclk: clk-0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@ cpu0: cpu@0 {
|
|||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
clocks = <&k3_clks 135 0>;
|
||||
};
|
||||
|
||||
|
|
@ -62,6 +63,7 @@ cpu1: cpu@1 {
|
|||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
clocks = <&k3_clks 136 0>;
|
||||
};
|
||||
|
||||
|
|
@ -77,6 +79,7 @@ cpu2: cpu@2 {
|
|||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
clocks = <&k3_clks 137 0>;
|
||||
};
|
||||
|
||||
|
|
@ -92,10 +95,54 @@ cpu3: cpu@3 {
|
|||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
clocks = <&k3_clks 138 0>;
|
||||
};
|
||||
};
|
||||
|
||||
a53_opp_table: opp-table {
|
||||
compatible = "operating-points-v2-ti-cpu";
|
||||
opp-shared;
|
||||
syscon = <&opp_efuse_table>;
|
||||
|
||||
opp-200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
opp-supported-hw = <0x01 0x0007>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-supported-hw = <0x01 0x0007>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-supported-hw = <0x01 0x0007>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-supported-hw = <0x01 0x0007>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-supported-hw = <0x01 0x0006>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-1250000000 {
|
||||
opp-hz = /bits/ 64 <1250000000>;
|
||||
opp-supported-hw = <0x01 0x0004>;
|
||||
clock-latency-ns = <6000000>;
|
||||
opp-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
l2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
|
|
|
|||
|
|
@ -82,8 +82,8 @@ simple-audio-card,cpu {
|
|||
};
|
||||
|
||||
sound_master: simple-audio-card,codec {
|
||||
sound-dai = <&audio_codec>;
|
||||
clocks = <&audio_refclk1>;
|
||||
sound-dai = <&audio_codec>;
|
||||
clocks = <&audio_refclk1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -433,8 +433,6 @@ &mcasp2 {
|
|||
0 0 0 0
|
||||
0 0 0 0
|
||||
>;
|
||||
tx-num-evt = <32>;
|
||||
rx-num-evt = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -56,6 +56,18 @@ linux,cma {
|
|||
linux,cma-default;
|
||||
};
|
||||
|
||||
mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9cb00000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_memory_region: m4f-memory@9cc00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9cc00000 0x00 0xe00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
secure_tfa_ddr: tfa@9e780000 {
|
||||
reg = <0x00 0x9e780000 0x00 0x80000>;
|
||||
alignment = <0x1000>;
|
||||
|
|
@ -464,6 +476,13 @@ mbox_m4_0: mbox-m4-0 {
|
|||
};
|
||||
};
|
||||
|
||||
&mcu_m4fss {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_m4_0>;
|
||||
memory-region = <&mcu_m4fss_dma_memory_region>,
|
||||
<&mcu_m4fss_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -1175,6 +1175,33 @@ ecap2: pwm@23120000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
eqep0: counter@23200000 {
|
||||
compatible = "ti,am62-eqep";
|
||||
reg = <0x00 0x23200000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 59 0>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eqep1: counter@23210000 {
|
||||
compatible = "ti,am62-eqep";
|
||||
reg = <0x00 0x23210000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 60 0>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eqep2: counter@23220000 {
|
||||
compatible = "ti,am62-eqep";
|
||||
reg = <0x00 0x23220000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 62 0>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_rti0: watchdog@e000000 {
|
||||
compatible = "ti,j7-rti-wdt";
|
||||
reg = <0x00 0xe000000 0x00 0x100>;
|
||||
|
|
@ -1261,6 +1288,11 @@ icssg0_mii_g_rt: mii-g-rt@33000 {
|
|||
reg = <0x33000 0x1000>;
|
||||
};
|
||||
|
||||
icssg0_pa_stats: pa-stats@2c000 {
|
||||
compatible = "ti,pruss-pa-st", "syscon";
|
||||
reg = <0x2c000 0x1000>;
|
||||
};
|
||||
|
||||
icssg0_intc: interrupt-controller@20000 {
|
||||
compatible = "ti,icssg-intc";
|
||||
reg = <0x20000 0x2000>;
|
||||
|
|
@ -1426,6 +1458,11 @@ icssg1_mii_g_rt: mii-g-rt@33000 {
|
|||
reg = <0x33000 0x1000>;
|
||||
};
|
||||
|
||||
icssg1_pa_stats: pa-stats@2c000 {
|
||||
compatible = "ti,pruss-pa-st", "syscon";
|
||||
reg = <0x2c000 0x1000>;
|
||||
};
|
||||
|
||||
icssg1_intc: interrupt-controller@20000 {
|
||||
compatible = "ti,icssg-intc";
|
||||
reg = <0x20000 0x2000>;
|
||||
|
|
|
|||
|
|
@ -161,4 +161,17 @@ mcu_esm: esm@4100000 {
|
|||
/* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */
|
||||
ti,esm-pins = <0>, <1>, <2>, <85>;
|
||||
};
|
||||
|
||||
mcu_m4fss: m4fss@5000000 {
|
||||
compatible = "ti,am64-m4fss";
|
||||
reg = <0x00 0x5000000 0x00 0x30000>,
|
||||
<0x00 0x5040000 0x00 0x10000>;
|
||||
reg-names = "iram", "dram";
|
||||
resets = <&k3_reset 9 1>;
|
||||
firmware-name = "am64-mcu-m4f0_0-fw";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <9>;
|
||||
ti,sci-proc-ids = <0x18 0xff>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -87,6 +87,18 @@ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
|||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_memory_region: m4f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
|
|
@ -240,6 +252,15 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "okay";
|
||||
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -333,6 +354,13 @@ &main_r5fss1_core1 {
|
|||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_m4fss {
|
||||
mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
|
||||
memory-region = <&mcu_m4fss_dma_memory_region>,
|
||||
<&mcu_m4fss_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -354,7 +382,6 @@ serial_flash: flash@0 {
|
|||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
|
|
|
|||
51
arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
Normal file
51
arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the
|
||||
* AM642 EVM.
|
||||
*
|
||||
* AM642 EVM Product Link: https://www.ti.com/tool/TMDS64EVM
|
||||
*
|
||||
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
/*
|
||||
* Since Root Complex and Endpoint modes are mutually exclusive
|
||||
* disable Root Complex mode.
|
||||
*/
|
||||
&pcie0_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
||||
pcie0_ep: pcie-ep@f102000 {
|
||||
compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
|
||||
reg = <0x00 0x0f102000 0x00 0x1000>,
|
||||
<0x00 0x0f100000 0x00 0x400>,
|
||||
<0x00 0x0d000000 0x00 0x00800000>,
|
||||
<0x00 0x68000000 0x00 0x08000000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
|
||||
max-link-speed = <2>;
|
||||
num-lanes = <1>;
|
||||
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 114 0>;
|
||||
clock-names = "fck";
|
||||
max-functions = /bits/ 8 <1>;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
|
||||
};
|
||||
};
|
||||
|
|
@ -101,6 +101,18 @@ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_memory_region: m4f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
|
|
@ -253,6 +265,7 @@ icssg1_eth: icssg1-eth {
|
|||
ti,mii-g-rt = <&icssg1_mii_g_rt>;
|
||||
ti,mii-rt = <&icssg1_mii_rt>;
|
||||
ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
|
||||
ti,pa-stats = <&icssg1_pa_stats>;
|
||||
interrupt-parent = <&icssg1_intc>;
|
||||
interrupts = <24 0 2>, <25 1 3>;
|
||||
interrupt-names = "tx_ts0", "tx_ts1";
|
||||
|
|
@ -450,7 +463,7 @@ AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */
|
|||
>;
|
||||
};
|
||||
|
||||
icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{
|
||||
icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
|
||||
AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
|
||||
|
|
@ -776,6 +789,13 @@ &main_r5fss1_core1 {
|
|||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_m4fss {
|
||||
mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
|
||||
memory-region = <&mcu_m4fss_dma_memory_region>,
|
||||
<&mcu_m4fss_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -344,6 +344,10 @@ icssg0_phy2: ethernet-phy@2 {
|
|||
};
|
||||
};
|
||||
|
||||
&i2c_som_rtc {
|
||||
trickle-resistor-ohms = <3000>;
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -423,7 +427,6 @@ &sdhci1 {
|
|||
vmmc-supply = <&vcc_3v3_mmc>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
no-1-8-v;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -99,6 +99,18 @@ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_memory_region: m4f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
|
|
@ -357,6 +369,16 @@ main_ecap0_pins_default: main-ecap0-default-pins {
|
|||
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
|
||||
>;
|
||||
};
|
||||
|
||||
main_eqep0_pins_default: main-eqep0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00a0, PIN_INPUT, 3) /* (N16) GPMC0_WPn.EQEP0_A */
|
||||
AM64X_IOPAD(0x00a4, PIN_INPUT, 3) /* (N17) GPMC0_DIR.EQEP0_B */
|
||||
AM64X_IOPAD(0x00ac, PIN_INPUT, 3) /* (R20) GPMC0_CSn1.EQEP0_I */
|
||||
AM64X_IOPAD(0x00a8, PIN_INPUT, 3) /* (R19) GPMC0_CSn0.EQEP0_S */
|
||||
>;
|
||||
};
|
||||
|
||||
main_wlan_en_pins_default: main-wlan-en-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
|
||||
|
|
@ -681,9 +703,23 @@ &main_r5fss1_core1 {
|
|||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_m4fss {
|
||||
mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
|
||||
memory-region = <&mcu_m4fss_dma_memory_region>,
|
||||
<&mcu_m4fss_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecap0 {
|
||||
status = "okay";
|
||||
/* PWM is available on Pin 1 of header J3 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_ecap0_pins_default>;
|
||||
};
|
||||
|
||||
&eqep0 {
|
||||
status = "okay";
|
||||
/* EQEP0 A & B available on pins 18 & 22 of J4 header */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_eqep0_pins_default>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1167,6 +1167,11 @@ icssg0_mii_g_rt: mii-g-rt@33000 {
|
|||
reg = <0x33000 0x1000>;
|
||||
};
|
||||
|
||||
icssg0_pa_stats: pa-stats@2c000 {
|
||||
compatible = "ti,pruss-pa-st", "syscon";
|
||||
reg = <0x2c000 0x1000>;
|
||||
};
|
||||
|
||||
icssg0_intc: interrupt-controller@20000 {
|
||||
compatible = "ti,icssg-intc";
|
||||
reg = <0x20000 0x2000>;
|
||||
|
|
@ -1333,6 +1338,11 @@ icssg1_mii_g_rt: mii-g-rt@33000 {
|
|||
reg = <0x33000 0x1000>;
|
||||
};
|
||||
|
||||
icssg1_pa_stats: pa-stats@2c000 {
|
||||
compatible = "ti,pruss-pa-st", "syscon";
|
||||
reg = <0x2c000 0x1000>;
|
||||
};
|
||||
|
||||
icssg1_intc: interrupt-controller@20000 {
|
||||
compatible = "ti,icssg-intc";
|
||||
reg = <0x20000 0x2000>;
|
||||
|
|
@ -1499,6 +1509,11 @@ icssg2_mii_g_rt: mii-g-rt@33000 {
|
|||
reg = <0x33000 0x1000>;
|
||||
};
|
||||
|
||||
icssg2_pa_stats: pa-stats@2c000 {
|
||||
compatible = "ti,pruss-pa-st", "syscon";
|
||||
reg = <0x2c000 0x1000>;
|
||||
};
|
||||
|
||||
icssg2_intc: interrupt-controller@20000 {
|
||||
compatible = "ti,icssg-intc";
|
||||
reg = <0x20000 0x2000>;
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@ icssg2_eth: icssg2-eth {
|
|||
|
||||
ti,mii-g-rt = <&icssg2_mii_g_rt>;
|
||||
ti,mii-rt = <&icssg2_mii_rt>;
|
||||
ti,pa-stats = <&icssg2_pa_stats>;
|
||||
ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
|
||||
|
||||
interrupt-parent = <&icssg2_intc>;
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@ icssg0_eth: icssg0-eth {
|
|||
|
||||
ti,mii-g-rt = <&icssg0_mii_g_rt>;
|
||||
ti,mii-rt = <&icssg0_mii_rt>;
|
||||
ti,pa-stats = <&icssg0_pa_stats>;
|
||||
ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
|
||||
|
||||
interrupt-parent = <&icssg0_intc>;
|
||||
|
|
@ -109,6 +110,7 @@ icssg1_eth: icssg1-eth {
|
|||
|
||||
ti,mii-g-rt = <&icssg1_mii_g_rt>;
|
||||
ti,mii-rt = <&icssg1_mii_rt>;
|
||||
ti,pa-stats = <&icssg1_pa_stats>;
|
||||
ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
|
||||
|
||||
interrupt-parent = <&icssg1_intc>;
|
||||
|
|
|
|||
|
|
@ -184,6 +184,7 @@ main_uart8_pins_default: main-uart8-default-pins {
|
|||
J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
|
||||
J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_i2c0_pins_default: main-i2c0-default-pins {
|
||||
|
|
@ -211,6 +212,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
|
|||
J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
|
||||
J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
|
||||
|
|
@ -313,6 +315,7 @@ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
|
|||
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
|
||||
J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
|
||||
|
|
@ -372,6 +375,7 @@ mcu_uart0_pins_default: mcu-uart0-default-pins {
|
|||
J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
|
||||
J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 {
|
||||
|
|
@ -413,6 +417,7 @@ &wkup_uart0 {
|
|||
status = "reserved";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_uart0_pins_default>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&wkup_i2c0 {
|
||||
|
|
@ -495,6 +500,7 @@ &mcu_uart0 {
|
|||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_uart0_pins_default>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_uart8 {
|
||||
|
|
@ -503,6 +509,7 @@ &main_uart8 {
|
|||
pinctrl-0 = <&main_uart8_pins_default>;
|
||||
/* Shared with TFA on this platform */
|
||||
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
|
|
@ -597,6 +604,7 @@ &main_sdhci1 {
|
|||
disable-wp;
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
vqmmc-supply = <&vdd_sd_dv>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&mcu_cpsw {
|
||||
|
|
|
|||
|
|
@ -156,6 +156,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
|
|||
J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
|
||||
J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -169,6 +170,7 @@ eeprom@51 {
|
|||
/* AT24C512C-MAHM-T */
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x51>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -190,7 +192,6 @@ flash@0 {
|
|||
cdns,read-delay = <4>;
|
||||
|
||||
partitions {
|
||||
bootph-all;
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -226,9 +227,9 @@ partition@800000 {
|
|||
};
|
||||
|
||||
partition@3fc0000 {
|
||||
bootph-pre-ram;
|
||||
label = "ospi.phypattern";
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -129,6 +129,7 @@ J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */
|
|||
J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
|
||||
J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
wkup_uart0_pins_default: wkup-uart0-default-pins {
|
||||
|
|
@ -136,6 +137,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
|
|||
J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
|
||||
J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
|
||||
|
|
@ -204,6 +206,7 @@ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
|
|||
J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
|
||||
J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-default-pins {
|
||||
|
|
@ -238,6 +241,7 @@ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
|
|||
J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
|
||||
J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
|
||||
|
|
@ -254,11 +258,12 @@ J721E_IOPAD(0x38, PIN_OUTPUT, 0) /* (Y21) MCAN3_TX */
|
|||
};
|
||||
};
|
||||
|
||||
&main_pmx1 {
|
||||
&main_pmx2 {
|
||||
main_usbss0_pins_default: main-usbss0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -267,12 +272,14 @@ &wkup_uart0 {
|
|||
status = "reserved";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_uart0_pins_default>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_uart0_pins_default>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
|
|
@ -281,6 +288,7 @@ &main_uart0 {
|
|||
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
|
|
@ -379,6 +387,7 @@ &main_sdhci0 {
|
|||
/* eMMC */
|
||||
status = "okay";
|
||||
non-removable;
|
||||
bootph-all;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
|
@ -390,6 +399,7 @@ &main_sdhci1 {
|
|||
pinctrl-names = "default";
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
vqmmc-supply = <&vdd_sd_dv>;
|
||||
bootph-all;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
|
@ -401,11 +411,13 @@ &serdes_ln_ctrl {
|
|||
|
||||
&usb_serdes_mux {
|
||||
idle-states = <1>; /* USB0 to SERDES lane 3 */
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usbss0_pins_default>;
|
||||
bootph-all;
|
||||
ti,vbus-divider;
|
||||
ti,usb2-only;
|
||||
};
|
||||
|
|
@ -413,6 +425,7 @@ &usbss0 {
|
|||
&usb0 {
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "high-speed";
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&tscadc0 {
|
||||
|
|
|
|||
53
arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
Normal file
53
arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the
|
||||
* J7 common processor board.
|
||||
*
|
||||
* J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
|
||||
*
|
||||
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
/*
|
||||
* Since Root Complex and Endpoint modes are mutually exclusive
|
||||
* disable Root Complex mode.
|
||||
*/
|
||||
&pcie1_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
||||
pcie1_ep: pcie-ep@2910000 {
|
||||
compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
|
||||
reg = <0x00 0x02910000 0x00 0x1000>,
|
||||
<0x00 0x02917000 0x00 0x400>,
|
||||
<0x00 0x0d800000 0x00 0x00800000>,
|
||||
<0x00 0x18000000 0x00 0x08000000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 240 6>;
|
||||
clock-names = "fck";
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
|
||||
};
|
||||
};
|
||||
|
|
@ -136,6 +136,7 @@ secure_proxy_main: mailbox@32c00000 {
|
|||
<0x00 0x32800000 0x00 0x100000>;
|
||||
interrupt-names = "rx_011";
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
hwspinlock: spinlock@30e00000 {
|
||||
|
|
@ -426,10 +427,28 @@ main_pmx0: pinctrl@11c000 {
|
|||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
main_pmx1: pinctrl@11c11c {
|
||||
main_pmx1: pinctrl@11c110 {
|
||||
compatible = "ti,j7200-padconf", "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x00 0x11c11c 0x00 0xc>;
|
||||
reg = <0x00 0x11c110 0x00 0x004>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
main_pmx2: pinctrl@11c11c {
|
||||
compatible = "ti,j7200-padconf", "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x00 0x11c11c 0x00 0x00c>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
main_pmx3: pinctrl@11c164 {
|
||||
compatible = "ti,j7200-padconf", "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x00 0x11c164 0x00 0x008>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
|
|
@ -1145,7 +1164,7 @@ main_spi0: spi@2100000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 266 1>;
|
||||
clocks = <&k3_clks 266 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1156,7 +1175,7 @@ main_spi1: spi@2110000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 267 1>;
|
||||
clocks = <&k3_clks 267 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1167,7 +1186,7 @@ main_spi2: spi@2120000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 268 1>;
|
||||
clocks = <&k3_clks 268 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1178,7 +1197,7 @@ main_spi3: spi@2130000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 269 1>;
|
||||
clocks = <&k3_clks 269 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1189,7 +1208,7 @@ main_spi4: spi@2140000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 270 1>;
|
||||
clocks = <&k3_clks 270 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1200,7 +1219,7 @@ main_spi5: spi@2150000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 271 1>;
|
||||
clocks = <&k3_clks 271 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1211,7 +1230,7 @@ main_spi6: spi@2160000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 272 1>;
|
||||
clocks = <&k3_clks 272 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1222,7 +1241,7 @@ main_spi7: spi@2170000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 273 1>;
|
||||
clocks = <&k3_clks 273 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1527,6 +1546,7 @@ main_r5fss0_core1: r5f@5d00000 {
|
|||
main_esm: esm@700000 {
|
||||
compatible = "ti,j721e-esm";
|
||||
reg = <0x0 0x700000 0x0 0x1000>;
|
||||
bootph-pre-ram;
|
||||
ti,esm-pins = <656>, <657>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -21,16 +21,19 @@ dmsc: system-controller@44083000 {
|
|||
k3_pds: power-controller {
|
||||
compatible = "ti,sci-pm-domain";
|
||||
#power-domain-cells = <2>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
k3_clks: clock-controller {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
k3_reset: reset-controller {
|
||||
compatible = "ti,sci-reset";
|
||||
#reset-cells = <2>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -44,6 +47,7 @@ mcu_timer0: timer@40400000 {
|
|||
assigned-clocks = <&k3_clks 35 1>;
|
||||
assigned-clock-parents = <&k3_clks 35 2>;
|
||||
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
|
||||
bootph-pre-ram;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
|
|
@ -191,6 +195,7 @@ wkup_conf: bus@43000000 {
|
|||
chipid: chipid@14 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x14 0x4>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -344,6 +349,7 @@ mcu_ringacc: ringacc@2b800000 {
|
|||
<0x00 0x28440000 0x00 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg",
|
||||
"proxy_target", "cfg";
|
||||
bootph-all;
|
||||
ti,num-rings = <286>;
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,sci = <&dmsc>;
|
||||
|
|
@ -363,6 +369,7 @@ mcu_udmap: dma-controller@285c0000 {
|
|||
"tchan", "rchan", "rflow";
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
#dma-cells = <1>;
|
||||
bootph-all;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <236>;
|
||||
|
|
@ -383,6 +390,8 @@ secure_proxy_mcu: mailbox@2a480000 {
|
|||
reg = <0x0 0x2a480000 0x0 0x80000>,
|
||||
<0x0 0x2a380000 0x0 0x80000>,
|
||||
<0x0 0x2a400000 0x0 0x80000>;
|
||||
bootph-pre-ram;
|
||||
|
||||
/*
|
||||
* Marked Disabled:
|
||||
* Node is incomplete as it is meant for bootloaders and
|
||||
|
|
@ -494,7 +503,7 @@ mcu_spi0: spi@40300000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 274 0>;
|
||||
clocks = <&k3_clks 274 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -505,7 +514,7 @@ mcu_spi1: spi@40310000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 275 0>;
|
||||
clocks = <&k3_clks 275 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -516,7 +525,7 @@ mcu_spi2: spi@40320000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 276 0>;
|
||||
clocks = <&k3_clks 276 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -534,6 +543,7 @@ hbmc_mux: mux-controller@47000004 {
|
|||
reg = <0x00 0x47000004 0x00 0x4>;
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x0 0x2>; /* HBMC select */
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
hbmc: hyperbus@47034000 {
|
||||
|
|
@ -652,6 +662,7 @@ wkup_vtm0: temperature-sensor@42040000 {
|
|||
<0x00 0x42050000 0x00 0x350>;
|
||||
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
mcu_esm: esm@40800000 {
|
||||
|
|
|
|||
|
|
@ -121,6 +121,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
|
|||
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
|
||||
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
|
||||
|
|
@ -137,6 +138,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
|
|||
J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
|
||||
J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -146,6 +148,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
|
|||
J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
|
||||
J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -186,6 +189,7 @@ &hbmc {
|
|||
flash@0,0 {
|
||||
compatible = "cypress,hyperflash", "cfi-flash";
|
||||
reg = <0x00 0x00 0x4000000>;
|
||||
bootph-all;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
|
|
@ -347,6 +351,7 @@ bucka1: buck1 {
|
|||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
bucka2: buck2 {
|
||||
|
|
@ -520,6 +525,7 @@ partition@800000 {
|
|||
partition@3fc0000 {
|
||||
label = "ospi.phypattern";
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -193,6 +193,7 @@ J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
|
|||
J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
|
||||
J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-default-pins {
|
||||
|
|
@ -234,6 +235,7 @@ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
|
|||
J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
|
||||
J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
|
||||
|
|
@ -247,6 +249,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
|
|||
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
|
||||
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_usbss1_pins_default: main-usbss1-default-pins {
|
||||
|
|
@ -342,6 +345,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
|
|||
J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
|
||||
J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
mcu_uart0_pins_default: mcu-uart0-default-pins {
|
||||
|
|
@ -351,6 +355,7 @@ J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
|
|||
J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
|
||||
J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
sw11_button_pins_default: sw11-button-default-pins {
|
||||
|
|
@ -370,6 +375,7 @@ J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
|
|||
J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
|
||||
J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
|
||||
|
|
@ -435,12 +441,14 @@ &wkup_uart0 {
|
|||
status = "reserved";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_uart0_pins_default>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_uart0_pins_default>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
|
|
@ -449,6 +457,7 @@ &main_uart0 {
|
|||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
/* Shared with ATF on this platform */
|
||||
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
|
|
@ -487,6 +496,7 @@ &main_sdhci0 {
|
|||
/* eMMC */
|
||||
status = "okay";
|
||||
non-removable;
|
||||
bootph-all;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
|
@ -498,12 +508,14 @@ &main_sdhci1 {
|
|||
vqmmc-supply = <&vdd_sd_dv_alt>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
bootph-all;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&usb_serdes_mux {
|
||||
idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
|
|
@ -513,6 +525,7 @@ &serdes_ln_ctrl {
|
|||
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
|
||||
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
|
||||
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&serdes_wiz3 {
|
||||
|
|
@ -533,6 +546,7 @@ serdes3_usb_link: phy@0 {
|
|||
&usbss0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usbss0_pins_default>;
|
||||
bootph-all;
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
|
|
@ -541,6 +555,7 @@ &usb0 {
|
|||
maximum-speed = "super-speed";
|
||||
phys = <&serdes3_usb_link>;
|
||||
phy-names = "cdns3,usb3-phy";
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
|
|
@ -613,6 +628,7 @@ partition@800000 {
|
|||
partition@3fe0000 {
|
||||
label = "qspi.phypattern";
|
||||
reg = <0x3fe0000 0x20000>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -226,6 +226,7 @@ secure_proxy_main: mailbox@32c00000 {
|
|||
<0x00 0x32800000 0x00 0x100000>;
|
||||
interrupt-names = "rx_011";
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
smmu0: iommu@36600000 {
|
||||
|
|
@ -2853,6 +2854,7 @@ main_spi7: spi@2170000 {
|
|||
main_esm: esm@700000 {
|
||||
compatible = "ti,j721e-esm";
|
||||
reg = <0x0 0x700000 0x0 0x1000>;
|
||||
bootph-pre-ram;
|
||||
ti,esm-pins = <344>, <345>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -21,16 +21,19 @@ dmsc: system-controller@44083000 {
|
|||
k3_pds: power-controller {
|
||||
compatible = "ti,sci-pm-domain";
|
||||
#power-domain-cells = <2>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
k3_clks: clock-controller {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
k3_reset: reset-controller {
|
||||
compatible = "ti,sci-reset";
|
||||
#reset-cells = <2>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -61,6 +64,7 @@ wkup_conf: bus@43000000 {
|
|||
chipid: chipid@14 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x14 0x4>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -112,6 +116,7 @@ mcu_timer0: timer@40400000 {
|
|||
assigned-clocks = <&k3_clks 35 1>;
|
||||
assigned-clock-parents = <&k3_clks 35 2>;
|
||||
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
|
||||
bootph-pre-ram;
|
||||
ti,timer-pwm;
|
||||
/* Non-MPU Firmware usage */
|
||||
status = "reserved";
|
||||
|
|
@ -362,6 +367,7 @@ hbmc_mux: mux-controller@47000004 {
|
|||
reg = <0x00 0x47000004 0x00 0x4>;
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x0 0x2>; /* HBMC select */
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
hbmc: hyperbus@47034000 {
|
||||
|
|
@ -470,6 +476,7 @@ mcu_ringacc: ringacc@2b800000 {
|
|||
<0x0 0x2a500000 0x0 0x40000>,
|
||||
<0x0 0x28440000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
|
||||
bootph-all;
|
||||
ti,num-rings = <286>;
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,sci = <&dmsc>;
|
||||
|
|
@ -489,6 +496,7 @@ mcu_udmap: dma-controller@285c0000 {
|
|||
"tchan", "rchan", "rflow";
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
#dma-cells = <1>;
|
||||
bootph-all;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <236>;
|
||||
|
|
@ -509,6 +517,7 @@ secure_proxy_mcu: mailbox@2a480000 {
|
|||
reg = <0x0 0x2a480000 0x0 0x80000>,
|
||||
<0x0 0x2a380000 0x0 0x80000>,
|
||||
<0x0 0x2a400000 0x0 0x80000>;
|
||||
bootph-pre-ram;
|
||||
/*
|
||||
* Marked Disabled:
|
||||
* Node is incomplete as it is meant for bootloaders and
|
||||
|
|
@ -654,7 +663,7 @@ mcu_spi0: spi@40300000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 274 0>;
|
||||
clocks = <&k3_clks 274 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -665,7 +674,7 @@ mcu_spi1: spi@40310000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 275 0>;
|
||||
clocks = <&k3_clks 275 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -676,7 +685,7 @@ mcu_spi2: spi@40320000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 276 0>;
|
||||
clocks = <&k3_clks 276 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -687,6 +696,7 @@ wkup_vtm0: temperature-sensor@42040000 {
|
|||
<0x00 0x43000300 0x00 0x10>;
|
||||
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
mcu_esm: esm@40800000 {
|
||||
|
|
|
|||
|
|
@ -346,6 +346,7 @@ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
|
|||
J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
|
||||
J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_uart0_pins_default: main-uart0-default-pins {
|
||||
|
|
@ -355,6 +356,7 @@ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
|
|||
J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
|
||||
J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-default-pins {
|
||||
|
|
@ -390,12 +392,14 @@ main_usbss0_pins_default: main-usbss0-default-pins {
|
|||
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
|
||||
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_usbss1_pins_default: main-usbss1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins {
|
||||
|
|
@ -594,6 +598,7 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
|
|||
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
|
||||
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
|
||||
|
|
@ -622,6 +627,7 @@ J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
|
|||
J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
|
||||
J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
|
||||
|
|
@ -629,6 +635,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
|
|||
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
|
||||
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
mcu_mcan0_pins_default: mcu-mcan0-default-pins {
|
||||
|
|
@ -657,6 +664,7 @@ &wkup_uart0 {
|
|||
status = "reserved";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_uart0_pins_default>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&wkup_i2c0 {
|
||||
|
|
@ -821,6 +829,7 @@ &mcu_uart0 {
|
|||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_uart0_pins_default>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
|
|
@ -829,6 +838,7 @@ &main_uart0 {
|
|||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
/* Shared with ATF on this platform */
|
||||
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
|
|
@ -844,6 +854,7 @@ &main_sdhci1 {
|
|||
vqmmc-supply = <&vdd_sd_dv_alt>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
bootph-all;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
|
@ -908,6 +919,7 @@ partition@800000 {
|
|||
partition@3fc0000 {
|
||||
label = "ospi.phypattern";
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1003,6 +1015,7 @@ &wkup_gpio0 {
|
|||
|
||||
&usb_serdes_mux {
|
||||
idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
|
|
@ -1012,6 +1025,7 @@ &serdes_ln_ctrl {
|
|||
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
|
||||
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
|
||||
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&serdes_wiz3 {
|
||||
|
|
@ -1050,6 +1064,7 @@ &mhdp {
|
|||
&usbss0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usbss0_pins_default>;
|
||||
bootph-all;
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
|
|
@ -1058,6 +1073,7 @@ &usb0 {
|
|||
maximum-speed = "super-speed";
|
||||
phys = <&serdes3_usb_link>;
|
||||
phy-names = "cdns3,usb3-phy";
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&serdes2 {
|
||||
|
|
@ -1073,6 +1089,7 @@ serdes2_usb_link: phy@1 {
|
|||
&usbss1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usbss1_pins_default>;
|
||||
bootph-all;
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
|
|
@ -1081,6 +1098,7 @@ &usb1 {
|
|||
maximum-speed = "super-speed";
|
||||
phys = <&serdes2_usb_link>;
|
||||
phy-names = "cdns3,usb3-phy";
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&mcu_cpsw {
|
||||
|
|
|
|||
|
|
@ -151,6 +151,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
|
|||
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
|
||||
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
pmic_irq_pins_default: pmic-irq-default-pins {
|
||||
|
|
@ -173,6 +174,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
|
|||
J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
|
||||
J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
|
||||
|
|
@ -192,6 +194,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */
|
|||
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */
|
||||
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -422,6 +425,7 @@ partition@800000 {
|
|||
partition@3fe0000 {
|
||||
label = "ospi.phypattern";
|
||||
reg = <0x3fe0000 0x20000>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -440,6 +444,7 @@ &hbmc {
|
|||
flash@0,0 {
|
||||
compatible = "cypress,hyperflash", "cfi-flash";
|
||||
reg = <0x00 0x00 0x4000000>;
|
||||
bootph-all;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
|
|
|
|||
|
|
@ -138,6 +138,7 @@ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
|
|||
J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
|
||||
J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_i2c3_pins_default: main-i2c3-default-pins {
|
||||
|
|
@ -165,6 +166,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
|
|||
J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
|
||||
J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
|
||||
|
|
@ -177,6 +179,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
|
|||
pinctrl-single,pins = <
|
||||
J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_mcan3_pins_default: main-mcan3-default-pins {
|
||||
|
|
@ -200,6 +203,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
|
|||
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
|
||||
J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
mcu_uart0_pins_default: mcu-uart0-default-pins {
|
||||
|
|
@ -209,6 +213,7 @@ J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
|
|||
J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
|
||||
J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
|
||||
|
|
@ -301,6 +306,7 @@ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
|
|||
J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
|
||||
J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -316,12 +322,14 @@ &wkup_uart0 {
|
|||
status = "reserved";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_uart0_pins_default>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_uart0_pins_default>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_uart8 {
|
||||
|
|
@ -330,6 +338,7 @@ &main_uart8 {
|
|||
pinctrl-0 = <&main_uart8_pins_default>;
|
||||
/* Shared with TFA on this platform */
|
||||
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
|
|
@ -383,6 +392,7 @@ &main_sdhci0 {
|
|||
/* eMMC */
|
||||
status = "okay";
|
||||
non-removable;
|
||||
bootph-all;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
|
@ -395,6 +405,7 @@ &main_sdhci1 {
|
|||
disable-wp;
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
vqmmc-supply = <&vdd_sd_dv>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&mcu_cpsw {
|
||||
|
|
@ -444,6 +455,7 @@ &usbss0 {
|
|||
status = "okay";
|
||||
pinctrl-0 = <&main_usbss0_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
bootph-all;
|
||||
ti,vbus-divider;
|
||||
ti,usb2-only;
|
||||
};
|
||||
|
|
@ -451,6 +463,7 @@ &usbss0 {
|
|||
&usb0 {
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "high-speed";
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&ospi1 {
|
||||
|
|
@ -464,6 +477,7 @@ flash@0 {
|
|||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <40000000>;
|
||||
bootph-all;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
|
|
|
|||
|
|
@ -816,6 +816,7 @@ secure_proxy_main: mailbox@32c00000 {
|
|||
<0x00 0x32800000 0x00 0x100000>;
|
||||
interrupt-names = "rx_011";
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
hwspinlock: spinlock@30e00000 {
|
||||
|
|
@ -1708,7 +1709,7 @@ main_spi0: spi@2100000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 339 1>;
|
||||
clocks = <&k3_clks 339 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1719,7 +1720,7 @@ main_spi1: spi@2110000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 340 1>;
|
||||
clocks = <&k3_clks 340 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1730,7 +1731,7 @@ main_spi2: spi@2120000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 341 1>;
|
||||
clocks = <&k3_clks 341 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1741,7 +1742,7 @@ main_spi3: spi@2130000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 342 1>;
|
||||
clocks = <&k3_clks 342 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1752,7 +1753,7 @@ main_spi4: spi@2140000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 343 1>;
|
||||
clocks = <&k3_clks 343 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1763,7 +1764,7 @@ main_spi5: spi@2150000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 344 1>;
|
||||
clocks = <&k3_clks 344 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1774,7 +1775,7 @@ main_spi6: spi@2160000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 345 1>;
|
||||
clocks = <&k3_clks 345 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1785,7 +1786,7 @@ main_spi7: spi@2170000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 346 1>;
|
||||
clocks = <&k3_clks 346 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -21,16 +21,19 @@ sms: system-controller@44083000 {
|
|||
k3_pds: power-controller {
|
||||
compatible = "ti,sci-pm-domain";
|
||||
#power-domain-cells = <2>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
k3_clks: clock-controller {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
k3_reset: reset-controller {
|
||||
compatible = "ti,sci-reset";
|
||||
#reset-cells = <2>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -43,6 +46,7 @@ wkup_conf: bus@43000000 {
|
|||
chipid: chipid@14 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x14 0x4>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -53,6 +57,8 @@ secure_proxy_sa3: mailbox@43600000 {
|
|||
reg = <0x00 0x43600000 0x00 0x10000>,
|
||||
<0x00 0x44880000 0x00 0x20000>,
|
||||
<0x00 0x44860000 0x00 0x20000>;
|
||||
bootph-pre-ram;
|
||||
|
||||
/*
|
||||
* Marked Disabled:
|
||||
* Node is incomplete as it is meant for bootloaders and
|
||||
|
|
@ -167,6 +173,7 @@ mcu_timer0: timer@40400000 {
|
|||
assigned-clocks = <&k3_clks 35 1>;
|
||||
assigned-clock-parents = <&k3_clks 35 2>;
|
||||
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
|
||||
bootph-pre-ram;
|
||||
ti,timer-pwm;
|
||||
/* Non-MPU Firmware usage */
|
||||
status = "reserved";
|
||||
|
|
@ -361,6 +368,7 @@ wkup_i2c0: i2c@42120000 {
|
|||
clocks = <&k3_clks 223 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
|
||||
bootph-all;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -425,7 +433,7 @@ mcu_spi0: spi@40300000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 347 0>;
|
||||
clocks = <&k3_clks 347 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -436,7 +444,7 @@ mcu_spi1: spi@40310000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 348 0>;
|
||||
clocks = <&k3_clks 348 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -447,7 +455,7 @@ mcu_spi2: spi@40320000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 349 0>;
|
||||
clocks = <&k3_clks 349 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -469,6 +477,7 @@ mcu_ringacc: ringacc@2b800000 {
|
|||
<0x0 0x2a500000 0x0 0x40000>,
|
||||
<0x0 0x28440000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
|
||||
bootph-all;
|
||||
ti,num-rings = <286>;
|
||||
ti,sci-rm-range-gp-rings = <0x1>;
|
||||
ti,sci = <&sms>;
|
||||
|
|
@ -488,6 +497,7 @@ mcu_udmap: dma-controller@285c0000 {
|
|||
"tchan", "rchan", "rflow";
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
#dma-cells = <1>;
|
||||
bootph-all;
|
||||
|
||||
ti,sci = <&sms>;
|
||||
ti,sci-dev-id = <273>;
|
||||
|
|
@ -507,6 +517,8 @@ secure_proxy_mcu: mailbox@2a480000 {
|
|||
reg = <0x00 0x2a480000 0x00 0x80000>,
|
||||
<0x00 0x2a380000 0x00 0x80000>,
|
||||
<0x00 0x2a400000 0x00 0x80000>;
|
||||
bootph-pre-ram;
|
||||
|
||||
/*
|
||||
* Marked Disabled:
|
||||
* Node is incomplete as it is meant for bootloaders and
|
||||
|
|
@ -667,6 +679,7 @@ wkup_vtm0: temperature-sensor@42040000 {
|
|||
<0x00 0x42050000 0x0 0x350>;
|
||||
power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
mcu_r5fss0: r5fss@41000000 {
|
||||
|
|
|
|||
|
|
@ -170,6 +170,7 @@ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
|
|||
J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
|
||||
J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -188,6 +189,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
|
|||
J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
|
||||
J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
|
||||
>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -440,6 +442,7 @@ flash@0 {
|
|||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
bootph-all;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
|
|
|
|||
|
|
@ -135,7 +135,7 @@ usbss1: usb@f920000 {
|
|||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
usb1: usb@31200000{
|
||||
usb1: usb@31200000 {
|
||||
compatible = "cdns,usb3";
|
||||
reg = <0x00 0x31200000 0x00 0x10000>,
|
||||
<0x00 0x31210000 0x00 0x10000>,
|
||||
|
|
|
|||
26
arch/arm64/boot/dts/ti/k3-j742s2-evm.dts
Normal file
26
arch/arm64/boot/dts/ti/k3-j742s2-evm.dts
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
* EVM Board Schematics: https://www.ti.com/lit/zip/SPAC001
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "k3-j742s2.dtsi"
|
||||
#include "k3-j784s4-j742s2-evm-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments J742S2 EVM";
|
||||
compatible = "ti,j742s2-evm", "ti,j742s2";
|
||||
|
||||
memory@80000000 {
|
||||
/* 16G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||
<0x00000008 0x80000000 0x00000003 0x80000000>;
|
||||
device_type = "memory";
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
45
arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi
Normal file
45
arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Device Tree Source for J742S2 SoC Family
|
||||
*
|
||||
* TRM: https://www.ti.com/lit/pdf/spruje3
|
||||
*
|
||||
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
*/
|
||||
|
||||
&c71_0 {
|
||||
firmware-name = "j742s2-c71_0-fw";
|
||||
};
|
||||
|
||||
&c71_1 {
|
||||
firmware-name = "j742s2-c71_1-fw";
|
||||
};
|
||||
|
||||
&c71_2 {
|
||||
firmware-name = "j742s2-c71_2-fw";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
firmware-name = "j742s2-main-r5f0_0-fw";
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
firmware-name = "j742s2-main-r5f0_1-fw";
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
firmware-name = "j742s2-main-r5f1_0-fw";
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
firmware-name = "j742s2-main-r5f1_1-fw";
|
||||
};
|
||||
|
||||
&main_r5fss2_core0 {
|
||||
firmware-name = "j742s2-main-r5f2_0-fw";
|
||||
};
|
||||
|
||||
&main_r5fss2_core1 {
|
||||
firmware-name = "j742s2-main-r5f2_1-fw";
|
||||
};
|
||||
98
arch/arm64/boot/dts/ti/k3-j742s2.dtsi
Normal file
98
arch/arm64/boot/dts/ti/k3-j742s2.dtsi
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Device Tree Source for J742S2 SoC Family
|
||||
*
|
||||
* TRM: https://www.ti.com/lit/pdf/spruje3
|
||||
*
|
||||
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
*/
|
||||
#include "k3-j784s4-j742s2-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 J742S2 SoC";
|
||||
compatible = "ti,j742s2";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x002>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x003>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "k3-j742s2-main.dtsi"
|
||||
File diff suppressed because it is too large
Load Diff
148
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi
Normal file
148
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi
Normal file
|
|
@ -0,0 +1,148 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Device Tree Source for J784S4 and J742S2 SoC Family
|
||||
*
|
||||
* TRM (j784s4) (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52
|
||||
* TRM (j742s2): https://www.ti.com/lit/pdf/spruje3
|
||||
*
|
||||
* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x200000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
next-level-cache = <&msmc_l3>;
|
||||
};
|
||||
|
||||
L2_1: l2-cache1 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x200000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
next-level-cache = <&msmc_l3>;
|
||||
};
|
||||
|
||||
msmc_l3: l3-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
a72_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
/* Recommendation from GIC500 TRM Table A.3 */
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: bus@100000 {
|
||||
bootph-all;
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
|
||||
<0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
|
||||
<0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
|
||||
<0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/
|
||||
<0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/
|
||||
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/
|
||||
<0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/
|
||||
<0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
|
||||
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
|
||||
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
|
||||
<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
|
||||
<0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */
|
||||
<0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */
|
||||
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
|
||||
<0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
|
||||
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
|
||||
<0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */
|
||||
<0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */
|
||||
<0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */
|
||||
<0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */
|
||||
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
|
||||
|
||||
/* MCUSS_WKUP Range */
|
||||
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
|
||||
<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
|
||||
|
||||
cbass_mcu_wakeup: bus@28380000 {
|
||||
bootph-all;
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
|
||||
<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
|
||||
};
|
||||
};
|
||||
|
||||
thermal_zones: thermal-zones {
|
||||
#include "k3-j784s4-j742s2-thermal-common.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include peripherals from each bus segment */
|
||||
#include "k3-j784s4-j742s2-main-common.dtsi"
|
||||
#include "k3-j784s4-j742s2-mcu-wakeup-common.dtsi"
|
||||
1481
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
Normal file
1481
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
2671
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
Normal file
2671
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -1,13 +1,12 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals
|
||||
* Device Tree Source for J784S4 and J742S2 SoC Family MCU/WAKEUP Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_mcu_wakeup {
|
||||
sms: system-controller@44083000 {
|
||||
bootph-all;
|
||||
compatible = "ti,k2g-sci";
|
||||
ti,host-id = <12>;
|
||||
|
||||
|
|
@ -39,7 +38,6 @@ k3_reset: reset-controller {
|
|||
};
|
||||
|
||||
wkup_conf: bus@43000000 {
|
||||
bootph-all;
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -59,6 +57,8 @@ secure_proxy_sa3: mailbox@43600000 {
|
|||
reg = <0x00 0x43600000 0x00 0x10000>,
|
||||
<0x00 0x44880000 0x00 0x20000>,
|
||||
<0x00 0x44860000 0x00 0x20000>;
|
||||
bootph-pre-ram;
|
||||
|
||||
/*
|
||||
* Marked Disabled:
|
||||
* Node is incomplete as it is meant for bootloaders and
|
||||
|
|
@ -172,13 +172,13 @@ mcu_timer0: timer@40400000 {
|
|||
assigned-clocks = <&k3_clks 35 2>;
|
||||
assigned-clock-parents = <&k3_clks 35 3>;
|
||||
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
|
||||
bootph-all;
|
||||
ti,timer-pwm;
|
||||
/* Non-MPU Firmware usage */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
mcu_timer1: timer@40410000 {
|
||||
bootph-all;
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x40410000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -458,7 +458,6 @@ mcu_spi2: spi@40320000 {
|
|||
};
|
||||
|
||||
mcu_navss: bus@28380000 {
|
||||
bootph-all;
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -515,6 +514,8 @@ secure_proxy_mcu: mailbox@2a480000 {
|
|||
reg = <0x00 0x2a480000 0x00 0x80000>,
|
||||
<0x00 0x2a380000 0x00 0x80000>,
|
||||
<0x00 0x2a400000 0x00 0x80000>;
|
||||
bootph-pre-ram;
|
||||
|
||||
/*
|
||||
* Marked Disabled:
|
||||
* Node is incomplete as it is meant for bootloaders and
|
||||
|
|
@ -632,6 +633,7 @@ wkup_vtm0: temperature-sensor@42040000 {
|
|||
<0x00 0x42050000 0x00 0x350>;
|
||||
power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
tscadc0: tscadc@40200000 {
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -8,18 +8,11 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
#include "k3-pinctrl.h"
|
||||
#include "k3-j784s4-j742s2-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 J784S4 SoC";
|
||||
compatible = "ti,j784s4";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -174,130 +167,6 @@ cpu7: cpu@103 {
|
|||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x200000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
next-level-cache = <&msmc_l3>;
|
||||
};
|
||||
|
||||
L2_1: l2-cache1 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x200000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
next-level-cache = <&msmc_l3>;
|
||||
};
|
||||
|
||||
msmc_l3: l3-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
a72_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
/* Recommendation from GIC500 TRM Table A.3 */
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: bus@100000 {
|
||||
bootph-all;
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
|
||||
<0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
|
||||
<0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
|
||||
<0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/
|
||||
<0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/
|
||||
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/
|
||||
<0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/
|
||||
<0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
|
||||
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
|
||||
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
|
||||
<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
|
||||
<0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */
|
||||
<0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */
|
||||
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
|
||||
<0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
|
||||
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
|
||||
<0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */
|
||||
<0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */
|
||||
<0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */
|
||||
<0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */
|
||||
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
|
||||
|
||||
/* MCUSS_WKUP Range */
|
||||
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
|
||||
<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
|
||||
|
||||
cbass_mcu_wakeup: bus@28380000 {
|
||||
bootph-all;
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
|
||||
<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
|
||||
};
|
||||
};
|
||||
|
||||
thermal_zones: thermal-zones {
|
||||
#include "k3-j784s4-thermal.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include peripherals from each bus segment */
|
||||
#include "k3-j784s4-main.dtsi"
|
||||
#include "k3-j784s4-mcu-wakeup.dtsi"
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user