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dt-bindings: clock: qcom: Document Nord display clock controller

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Add Device Tree binding documentation for the display clock controller
on the Qualcomm Nord SoC.

The Nord platform contains two instances of the display clock controller,
DISPCC_0 and DISPCC_1. Update the bindings to include compatible strings
for both instances.

Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260724-nords_mm_v1-v3-3-32b45232217f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Taniya Das 2026-07-24 16:25:07 +05:30 committed by Bjorn Andersson
parent 936e98ef12
commit d6c34c2929
2 changed files with 118 additions and 0 deletions
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3
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
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@ -16,6 +16,7 @@ description: |
See also:
- include/dt-bindings/clock/qcom,kaanapali-dispcc.h
- include/dt-bindings/clock/qcom,nord-dispcc.h
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
- include/dt-bindings/clock/qcom,sm8750-dispcc.h
@ -25,6 +26,8 @@ properties:
compatible:
enum:
- qcom,kaanapali-dispcc
- qcom,nord-dispcc0
- qcom,nord-dispcc1
- qcom,sar2130p-dispcc
- qcom,sm8550-dispcc
- qcom,sm8650-dispcc

115
include/dt-bindings/clock/qcom,nord-dispcc.h Normal file
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@ -0,0 +1,115 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_NORD_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_NORD_H
/* DISP_CC_0 and DISP_CC_1 clocks */
#define MDSS_DISP_CC_ACMU_CLK 0
#define MDSS_DISP_CC_MDSS_ACCU_SHIFT_CLK 1
#define MDSS_DISP_CC_MDSS_AHB1_CLK 2
#define MDSS_DISP_CC_MDSS_AHB_CLK 3
#define MDSS_DISP_CC_MDSS_AHB_CLK_SRC 4
#define MDSS_DISP_CC_MDSS_BYTE0_CLK 5
#define MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC 6
#define MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 7
#define MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK 8
#define MDSS_DISP_CC_MDSS_BYTE1_CLK 9
#define MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC 10
#define MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 11
#define MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK 12
#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK 13
#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 14
#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK 15
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK 16
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 17
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 18
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 19
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK 20
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 21
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK 22
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 23
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK 24
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC 25
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK 26
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC 27
#define MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 28
#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK 29
#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 30
#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK 31
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK 32
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 33
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 34
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 35
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK 36
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 37
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK 38
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 39
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK 40
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK_SRC 41
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK 42
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK_SRC 43
#define MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 44
#define MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK 45
#define MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 46
#define MDSS_DISP_CC_MDSS_DPTX2_CRYPTO_CLK 47
#define MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK 48
#define MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 49
#define MDSS_DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 50
#define MDSS_DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 51
#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK 52
#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 53
#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK 54
#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 55
#define MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK 56
#define MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 57
#define MDSS_DISP_CC_MDSS_DPTX3_CRYPTO_CLK 58
#define MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK 59
#define MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 60
#define MDSS_DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 61
#define MDSS_DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 62
#define MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK 63
#define MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 64
#define MDSS_DISP_CC_MDSS_ESC0_CLK 65
#define MDSS_DISP_CC_MDSS_ESC0_CLK_SRC 66
#define MDSS_DISP_CC_MDSS_ESC1_CLK 67
#define MDSS_DISP_CC_MDSS_ESC1_CLK_SRC 68
#define MDSS_DISP_CC_MDSS_MDP1_CLK 69
#define MDSS_DISP_CC_MDSS_MDP_CLK 70
#define MDSS_DISP_CC_MDSS_MDP_CLK_SRC 71
#define MDSS_DISP_CC_MDSS_MDP_LUT1_CLK 72
#define MDSS_DISP_CC_MDSS_MDP_LUT_CLK 73
#define MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK 74
#define MDSS_DISP_CC_MDSS_PCLK0_CLK 75
#define MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC 76
#define MDSS_DISP_CC_MDSS_PCLK1_CLK 77
#define MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC 78
#define MDSS_DISP_CC_MDSS_PCLK2_CLK 79
#define MDSS_DISP_CC_MDSS_PCLK2_CLK_SRC 80
#define MDSS_DISP_CC_MDSS_RSCC_AHB_CLK 81
#define MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK 82
#define MDSS_DISP_CC_MDSS_VSYNC1_CLK 83
#define MDSS_DISP_CC_MDSS_VSYNC_CLK 84
#define MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC 85
#define MDSS_DISP_CC_PLL0 86
#define MDSS_DISP_CC_PLL1 87
#define MDSS_DISP_CC_PLL2 88
#define MDSS_DISP_CC_PLL3 89
#define MDSS_DISP_CC_SLEEP_CLK 90
#define MDSS_DISP_CC_SLEEP_CLK_SRC 91
#define MDSS_DISP_CC_SM_DIV_CLK_SRC 92
#define MDSS_DISP_CC_XO_CLK 93
#define MDSS_DISP_CC_XO_CLK_SRC 94
/* DISP_CC_0 and DISP_CC_1 power domains */
#define MDSS_DISP_CC_MDSS_CORE_GDSC 0
#define MDSS_DISP_CC_MDSS_CORE_INT2_GDSC 1
/* DISP_CC_0 and DISP_CC_1 resets */
#define MDSS_DISP_CC_MDSS_CORE_BCR 0
#define MDSS_DISP_CC_MDSS_CORE_INT2_BCR 1
#define MDSS_DISP_CC_MDSS_RSCC_BCR 2
#endif