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clk: qcom: negcc-nord: keep GPU2 CFG clock enabled via critical CBCR

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The GPU2 CFG clock must remain enabled for correct operation and
should not be exposed as a controllable clk_branch.

Remove the clk_branch and mark its CBCR as critical instead to
prevent unintended gating. This follows the same approach as
'nw_gcc_gpu_cfg_ahb_clk' and aligns with other always-on clocks in
Qualcomm CC drivers.

Fixes: a4f780cd5c ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260724-nords_mm_v1-v3-2-32b45232217f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Taniya Das 2026-07-24 16:25:06 +05:30 committed by Bjorn Andersson
parent 6c3a4d9715
commit 936e98ef12
1 changed files with 6 additions and 16 deletions
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22
drivers/clk/qcom/negcc-nord.c
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@ -927,21 +927,6 @@ static struct clk_branch ne_gcc_gp2_clk = {
},
};
static struct clk_branch ne_gcc_gpu_2_cfg_clk = {
.halt_reg = 0x34004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x34004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x34004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "ne_gcc_gpu_2_cfg_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch ne_gcc_gpu_2_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
@ -1792,7 +1777,6 @@ static struct clk_regmap *ne_gcc_nord_clocks[] = {
[NE_GCC_GPLL0] = &ne_gcc_gpll0.clkr,
[NE_GCC_GPLL0_OUT_EVEN] = &ne_gcc_gpll0_out_even.clkr,
[NE_GCC_GPLL2] = &ne_gcc_gpll2.clkr,
[NE_GCC_GPU_2_CFG_CLK] = &ne_gcc_gpu_2_cfg_clk.clkr,
[NE_GCC_GPU_2_GPLL0_CLK_SRC] = &ne_gcc_gpu_2_gpll0_clk_src.clkr,
[NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC] = &ne_gcc_gpu_2_gpll0_div_clk_src.clkr,
[NE_GCC_GPU_2_HSCNOC_GFX_CLK] = &ne_gcc_gpu_2_hscnoc_gfx_clk.clkr,
@ -1921,10 +1905,16 @@ static void clk_nord_regs_configure(struct device *dev, struct regmap *regmap)
qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_axi_clk, true);
}
static const u32 ne_gcc_nord_critical_cbcrs[] = {
0x34004, /* NE_GCC_GPU_2_CFG_CLK */
};
static const struct qcom_cc_driver_data ne_gcc_nord_driver_data = {
.dfs_rcgs = ne_gcc_nord_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(ne_gcc_nord_dfs_clocks),
.clk_regs_configure = clk_nord_regs_configure,
.clk_cbcrs = ne_gcc_nord_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(ne_gcc_nord_critical_cbcrs),
};
static const struct qcom_cc_desc ne_gcc_nord_desc = {