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clk: qcom: gcc-nord: mark PCIe link clocks as critical

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The PCIe link AHB and XO clocks must remain enabled for proper
operation. Representing them as clk_branch instances allows them
to be gated, which is undesirable.

Remove their clk_branch definitions and register their CBCRs as
critical clocks instead so they remain enabled.

This matches the handling of similar always-on clocks in other
Qualcomm clock drivers.

Fixes: a4f780cd5c ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260724-nords_mm_v1-v3-1-32b45232217f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Taniya Das 2026-07-24 16:25:05 +05:30 committed by Bjorn Andersson
parent 470bd66370
commit 6c3a4d9715
1 changed files with 7 additions and 30 deletions
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37
drivers/clk/qcom/gcc-nord.c
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@ -1185,34 +1185,6 @@ static struct clk_branch gcc_pcie_d_slv_q2a_axi_clk = {
},
};
static struct clk_branch gcc_pcie_link_ahb_clk = {
.halt_reg = 0x52464,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52464,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_link_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_link_xo_clk = {
.halt_reg = 0x52468,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x52468,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52468,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_link_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_noc_async_bridge_clk = {
.halt_reg = 0x52048,
.halt_check = BRANCH_HALT_SKIP,
@ -1758,8 +1730,6 @@ static struct clk_regmap *gcc_nord_clocks[] = {
[GCC_PCIE_D_PIPE_CLK_SRC] = &gcc_pcie_d_pipe_clk_src.clkr,
[GCC_PCIE_D_SLV_AXI_CLK] = &gcc_pcie_d_slv_axi_clk.clkr,
[GCC_PCIE_D_SLV_Q2A_AXI_CLK] = &gcc_pcie_d_slv_q2a_axi_clk.clkr,
[GCC_PCIE_LINK_AHB_CLK] = &gcc_pcie_link_ahb_clk.clkr,
[GCC_PCIE_LINK_XO_CLK] = &gcc_pcie_link_xo_clk.clkr,
[GCC_PCIE_NOC_ASYNC_BRIDGE_CLK] = &gcc_pcie_noc_async_bridge_clk.clkr,
[GCC_PCIE_NOC_CNOC_SF_QX_CLK] = &gcc_pcie_noc_cnoc_sf_qx_clk.clkr,
[GCC_PCIE_NOC_M_CFG_CLK] = &gcc_pcie_noc_m_cfg_clk.clkr,
@ -1850,9 +1820,16 @@ static const struct regmap_config gcc_nord_regmap_config = {
.fast_io = true,
};
static const u32 gcc_nord_critical_cbcrs[] = {
0x52464, /* GCC_PCIE_LINK_AHB_CLK */
0x52468, /* GCC_PCIE_LINK_XO_CLK */
};
static const struct qcom_cc_driver_data gcc_nord_driver_data = {
.dfs_rcgs = gcc_nord_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_nord_dfs_clocks),
.clk_cbcrs = gcc_nord_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_nord_critical_cbcrs),
};
static const struct qcom_cc_desc gcc_nord_desc = {