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clk: qcom: clean-up simple provider misuse of the consumer API

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Clock provider should not be using the consumer interface.
In other words, a provider should not be dealing with struct clk.

This change targets occurrences for which the provider uses the
consumer interface and corresponding clk_hw interface exist.

Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260724-clk-provider-simple-clean-v2-2-56f306156d25@baylibre.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Jerome Brunet 2026-07-24 11:03:53 +02:00 committed by Bjorn Andersson
parent a5c2859ffe
commit 470bd66370
4 changed files with 6 additions and 6 deletions
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4
drivers/clk/qcom/clk-hfpll.c
View File

@ -166,7 +166,7 @@ static int clk_hfpll_set_rate(struct clk_hw *hw, unsigned long rate,
spin_lock_irqsave(&h->lock, flags);
enabled = __clk_is_enabled(hw->clk);
enabled = clk_hw_is_enabled(hw);
if (enabled)
__clk_hfpll_disable(h);
@ -220,7 +220,7 @@ static int clk_hfpll_init(struct clk_hw *hw)
regmap_read(regmap, hd->status_reg, &status);
if (!(status & BIT(hd->lock_bit))) {
WARN(1, "HFPLL %s is ON, but not locked!\n",
__clk_get_name(hw->clk));
clk_hw_get_name(hw));
clk_hfpll_disable(hw);
__clk_hfpll_init_once(hw);
}

2
drivers/clk/qcom/clk-krait.c
View File

@ -68,7 +68,7 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
sel = clk_mux_index_to_val(mux->parent_map, 0, index);
mux->en_mask = sel;
/* Don't touch mux if CPU is off as it won't work */
if (__clk_is_enabled(hw->clk))
if (clk_hw_is_enabled(hw))
__krait_mux_set_sel(mux, sel);
mux->reparent = true;

4
drivers/clk/qcom/clk-rcg.c
View File

@ -208,7 +208,7 @@ static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
bool banked_p = !!rcg->p[1].pre_div_width;
struct clk_hw *hw = &rcg->clkr.hw;
enabled = __clk_is_enabled(hw->clk);
enabled = clk_hw_is_enabled(hw);
ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
if (ret)
@ -771,7 +771,7 @@ static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsigned long rate,
regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
ret = __clk_rcg_set_rate(rcg, f);
/* Switch back to M/N if it's clocking */
if (__clk_is_enabled(hw->clk))
if (clk_hw_is_enabled(hw))
regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
return ret;

2
drivers/clk/qcom/clk-rcg2.c
View File

@ -489,7 +489,7 @@ static int clk_rcg2_determine_gp_rate(struct clk_hw *hw,
u64 parent_rate;
parent = clk_hw_get_parent(hw);
parent_rate = clk_get_rate(parent->clk);
parent_rate = clk_hw_get_rate(parent);
if (!parent_rate)
return -EINVAL;