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clk: rockchip: rk3308: Add pclk_wdt

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Change-Id: I1946b3550c11d6fde424c8493eaf925ff2dcfce4
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao 2018-03-23 20:30:50 +08:00 committed by Tao Huang
parent 699150fe82
commit d5e8f70d5f
3 changed files with 10 additions and 2 deletions
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2
arch/arm64/boot/dts/rockchip/rk3308.dtsi
View File

@ -228,7 +228,7 @@ u2phy_host: host-port {
wdt: watchdog@ff080000 {
compatible = "snps,dw-wdt";
reg = <0x0 0xff080000 0x0 0x100>;
clocks = <&cru PCLK_WDT_NS>;
clocks = <&cru PCLK_WDT>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};

8
drivers/clk/rockchip/clk-rk3308.c
View File

@ -954,6 +954,14 @@ static void __init rk3308_clk_init(struct device_node *np)
else
rockchip_clk_add_lookup(ctx, clk, ACLK_DMAC1);
/* watchdog pclk is controlled by sgrf. */
clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_bus", 0, 1, 1);
if (IS_ERR(clk))
pr_warn("%s: could not register clock pclk_wdt: %ld\n",
__func__, PTR_ERR(clk));
else
rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
rockchip_clk_register_plls(ctx, rk3308_pll_clks,
ARRAY_SIZE(rk3308_pll_clks),
RK3308_GRF_SOC_STATUS0);

2
include/dt-bindings/clock/rk3308-cru.h
View File

@ -178,7 +178,7 @@
#define PCLK_TSADC 211
#define PCLK_TIMER 212
#define PCLK_OTP_NS 213
#define PCLK_WDT_NS 214
#define PCLK_WDT 214
#define PCLK_GPIO0 215
#define PCLK_GPIO1 216
#define PCLK_GPIO2 217