diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index 21efd7006ea8..289a4319b0ba 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -228,7 +228,7 @@ u2phy_host: host-port {
 	wdt: watchdog@ff080000 {
 		compatible = "snps,dw-wdt";
 		reg = <0x0 0xff080000 0x0 0x100>;
-		clocks = <&cru PCLK_WDT_NS>;
+		clocks = <&cru PCLK_WDT>;
 		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
 	};
diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c
index 92f3cee38f53..44ff7e667606 100644
--- a/drivers/clk/rockchip/clk-rk3308.c
+++ b/drivers/clk/rockchip/clk-rk3308.c
@@ -954,6 +954,14 @@ static void __init rk3308_clk_init(struct device_node *np)
 	else
 		rockchip_clk_add_lookup(ctx, clk, ACLK_DMAC1);
 
+	/* watchdog pclk is controlled by sgrf. */
+	clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_bus", 0, 1, 1);
+	if (IS_ERR(clk))
+		pr_warn("%s: could not register clock pclk_wdt: %ld\n",
+			__func__, PTR_ERR(clk));
+	else
+		rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
+
 	rockchip_clk_register_plls(ctx, rk3308_pll_clks,
 				   ARRAY_SIZE(rk3308_pll_clks),
 				   RK3308_GRF_SOC_STATUS0);
diff --git a/include/dt-bindings/clock/rk3308-cru.h b/include/dt-bindings/clock/rk3308-cru.h
index a1ed0c34b1aa..17bb39a427ac 100644
--- a/include/dt-bindings/clock/rk3308-cru.h
+++ b/include/dt-bindings/clock/rk3308-cru.h
@@ -178,7 +178,7 @@
 #define PCLK_TSADC		211
 #define PCLK_TIMER		212
 #define PCLK_OTP_NS		213
-#define PCLK_WDT_NS		214
+#define PCLK_WDT		214
 #define PCLK_GPIO0		215
 #define PCLK_GPIO1		216
 #define PCLK_GPIO2		217