arm64: fix cpu-feature-registers Malformed table

The "visible" column was dropped so that last line's extra pieces
should also be dropped to prevent a docs build error:

Documentation/arch/arm64/cpu-feature-registers.rst:170: ERROR: Malformed table.
Right border not aligned or missing.

+------------------------------+---------+
| Name                         |  bits   |
+------------------------------+---------+
| RNDR                         | [63-60] |
+------------------------------+---------+
| TS                           | [55-52] |
+------------------------------+---------+
...
+------------------------------+---------+
| AES                          | [7-4]   |
+------------------------------+---------+---------+ [docutils]

Fixes: bc7f7ddc64 ("arm64: Remove hidden bitfields from cpu-feature-registers.rst")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Will Deacon <will@kernel.org>

Documentation/arch/arm64/cpu-feature-registers.rst

@@ -167,7 +167,7 @@ infrastructure:
      | SHA1                         | [11-8]  |
      +------------------------------+---------+
      | AES                          | [7-4]   |
-     +------------------------------+---------+---------+
+     +------------------------------+---------+
 
 
   ID_AA64ISAR1_EL1 - Instruction set attribute register 1