From d50a908ffde534596107072c4897cf17c5ccd9e5 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 26 Jul 2026 17:10:02 -0700 Subject: [PATCH] arm64: fix cpu-feature-registers Malformed table The "visible" column was dropped so that last line's extra pieces should also be dropped to prevent a docs build error: Documentation/arch/arm64/cpu-feature-registers.rst:170: ERROR: Malformed table. Right border not aligned or missing. +------------------------------+---------+ | Name | bits | +------------------------------+---------+ | RNDR | [63-60] | +------------------------------+---------+ | TS | [55-52] | +------------------------------+---------+ ... +------------------------------+---------+ | AES | [7-4] | +------------------------------+---------+---------+ [docutils] Fixes: bc7f7ddc64df ("arm64: Remove hidden bitfields from cpu-feature-registers.rst") Signed-off-by: Randy Dunlap Signed-off-by: Will Deacon --- Documentation/arch/arm64/cpu-feature-registers.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst index fc63ccb666bf..f603afe323d6 100644 --- a/Documentation/arch/arm64/cpu-feature-registers.rst +++ b/Documentation/arch/arm64/cpu-feature-registers.rst @@ -167,7 +167,7 @@ infrastructure: | SHA1 | [11-8] | +------------------------------+---------+ | AES | [7-4] | - +------------------------------+---------+---------+ + +------------------------------+---------+ ID_AA64ISAR1_EL1 - Instruction set attribute register 1