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arm64: dts: exynos990: Add USB nodes

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Add USB controller and USB PHY controller nodes for use in
the Exynos990 SoC.

This SoC supports USB full-speed, high-speed and super-speed modes.

Due to the inability to test PIPE3, USB super-speed is not enabled, and
the USB PHY is only configured for UTMI+ operation for now.

Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-2-55033f73d1b0@mentallysanemainliners.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Igor Belwon 2025-07-10 18:50:06 +02:00 committed by Krzysztof Kozlowski
parent ad211501ff
commit d3830b5b0d
1 changed files with 31 additions and 0 deletions
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31
arch/arm64/boot/dts/exynos/exynos990.dtsi
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@ -278,6 +278,37 @@ cmu_hsi0: clock-controller@10a00000 {
"dpgtc";
};
usbdrd_phy: phy@10c00000 {
compatible = "samsung,exynos990-usbdrd-phy";
reg = <0x10c00000 0x100>;
clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>,
<&oscclk>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
status = "disabled";
};
usbdrd: usb@10e00000 {
compatible = "samsung,exynos990-dwusb3",
"samsung,exynos850-dwusb3";
ranges = <0x0 0x10e00000 0x10000>;
clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>,
<&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40>;
clock-names = "bus_early", "ref";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
usbdrd_dwc3: usb@0 {
compatible = "snps,dwc3";
reg = <0x0 0x10000>;
interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy 0>;
phy-names = "usb2-phy";
};
};
pinctrl_hsi1: pinctrl@13040000 {
compatible = "samsung,exynos990-pinctrl";
reg = <0x13040000 0x1000>;