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- Add power domain and reset for SoC
- Add GPIO for both SoC and Radxa Orion O6 board -----BEGIN PGP SIGNATURE----- iQHLBAABCgA1FiEEE9MyVaemtW1m4wM6rfNrQFP6hVAFAmnKMQ4XHHBldGVyLmNo ZW5AY2l4dGVjaC5jb20ACgkQrfNrQFP6hVBFHgwAgMcA3aiQyJlK2qoovziTXWrb 9lPOXFthuNmoqlVUs7cYS/A3n/zkmIroc9tZ9xgMqHk0VfUdrvWs7R65+cNvQndE OumWt60WpRP3oT6l6zD1K/7lrFioBAs41zAyPzmtCFYeFwVrIig3nnrOaHp5+8H6 Wc1gzARVhq7OhwP5+uct+28NPyYGkKov+B03ky1RFIcD8DnAha+19W+tVM5YI8X3 cDESQJTw1TSTCB/R2VBHDYF+DiKCtOCfFK1PK4ULVcvbXBFK9Gf/lU81AiE+DZyA gLEphiYy1/YzpB7tOJBLuSUuZYqxUke3akwVz0tohvWThfGJbzoZWDw72KfzTgx5 5Gqds40p1QDL9J7KLSN4HEn9SJ2SsNz6V9DXVG4lZeR2WJ9H8AIjA7CWXnj3G46Q a/ki3NB0E1w4vlFCKXiYYsIZbVk+Cz8cJmwv2Q7Wc/urY/lv7sSaKjNeW5/yCYW/ 3lmoe++i9ge3J/ZBfUYKt4iiCvItEU+LWJm5Br+L =LF6r -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmnNhz8ACgkQmmx57+YA GNnedw/9EcyKC8MP6deL28yvi23o64qtXsZfuchQYEjtwYhnw050rVF3aG2Ifoku QhdbMdM6MlzhU08jZuQXJTwoQ15eptSM2MkxT+nLCchQ+aFFa4Cz/Xk9u5UVBHHg +VPUWwo2ig0b003JTZA+rnHHD7r3kQ7jHS2Qm2hCKqAPII6ufP3J8eUsOeNu+1at BkLuxwaUxvQUq+0T+i6W0BcasFJv33sbWx30u7dSTpvFuLiSFnIDcXW+2/0R5Oa/ PPxXibiCT74foKekg+KEFMOltPaOyAklAsCKLodvrfD3lvQvE9VVtMwtpkoXGwgn TFOQ4/fnO3VPx9/TseamfLQzgD1kL5tNLaN21VRDJ6UqAzK8RUaPfD5Du4G9EFor N0R3fVi9uNlPMKKv8bq0AaAhec5RrXlPgL4y7NIMYebSP1gGuhP46U1D3pd0veTr gbu0871I60gXSERvCwAG9ZA1YmMDwMyNd3jnQZsqPVF2ur3UaGw3LNvPlv+tmvQ6 VNMDL+ZnNsKm+XR2wYGOilKer2JGyfFPOnUsAbDH2X+NOMfsJKj+2hVQVl9Jj60d pRfj+Jesjnk7XBasKx1grdiAa9i5amkfoTzMlEIEdzSB39FL8viKQU89yBiUwVrr h9BGoT4ueI3/pWFratN3AUSEQAz+GuoEdbQWCjnSwFDMO5g5Fho= =UosP -----END PGP SIGNATURE----- Merge tag 'cix-dt-v7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix into soc/dt - Add power domain and reset for SoC - Add GPIO for both SoC and Radxa Orion O6 board * tag 'cix-dt-v7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix: arm64: dts: cix: add FCH(S0)/S5 GPIO controllers for sky1 arm64: dts: cix: Add scmi powerdomain nodes for sky1 arm64: dts: cix: add support for cix sky1 resets Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
d2be897ff9
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@ -36,6 +36,22 @@ linux,cma {
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};
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&fch_gpio0 {
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status = "okay";
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};
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&fch_gpio1 {
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status = "okay";
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};
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&fch_gpio2 {
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status = "okay";
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};
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&fch_gpio3 {
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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@ -86,6 +102,18 @@ &pcie_x1_1_rc {
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status = "okay";
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};
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&s5_gpio0 {
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status = "okay";
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};
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&s5_gpio1 {
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status = "okay";
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};
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&s5_gpio2 {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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33
arch/arm64/boot/dts/cix/sky1-power.h
Normal file
33
arch/arm64/boot/dts/cix/sky1-power.h
Normal file
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@ -0,0 +1,33 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2026 Cix Technology Group Co., Ltd.
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*/
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#ifndef __SKY1_POWER_H__
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#define __SKY1_POWER_H__
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/* The Rich OS need flow the macro */
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#define SKY1_PD_AUDIO 0
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#define SKY1_PD_PCIE_CTRL0 1
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#define SKY1_PD_PCIE_DUMMY 2
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#define SKY1_PD_PCIEHUB 3
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#define SKY1_PD_MMHUB 4
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#define SKY1_PD_MMHUB_SMMU 5
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#define SKY1_PD_DPU0 6
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#define SKY1_PD_DPU1 7
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#define SKY1_PD_DPU2 8
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#define SKY1_PD_DPU3 9
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#define SKY1_PD_DPU4 10
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#define SKY1_PD_VPU_TOP 11
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#define SKY1_PD_VPU_CORE0 12
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#define SKY1_PD_VPU_CORE1 13
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#define SKY1_PD_VPU_CORE2 14
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#define SKY1_PD_VPU_CORE3 15
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#define SKY1_PD_NPU_CORE0 16
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#define SKY1_PD_NPU_CORE1 17
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#define SKY1_PD_NPU_CORE2 18
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#define SKY1_PD_NPU_TOP 19
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#define SKY1_PD_ISP0 20
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#define SKY1_PD_GPU 21
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#endif
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@ -6,6 +6,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/cix,sky1.h>
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#include "sky1-power.h"
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/ {
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interrupt-parent = <&gic>;
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@ -168,6 +169,19 @@ scmi_clk: protocol@14 {
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#clock-cells = <1>;
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};
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};
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ap_to_tfa_scmi: scmi-1 {
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compatible = "arm,scmi-smc";
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arm,smc-id = <0xc2000001>;
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#address-cells = <1>;
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#size-cells = <0>;
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shmem = <&ap_tfa_scmi_mem>;
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smc_devpd: protocol@11 {
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reg = <0x11>;
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#power-domain-cells = <1>;
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};
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};
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};
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pmu-a520 {
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@ -185,6 +199,13 @@ psci {
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method = "smc";
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};
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s5_gpio_apb_clk: clock-100000000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "s5_gpio_apb_clk";
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};
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soc@0 {
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compatible = "simple-bus";
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ranges = <0 0 0 0 0x20 0>;
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@ -348,6 +369,76 @@ i3c1: i3c@4100000 {
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status = "disabled";
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};
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fch_gpio0: gpio-controller@4120000 {
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compatible = "cdns,gpio-r1p02";
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reg = <0x0 0x4120000 0x0 0x1000>;
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clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>;
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interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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fch_gpio1: gpio-controller@4130000 {
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compatible = "cdns,gpio-r1p02";
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reg = <0x0 0x4130000 0x0 0x1000>;
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clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>;
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interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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fch_gpio2: gpio-controller@4140000 {
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compatible = "cdns,gpio-r1p02";
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reg = <0x0 0x4140000 0x0 0x1000>;
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clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>;
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interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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fch_gpio3: gpio-controller@4150000 {
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compatible = "cdns,gpio-r1p02";
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reg = <0x0 0x4150000 0x0 0x1000>;
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clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <17>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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syscon: syscon@4160000 {
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compatible = "cix,sky1-system-control", "syscon";
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reg = <0x0 0x4160000 0x0 0x100>;
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#reset-cells = <1>;
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};
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iomuxc: pinctrl@4170000 {
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compatible = "cix,sky1-pinctrl";
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reg = <0x0 0x04170000 0x0 0x1000>;
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@ -428,6 +519,7 @@ pcie_x8_rc: pcie@a010000 {
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#size-cells = <2>;
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bus-range = <0xc0 0xff>;
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device_type = "pci";
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power-domains = <&smc_devpd SKY1_PD_PCIE_CTRL0>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
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@ -568,10 +660,70 @@ ppi_partition1: interrupt-partition-1 {
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};
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};
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s5_syscon: syscon@16000000 {
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compatible = "cix,sky1-s5-system-control", "syscon";
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reg = <0x0 0x16000000 0x0 0x1000>;
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#reset-cells = <1>;
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};
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s5_gpio0: gpio-controller@16004000 {
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compatible = "cdns,gpio-r1p02";
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reg = <0x0 0x16004000 0x0 0x1000>;
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clocks = <&s5_gpio_apb_clk>;
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interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH 0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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s5_gpio1: gpio-controller@16005000 {
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compatible = "cdns,gpio-r1p02";
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reg = <0x0 0x16005000 0x0 0x1000>;
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clocks = <&s5_gpio_apb_clk>;
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interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <10>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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s5_gpio2: gpio-controller@16006000 {
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compatible = "cdns,gpio-r1p02";
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reg = <0x0 0x16006000 0x0 0x1000>;
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clocks = <&s5_gpio_apb_clk>;
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interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <10>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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iomuxc_s5: pinctrl@16007000 {
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compatible = "cix,sky1-pinctrl-s5";
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reg = <0x0 0x16007000 0x0 0x1000>;
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};
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ap_tfa_scmi_mem: shmem@84380000 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x84380000 0x0 0x80>;
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reg-io-width = <4>;
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};
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};
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timer {
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