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One new board the ROC-RK3588-RT, gpu improvements for RK3328, frequency

Browse Source 
scaling for the RK3528 and the very first small steps for camera
 support on the RK3588 - with the CSI-DPHY support, with more hopefully
 to come soon'ish :-) .
 
 And apart from those bigger points, some more individual peripheral work
 on some boards.
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Merge tag 'v6.18-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

One new board the ROC-RK3588-RT, gpu improvements for RK3328, frequency
scaling for the RK3528 and the very first small steps for camera
support on the RK3588 - with the CSI-DPHY support, with more hopefully
to come soon'ish :-) .

And apart from those bigger points, some more individual peripheral work
on some boards.

* tag 'v6.18-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT
  dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT
  arm64: dts: rockchip: update pinctrl names for Radxa E52C
  arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C
  arm64: dts: rockchip: Add USB and charger to Gameforce Ace
  arm64: dts: rockchip: enable the Mali GPU on RK3328 boards
  arm64: dts: rockchip: add GPU powerdomain, opps, and cooling to rk3328
  arm64: dts: rockchip: Fix network on rk3576 evb1 board
  arm64: dts: rockchip: add mipi csi-2 dphy nodes to rk3588
  dt-bindings: soc: rockchip: add rk3588 csidphy grf syscon
  arm64: dts: rockchip: Add rk3528 CPU frequency scaling support
  arm64: dts: rockchip: enable HDMI Receiver on NanoPC T6

Link: https://lore.kernel.org/r/2079092.kXSN5OTJKJ@diego
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-09-23 22:47:26 +02:00
commit d1f862c0b9
14 changed files with 1434 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@ -258,6 +258,11 @@ properties:
- const: firefly,roc-rk3576-pc
- const: rockchip,rk3576
- description: Firefly ROC-RK3588-RT
items:
- const: firefly,roc-rk3588-rt
- const: rockchip,rk3588
- description: Firefly Station M2
items:
- const: firefly,rk3566-roc-pc

1
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
View File

@ -48,6 +48,7 @@ properties:
- rockchip,rk3576-vop-grf
- rockchip,rk3588-bigcore0-grf
- rockchip,rk3588-bigcore1-grf
- rockchip,rk3588-csidphy-grf
- rockchip,rk3588-dcphy-grf
- rockchip,rk3588-hdptxphy-grf
- rockchip,rk3588-ioc

1
arch/arm64/boot/dts/rockchip/Makefile
View File

@ -181,6 +181,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-max.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-ultra.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-roc-rt.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5-itx.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo

4
arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
View File

@ -44,10 +44,6 @@ &codec {
mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
};
&gpu {
mali-supply = <&vdd_logic>;
};
&pinctrl {
ir {
ir_int: ir-int {

4
arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
View File

@ -167,6 +167,10 @@ &gmac2io {
status = "okay";
};
&gpu {
mali-supply = <&vdd_logic>;
};
&hdmi {
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
View File

@ -152,6 +152,10 @@ &gmac2io {
status = "okay";
};
&gpu {
mali-supply = <&vdd_logic>;
};
&hdmi {
avdd-0v9-supply = <&vdd_10>;
avdd-1v8-supply = <&vcc_18>;

40
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@ -331,6 +331,11 @@ power: power-controller {
#address-cells = <1>;
#size-cells = <0>;
power-domain@RK3328_PD_GPU {
reg = <RK3328_PD_GPU>;
clocks = <&cru ACLK_GPU>;
#power-domain-cells = <0>;
};
power-domain@RK3328_PD_HEVC {
reg = <RK3328_PD_HEVC>;
clocks = <&cru SCLK_VENC_CORE>;
@ -570,9 +575,13 @@ map0 {
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <4096>;
};
map1 {
trip = <&target>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <4096>;
};
};
};
};
tsadc: tsadc@ff250000 {
@ -651,7 +660,36 @@ gpu: gpu@ff300000 {
"ppmmu1";
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
clock-names = "bus", "core";
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&power RK3328_PD_GPU>;
resets = <&cru SRST_GPU_A>;
#cooling-cells = <2>;
};
gpu_opp_table: opp-table-gpu {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1075000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1075000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1075000>;
};
opp-500000000 {
/* causes stability issues */
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1150000>;
status = "disabled";
};
};
h265e_mmu: iommu@ff330200 {

39
arch/arm64/boot/dts/rockchip/rk3528.dtsi
View File

@ -54,6 +54,7 @@ cpu0: cpu@0 {
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_clk SCMI_CLK_CPU>;
operating-points-v2 = <&cpu_opp_table>;
};
cpu1: cpu@1 {
@ -62,6 +63,7 @@ cpu1: cpu@1 {
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_clk SCMI_CLK_CPU>;
operating-points-v2 = <&cpu_opp_table>;
};
cpu2: cpu@2 {
@ -70,6 +72,7 @@ cpu2: cpu@2 {
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_clk SCMI_CLK_CPU>;
operating-points-v2 = <&cpu_opp_table>;
};
cpu3: cpu@3 {
@ -78,6 +81,7 @@ cpu3: cpu@3 {
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_clk SCMI_CLK_CPU>;
operating-points-v2 = <&cpu_opp_table>;
};
};
@ -96,6 +100,41 @@ scmi_clk: protocol@14 {
};
};
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <875000 875000 1100000>;
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <925000 925000 1100000>;
clock-latency-ns = <40000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <975000 975000 1100000>;
clock-latency-ns = <40000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1037500 1037500 1100000>;
clock-latency-ns = <40000>;
};
opp-2016000000 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <1100000 1100000 1100000>;
clock-latency-ns = <40000>;
};
};
gpu_opp_table: opp-table-gpu {
compatible = "operating-points-v2";

38
arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts
View File

@ -275,9 +275,6 @@ &eth0m0_rx_bus2
&eth0m0_rgmii_clk
&eth0m0_rgmii_bus
&ethm0_clk0_25m_out>;
snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x21>;
status = "okay";
};
@ -293,9 +290,6 @@ &eth1m0_rx_bus2
&eth1m0_rgmii_clk
&eth1m0_rgmii_bus
&ethm0_clk1_25m_out>;
snps,reset-gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x20>;
status = "okay";
};
@ -715,18 +709,32 @@ hym8563: rtc@51 {
};
&mdio0 {
rgmii_phy0: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
clocks = <&cru REFCLKO25M_GMAC0_OUT>;
assigned-clocks = <&cru REFCLKO25M_GMAC0_OUT>;
assigned-clock-rates = <25000000>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_phy0_rst>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
};
};
&mdio1 {
rgmii_phy1: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
clocks = <&cru REFCLKO25M_GMAC1_OUT>;
assigned-clocks = <&cru REFCLKO25M_GMAC1_OUT>;
assigned-clock-rates = <25000000>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_phy1_rst>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
};
};
@ -786,6 +794,16 @@ rtc_int: rtc-int {
};
};
network {
rgmii_phy0_rst: rgmii-phy0-rst {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
rgmii_phy1_rst: rgmii-phy1-rst {
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie0 {
pcie0_rst: pcie0-rst {
rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;

26
arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts
View File

@ -42,7 +42,7 @@ button-0 {
keys-1 {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&btn_0>;
pinctrl-0 = <&pwm15_ir_m1>;
button-1 {
label = "User";
@ -55,7 +55,7 @@ button-1 {
leds-0 {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_0>;
pinctrl-0 = <&power_led>;
led-0 {
color = <LED_COLOR_ID_GREEN>;
@ -98,16 +98,6 @@ vcc_1v1_nldo_s3: regulator-1v1 {
vin-supply = <&vcc_sysin>;
};
vcc_3v3_pmu: regulator-3v3-0 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_s3>;
};
vcc_3v3_s0: regulator-3v3-1 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_s0";
@ -312,13 +302,13 @@ &pcie2x1l2 {
&pinctrl {
keys {
btn_0: button-0 {
pwm15_ir_m1: pwm15-ir-m1 {
rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
led_0: led-0 {
power_led: power-led {
rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@ -334,19 +324,19 @@ pcie20x1_2_perstn_m0: pcie-2 {
};
regulators {
vcc_5v0_pwren_h: regulator-5v0-1 {
vcc_5v0_pwren_h: vcc-5v0-pwren-h {
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
rtc {
rtc_int_l: rtc-0 {
rtc_int_l: rtc-int-l {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
usb_otg_pwren_h: regulator-5v0-0 {
usb_otg_pwren_h: usb-otg-pwren-h {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@ -538,7 +528,7 @@ regulator-state-mem {
};
};
vcc_3v3_s3: dcdc-reg8 {
vcc_3v3_s3: vcc_3v3_pmu: dcdc-reg8 {
regulator-name = "vcc_3v3_s3";
regulator-always-on;
regulator-boot-on;

34
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
View File

@ -621,6 +621,16 @@ php_grf: syscon@fd5b0000 {
reg = <0x0 0xfd5b0000 0x0 0x1000>;
};
csidphy0_grf: syscon@fd5b4000 {
compatible = "rockchip,rk3588-csidphy-grf", "syscon";
reg = <0x0 0xfd5b4000 0x0 0x1000>;
};
csidphy1_grf: syscon@fd5b5000 {
compatible = "rockchip,rk3588-csidphy-grf", "syscon";
reg = <0x0 0xfd5b5000 0x0 0x1000>;
};
pipe_phy0_grf: syscon@fd5bc000 {
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
reg = <0x0 0xfd5bc000 0x0 0x100>;
@ -3176,6 +3186,30 @@ mipidcphy1: phy@fedb0000 {
status = "disabled";
};
csi_dphy0: phy@fedc0000 {
compatible = "rockchip,rk3588-csi-dphy";
reg = <0x0 0xfedc0000 0x0 0x8000>;
clocks = <&cru PCLK_CSIPHY0>;
clock-names = "pclk";
#phy-cells = <0>;
resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>;
reset-names = "apb", "phy";
rockchip,grf = <&csidphy0_grf>;
status = "disabled";
};
csi_dphy1: phy@fedc8000 {
compatible = "rockchip,rk3588-csi-dphy";
reg = <0x0 0xfedc8000 0x0 0x8000>;
clocks = <&cru PCLK_CSIPHY1>;
clock-names = "pclk";
#phy-cells = <0>;
resets = <&cru SRST_P_CSIPHY1>, <&cru SRST_CSIPHY1>;
reset-names = "apb", "phy";
rockchip,grf = <&csidphy1_grf>;
status = "disabled";
};
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;

17
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
View File

@ -391,6 +391,17 @@ &hdmi1_sound {
status = "okay";
};
&hdmi_receiver_cma {
status = "okay";
};
&hdmi_receiver {
hpd-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>;
pinctrl-names = "default";
status = "okay";
};
&hdptxphy0 {
status = "okay";
};
@ -629,6 +640,12 @@ usr_led_pin: usr-led-pin {
};
};
hdmirx {
hdmirx_hpd: hdmirx-5v-detection {
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
headphone {
hp_det: hp-det {
rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;

1132
arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts Normal file
View File

File diff suppressed because it is too large Load Diff

122
arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts
View File

@ -612,6 +612,56 @@ &i2c6 {
pinctrl-0 = <&i2c6m3_xfer>;
status = "okay";
fusb302: typec@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PC7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&usbc0_int>;
pinctrl-names = "default";
vbus-supply = <&usb_otg_vbus>;
connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
op-sink-microwatt = <1000000>;
power-role = "dual";
self-powered;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM)
PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>;
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
try-power-role = "sink";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_orien_sw: endpoint {
remote-endpoint = <&usbdp_phy0_orientation_switch>;
};
};
port@1 {
reg = <1>;
usbc0_role_sw: endpoint {
remote-endpoint = <&dwc3_0_role_switch>;
};
};
port@2 {
reg = <2>;
dp_altmode_mux: endpoint {
remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
};
};
};
};
};
rtc_hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
@ -640,8 +690,34 @@ battery@62 {
0x2F 0x00 0x64 0xA5 0xB5 0x1C 0xF0 0x49>;
cellwise,monitor-interval-ms = <5000>;
monitored-battery = <&battery>;
power-supplies = <&bq25703>;
status = "okay";
};
bq25703: charger@6b {
compatible = "ti,bq25703a";
reg = <0x6b>;
input-current-limit-microamp = <5000000>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD5 IRQ_TYPE_LEVEL_LOW>;
monitored-battery = <&battery>;
pinctrl-0 = <&charger_int_h>;
pinctrl-names = "default";
power-supplies = <&fusb302>;
regulators {
usb_otg_vbus: vbus {
enable-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&boost_enable_h>;
pinctrl-names = "default";
regulator-max-microamp = <960000>;
regulator-max-microvolt = <5088000>;
regulator-min-microamp = <512000>;
regulator-min-microvolt = <4992000>;
regulator-name = "usb_otg_vbus";
};
};
};
};
&i2c7 {
@ -853,6 +929,12 @@ usbc0_int: usbc0-int {
rockchip,pins =
<0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
};
usbc_sbu_dc: usbc-sbu-dc {
rockchip,pins =
<4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>,
<4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
vcc3v3-lcd {
@ -1286,6 +1368,46 @@ bluetooth {
};
};
&usb_host0_xhci {
usb-role-switch;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
dwc3_0_role_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_role_sw>;
};
};
};
&usbdp_phy0 {
mode-switch;
orientation-switch;
pinctrl-0 = <&usbc_sbu_dc>;
pinctrl-names = "default";
sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
rockchip,dp-lane-mux = <2 3>;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
usbdp_phy0_orientation_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_orien_sw>;
};
usbdp_phy0_dp_altmode_mux: endpoint@1 {
reg = <1>;
remote-endpoint = <&dp_altmode_mux>;
};
};
};
&vop {
status = "okay";
};