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arm64: dts: mediatek: mt8188: Add missing #reset-cells property

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The binding now require the '#reset-cells' property but the
devicetree has not been updated which trigger dtb-check errors.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Julien Massot <julien.massot@collabora.com>
Link: https://lore.kernel.org/r/20250516-dtb-check-mt8188-v2-2-fb60bef1b8e1@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Julien Massot 2025-05-16 16:12:14 +02:00 committed by AngeloGioacchino Del Regno
parent 781cffe8d4
commit cf57ec7b9f
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GPG Key ID: 9A3604CFAD978478
1 changed files with 10 additions and 0 deletions
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10
arch/arm64/boot/dts/mediatek/mt8188.dtsi
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@ -2647,36 +2647,42 @@ imgsys1_dip_top: clock-controller@15110000 {
compatible = "mediatek,mt8188-imgsys1-dip-top";
reg = <0 0x15110000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
imgsys1_dip_nr: clock-controller@15130000 {
compatible = "mediatek,mt8188-imgsys1-dip-nr";
reg = <0 0x15130000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
imgsys_wpe1: clock-controller@15220000 {
compatible = "mediatek,mt8188-imgsys-wpe1";
reg = <0 0x15220000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
ipesys: clock-controller@15330000 {
compatible = "mediatek,mt8188-ipesys";
reg = <0 0x15330000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
imgsys_wpe2: clock-controller@15520000 {
compatible = "mediatek,mt8188-imgsys-wpe2";
reg = <0 0x15520000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
imgsys_wpe3: clock-controller@15620000 {
compatible = "mediatek,mt8188-imgsys-wpe3";
reg = <0 0x15620000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
camsys: clock-controller@16000000 {
@ -2689,24 +2695,28 @@ camsys_rawa: clock-controller@1604f000 {
compatible = "mediatek,mt8188-camsys-rawa";
reg = <0 0x1604f000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
camsys_yuva: clock-controller@1606f000 {
compatible = "mediatek,mt8188-camsys-yuva";
reg = <0 0x1606f000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
camsys_rawb: clock-controller@1608f000 {
compatible = "mediatek,mt8188-camsys-rawb";
reg = <0 0x1608f000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
camsys_yuvb: clock-controller@160af000 {
compatible = "mediatek,mt8188-camsys-yuvb";
reg = <0 0x160af000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
ccusys: clock-controller@17200000 {