github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-25 15:41:52 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board

Browse Source 
Introduce PCIe controller nodes to EN7581 SoC and EN7581 evaluation
board.

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/20250517-en7581-evb-pcie-v1-2-97297eb063bb@kernel.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Lorenzo Bianconi 2025-05-17 17:19:44 +02:00 committed by AngeloGioacchino Del Regno
parent ed0c3aacf5
commit 781cffe8d4
No known key found for this signature in database
GPG Key ID: 9A3604CFAD978478
2 changed files with 131 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
arch/arm64/boot/dts/airoha/en7581-evb.dts
View File

@ -67,6 +67,32 @@ reserved_bmt@7e00000 {
&en7581_pinctrl {
gpio-ranges = <&en7581_pinctrl 0 13 47>;
pcie0_rst_pins: pcie0-rst-pins {
conf {
pins = "pcie_reset0";
drive-open-drain = <1>;
};
};
pcie1_rst_pins: pcie1-rst-pins {
conf {
pins = "pcie_reset1";
drive-open-drain = <1>;
};
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_rst_pins>;
status = "okay";
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_rst_pins>;
status = "okay";
};
&i2c0 {

105
arch/arm64/boot/dts/airoha/en7581.dtsi
View File

@ -180,6 +180,111 @@ scuclk: clock-controller@1fb00000 {
#reset-cells = <1>;
};
pbus_csr: syscon@1fbe3400 {
compatible = "airoha,en7581-pbus-csr", "syscon";
reg = <0x0 0x1fbe3400 0x0 0xff>;
};
pciephy: phy@1fa5a000 {
compatible = "airoha,en7581-pcie-phy";
reg = <0x0 0x1fa5a000 0x0 0xfff>,
<0x0 0x1fa5b000 0x0 0xfff>,
<0x0 0x1fa5c000 0x0 0xfff>,
<0x0 0x1fc10044 0x0 0x4>,
<0x0 0x1fc30044 0x0 0x4>,
<0x0 0x1fc15030 0x0 0x104>;
reg-names = "csr-2l", "pma0", "pma1",
"p0-xr-dtime", "p1-xr-dtime",
"rx-aeq";
#phy-cells = <0>;
};
pcie0: pcie@1fc00000 {
compatible = "airoha,en7581-pcie";
device_type = "pci";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
reg = <0x0 0x1fc00000 0x0 0x1670>;
reg-names = "pcie-mac";
clocks = <&scuclk EN7523_CLK_PCIE>;
clock-names = "sys-ck";
phys = <&pciephy>;
phy-names = "pcie-phy";
ranges = <0x02000000 0 0x20000000 0x0 0x20000000 0 0x4000000>;
resets = <&scuclk EN7581_PCIE0_RST>,
<&scuclk EN7581_PCIE1_RST>,
<&scuclk EN7581_PCIE2_RST>;
reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
mediatek,pbus-csr = <&pbus_csr 0x0 0x4>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
status = "disabled";
pcie_intc0: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie1: pcie@1fc20000 {
compatible = "airoha,en7581-pcie";
device_type = "pci";
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
reg = <0x0 0x1fc20000 0x0 0x1670>;
reg-names = "pcie-mac";
clocks = <&scuclk EN7523_CLK_PCIE>;
clock-names = "sys-ck";
phys = <&pciephy>;
phy-names = "pcie-phy";
ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>;
resets = <&scuclk EN7581_PCIE0_RST>,
<&scuclk EN7581_PCIE1_RST>,
<&scuclk EN7581_PCIE2_RST>;
reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
mediatek,pbus-csr = <&pbus_csr 0x8 0xc>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
status = "disabled";
pcie_intc1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
uart1: serial@1fbf0000 {
compatible = "ns16550";
reg = <0x0 0x1fbf0000 0x0 0x30>;