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TI K3 device tree updates for v6.14

Browse Source 
Generic Fixups/Cleanups:
 - Remove unused and undocumented "ti,(rx|tx)-fifo-depth" properties for
   ethernet phy
 - Clock description added to ICSS-G
 
 SoC Specific features and Fixes:
 - Duplicate GICR reg defines in am62x/am62ax
 - Mailbox nodes are enabled at board level bringing AM67/j722s/am62p to same
   behavior as other K3 SoCs.
 - Introduction of deep-sleep state defines for pinctrl header
 
 AM62Ax
 - Enable ti-sysc for wkup_uart0
 
 AM64:
 - Switch ICSSG clock to core clock.
 
 J7200:
 - Disable SPI1 loopback default.
 
 J784s4:
 - Clock ID fix for McSPI instances
 - Use j7200-padconf compatibility for padconf to enable suspend-to-ram support.
 
 Board Specific:
 
 AM62
 - phyboard - hdmi bridge regulator and using 16bit input for hdmi bridge,
   vcc-supply for i2c eeprom
 - SK - SoC wakeup using USB1, Add bootph property around cpsw mac syscon node,
   M4 mailbox node redefinition fixup.
 - BeaglePlay: Fix ethernet phy reset time
 
 AM64
 - hummingboard-t: Convert PCIE/USB overlays to independent dts.
 
 j7200:
 - EVM: fix typo in overlay name.
 
 j721e:
 - EVM: overlay for pcie1 endpoint mode.
 
 j722s:
 - EVM: Add mcu_i2c0 support for expansion pins., Add USB0 DFU support, Enable
   PMIC
 - AM67a-beagley-ai: Add remote proc nodes
 
 j784s4:
 - AM69-SK/ j784s4-EVM - Mark PMIC regulators with bootph-all property to
   indicate ones that are needed through boot phases.
 - AM69-sk: PIC0 Endpoint mode overlay, USB Superspeed mode.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEE+KKGk1TrgjIXoxo03bWEnRc2JJ0FAmeBg4IACgkQ3bWEnRc2
 JJ2S7w//QzPdkA1niL7/KXOadjUgrVJkUe4Ck9tpBYPGmDRxowONF2z6fauNRvDt
 OOxxmwfPwbDwGP0GLxYUOIf6WzXFB6IQhkFOgItxhjDnu9MUIHDCE4IVCgewwiil
 wpXZ7pPqMu7N13IfmpLgPGV4m/KUGjbN2ZBNvFw3SEV5VDA9r7pruGNpBC3z6Nzj
 V3e9bCVWvxTxUX3vOI5Wxq+Oqpo+lSc7MRDedb/fgVRwrt5+LQ7EIN6R2EVsHDR7
 BtINNRbduzsfHZmSXXYIKnv6XMdsoTqfauMa9YQzNg3DoI6ua5Yqh0RwOkM0IS4P
 l7hFHKrmiiU+zKH0kVwc7T0ipmvspU61uGPQx/6tlZGIacTXBg/KazHYfpgdLIwJ
 hoZfGCfab3kjo7tpciTkjIPib6NHbhpOS5QVx3NKk9KUYrutahVeZE6KnQ2eVUWm
 Xhbu1AFCTzZvC8Q2cBQdsRgAkON8pjQWjF6D5YLJPrTaQ2SNyW2d7FQavC0GHkZK
 TCiPbmP/Cskw8LkpW4PEJOjdiOYZlBj3Vepr4+A6gZNMESZkrVb4X4Ub6KTMDOBK
 /jrw8aecyZMCUlMHmnb3t66J2sWpnTUPDf1P4686o1gGiIHlig7abdbthVG/VGPr
 MsLXM9w9Mrtv7ld9Ra9hu4npJzZMZtJi/PInnOTh2BKvJkOu3J8=
 =CWTE
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmeJF3YACgkQYKtH/8kJ
 Uidj0w//XTlHUzbYxgXLsrW6ORNephizA2FsKasXX/s1/fhrY2hc5gRWdTM5JYHd
 IG+HVlB95GPhy9f61VjEcj+WDHXzc3wx0vbhaODIPUOuZ8U+dqn7l5TEqZkWsRMN
 Ay44AbjnMZxubrsxMxa8DT3WVxezjdV8UcObDhG7xmMNxxalh0JRXZF98PldzAGE
 hKM1mdnWqp1aqfKCQrAFmkQoZtNu/wlzh8nHUIO5tRIKjyYdLEFd3l4VUGtWHAtp
 kbc7TktXkJDmYYA0l5mm9B+RRvwjr8tobk1imtIIIQcWOiboqCQr95hYLE0DEd31
 7XEnseNqDLGdnEvwEBwLw3ADnTYbLxwVofn4zqy+LWHNcKAYmG/HhGYUe1UOuDH+
 DCpJ73uNO9/rlnKpOL5rYHR/+ZgacPZ3vAVjXiNdIhsB6eiX9tYvaZ62reoUvq+a
 m2ynRGopQGlwmZdpOQaExWWxJNIjqxP/MesN+DlOO5E3hfF1I7ZW1eoqDU1iF3mZ
 Y/P8nEWRvietQ2MIwl0T2qjkViIvOwmZHeFk0/x7wYHrRAgnWS2g95ThcfDg1jbF
 M2/8h9pgX1Y/6L/eFc0CMe+lIxpi4NXNRdUUkMKd+z0aUHxfHC+rnL4zp76OpT0x
 WLYKvHSsg0cPYboi6kzBszqHHbx62DmgHYazUxExvVh08+3D6x0=
 =vrRY
 -----END PGP SIGNATURE-----

Merge tag 'ti-k3-dt-for-v6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt

TI K3 device tree updates for v6.14

Generic Fixups/Cleanups:
- Remove unused and undocumented "ti,(rx|tx)-fifo-depth" properties for
  ethernet phy
- Clock description added to ICSS-G

SoC Specific features and Fixes:
- Duplicate GICR reg defines in am62x/am62ax
- Mailbox nodes are enabled at board level bringing AM67/j722s/am62p to same
  behavior as other K3 SoCs.
- Introduction of deep-sleep state defines for pinctrl header

AM62Ax
- Enable ti-sysc for wkup_uart0

AM64:
- Switch ICSSG clock to core clock.

J7200:
- Disable SPI1 loopback default.

J784s4:
- Clock ID fix for McSPI instances
- Use j7200-padconf compatibility for padconf to enable suspend-to-ram support.

Board Specific:

AM62
- phyboard - hdmi bridge regulator and using 16bit input for hdmi bridge,
  vcc-supply for i2c eeprom
- SK - SoC wakeup using USB1, Add bootph property around cpsw mac syscon node,
  M4 mailbox node redefinition fixup.
- BeaglePlay: Fix ethernet phy reset time

AM64
- hummingboard-t: Convert PCIE/USB overlays to independent dts.

j7200:
- EVM: fix typo in overlay name.

j721e:
- EVM: overlay for pcie1 endpoint mode.

j722s:
- EVM: Add mcu_i2c0 support for expansion pins., Add USB0 DFU support, Enable
  PMIC
- AM67a-beagley-ai: Add remote proc nodes

j784s4:
- AM69-SK/ j784s4-EVM - Mark PMIC regulators with bootph-all property to
  indicate ones that are needed through boot phases.
- AM69-sk: PIC0 Endpoint mode overlay, USB Superspeed mode.

* tag 'ti-k3-dt-for-v6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (31 commits)
  arm64: dts: ti: k3-am62a-wakeup: Configure ti-sysc for wkup_uart0
  arm64: dts: ti: k3-j722s-evm: Enable PMIC
  arm64: dts: ti: k3-am69-sk: Add USB SuperSpeed support
  arm64: dts: ti: k3-am625-beagleplay: Fix DP83TD510E reset time
  arm64: dts: ti: k3-am642-hummingboard-t: Convert overlay to board dts
  arm64: dts: ti: k3-am69-sk: Add overlay for PCIE0 Endpoint Mode
  arm64: dts: ti: k3-am68-sk-base-board: Add overlay for PCIE1 Endpoint Mode
  arm64: dts: ti: k3-j721e-evm: Add overlay for PCIE1 Endpoint Mode
  arm64: dts: ti: Makefile: Fix typo "k3-j7200-evm-pcie1-ep.dtbo"
  arm64: dts: ti: k3-j7200: Add node to disable loopback connection
  arm64: dts: ti: k3-j784s4: Use ti,j7200-padconf compatible
  arm64: dts: ti: k3-am62p-j722s-common-main: Enable USB0 for DFU boot
  arm64: dts: ti: k3-am62a: Remove duplicate GICR reg
  arm64: dts: ti: k3-am62: Remove duplicate GICR reg
  arm64: dts: ti: k3-am67a-beagley-ai: Add remote processor nodes
  arm64: dts: ti: k3-am62p: Enable Mailbox nodes at the board level
  arm64: dts: ti: k3-am625-sk: Remove M4 mailbox node redefinition
  arm64: dts: ti: k3-j722s-evm: Enable support for mcu_i2c0
  arm64: dts: ti: k3-am62x-sk-common: Add bootph-all property in cpsw_mac_syscon node
  arm64: dts: ti: Remove unused and undocumented "ti,(rx|tx)-fifo-depth" properties
  ...

Link: https://lore.kernel.org/r/20250110210812.bdpypzvmg6s6sr5t@itinerary
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-01-16 15:20:53 +01:00
commit ce4805664b
28 changed files with 654 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
View File

@ -92,6 +92,16 @@ properties:
description: |
This property is as per sci-pm-domain.txt.
clocks:
items:
- description: ICSSG_CORE Clock
- description: ICSSG_IEP Clock
- description: ICSSG_RGMII_MHZ_250 Clock
- description: ICSSG_RGMII_MHZ_50 Clock
- description: ICSSG_RGMII_MHZ_5 Clock
- description: ICSSG_UART Clock
- description: ICSSG_ICLK Clock
patternProperties:
memories@[a-f0-9]+$:

19
arch/arm64/boot/dts/ti/Makefile
View File

@ -42,10 +42,6 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-imx219.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo
# Boards with AM64x SoC
k3-am642-hummingboard-t-pcie-dtbs := \
k3-am642-hummingboard-t.dtb k3-am642-hummingboard-t-pcie.dtbo
k3-am642-hummingboard-t-usb3-dtbs := \
k3-am642-hummingboard-t.dtb k3-am642-hummingboard-t-usb3.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac-mii.dtbo
@ -107,11 +103,13 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board-infotainment.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie1-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo
# Boards with J721s2 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board-pcie1-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo
k3-j721s2-evm-dtbs := k3-j721s2-common-proc-board.dtb k3-j721s2-evm-gesi-exp-board.dtbo
@ -124,6 +122,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
# Boards with J784s4 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-pcie0-pcie1-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
@ -192,14 +191,20 @@ k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \
k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo
k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
k3-am68-sk-base-board-pcie1-ep-dtbs := k3-am68-sk-base-board.dtb \
k3-am68-sk-base-board-pcie1-ep.dtbo
k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
k3-am69-sk-pcie0-ep-dtbs := k3-am69-sk.dtb \
k3-am69-sk-pcie0-ep.dtbo
k3-j7200-evm-pcie1-ep-dtbs := k3-j7200-common-proc-board.dtb \
k3-j7200-evm-pcie1-ep.dtbo
k3-j721e-common-proc-board-infotainment-dtbs := k3-j721e-common-proc-board.dtb \
k3-j721e-common-proc-board-infotainment.dtbo
k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \
k3-j721e-evm-pcie0-ep.dtbo
k3-j721e-evm-pcie1-ep-dtbs := k3-j721e-common-proc-board.dtb \
k3-j721e-evm-pcie1-ep.dtbo
k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
@ -229,10 +234,13 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \
k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \
k3-am68-sk-base-board-csi2-dual-imx219.dtb \
k3-am68-sk-base-board-pcie1-ep.dtb \
k3-am69-sk-csi2-dual-imx219.dtb \
k3-j7200-evm-pcie1-ep.dtbo \
k3-am69-sk-pcie0-ep.dtb \
k3-j7200-evm-pcie1-ep.dtb \
k3-j721e-common-proc-board-infotainment.dtb \
k3-j721e-evm-pcie0-ep.dtb \
k3-j721e-evm-pcie1-ep.dtb \
k3-j721e-sk-csi2-dual-imx219.dtb \
k3-j721s2-evm-pcie1-ep.dtb \
k3-j784s4-evm-pcie0-pcie1-ep.dtb \
@ -255,6 +263,7 @@ DTC_FLAGS_k3-am68-sk-base-board += -@
DTC_FLAGS_k3-am69-sk += -@
DTC_FLAGS_k3-j7200-common-proc-board += -@
DTC_FLAGS_k3-j721e-common-proc-board += -@
DTC_FLAGS_k3-j721e-evm-pcie0-ep += -@
DTC_FLAGS_k3-j721e-sk += -@
DTC_FLAGS_k3-j721s2-common-proc-board += -@
DTC_FLAGS_k3-j784s4-evm += -@

1
arch/arm64/boot/dts/ti/k3-am62-main.dtsi
View File

@ -23,7 +23,6 @@ gic500: interrupt-controller@1800000 {
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x01 0x00000000 0x00 0x2000>, /* GICC */
<0x01 0x00010000 0x00 0x1000>, /* GICH */
<0x01 0x00020000 0x00 0x2000>; /* GICV */

11
arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
View File

@ -95,6 +95,16 @@ vdd_1v8: regulator-vdd-1v8 {
regulator-boot-on;
};
vddshv_3v3: regulator-vddshv-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDSHV0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vdd_3v3>;
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@ -313,6 +323,7 @@ eeprom@50 {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x50>;
vcc-supply = <&vddshv_3v3>;
};
i2c_som_rtc: rtc@52 {

2
arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
View File

@ -610,7 +610,7 @@ cpsw3g_phy1: ethernet-phy@1 {
reg = <1>;
reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <25>;
reset-deassert-us = <60000>; /* T2 */
reset-deassert-us = <35>;
};
};

7
arch/arm64/boot/dts/ti/k3-am625-sk.dts
View File

@ -219,13 +219,6 @@ cpsw3g_phy1: ethernet-phy@1 {
};
};
&mailbox0_cluster0 {
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
};
&fss {
bootph-all;
};

1
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
View File

@ -18,7 +18,6 @@ gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x01 0x00000000 0x00 0x2000>, /* GICC */
<0x01 0x00010000 0x00 0x1000>, /* GICH */
<0x01 0x00020000 0x00 0x2000>; /* GICV */

36
arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
View File

@ -2,9 +2,11 @@
/*
* Device Tree Source for AM62A SoC Family Wakeup Domain peripherals
*
* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/bus/ti-sysc.h>
&cbass_wakeup {
wkup_conf: bus@43000000 {
compatible = "simple-bus";
@ -38,14 +40,34 @@ usb1_phy_ctrl: syscon@4018 {
};
};
wkup_uart0: serial@2b300000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x2b300000 0x00 0x100>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
target-module@2b300050 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0 0x2b300050 0 0x4>,
<0 0x2b300054 0 0x4>,
<0 0x2b300058 0 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
ti,no-reset-on-init;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "fclk";
status = "disabled";
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x2b300000 0x100000>;
wkup_uart0: serial@0 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0 0x100>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
wkup_i2c0: i2c@2b200000 {

5
arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
View File

@ -651,6 +651,7 @@ usb0: usb@31000000 {
interrupt-names = "host", "peripheral";
maximum-speed = "high-speed";
dr_mode = "otg";
bootph-all;
snps,usb2-gadget-lpm-disable;
snps,usb2-lpm-disable;
};
@ -768,6 +769,7 @@ mailbox0_cluster0: mailbox@29000000 {
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
status = "disabled";
};
mailbox0_cluster1: mailbox@29010000 {
@ -777,6 +779,7 @@ mailbox0_cluster1: mailbox@29010000 {
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
status = "disabled";
};
mailbox0_cluster2: mailbox@29020000 {
@ -786,6 +789,7 @@ mailbox0_cluster2: mailbox@29020000 {
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
status = "disabled";
};
mailbox0_cluster3: mailbox@29030000 {
@ -795,6 +799,7 @@ mailbox0_cluster3: mailbox@29030000 {
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
status = "disabled";
};
ecap0: pwm@23100000 {

4
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
View File

@ -621,6 +621,8 @@ partition@3fc0000 {
};
&mailbox0_cluster0 {
status = "okay";
mbox_r5_0: mbox-r5-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
@ -628,6 +630,8 @@ mbox_r5_0: mbox-r5-0 {
};
&mailbox0_cluster1 {
status = "okay";
mbox_mcu_r5_0: mbox-mcu-r5-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;

24
arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi
View File

@ -112,6 +112,25 @@ vcc_1v8: regulator-vcc-1v8 {
regulator-boot-on;
};
vcc_3v3_hdmi: regulator-vcc-3v3-hdmi {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3_HDMI";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_sw>;
regulator-always-on;
regulator-boot-on;
};
vcc_1v2_hdmi: regulator-vcc-1v2-hdmi {
compatible = "regulator-fixed";
regulator-name = "HDMI_CVCC";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
vcc_3v3_mmc: regulator-vcc-3v3-mmc {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3_MMC";
@ -367,6 +386,9 @@ sii9022: bridge-hdmi@39 {
pinctrl-names = "default";
pinctrl-0 = <&hdmi_int_pins_default>;
iovcc-supply = <&vcc_3v3_hdmi>;
cvcc12-supply = <&vcc_1v2_hdmi>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -376,6 +398,7 @@ port@0 {
sii9022_in: endpoint {
remote-endpoint = <&dpi1_out>;
bus-width = <16>;
};
};
@ -393,6 +416,7 @@ eeprom@51 {
compatible = "atmel,24c02";
pagesize = <16>;
reg = <0x51>;
vcc-supply = <&vcc_3v3_mmc>;
};
};

6
arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
View File

@ -256,7 +256,7 @@ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */
main_usb1_pins_default: main-usb1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */
AM62X_IOPAD(0x0258, PIN_OUTPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (F18/E16) USB1_DRVVBUS */
>;
};
@ -315,6 +315,10 @@ AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */
};
};
&cpsw_mac_syscon {
bootph-all;
};
&wkup_uart0 {
/* WKUP UART0 is used by DM firmware */
bootph-pre-ram;

22
arch/arm64/boot/dts/ti/k3-am64-main.dtsi
View File

@ -1227,6 +1227,15 @@ icssg0: icssg@30000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x30000000 0x80000>;
clocks = <&k3_clks 81 0>, /* icssg0_core_clk */
<&k3_clks 81 3>, /* icssg0_iep_clk */
<&k3_clks 81 16>, /* icssg0_rgmii_mhz_250_clk */
<&k3_clks 81 17>, /* icssg0_rgmii_mhz_50_clk */
<&k3_clks 81 18>, /* icssg0_rgmii_mhz_5_clk */
<&k3_clks 81 19>, /* icssg0_uart_clk */
<&k3_clks 81 20>; /* icssg0_iclk */
assigned-clocks = <&k3_clks 81 0>;
assigned-clock-parents = <&k3_clks 81 2>;
icssg0_mem: memories@0 {
reg = <0x0 0x2000>,
@ -1252,7 +1261,7 @@ icssg0_coreclk_mux: coreclk-mux@3c {
clocks = <&k3_clks 81 0>, /* icssg0_core_clk */
<&k3_clks 81 20>; /* icssg0_iclk */
assigned-clocks = <&icssg0_coreclk_mux>;
assigned-clock-parents = <&k3_clks 81 20>;
assigned-clock-parents = <&k3_clks 81 0>;
};
icssg0_iepclk_mux: iepclk-mux@30 {
@ -1397,6 +1406,15 @@ icssg1: icssg@30080000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x30080000 0x80000>;
clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
<&k3_clks 82 3>, /* icssg1_iep_clk */
<&k3_clks 82 16>, /* icssg1_rgmii_mhz_250_clk */
<&k3_clks 82 17>, /* icssg1_rgmii_mhz_50_clk */
<&k3_clks 82 18>, /* icssg1_rgmii_mhz_5_clk */
<&k3_clks 82 19>, /* icssg1_uart_clk */
<&k3_clks 82 20>; /* icssg1_iclk */
assigned-clocks = <&k3_clks 82 0>;
assigned-clock-parents = <&k3_clks 82 2>;
icssg1_mem: memories@0 {
reg = <0x0 0x2000>,
@ -1422,7 +1440,7 @@ icssg1_coreclk_mux: coreclk-mux@3c {
clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
<&k3_clks 82 20>; /* icssg1_iclk */
assigned-clocks = <&icssg1_coreclk_mux>;
assigned-clock-parents = <&k3_clks 82 20>;
assigned-clock-parents = <&k3_clks 82 0>;
};
icssg1_iepclk_mux: iepclk-mux@30 {

14
arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-pcie.dtso → arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-pcie.dts
View File

@ -2,17 +2,19 @@
/*
* Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
*
* Overlay for SolidRun AM642 HummingBoard-T to enable PCI-E.
* DTS for SolidRun AM642 HummingBoard-T,
* running on Cortex A53, with PCI-E.
*
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include "k3-am642-hummingboard-t.dts"
#include "k3-serdes.h"
/ {
model = "SolidRun AM642 HummingBoard-T with PCI-E";
};
&pcie0_rc {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_pins>;

13
arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-usb3.dtso → arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-usb3.dts
View File

@ -2,16 +2,19 @@
/*
* Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
*
* Overlay for SolidRun AM642 HummingBoard-T to enable USB-3.1.
* DTS for SolidRun AM642 HummingBoard-T,
* running on Cortex A53, with USB-3.1 Gen 1.
*
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/phy/phy.h>
#include "k3-am642-hummingboard-t.dts"
#include "k3-serdes.h"
/ {
model = "SolidRun AM642 HummingBoard-T with USB-3.1 Gen 1";
};
&serdes0 {
#address-cells = <1>;
#size-cells = <0>;

6
arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
View File

@ -201,8 +201,6 @@ cpsw3g_phy0: ethernet-phy@0 {
reset-gpios = <&main_gpio0 44 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
@ -230,8 +228,6 @@ icssg1_phy03: ethernet-phy@3 {
reset-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
@ -242,8 +238,6 @@ icssg1_phy0c: ethernet-phy@c {
reset-gpios = <&main_gpio1 51 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};

158
arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts
View File

@ -50,11 +50,71 @@ secure_ddr: optee@9e800000 {
no-map;
};
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
c7x_0_dma_memory_region: c7x-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
c7x_0_memory_region: c7x-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
c7x_1_dma_memory_region: c7x-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
c7x_1_memory_region: c7x-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x1c00000>;
alignment = <0x1000>;
no-map;
};
};
vsys_5v0: regulator-1 {
@ -391,3 +451,101 @@ &sdhci1 {
ti,fails-without-test-cd;
status = "okay";
};
&mailbox0_cluster0 {
status = "okay";
mbox_wkup_r5_0: mbox-wkup-r5-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
};
&mailbox0_cluster1 {
status = "okay";
mbox_mcu_r5_0: mbox-mcu-r5-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
};
&mailbox0_cluster2 {
status = "okay";
mbox_c7x_0: mbox-c7x-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
};
&mailbox0_cluster3 {
status = "okay";
mbox_main_r5_0: mbox-main-r5-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_c7x_1: mbox-c7x-1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
/* Timers are used by Remoteproc firmware */
&main_timer0 {
status = "reserved";
};
&main_timer1 {
status = "reserved";
};
&main_timer2 {
status = "reserved";
};
&wkup_r5fss0 {
status = "okay";
};
&wkup_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>;
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
<&wkup_r5fss0_core0_memory_region>;
};
&mcu_r5fss0 {
status = "okay";
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&main_r5fss0 {
status = "okay";
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&c7x_0 {
mboxes = <&mailbox0_cluster2 &mbox_c7x_0>;
memory-region = <&c7x_0_dma_memory_region>,
<&c7x_0_memory_region>;
status = "okay";
};
&c7x_1 {
mboxes = <&mailbox0_cluster3 &mbox_c7x_1>;
memory-region = <&c7x_1_dma_memory_region>,
<&c7x_1_memory_region>;
status = "okay";
};

53
arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso Normal file
View File

@ -0,0 +1,53 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the
* AM68-SK board.
*
* AM68-SK Board Product Link: https://www.ti.com/tool/SK-AM68
*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
#include "k3-pinctrl.h"
/*
* Since Root Complex and Endpoint modes are mutually exclusive
* disable Root Complex mode.
*/
&pcie1_rc {
status = "disabled";
};
&cbass_main {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic500>;
pcie1_ep: pcie-ep@2910000 {
compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x00800000>,
<0x00 0x18000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 276 41>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
};
};

53
arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso Normal file
View File

@ -0,0 +1,53 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT Overlay for enabling PCIE0 instances of PCIe in Endpoint Configuration
* on AM69-SK.
*
* AM69-SK Product Link: https://www.ti.com/tool/SK-AM69
*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
#include "k3-pinctrl.h"
/*
* Since Root Complex and Endpoint modes are mutually exclusive
* disable Root Complex mode.
*/
&pcie0_rc {
status = "disabled";
};
&cbass_main {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic500>;
pcie0_ep: pcie-ep@2900000 {
compatible = "ti,j784s4-pcie-ep";
reg = <0x00 0x02900000 0x00 0x1000>,
<0x00 0x02907000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x10000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 332 0>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
phys = <&serdes1_pcie_link>;
phy-names = "pcie-phy";
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
};
};

41
arch/arm64/boot/dts/ti/k3-am69-sk.dts
View File

@ -484,6 +484,12 @@ J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */
>;
};
main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */
>;
};
};
&wkup_pmx0 {
@ -755,6 +761,7 @@ bucka12: buck12 {
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
bucka3: buck3 {
@ -763,6 +770,7 @@ bucka3: buck3 {
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
bucka4: buck4 {
@ -771,6 +779,7 @@ bucka4: buck4 {
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
bucka5: buck5 {
@ -779,6 +788,7 @@ bucka5: buck5 {
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
ldoa1: ldo1 {
@ -787,6 +797,7 @@ ldoa1: ldo1 {
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
ldoa2: ldo2 {
@ -795,6 +806,7 @@ ldoa2: ldo2 {
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
ldoa3: ldo3 {
@ -803,6 +815,7 @@ ldoa3: ldo3 {
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
ldoa4: ldo4 {
@ -811,6 +824,7 @@ ldoa4: ldo4 {
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
};
};
@ -1299,6 +1313,14 @@ serdes0_pcie_link: phy@0 {
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>;
};
serdes0_usb_link: phy@3 {
reg = <3>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz0 4>;
};
};
&serdes_wiz1 {
@ -1339,3 +1361,22 @@ &pcie3_rc {
phy-names = "pcie-phy";
num-lanes = <1>;
};
&usb_serdes_mux {
idle-states = <0>; /* USB0 to SERDES0 */
};
&usbss0 {
status = "okay";
pinctrl-0 = <&main_usbss0_pins_default>;
pinctrl-names = "default";
ti,vbus-divider;
};
&usb0 {
status = "okay";
dr_mode = "otg";
maximum-speed = "super-speed";
phys = <&serdes0_usb_link>;
phy-names = "cdns3,usb3-phy";
};

4
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
View File

@ -409,6 +409,10 @@ &serdes_ln_ctrl {
<J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
};
&mcu_spi1 {
mux-controls = <&spi1_linkdis 0>;
};
&usb_serdes_mux {
idle-states = <1>; /* USB0 to SERDES lane 3 */
bootph-all;

7
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
View File

@ -184,6 +184,13 @@ phy_gmii_sel: phy@4040 {
reg = <0x4040 0x4>;
#phy-cells = <1>;
};
spi1_linkdis: mux-controller@4060 {
compatible = "reg-mux";
reg = <0x4060 0x4>;
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x1>;
};
};
wkup_conf: bus@43000000 {

53
arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso Normal file
View File

@ -0,0 +1,53 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the
* J7 common processor board.
*
* J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
#include "k3-pinctrl.h"
/*
* Since Root Complex and Endpoint modes are mutually exclusive
* disable Root Complex mode.
*/
&pcie1_rc {
status = "disabled";
};
&cbass_main {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic500>;
pcie1_ep: pcie-ep@2910000 {
compatible = "ti,j721e-pcie-ep";
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x00800000>,
<0x00 0x18000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 240 1>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
phys = <&serdes1_pcie_link>;
phy-names = "pcie-phy";
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
};
};

102
arch/arm64/boot/dts/ti/k3-j722s-evm.dts
View File

@ -359,6 +359,13 @@ audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins {
J722S_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
>;
};
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x030, PIN_INPUT, 7) /* (K23) GPIO0_12 */
>;
};
};
&cpsw3g {
@ -406,6 +413,13 @@ &main_uart5 {
&mcu_pmx0 {
mcu_i2c0_pins_default: mcu-i2c0-default-pins {
pinctrl-single,pins = <
J722S_MCU_IOPAD(0x048, PIN_INPUT, 0) /* (E11) MCU_I2C0_SDA */
J722S_MCU_IOPAD(0x044, PIN_INPUT, 0) /* (B13) MCU_I2C0_SCL */
>;
};
mcu_mcan0_pins_default: mcu-mcan0-default-pins {
pinctrl-single,pins = <
J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */
@ -459,6 +473,87 @@ &wkup_i2c0 {
clock-frequency = <400000>;
status = "okay";
bootph-all;
tps65224: pmic@48 {
compatible = "ti,tps65224-q1";
reg = <0x48>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins_default>;
interrupt-parent = <&main_gpio0>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
ti,primary-pmic;
gpio-controller;
#gpio-cells = <2>;
buck12-supply = <&vsys_io_3v3>;
buck3-supply = <&vsys_io_3v3>;
buck4-supply = <&vsys_io_3v3>;
ldo1-supply = <&vsys_io_3v3>;
ldo2-supply = <&vsys_io_3v3>;
ldo3-supply = <&vsys_io_3v3>;
regulators {
buck1: buck1 {
regulator-name = "vcc1v8_io_buck1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
buck2: buck2 {
regulator-name = "vcc1v1_ddr_buck2";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
buck3: buck3 {
regulator-name = "vcc0v85_ram_buck3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
buck4: buck4 {
regulator-name = "vcc0v75_ioret_buck4";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: ldo1 {
regulator-name = "vdda1v8_pll_ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: ldo2 {
regulator-name = "dvdd3v3_ldo2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: ldo3 {
regulator-name = "vdd1v85_phy_ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&k3_clks {
@ -812,3 +907,10 @@ &main_mcan0 {
&mcu_gpio0 {
status = "okay";
};
&mcu_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_i2c0_pins_default>;
clock-frequency = <400000>;
status = "okay";
};

8
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
View File

@ -635,6 +635,7 @@ bucka12: buck12 {
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
bucka3: buck3 {
@ -643,6 +644,7 @@ bucka3: buck3 {
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
bucka4: buck4 {
@ -651,6 +653,7 @@ bucka4: buck4 {
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
bucka5: buck5 {
@ -659,6 +662,7 @@ bucka5: buck5 {
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
ldoa1: ldo1 {
@ -667,6 +671,7 @@ ldoa1: ldo1 {
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
ldoa2: ldo2 {
@ -675,6 +680,7 @@ ldoa2: ldo2 {
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
ldoa3: ldo3 {
@ -683,6 +689,7 @@ ldoa3: ldo3 {
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
ldoa4: ldo4 {
@ -691,6 +698,7 @@ ldoa4: ldo4 {
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
};
};

22
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
View File

@ -224,7 +224,7 @@ main_gpio_intr: interrupt-controller@a00000 {
};
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
compatible = "ti,j7200-padconf", "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x11c000 0x00 0x120>;
#pinctrl-cells = <1>;
@ -234,7 +234,7 @@ main_pmx0: pinctrl@11c000 {
/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
main_timerio_input: pinctrl@104200 {
compatible = "pinctrl-single";
compatible = "ti,j7200-padconf", "pinctrl-single";
reg = <0x00 0x104200 0x00 0x50>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
@ -243,7 +243,7 @@ main_timerio_input: pinctrl@104200 {
/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
main_timerio_output: pinctrl@104280 {
compatible = "pinctrl-single";
compatible = "ti,j7200-padconf", "pinctrl-single";
reg = <0x00 0x104280 0x00 0x20>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
@ -2040,7 +2040,7 @@ main_spi0: spi@2100000 {
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 376 1>;
clocks = <&k3_clks 376 0>;
status = "disabled";
};
@ -2051,7 +2051,7 @@ main_spi1: spi@2110000 {
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 377 1>;
clocks = <&k3_clks 377 0>;
status = "disabled";
};
@ -2062,7 +2062,7 @@ main_spi2: spi@2120000 {
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 378 1>;
clocks = <&k3_clks 378 0>;
status = "disabled";
};
@ -2073,7 +2073,7 @@ main_spi3: spi@2130000 {
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 379 1>;
clocks = <&k3_clks 379 0>;
status = "disabled";
};
@ -2084,7 +2084,7 @@ main_spi4: spi@2140000 {
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 380 1>;
clocks = <&k3_clks 380 0>;
status = "disabled";
};
@ -2095,7 +2095,7 @@ main_spi5: spi@2150000 {
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 381 1>;
clocks = <&k3_clks 381 0>;
status = "disabled";
};
@ -2106,7 +2106,7 @@ main_spi6: spi@2160000 {
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 382 1>;
clocks = <&k3_clks 382 0>;
status = "disabled";
};
@ -2117,7 +2117,7 @@ main_spi7: spi@2170000 {
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 383 1>;
clocks = <&k3_clks 383 0>;
status = "disabled";
};

12
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi
View File

@ -76,7 +76,7 @@ mcu_ram: sram@41c00000 {
};
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
compatible = "ti,j7200-padconf", "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c000 0x00 0x034>;
#pinctrl-cells = <1>;
@ -85,7 +85,7 @@ wkup_pmx0: pinctrl@4301c000 {
};
wkup_pmx1: pinctrl@4301c038 {
compatible = "pinctrl-single";
compatible = "ti,j7200-padconf", "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c038 0x00 0x02c>;
#pinctrl-cells = <1>;
@ -94,7 +94,7 @@ wkup_pmx1: pinctrl@4301c038 {
};
wkup_pmx2: pinctrl@4301c068 {
compatible = "pinctrl-single";
compatible = "ti,j7200-padconf", "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c068 0x00 0x120>;
#pinctrl-cells = <1>;
@ -103,7 +103,7 @@ wkup_pmx2: pinctrl@4301c068 {
};
wkup_pmx3: pinctrl@4301c190 {
compatible = "pinctrl-single";
compatible = "ti,j7200-padconf", "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c190 0x00 0x004>;
#pinctrl-cells = <1>;
@ -125,7 +125,7 @@ wkup_gpio_intr: interrupt-controller@42200000 {
/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
mcu_timerio_input: pinctrl@40f04200 {
compatible = "pinctrl-single";
compatible = "ti,j7200-padconf", "pinctrl-single";
reg = <0x00 0x40f04200 0x00 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
@ -136,7 +136,7 @@ mcu_timerio_input: pinctrl@40f04200 {
/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
mcu_timerio_output: pinctrl@40f04280 {
compatible = "pinctrl-single";
compatible = "ti,j7200-padconf", "pinctrl-single";
reg = <0x00 0x40f04280 0x00 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;

19
arch/arm64/boot/dts/ti/k3-pinctrl.h
View File

@ -12,6 +12,12 @@
#define PULLTYPESEL_SHIFT (17)
#define RXACTIVE_SHIFT (18)
#define DEBOUNCE_SHIFT (11)
#define FORCE_DS_EN_SHIFT (15)
#define DS_EN_SHIFT (24)
#define DS_OUT_DIS_SHIFT (25)
#define DS_OUT_VAL_SHIFT (26)
#define DS_PULLUD_EN_SHIFT (27)
#define DS_PULLTYPE_SEL_SHIFT (28)
#define PULL_DISABLE (1 << PULLUDEN_SHIFT)
#define PULL_ENABLE (0 << PULLUDEN_SHIFT)
@ -38,6 +44,19 @@
#define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT)
#define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT)
#define PIN_DS_FORCE_DISABLE (0 << FORCE_DS_EN_SHIFT)
#define PIN_DS_FORCE_ENABLE (1 << FORCE_DS_EN_SHIFT)
#define PIN_DS_IO_OVERRIDE_DISABLE (0 << DS_IO_OVERRIDE_EN_SHIFT)
#define PIN_DS_IO_OVERRIDE_ENABLE (1 << DS_IO_OVERRIDE_EN_SHIFT)
#define PIN_DS_OUT_ENABLE (0 << DS_OUT_DIS_SHIFT)
#define PIN_DS_OUT_DISABLE (1 << DS_OUT_DIS_SHIFT)
#define PIN_DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT)
#define PIN_DS_OUT_VALUE_ONE (1 << DS_OUT_VAL_SHIFT)
#define PIN_DS_PULLUD_ENABLE (0 << DS_PULLUD_EN_SHIFT)
#define PIN_DS_PULLUD_DISABLE (1 << DS_PULLUD_EN_SHIFT)
#define PIN_DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT)
#define PIN_DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT)
/* Default mux configuration for gpio-ranges to use with pinctrl */
#define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7)