From a4b422390be3c4147db6d97b016adecb3573635d Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Fri, 1 Nov 2024 14:14:24 +0100 Subject: [PATCH 01/31] arm64: dts: ti: k3-am62x-phyboard-lyra: Set RGB input to 16-bit for HDMI bridge The phyBOARD-Lyra connects only 16 pins to the SII902x HDMI bridge's RGB input. The default 24-bit setting causes incorrect color output. Update to 16-bit to match the hardware configuration. Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20241101131427.3815341-1-w.egorov@phytec.de Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi index d364c247833f..90d17169eba2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi @@ -376,6 +376,7 @@ port@0 { sii9022_in: endpoint { remote-endpoint = <&dpi1_out>; + bus-width = <16>; }; }; From 2a0418ac48d3083e2b209242237abef84497d19f Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Fri, 1 Nov 2024 14:14:25 +0100 Subject: [PATCH 02/31] arm64: dts: ti: k3-am62x-phyboard-lyra: Add HDMI bridge regulators Specify I/0 voltage & core supply regulators used by the SII902x HDMI bridge and make them known to the bridge. This resolves the following warning: sii902x 1-0039: supply iovcc not found, using dummy regulator sii902x 1-0039: supply cvcc12 not found, using dummy regulator Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20241101131427.3815341-2-w.egorov@phytec.de Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am62x-phyboard-lyra.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi index 90d17169eba2..fdc3b200b2f0 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi @@ -112,6 +112,25 @@ vcc_1v8: regulator-vcc-1v8 { regulator-boot-on; }; + vcc_3v3_hdmi: regulator-vcc-3v3-hdmi { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_HDMI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_sw>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_1v2_hdmi: regulator-vcc-1v2-hdmi { + compatible = "regulator-fixed"; + regulator-name = "HDMI_CVCC"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + vcc_3v3_mmc: regulator-vcc-3v3-mmc { compatible = "regulator-fixed"; regulator-name = "VCC_3V3_MMC"; @@ -367,6 +386,9 @@ sii9022: bridge-hdmi@39 { pinctrl-names = "default"; pinctrl-0 = <&hdmi_int_pins_default>; + iovcc-supply = <&vcc_3v3_hdmi>; + cvcc12-supply = <&vcc_1v2_hdmi>; + ports { #address-cells = <1>; #size-cells = <0>; From 4ffe12ccae4ab20e5dc41dc428f909467ed7cc4d Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Fri, 1 Nov 2024 14:14:26 +0100 Subject: [PATCH 03/31] arm64: dts: ti: k3-am62-phycore-som: Define vcc-supply for I2C EEPROM Specify the regulator for the EEPROM supply voltage and associate it with the EEPROM device. This resolves the following warning: at24 0-0050: supply vcc not found, using dummy regulator Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20241101131427.3815341-3-w.egorov@phytec.de Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index 5952874fe429..2ef4cbaec789 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -95,6 +95,16 @@ vdd_1v8: regulator-vdd-1v8 { regulator-boot-on; }; + vddshv_3v3: regulator-vddshv-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDSHV0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + regulator-boot-on; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -313,6 +323,7 @@ eeprom@50 { compatible = "atmel,24c32"; pagesize = <32>; reg = <0x50>; + vcc-supply = <&vddshv_3v3>; }; i2c_som_rtc: rtc@52 { From 80ad23c4032c6b2afe225c866b9496472965b9ed Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Fri, 1 Nov 2024 14:14:27 +0100 Subject: [PATCH 04/31] arm64: dts: ti: am62-phyboard-lyra: Provide a vcc-supply for the I2C EEPROM Add the missing vcc-supply property to the EEPROM node which resolves the following warning: at24 1-0051: supply vcc not found, using dummy regulator Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20241101131427.3815341-4-w.egorov@phytec.de Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi index fdc3b200b2f0..922cad14c9f8 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi @@ -416,6 +416,7 @@ eeprom@51 { compatible = "atmel,24c02"; pagesize = <16>; reg = <0x51>; + vcc-supply = <&vcc_3v3_mmc>; }; }; From 94a7666e3eb9f52f0097c0ca6fb093f5f20d4462 Mon Sep 17 00:00:00 2001 From: Anurag Dutta Date: Mon, 4 Nov 2024 17:42:41 +0530 Subject: [PATCH 05/31] arm64: dts: ti: k3-j784s4: Fix clock IDs for MCSPI instances The clock IDs for multiple MCSPI instances across wakeup domain in J784s4 are incorrect when compared with documentation [1]. Fix the clock IDs to their appropriate values. [1] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j784s4/clocks.html Signed-off-by: Anurag Dutta Link: https://lore.kernel.org/r/20241104121241.102027-1-a-dutta@ti.com Signed-off-by: Nishanth Menon --- .../dts/ti/k3-j784s4-j742s2-main-common.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 7721852c1f68..f27f7ae51479 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -2040,7 +2040,7 @@ main_spi0: spi@2100000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 376 1>; + clocks = <&k3_clks 376 0>; status = "disabled"; }; @@ -2051,7 +2051,7 @@ main_spi1: spi@2110000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 377 1>; + clocks = <&k3_clks 377 0>; status = "disabled"; }; @@ -2062,7 +2062,7 @@ main_spi2: spi@2120000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 378 1>; + clocks = <&k3_clks 378 0>; status = "disabled"; }; @@ -2073,7 +2073,7 @@ main_spi3: spi@2130000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 379 1>; + clocks = <&k3_clks 379 0>; status = "disabled"; }; @@ -2084,7 +2084,7 @@ main_spi4: spi@2140000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 380 1>; + clocks = <&k3_clks 380 0>; status = "disabled"; }; @@ -2095,7 +2095,7 @@ main_spi5: spi@2150000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 381 1>; + clocks = <&k3_clks 381 0>; status = "disabled"; }; @@ -2106,7 +2106,7 @@ main_spi6: spi@2160000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 382 1>; + clocks = <&k3_clks 382 0>; status = "disabled"; }; @@ -2117,7 +2117,7 @@ main_spi7: spi@2170000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 383 1>; + clocks = <&k3_clks 383 0>; status = "disabled"; }; From 325aa0f6b36eab0fe7d7efdb49b55cf7d664424a Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 5 Dec 2024 17:31:28 +0530 Subject: [PATCH 06/31] arm64: dts: ti: k3-pinctrl: Introduce deep sleep macros The behavior of pins in deep sleep mode can be configured by programming the corresponding bits in the respective Pad Configuration register. Add macros to support this. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20241205120134.754664-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h index 22b8d73cfd32..cac7cccc1112 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -12,6 +12,12 @@ #define PULLTYPESEL_SHIFT (17) #define RXACTIVE_SHIFT (18) #define DEBOUNCE_SHIFT (11) +#define FORCE_DS_EN_SHIFT (15) +#define DS_EN_SHIFT (24) +#define DS_OUT_DIS_SHIFT (25) +#define DS_OUT_VAL_SHIFT (26) +#define DS_PULLUD_EN_SHIFT (27) +#define DS_PULLTYPE_SEL_SHIFT (28) #define PULL_DISABLE (1 << PULLUDEN_SHIFT) #define PULL_ENABLE (0 << PULLUDEN_SHIFT) @@ -38,6 +44,19 @@ #define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) #define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) +#define PIN_DS_FORCE_DISABLE (0 << FORCE_DS_EN_SHIFT) +#define PIN_DS_FORCE_ENABLE (1 << FORCE_DS_EN_SHIFT) +#define PIN_DS_IO_OVERRIDE_DISABLE (0 << DS_IO_OVERRIDE_EN_SHIFT) +#define PIN_DS_IO_OVERRIDE_ENABLE (1 << DS_IO_OVERRIDE_EN_SHIFT) +#define PIN_DS_OUT_ENABLE (0 << DS_OUT_DIS_SHIFT) +#define PIN_DS_OUT_DISABLE (1 << DS_OUT_DIS_SHIFT) +#define PIN_DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) +#define PIN_DS_OUT_VALUE_ONE (1 << DS_OUT_VAL_SHIFT) +#define PIN_DS_PULLUD_ENABLE (0 << DS_PULLUD_EN_SHIFT) +#define PIN_DS_PULLUD_DISABLE (1 << DS_PULLUD_EN_SHIFT) +#define PIN_DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT) +#define PIN_DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT) + /* Default mux configuration for gpio-ranges to use with pinctrl */ #define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7) From 527f884d2d94981016e181dcbd4c4b5bf597c0ad Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 5 Dec 2024 17:31:29 +0530 Subject: [PATCH 07/31] arm64: dts: ti: k3-am62x-sk-common: Support SoC wakeup using USB1 wakeup After the SoC has entered the Deep Sleep mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requires that the pin corresponding to the Type-A connector remains pulled up even after the SoC has entered the Deep Sleep mode. Hence, enable Deep Sleep pullup / pulldown selection for the USB1_DRVVBUS pin and set its Deep Sleep state to PULL_UP. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20241205120134.754664-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 6957b3e44c82..8b6316454639 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -256,7 +256,7 @@ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */ main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < - AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ + AM62X_IOPAD(0x0258, PIN_OUTPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (F18/E16) USB1_DRVVBUS */ >; }; From 0cd578054e7107cab921ff0c24f4ac6d14d3661b Mon Sep 17 00:00:00 2001 From: Andrew Halaney Date: Wed, 13 Nov 2024 10:15:16 +0100 Subject: [PATCH 08/31] arm64: dts: ti: k3-j784s4-evm: Mark tps659413 regulators as bootph-all In order for the MCU domain to access this PMIC, a regulator needs to be marked appropriately otherwise it is not seen by SPL and therefore not configured. This is necessary if the MCU domain is to program the TPS6594 MCU ESM state machine, which is required to wire up the watchdog in a manner that will reset the board. Signed-off-by: Andrew Halaney Reviewed-by: Beleswar Padhi Tested-by: Udit Kumar Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20241113-b4-j784s4-tps6594-bootph-v4-1-102ddaa1bdc6@redhat.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index b2e2b9f507a9..2664f74a9c7a 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -635,6 +635,7 @@ bucka12: buck12 { regulator-max-microvolt = <1100000>; regulator-boot-on; regulator-always-on; + bootph-all; }; bucka3: buck3 { @@ -643,6 +644,7 @@ bucka3: buck3 { regulator-max-microvolt = <850000>; regulator-boot-on; regulator-always-on; + bootph-all; }; bucka4: buck4 { @@ -651,6 +653,7 @@ bucka4: buck4 { regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; bucka5: buck5 { @@ -659,6 +662,7 @@ bucka5: buck5 { regulator-max-microvolt = <850000>; regulator-boot-on; regulator-always-on; + bootph-all; }; ldoa1: ldo1 { @@ -667,6 +671,7 @@ ldoa1: ldo1 { regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; ldoa2: ldo2 { @@ -675,6 +680,7 @@ ldoa2: ldo2 { regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; + bootph-all; }; ldoa3: ldo3 { @@ -683,6 +689,7 @@ ldoa3: ldo3 { regulator-max-microvolt = <800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; ldoa4: ldo4 { @@ -691,6 +698,7 @@ ldoa4: ldo4 { regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; }; }; From 0a41157c5a988520debb656325722f401163eca3 Mon Sep 17 00:00:00 2001 From: Andrew Halaney Date: Wed, 13 Nov 2024 10:15:17 +0100 Subject: [PATCH 09/31] arm64: dts: ti: k3-am69-sk: Mark tps659413 regulators as bootph-all In order for the MCU domain to access this PMIC, a regulator needs to be marked appropriately otherwise it is not seen by SPL and therefore not configured. This is necessary if the MCU domain is to program the TPS6594 MCU ESM state machine, which is required to wire up the watchdog in a manner that will reset the board. Signed-off-by: Andrew Halaney Reviewed-by: Beleswar Padhi Tested-by: Udit Kumar Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20241113-b4-j784s4-tps6594-bootph-v4-2-102ddaa1bdc6@redhat.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 1e36965a1403..5f24a1608bdc 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -755,6 +755,7 @@ bucka12: buck12 { regulator-max-microvolt = <1100000>; regulator-boot-on; regulator-always-on; + bootph-all; }; bucka3: buck3 { @@ -763,6 +764,7 @@ bucka3: buck3 { regulator-max-microvolt = <850000>; regulator-boot-on; regulator-always-on; + bootph-all; }; bucka4: buck4 { @@ -771,6 +773,7 @@ bucka4: buck4 { regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; bucka5: buck5 { @@ -779,6 +782,7 @@ bucka5: buck5 { regulator-max-microvolt = <850000>; regulator-boot-on; regulator-always-on; + bootph-all; }; ldoa1: ldo1 { @@ -787,6 +791,7 @@ ldoa1: ldo1 { regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; ldoa2: ldo2 { @@ -795,6 +800,7 @@ ldoa2: ldo2 { regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; + bootph-all; }; ldoa3: ldo3 { @@ -803,6 +809,7 @@ ldoa3: ldo3 { regulator-max-microvolt = <800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; ldoa4: ldo4 { @@ -811,6 +818,7 @@ ldoa4: ldo4 { regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; }; }; From f7ed5ae30cf395d92a3e1e3c843fa86ce96167b8 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Wed, 13 Nov 2024 16:39:54 +0530 Subject: [PATCH 10/31] dt-bindings: soc: ti: pruss: Add clocks for ICSSG The ICSSG module has 7 clocks for each instance. These clocks are ICSSG0_CORE_CLK, ICSSG0_IEP_CLK, ICSSG0_ICLK, ICSSG0_UART_CLK, RGMII_MHZ_250_CLK, RGMII_MHZ_50_CLK and RGMII_MHZ_5_CLK These clocks are described in AM64x TRM Section 6.4.3 Table 6-398. Add these clocks to the dt binding of ICSSG. Link: https://www.ti.com/lit/pdf/spruim2 (AM64x TRM) Signed-off-by: MD Danish Anwar Reviewed-by: Roger Quadros Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20241113110955.3876045-2-danishanwar@ti.com Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml index 3cb1471cc6b6..927b3200e29e 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml @@ -92,6 +92,16 @@ properties: description: | This property is as per sci-pm-domain.txt. + clocks: + items: + - description: ICSSG_CORE Clock + - description: ICSSG_IEP Clock + - description: ICSSG_RGMII_MHZ_250 Clock + - description: ICSSG_RGMII_MHZ_50 Clock + - description: ICSSG_RGMII_MHZ_5 Clock + - description: ICSSG_UART Clock + - description: ICSSG_ICLK Clock + patternProperties: memories@[a-f0-9]+$: From 25aadf5039fe8920835fb1452db08afa27a0edd9 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Wed, 13 Nov 2024 16:39:55 +0530 Subject: [PATCH 11/31] arm64: dts: ti: k3-am64-main: Switch ICSSG clock to core clock ICSSG has 7 available clocks per instance. Add all the cloks to ICSSG nodes. ICSSG currently uses ICSSG_ICLK (clk id 20) which operates at 250MHz. Switch ICSSG clock to ICSSG_CORE clock (clk id 0) which operates at 333MHz. ICSSG_CORE clock will help get the most out of ICSSG as more cycles are needed to fully support all ICSSG features. This commit also changes assigned-clock-parents of coreclk-mux to ICSSG_CORE clock from ICSSG_ICLK. Performance update in dual mac mode With ICSSG_CORE Clk @ 333MHz Tx throughput - 934 Mbps Rx throughput - 914 Mbps, With ICSSG_ICLK clk @ 250MHz, Tx throughput - 920 Mbps Rx throughput - 706 Mbps Signed-off-by: MD Danish Anwar Tested-by: Wadim Egorov Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20241113110955.3876045-3-danishanwar@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index c66289a4362b..324eb44c258d 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1227,6 +1227,15 @@ icssg0: icssg@30000000 { #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x30000000 0x80000>; + clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ + <&k3_clks 81 3>, /* icssg0_iep_clk */ + <&k3_clks 81 16>, /* icssg0_rgmii_mhz_250_clk */ + <&k3_clks 81 17>, /* icssg0_rgmii_mhz_50_clk */ + <&k3_clks 81 18>, /* icssg0_rgmii_mhz_5_clk */ + <&k3_clks 81 19>, /* icssg0_uart_clk */ + <&k3_clks 81 20>; /* icssg0_iclk */ + assigned-clocks = <&k3_clks 81 0>; + assigned-clock-parents = <&k3_clks 81 2>; icssg0_mem: memories@0 { reg = <0x0 0x2000>, @@ -1252,7 +1261,7 @@ icssg0_coreclk_mux: coreclk-mux@3c { clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ <&k3_clks 81 20>; /* icssg0_iclk */ assigned-clocks = <&icssg0_coreclk_mux>; - assigned-clock-parents = <&k3_clks 81 20>; + assigned-clock-parents = <&k3_clks 81 0>; }; icssg0_iepclk_mux: iepclk-mux@30 { @@ -1397,6 +1406,15 @@ icssg1: icssg@30080000 { #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x30080000 0x80000>; + clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ + <&k3_clks 82 3>, /* icssg1_iep_clk */ + <&k3_clks 82 16>, /* icssg1_rgmii_mhz_250_clk */ + <&k3_clks 82 17>, /* icssg1_rgmii_mhz_50_clk */ + <&k3_clks 82 18>, /* icssg1_rgmii_mhz_5_clk */ + <&k3_clks 82 19>, /* icssg1_uart_clk */ + <&k3_clks 82 20>; /* icssg1_iclk */ + assigned-clocks = <&k3_clks 82 0>; + assigned-clock-parents = <&k3_clks 82 2>; icssg1_mem: memories@0 { reg = <0x0 0x2000>, @@ -1422,7 +1440,7 @@ icssg1_coreclk_mux: coreclk-mux@3c { clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ <&k3_clks 82 20>; /* icssg1_iclk */ assigned-clocks = <&icssg1_coreclk_mux>; - assigned-clock-parents = <&k3_clks 82 20>; + assigned-clock-parents = <&k3_clks 82 0>; }; icssg1_iepclk_mux: iepclk-mux@30 { From 09b428453219d470475d0d6447c954bf63b95705 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 15 Nov 2024 13:33:59 -0600 Subject: [PATCH 12/31] arm64: dts: ti: Remove unused and undocumented "ti,(rx|tx)-fifo-depth" properties Remove "ti,(rx|tx)-fifo-depth" properties which are both unused in the kernel and undocumented. Most likely they are leftovers from downstream. There are similar properties, but DP83867_PHYCR_FIFO_DEPTH_4_B_NIB represents the default value so adding them is not necessary. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20241115193359.3618020-1-robh@kernel.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts index e06a3b178b34..8f64d6272b1b 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -201,8 +201,6 @@ cpsw3g_phy0: ethernet-phy@0 { reset-gpios = <&main_gpio0 44 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <1000>; - ti,rx-fifo-depth = ; - ti,tx-fifo-depth = ; ti,rx-internal-delay = ; ti,clk-output-sel = ; }; @@ -230,8 +228,6 @@ icssg1_phy03: ethernet-phy@3 { reset-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <1000>; - ti,rx-fifo-depth = ; - ti,tx-fifo-depth = ; ti,rx-internal-delay = ; ti,clk-output-sel = ; }; @@ -242,8 +238,6 @@ icssg1_phy0c: ethernet-phy@c { reset-gpios = <&main_gpio1 51 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <1000>; - ti,rx-fifo-depth = ; - ti,tx-fifo-depth = ; ti,rx-internal-delay = ; ti,clk-output-sel = ; }; From 28596f0dbf2452a6629026cf4bd9763f2456be64 Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 14 Nov 2024 22:23:31 +0530 Subject: [PATCH 13/31] arm64: dts: ti: k3-am62x-sk-common: Add bootph-all property in cpsw_mac_syscon node Ethernet boot requires CPSW node to be present starting from R5 SPL stage. Add bootph-all property in CPSW MAC's eFuse node cpsw_mac_syscon to enable this node during SPL stage along with later boot stages so that CPSW port will get static MAC address. Reviewed-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar Link: https://lore.kernel.org/r/20241114165331.1279065-1-c-vankar@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 8b6316454639..2f129e8cd5b9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -315,6 +315,10 @@ AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */ }; }; +&cpsw_mac_syscon { + bootph-all; +}; + &wkup_uart0 { /* WKUP UART0 is used by DM firmware */ bootph-pre-ram; From 9442f963098f1eb9d1565fdd694e506d0c2c6f45 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Tue, 5 Nov 2024 14:42:24 +0530 Subject: [PATCH 14/31] arm64: dts: ti: k3-j722s-evm: Enable support for mcu_i2c0 Enable support for mcu_i2c0 and add pinmux required to bring out the mcu_i2c0 signals on 40-pin RPi expansion header on the J722S EVM. Signed-off-by: Bhavya Kapoor Signed-off-by: Shreyash Sinha Reviewed-by: Prasanth Babu Mantena Link: https://lore.kernel.org/r/20241105091224.23453-1-b-kapoor@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index a00f4a7d20d9..796287c76b69 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -406,6 +406,13 @@ &main_uart5 { &mcu_pmx0 { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x048, PIN_INPUT, 0) /* (E11) MCU_I2C0_SDA */ + J722S_MCU_IOPAD(0x044, PIN_INPUT, 0) /* (B13) MCU_I2C0_SCL */ + >; + }; + mcu_mcan0_pins_default: mcu-mcan0-default-pins { pinctrl-single,pins = < J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */ @@ -812,3 +819,10 @@ &main_mcan0 { &mcu_gpio0 { status = "okay"; }; + +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; +}; From 17d0723c6cf841ebaf510eaf9bb1ebf4991d6e9d Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 3 Dec 2024 10:40:31 -0600 Subject: [PATCH 15/31] arm64: dts: ti: k3-am625-sk: Remove M4 mailbox node redefinition This node is already defined in the included k3-am62x-sk-common.dtsi. Remove this redefinition. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20241203164031.20211-1-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index ae81ebb39d02..2fbfa3719345 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -219,13 +219,6 @@ cpsw3g_phy1: ethernet-phy@1 { }; }; -&mailbox0_cluster0 { - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - &fss { bootph-all; }; From 61c1c774d33a5305f5440380d2be5e23464cd3de Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 3 Dec 2024 11:41:13 -0600 Subject: [PATCH 16/31] arm64: dts: ti: k3-am62p: Enable Mailbox nodes at the board level Mailbox nodes defined in the top-level J722s/AM62p SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20241203174114.94751-1-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 4 ++++ arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 41e1c24b1144..39f5c2d12fad 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -768,6 +768,7 @@ mailbox0_cluster0: mailbox@29000000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster1: mailbox@29010000 { @@ -777,6 +778,7 @@ mailbox0_cluster1: mailbox@29010000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster2: mailbox@29020000 { @@ -786,6 +788,7 @@ mailbox0_cluster2: mailbox@29020000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster3: mailbox@29030000 { @@ -795,6 +798,7 @@ mailbox0_cluster3: mailbox@29030000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; ecap0: pwm@23100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 7f3dc39e12bc..ad71d2f27f53 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -621,6 +621,8 @@ partition@3fc0000 { }; &mailbox0_cluster0 { + status = "okay"; + mbox_r5_0: mbox-r5-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; @@ -628,6 +630,8 @@ mbox_r5_0: mbox-r5-0 { }; &mailbox0_cluster1 { + status = "okay"; + mbox_mcu_r5_0: mbox-mcu-r5-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; From 89d8dbee6d1860c69039d8859003808b5e90266c Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 3 Dec 2024 11:41:14 -0600 Subject: [PATCH 17/31] arm64: dts: ti: k3-am67a-beagley-ai: Add remote processor nodes Add nodes for the R5F and C7x cores on the SoC. This includes the mailbox and memory carveouts used by these remote cores. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20241203174114.94751-2-afd@ti.com Signed-off-by: Nishanth Menon --- .../arm64/boot/dts/ti/k3-am67a-beagley-ai.dts | 158 ++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts index 44dfbdf89277..9be6bba28c26 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts @@ -50,11 +50,71 @@ secure_ddr: optee@9e800000 { no-map; }; + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + c7x_1_memory_region: c7x-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x1c00000>; + alignment = <0x1000>; + no-map; + }; }; vsys_5v0: regulator-1 { @@ -391,3 +451,101 @@ &sdhci1 { ti,fails-without-test-cd; status = "okay"; }; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_wkup_r5_0: mbox-wkup-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + + mbox_main_r5_0: mbox-main-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c7x_1: mbox-c7x-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&main_r5fss0 { + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&c7x_0 { + mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status = "okay"; +}; + +&c7x_1 { + mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; + memory-region = <&c7x_1_dma_memory_region>, + <&c7x_1_memory_region>; + status = "okay"; +}; From 72c691d77ea5d0c4636fd3e9f0ad80d813c7d1a7 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Tue, 10 Dec 2024 14:59:24 -0600 Subject: [PATCH 18/31] arm64: dts: ti: k3-am62: Remove duplicate GICR reg The GIC Redistributor control register range is mapped twice. Remove the extra entry from the reg range. Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC") Reported-by: Bin Liu Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20241210-am62-gic-fixup-v1-1-758b4d5b4a0a@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 7cd727d10a5f..7d355aa73ea2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -23,7 +23,6 @@ gic500: interrupt-controller@1800000 { interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ <0x00 0x01880000 0x00 0xc0000>, /* GICR */ - <0x00 0x01880000 0x00 0xc0000>, /* GICR */ <0x01 0x00000000 0x00 0x2000>, /* GICC */ <0x01 0x00010000 0x00 0x1000>, /* GICH */ <0x01 0x00020000 0x00 0x2000>; /* GICV */ From 6f0232577e260cdbc25508e27bb0b75ade7e7ebc Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Tue, 10 Dec 2024 14:59:25 -0600 Subject: [PATCH 19/31] arm64: dts: ti: k3-am62a: Remove duplicate GICR reg The GIC Redistributor control range is mapped twice. Remove the extra entry from the reg range. Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Reported-by: Bin Liu Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20241210-am62-gic-fixup-v1-2-758b4d5b4a0a@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index a93e2cd7b8c7..a1daba7b1fad 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -18,7 +18,6 @@ gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ <0x00 0x01880000 0x00 0xc0000>, /* GICR */ - <0x00 0x01880000 0x00 0xc0000>, /* GICR */ <0x01 0x00000000 0x00 0x2000>, /* GICC */ <0x01 0x00010000 0x00 0x1000>, /* GICH */ <0x01 0x00020000 0x00 0x2000>; /* GICV */ From 3cc7633cab8b55a77c86aae3349d83ab1e13a5bb Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Fri, 20 Dec 2024 11:15:16 +0530 Subject: [PATCH 20/31] arm64: dts: ti: k3-am62p-j722s-common-main: Enable USB0 for DFU boot Add the "bootph-all" property to the "usb0" device-tree node. This is required for the USB0 instance of USB to be functional at all stages of USB DFU boot. Signed-off-by: Siddharth Vadapalli Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20241220054550.153360-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 39f5c2d12fad..6e3beb5c2e01 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -651,6 +651,7 @@ usb0: usb@31000000 { interrupt-names = "host", "peripheral"; maximum-speed = "high-speed"; dr_mode = "otg"; + bootph-all; snps,usb2-gadget-lpm-disable; snps,usb2-lpm-disable; }; From b48888c9c4af15fcaa57076aeff6c48c90809bc5 Mon Sep 17 00:00:00 2001 From: Thomas Richard Date: Mon, 30 Dec 2024 10:49:00 +0100 Subject: [PATCH 21/31] arm64: dts: ti: k3-j784s4: Use ti,j7200-padconf compatible Like on j7200, pinctrl contexts shall be saved and restored during suspend-to-ram. So use ti,j7200-padconf compatible. Signed-off-by: Thomas Richard Link: https://lore.kernel.org/r/20241230-j784s4-s2r-pinctrl-v2-1-35039fafe2ca@bootlin.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 6 +++--- .../dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index f27f7ae51479..83bbf94b58d1 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -224,7 +224,7 @@ main_gpio_intr: interrupt-controller@a00000 { }; main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x11c000 0x00 0x120>; #pinctrl-cells = <1>; @@ -234,7 +234,7 @@ main_pmx0: pinctrl@11c000 { /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x00 0x104200 0x00 0x50>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -243,7 +243,7 @@ main_timerio_input: pinctrl@104200 { /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x00 0x104280 0x00 0x20>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index 9638130caece..52e2965a3bf5 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -76,7 +76,7 @@ mcu_ram: sram@41c00000 { }; wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c000 0x00 0x034>; #pinctrl-cells = <1>; @@ -85,7 +85,7 @@ wkup_pmx0: pinctrl@4301c000 { }; wkup_pmx1: pinctrl@4301c038 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c038 0x00 0x02c>; #pinctrl-cells = <1>; @@ -94,7 +94,7 @@ wkup_pmx1: pinctrl@4301c038 { }; wkup_pmx2: pinctrl@4301c068 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c068 0x00 0x120>; #pinctrl-cells = <1>; @@ -103,7 +103,7 @@ wkup_pmx2: pinctrl@4301c068 { }; wkup_pmx3: pinctrl@4301c190 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c190 0x00 0x004>; #pinctrl-cells = <1>; @@ -125,7 +125,7 @@ wkup_gpio_intr: interrupt-controller@42200000 { /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x00 0x40f04200 0x00 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -136,7 +136,7 @@ mcu_timerio_input: pinctrl@40f04200 { /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x00 0x40f04280 0x00 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; From 6b51892b31fe83fe7cc8cf69e4bf7721cf08951b Mon Sep 17 00:00:00 2001 From: Anurag Dutta Date: Wed, 27 Nov 2024 13:26:44 +0530 Subject: [PATCH 22/31] arm64: dts: ti: k3-j7200: Add node to disable loopback connection CTRLMMR_MCU_SPI1_CTRL register controls if MCU_SPI1 is directly connected to SPI3 in the MAIN Domain (default) or if MCU_SPI1 and SPI3 are independently pinned out. By default, the field SPI1_LINKDIS (Bit 0) is set to 0h. In order to disable the direct connection, the SPI1_LINKDIS (Bit 0) needs to be set to 1h. Model this functionality as a "reg-mux" device and based on the idle-state property, enable/disable the connection bewtween MCU_SPI1 and MAIN_SPI3. The register field description has been referred from J7200 TRM [1] (Table 5-517. CTRLMMR_MCU_SPI1_CTRL Register Field Descriptions). [1] https://www.ti.com/lit/pdf/spruiu1 Signed-off-by: Anurag Dutta Link: https://lore.kernel.org/r/20241127075644.210759-1-a-dutta@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 4 ++++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index db43e7e10b76..f684ce6ad9ad 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -409,6 +409,10 @@ &serdes_ln_ctrl { , ; }; +&mcu_spi1 { + mux-controls = <&spi1_linkdis 0>; +}; + &usb_serdes_mux { idle-states = <1>; /* USB0 to SERDES lane 3 */ bootph-all; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 6a8453865874..56ab144fea07 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -184,6 +184,13 @@ phy_gmii_sel: phy@4040 { reg = <0x4040 0x4>; #phy-cells = <1>; }; + + spi1_linkdis: mux-controller@4060 { + compatible = "reg-mux"; + reg = <0x4060 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x1>; + }; }; wkup_conf: bus@43000000 { From a7543eaeb31544b9c3f6248cac8189aa1480c0f5 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 5 Dec 2024 16:20:33 +0530 Subject: [PATCH 23/31] arm64: dts: ti: Makefile: Fix typo "k3-j7200-evm-pcie1-ep.dtbo" The list of "dtbs" should contain the resultant "dtb" formed by applying the "dtbo" overlay on the base "dtb", rather than the "dtbo" itself. Hence, change "k3-j7200-evm-pcie1-ep.dtbo" to "k3-j7200-evm-pcie1-ep.dtb" in the list of "dtbs". Fixes: f43ec89bbc83 ("arm64: dts: ti: k3-j7200-evm: Add overlay for PCIE1 Endpoint Mode") Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20241205105041.749576-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index f71360f14f23..379bfa4425d4 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -230,7 +230,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ - k3-j7200-evm-pcie1-ep.dtbo \ + k3-j7200-evm-pcie1-ep.dtb \ k3-j721e-common-proc-board-infotainment.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ From c3015d4540a47ced846bf973e5a473fb4181662a Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 5 Dec 2024 16:20:34 +0530 Subject: [PATCH 24/31] arm64: dts: ti: k3-j721e-evm: Add overlay for PCIE1 Endpoint Mode Add overlay to enable the PCIE1 instance of PCIe on J721E-EVM in Endpoint mode of operation. Additionally, in order to support both PCIE0 and PCIE1 in Endpoint Mode of operation, enable applying device-tree overlays on "k3-j721e-evm-pcie0-ep.dtb", thereby allowing the overlay for PCIE1 in Endpoint mode to be applied on the aforementioned DTB. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20241205105041.749576-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 5 ++ .../boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso | 53 +++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 379bfa4425d4..03bacbc589ee 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -107,6 +107,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board-infotainment.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo @@ -200,6 +201,8 @@ k3-j721e-common-proc-board-infotainment-dtbs := k3-j721e-common-proc-board.dtb \ k3-j721e-common-proc-board-infotainment.dtbo k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo +k3-j721e-evm-pcie1-ep-dtbs := k3-j721e-common-proc-board.dtb \ + k3-j721e-evm-pcie1-ep.dtbo k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ @@ -233,6 +236,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j7200-evm-pcie1-ep.dtb \ k3-j721e-common-proc-board-infotainment.dtb \ k3-j721e-evm-pcie0-ep.dtb \ + k3-j721e-evm-pcie1-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtb \ @@ -255,6 +259,7 @@ DTC_FLAGS_k3-am68-sk-base-board += -@ DTC_FLAGS_k3-am69-sk += -@ DTC_FLAGS_k3-j7200-common-proc-board += -@ DTC_FLAGS_k3-j721e-common-proc-board += -@ +DTC_FLAGS_k3-j721e-evm-pcie0-ep += -@ DTC_FLAGS_k3-j721e-sk += -@ DTC_FLAGS_k3-j721s2-common-proc-board += -@ DTC_FLAGS_k3-j784s4-evm += -@ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso new file mode 100644 index 000000000000..a8cccdcf3e3b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the + * J7 common processor board. + * + * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie1_rc { + status = "disabled"; +}; + +&cbass_main { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 1>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + }; +}; From 58efed5800e901cf9b320c56e8879878f09b8291 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 5 Dec 2024 16:20:35 +0530 Subject: [PATCH 25/31] arm64: dts: ti: k3-am68-sk-base-board: Add overlay for PCIE1 Endpoint Mode Add overlay to enable the PCIE1 instance of PCIe on AM68-SK-Base-Board in Endpoint mode of operation. PCIE1 on AM68-SK-Base-Board supports x2 Lane operation unlike its counterpart on J721S2-EVM which supports x1 Lane. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20241205105041.749576-4-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 4 ++ .../ti/k3-am68-sk-base-board-pcie1-ep.dtso | 53 +++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 03bacbc589ee..04438f7136b8 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -113,6 +113,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo k3-j721s2-evm-dtbs := k3-j721s2-common-proc-board.dtb k3-j721s2-evm-gesi-exp-board.dtbo @@ -193,6 +194,8 @@ k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo +k3-am68-sk-base-board-pcie1-ep-dtbs := k3-am68-sk-base-board.dtb \ + k3-am68-sk-base-board-pcie1-ep.dtbo k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j7200-evm-pcie1-ep-dtbs := k3-j7200-common-proc-board.dtb \ @@ -232,6 +235,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ + k3-am68-sk-base-board-pcie1-ep.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ k3-j7200-evm-pcie1-ep.dtb \ k3-j721e-common-proc-board-infotainment.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso new file mode 100644 index 000000000000..455736e378cc --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the + * AM68-SK board. + * + * AM68-SK Board Product Link: https://www.ti.com/tool/SK-AM68 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie1_rc { + status = "disabled"; +}; + +&cbass_main { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 41>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + }; +}; From b09cc758bc015a100b440d5c70098aebd0ddcd43 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 5 Dec 2024 16:20:36 +0530 Subject: [PATCH 26/31] arm64: dts: ti: k3-am69-sk: Add overlay for PCIE0 Endpoint Mode Add overlay to enable the PCIE0 instance of PCIe on AM69-SK in Endpoint mode of operation. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20241205105041.749576-5-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 4 ++ .../boot/dts/ti/k3-am69-sk-pcie0-ep.dtso | 53 +++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 04438f7136b8..db5ae27467e7 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-pcie0-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo @@ -198,6 +199,8 @@ k3-am68-sk-base-board-pcie1-ep-dtbs := k3-am68-sk-base-board.dtb \ k3-am68-sk-base-board-pcie1-ep.dtbo k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo +k3-am69-sk-pcie0-ep-dtbs := k3-am69-sk.dtb \ + k3-am69-sk-pcie0-ep.dtbo k3-j7200-evm-pcie1-ep-dtbs := k3-j7200-common-proc-board.dtb \ k3-j7200-evm-pcie1-ep.dtbo k3-j721e-common-proc-board-infotainment-dtbs := k3-j721e-common-proc-board.dtb \ @@ -237,6 +240,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am68-sk-base-board-pcie1-ep.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ + k3-am69-sk-pcie0-ep.dtb \ k3-j7200-evm-pcie1-ep.dtb \ k3-j721e-common-proc-board-infotainment.dtb \ k3-j721e-evm-pcie0-ep.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso new file mode 100644 index 000000000000..9a5bcf282a9e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling PCIE0 instances of PCIe in Endpoint Configuration + * on AM69-SK. + * + * AM69-SK Product Link: https://www.ti.com/tool/SK-AM69 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie0_rc { + status = "disabled"; +}; + +&cbass_main { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + + pcie0_ep: pcie-ep@2900000 { + compatible = "ti,j784s4-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 332 0>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; + }; +}; From e2b69180431968250bf3c0c581155f1b37d057c1 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Wed, 1 Jan 2025 13:30:22 +0100 Subject: [PATCH 27/31] arm64: dts: ti: k3-am642-hummingboard-t: Convert overlay to board dts SolidRun HummingBoard-T has two options for M.2 connector, supporting either PCI-E or USB-3.1 Gen 1 - depending on configuration of a mux on the serdes lane. The required configurations in device-tree were modeled as overlays. The USB-3.1 overlay uses /delete-property/ to unset a boolean property on the usb controller limiting it to USB-2.0 by default. Overlays can not delete a property from the base dtb, therefore this overlay is at this time useless. Convert both overlays into full dts by including the base board dts. While the pcie overlay was functional, both are converted for a consistent user experience when selecting between the two mutually exclusive configurations. Reported-by: Geert Uytterhoeven Closes: https://lore.kernel.org/linux-devicetree/CAMuHMdXTgpTnJ9U7egC2XjFXXNZ5uiY1O+WxNd6LPJW5Rs5KTw@mail.gmail.com Fixes: bbef42084cc1 ("arm64: dts: ti: hummingboard-t: add overlays for m.2 pci-e and usb-3") Signed-off-by: Josua Mayer Link: https://lore.kernel.org/r/20250101-am64-hb-fix-overlay-v2-1-78143f5da28c@solid-run.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 4 ---- ...-pcie.dtso => k3-am642-hummingboard-t-pcie.dts} | 14 ++++++++------ ...-usb3.dtso => k3-am642-hummingboard-t-usb3.dts} | 13 ++++++++----- 3 files changed, 16 insertions(+), 15 deletions(-) rename arch/arm64/boot/dts/ti/{k3-am642-hummingboard-t-pcie.dtso => k3-am642-hummingboard-t-pcie.dts} (78%) rename arch/arm64/boot/dts/ti/{k3-am642-hummingboard-t-usb3.dtso => k3-am642-hummingboard-t-usb3.dts} (74%) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index db5ae27467e7..8a4bdf87e2d4 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -42,10 +42,6 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-imx219.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo # Boards with AM64x SoC -k3-am642-hummingboard-t-pcie-dtbs := \ - k3-am642-hummingboard-t.dtb k3-am642-hummingboard-t-pcie.dtbo -k3-am642-hummingboard-t-usb3-dtbs := \ - k3-am642-hummingboard-t.dtb k3-am642-hummingboard-t-usb3.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac-mii.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-pcie.dtso b/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-pcie.dts similarity index 78% rename from arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-pcie.dtso rename to arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-pcie.dts index bd9a5caf20da..023b2a6aaa56 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-pcie.dtso +++ b/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-pcie.dts @@ -2,17 +2,19 @@ /* * Copyright (C) 2023 Josua Mayer * - * Overlay for SolidRun AM642 HummingBoard-T to enable PCI-E. + * DTS for SolidRun AM642 HummingBoard-T, + * running on Cortex A53, with PCI-E. + * */ -/dts-v1/; -/plugin/; - -#include -#include +#include "k3-am642-hummingboard-t.dts" #include "k3-serdes.h" +/ { + model = "SolidRun AM642 HummingBoard-T with PCI-E"; +}; + &pcie0_rc { pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_pins>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-usb3.dtso b/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-usb3.dts similarity index 74% rename from arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-usb3.dtso rename to arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-usb3.dts index ffcc3bd3c7bc..ee9bd618f370 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-usb3.dtso +++ b/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t-usb3.dts @@ -2,16 +2,19 @@ /* * Copyright (C) 2023 Josua Mayer * - * Overlay for SolidRun AM642 HummingBoard-T to enable USB-3.1. + * DTS for SolidRun AM642 HummingBoard-T, + * running on Cortex A53, with USB-3.1 Gen 1. + * */ -/dts-v1/; -/plugin/; - -#include +#include "k3-am642-hummingboard-t.dts" #include "k3-serdes.h" +/ { + model = "SolidRun AM642 HummingBoard-T with USB-3.1 Gen 1"; +}; + &serdes0 { #address-cells = <1>; #size-cells = <0>; From eb2008a8fcd243fcb7d646bdf1909349b3faec6d Mon Sep 17 00:00:00 2001 From: Francesco Valla Date: Sun, 5 Jan 2025 17:26:30 +0100 Subject: [PATCH 28/31] arm64: dts: ti: k3-am625-beagleplay: Fix DP83TD510E reset time The reset deassert time for the DP83TD510E is incorrectly set to 60000us, while the datasheet states that the minimum time required after an hard reset is 30us (while 60ms is the time required for the Power-On Reset after supply stabilization). The error probably arose from the two timings being indicated by the same symbol (T2). Lower the required time to 35us, aligning it to the value required for the PHY to complete the reset AND to be able to accept the RMII master clock. This saves ~60ms on boot if the MDIO driver is built-in. Signed-off-by: Francesco Valla Link: https://lore.kernel.org/r/20250105162630.243899-1-francesco@valla.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index ee96f4f6deb0..75c80290b12a 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -610,7 +610,7 @@ cpsw3g_phy1: ethernet-phy@1 { reg = <1>; reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; reset-assert-us = <25>; - reset-deassert-us = <60000>; /* T2 */ + reset-deassert-us = <35>; }; }; From ff7b5e93f16ab68231fd039a33fea8c67fd25955 Mon Sep 17 00:00:00 2001 From: Dasnavis Sabiya Date: Wed, 8 Jan 2025 09:59:46 +0100 Subject: [PATCH 29/31] arm64: dts: ti: k3-am69-sk: Add USB SuperSpeed support AM69 SK board has two stacked USB3 connectors: 1. USB3 (Stacked TypeA + TypeC) 2. USB3 TypeA Hub interfaced through TUSB8041. The board uses SERDES0 Lane 3 for USB3 IP. So update the SerDes lane info for PCIe and USB. Add the pin mux data and enable USB 3.0 support with its respective SERDES settings. Signed-off-by: Dasnavis Sabiya Signed-off-by: Enric Balletbo i Serra Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20250108-am69sk-dt-usb-v3-1-bb4981534754@redhat.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 33 +++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 5f24a1608bdc..b85227052f97 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -484,6 +484,12 @@ J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ >; }; + main_usbss0_pins_default: main-usbss0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ + >; + }; + }; &wkup_pmx0 { @@ -1307,6 +1313,14 @@ serdes0_pcie_link: phy@0 { cdns,phy-type = ; resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>; }; + + serdes0_usb_link: phy@3 { + reg = <3>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 4>; + }; }; &serdes_wiz1 { @@ -1347,3 +1361,22 @@ &pcie3_rc { phy-names = "pcie-phy"; num-lanes = <1>; }; + +&usb_serdes_mux { + idle-states = <0>; /* USB0 to SERDES0 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; +}; + +&usb0 { + status = "okay"; + dr_mode = "otg"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; From 998ad09ad3b0ef1776fcb988af4916a062b92cc1 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Thu, 2 Jan 2025 16:08:14 +0530 Subject: [PATCH 30/31] arm64: dts: ti: k3-j722s-evm: Enable PMIC Add support for TPS6522x PMIC family on wakeup I2C0 bus. This device provides regulators (bucks and LDOs), along with GPIOs, and monitors SOC's MCU error signal. Signed-off-by: Udit Kumar Link: https://lore.kernel.org/r/20250102103814.102499-1-u-kumar1@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 88 +++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 796287c76b69..d184e9c1a0a5 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -359,6 +359,13 @@ audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { J722S_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ >; }; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x030, PIN_INPUT, 7) /* (K23) GPIO0_12 */ + >; + }; + }; &cpsw3g { @@ -466,6 +473,87 @@ &wkup_i2c0 { clock-frequency = <400000>; status = "okay"; bootph-all; + + tps65224: pmic@48 { + compatible = "ti,tps65224-q1"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&main_gpio0>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + ti,primary-pmic; + + gpio-controller; + #gpio-cells = <2>; + + buck12-supply = <&vsys_io_3v3>; + buck3-supply = <&vsys_io_3v3>; + buck4-supply = <&vsys_io_3v3>; + + ldo1-supply = <&vsys_io_3v3>; + ldo2-supply = <&vsys_io_3v3>; + ldo3-supply = <&vsys_io_3v3>; + + regulators { + + buck1: buck1 { + regulator-name = "vcc1v8_io_buck1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + buck2: buck2 { + regulator-name = "vcc1v1_ddr_buck2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3: buck3 { + regulator-name = "vcc0v85_ram_buck3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: buck4 { + regulator-name = "vcc0v75_ioret_buck4"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: ldo1 { + regulator-name = "vdda1v8_pll_ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: ldo2 { + regulator-name = "dvdd3v3_ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: ldo3 { + regulator-name = "vdd1v85_phy_ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &k3_clks { From 5532b8a9ce0e80514e37a1e082824934663580a3 Mon Sep 17 00:00:00 2001 From: Vibhore Vardhan Date: Tue, 31 Dec 2024 14:44:19 +0530 Subject: [PATCH 31/31] arm64: dts: ti: k3-am62a-wakeup: Configure ti-sysc for wkup_uart0 Similar to the TI K3-AM62x SoC commit ce27f7f9e328c8582a169f97f1466976561f1 ("arm64: dts: ti: k3-am62-wakeup: Configure ti-sysc for wkup_uart0"), The devices in the wkup domain are capable of waking up the system from suspend. We can configure the wkup domain devices in a generic way using the ti-sysc interconnect target module driver like we have done with the earlier TI SoCs. As ti-sysc manages the SYSCONFIG related registers independent of the child hardware device, the wake-up configuration is also set even if wkup_uart0 is reserved by sysfw. The wkup_uart0 device has interconnect target module register mapping like dra7 wkup uart. There is a 1 MB interconnect target range with one uart IP block in the target module. The power domain and clock affects the whole interconnect target module. Note we change the functional clock name to follow the ti-sysc binding and use "fck" instead of "fclk". Also note that we need to disable the target module reset as noted by Markus. Otherwise the sysfw using wkup_uart0 can get confused on some devices leading to boot time issues such as mbox timeouts. Signed-off-by: Vibhore Vardhan Signed-off-by: Markus Schneider-Pargmann [d-gole@ti.com: Reworded the entire commit message] Signed-off-by: Dhruva Gole Link: https://lore.kernel.org/r/20241231-am62a-dt-ti-sysc-wkup-v1-1-a9b0d18a2649@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 36 +++++++++++++++++---- 1 file changed, 29 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index 0b1dd5390cd3..b2c8f5351743 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -2,9 +2,11 @@ /* * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals * - * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ */ +#include + &cbass_wakeup { wkup_conf: bus@43000000 { compatible = "simple-bus"; @@ -38,14 +40,34 @@ usb1_phy_ctrl: syscon@4018 { }; }; - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = ; + target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0 0x2b300050 0 0x4>, + <0 0x2b300054 0 0x4>, + <0 0x2b300058 0 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; - clock-names = "fclk"; - status = "disabled"; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2b300000 0x100000>; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0 0x100>; + interrupts = ; + status = "disabled"; + }; }; wkup_i2c0: i2c@2b200000 {