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drm/amdgpu/psp_v15_0_8: Add get ras capability

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Add get ras capability for psp 15.0.8.

v2:Remove APU type check and IP version check.

Signed-off-by: Jinzhou Su <jinzhou.su@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jinzhou Su 2026-01-21 16:27:46 +08:00 committed by Alex Deucher
parent da8c276035
commit c6fa06fc4c
1 changed files with 21 additions and 0 deletions
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21
drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c
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@ -187,6 +187,26 @@ static void psp_v15_0_8_ring_set_wptr(struct psp_context *psp, uint32_t value)
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value);
}
static bool psp_v15_0_8_get_ras_capability(struct psp_context *psp)
{
struct amdgpu_device *adev = psp->adev;
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
u32 reg_data;
/* query ras cap should be done from host side */
if (amdgpu_sriov_vf(adev))
return false;
if (!con)
return false;
reg_data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_127);
adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0));
con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false;
return true;
}
static int psp_v15_0_8_get_fw_type(struct amdgpu_firmware_info *ucode,
enum psp_gfx_fw_type *type)
{
@ -334,6 +354,7 @@ static const struct psp_funcs psp_v15_0_8_funcs = {
.ring_get_wptr = psp_v15_0_8_ring_get_wptr,
.ring_set_wptr = psp_v15_0_8_ring_set_wptr,
.get_fw_type = psp_v15_0_8_get_fw_type,
.get_ras_capability = psp_v15_0_8_get_ras_capability,
};
void psp_v15_0_8_set_psp_funcs(struct psp_context *psp)