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drm/amd/display: Add DCN36 DMCUB

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DMCU-B (Display Micro-Controller Unit B) is a display microcontroller
used for shared display functionality with BIOS and for advanced
power saving display features.

Add case to support DCN3.6 as well.

V2: adjust copyright license text

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wayne Lin 2025-01-10 21:08:20 +08:00 committed by Alex Deucher
parent 8cb06693bc
commit c5dd47d9e6
4 changed files with 52 additions and 0 deletions
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1
drivers/gpu/drm/amd/display/dmub/src/Makefile
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@ -26,6 +26,7 @@ DMUB += dmub_dcn31.o dmub_dcn314.o dmub_dcn315.o dmub_dcn316.o
DMUB += dmub_dcn32.o
DMUB += dmub_dcn35.o
DMUB += dmub_dcn351.o
DMUB += dmub_dcn36.o
DMUB += dmub_dcn401.o
AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))

34
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c Normal file
View File

@ -0,0 +1,34 @@
/* SPDX-License-Identifier: MIT */
/* Copyright 2025 Advanced Micro Devices, Inc. */
#include "../dmub_srv.h"
#include "dmub_reg.h"
#include "dmub_dcn36.h"
#include "dcn/dcn_3_6_0_offset.h"
#include "dcn/dcn_3_6_0_sh_mask.h"
#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
#define CTX dmub
#define REGS dmub->regs_dcn35
#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
void dmub_srv_dcn36_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)
{
struct dmub_srv_dcn35_regs *regs = dmub->regs_dcn35;
#define REG_STRUCT regs
#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
DMUB_DCN35_REGS()
DMCUB_INTERNAL_REGS()
#undef DMUB_SR
#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
DMUB_DCN35_FIELDS()
#undef DMUB_SF
#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
DMUB_DCN35_FIELDS()
#undef DMUB_SF
#undef REG_STRUCT
}

13
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.h Normal file
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@ -0,0 +1,13 @@
/* SPDX-License-Identifier: MIT */
/* Copyright 2025 Advanced Micro Devices, Inc. */
#ifndef _DMUB_DCN36_H_
#define _DMUB_DCN36_H_
#include "dmub_dcn35.h"
struct dmub_srv;
void dmub_srv_dcn36_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);
#endif /* _DMUB_DCN36_H_ */

4
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
View File

@ -38,6 +38,7 @@
#include "dmub_dcn32.h"
#include "dmub_dcn35.h"
#include "dmub_dcn351.h"
#include "dmub_dcn36.h"
#include "dmub_dcn401.h"
#include "os_types.h"
/*
@ -314,6 +315,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
case DMUB_ASIC_DCN35:
case DMUB_ASIC_DCN351:
case DMUB_ASIC_DCN36:
dmub->regs_dcn35 = &dmub_srv_dcn35_regs;
funcs->configure_dmub_in_system_memory = dmub_dcn35_configure_dmub_in_system_memory;
funcs->send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd;
@ -352,6 +354,8 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
funcs->init_reg_offsets = dmub_srv_dcn35_regs_init;
if (asic == DMUB_ASIC_DCN351)
funcs->init_reg_offsets = dmub_srv_dcn351_regs_init;
if (asic == DMUB_ASIC_DCN36)
funcs->init_reg_offsets = dmub_srv_dcn36_regs_init;
funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up;
funcs->should_detect = dmub_dcn35_should_detect;