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drm/amd/display: Add DCN36 DML2 support

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Enable DML2 for DCN36.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wayne Lin 2025-01-10 20:41:03 +08:00 committed by Alex Deucher
parent 4bcba9844b
commit 8cb06693bc
4 changed files with 9 additions and 0 deletions
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1
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h
View File

@ -38,6 +38,7 @@ enum dml_project_id {
dml_project_dcn35 = 3,
dml_project_dcn351 = 4,
dml_project_dcn401 = 5,
dml_project_dcn36 = 6,
};
enum dml_prefetch_modes {
dml_prefetch_support_uclk_fclk_and_stutter_if_possible = 0,

1
drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c
View File

@ -301,6 +301,7 @@ void build_unoptimized_policy_settings(enum dml_project_id project, struct dml_m
policy->AssumeModeSupportAtMaxPwrStateEvenDRAMClockChangeNotSupported = true; // TOREVIEW: What does this mean?
policy->AssumeModeSupportAtMaxPwrStateEvenFClockChangeNotSupported = true; // TOREVIEW: What does this mean?
if (project == dml_project_dcn35 ||
project == dml_project_dcn36 ||
project == dml_project_dcn351) {
policy->DCCProgrammingAssumesScanDirectionUnknownFinal = false;
policy->EnhancedPrefetchScheduleAccelerationFinal = 0;

3
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
View File

@ -107,6 +107,7 @@ void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, stru
case dml_project_dcn35:
case dml_project_dcn351:
case dml_project_dcn36:
out->rob_buffer_size_kbytes = 64;
out->config_return_buffer_size_in_kbytes = 1792;
out->compressed_buffer_segment_size_in_kbytes = 64;
@ -292,6 +293,7 @@ void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, s
case dml_project_dcn35:
case dml_project_dcn351:
case dml_project_dcn36:
out->num_chans = 4;
out->round_trip_ping_latency_dcfclk_cycles = 106;
out->smn_latency_us = 2;
@ -506,6 +508,7 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
p->dcfclk_stas_mhz[3] = 1324;
p->dcfclk_stas_mhz[4] = p->in_states->state_array[1].dcfclk_mhz;
} else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
dml2->v20.dml_core_ctx.project != dml_project_dcn36 &&
dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
p->dcfclk_stas_mhz[0] = 300;
p->dcfclk_stas_mhz[1] = 615;

4
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
View File

@ -72,6 +72,7 @@ static void map_hw_resources(struct dml2_context *dml2,
in_out_display_cfg->hw.NumberOfDSCSlices[i] = mode_support_info->NumberOfDSCSlices[i];
in_out_display_cfg->hw.DLGRefClkFreqMHz = 24;
if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
dml2->v20.dml_core_ctx.project != dml_project_dcn36 &&
dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
/*dGPU default as 50Mhz*/
in_out_display_cfg->hw.DLGRefClkFreqMHz = 50;
@ -762,6 +763,9 @@ static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_op
case DCN_VERSION_3_51:
(*dml2)->v20.dml_core_ctx.project = dml_project_dcn351;
break;
case DCN_VERSION_3_6:
(*dml2)->v20.dml_core_ctx.project = dml_project_dcn36;
break;
case DCN_VERSION_3_2:
(*dml2)->v20.dml_core_ctx.project = dml_project_dcn32;
break;