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drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO

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Force idle_frames to 0 when DC3CO is eligible.

Changes in v2:
- Extend existing Wa_16025596647 condition
  instead of adding a new if block (Uma Shankar)

BSpec: 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patch.msgid.link/20260616162154.2630995-11-dibin.moolakadan.subrahmanian@intel.com
This commit is contained in:
Dibin Moolakadan Subrahmanian 2026-06-16 21:51:48 +05:30 committed by Animesh Manna
parent eda862176c
commit c525b2f81d
1 changed files with 5 additions and 4 deletions
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9
drivers/gpu/drm/i915/display/intel_psr.c
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@ -1082,10 +1082,11 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 psr_val = 0;
u8 idle_frames;
/* Wa_16025596647 */
if ((DISPLAY_VER(display) == 20 ||
IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
/* DC3CO / Wa_16025596647 */
if (intel_dp->psr.dc3co_allowed ||
((DISPLAY_VER(display) == 20 ||
IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used))
idle_frames = 0;
else
idle_frames = psr_compute_idle_frames(intel_dp);