From c525b2f81da88f79483667edde2f9c67b619ea75 Mon Sep 17 00:00:00 2001 From: Dibin Moolakadan Subrahmanian Date: Tue, 16 Jun 2026 21:51:48 +0530 Subject: [PATCH] drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO Force idle_frames to 0 when DC3CO is eligible. Changes in v2: - Extend existing Wa_16025596647 condition instead of adding a new if block (Uma Shankar) BSpec: 75253 Signed-off-by: Dibin Moolakadan Subrahmanian Reviewed-by: Uma Shankar Reviewed-by: Animesh Manna Signed-off-by: Animesh Manna Link: https://patch.msgid.link/20260616162154.2630995-11-dibin.moolakadan.subrahmanian@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 0f4263885416..091da8341b0f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1082,10 +1082,11 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) u32 psr_val = 0; u8 idle_frames; - /* Wa_16025596647 */ - if ((DISPLAY_VER(display) == 20 || - IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && - is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used) + /* DC3CO / Wa_16025596647 */ + if (intel_dp->psr.dc3co_allowed || + ((DISPLAY_VER(display) == 20 || + IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && + is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)) idle_frames = 0; else idle_frames = psr_compute_idle_frames(intel_dp);