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T-HEAD Devicetrees for 7.1

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Update the T-Head TH1520 RISC-V SoC device tree to support the
 Verisilicon DC8200 display controller (called DPU in manual) and the
 Synopsys DesignWare HDMI TX controller. In addition, enable HDMI output
 for the LicheePi 4a board.
 
 Signed-off-by: Drew Fustini <fustini@kernel.org>
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Merge tag 'thead-dt-for-v7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt

T-HEAD Devicetrees for 7.1

Update the T-Head TH1520 RISC-V SoC device tree to support the
Verisilicon DC8200 display controller (called DPU in manual) and the
Synopsys DesignWare HDMI TX controller. In addition, enable HDMI output
for the LicheePi 4a board.

* tag 'thead-dt-for-v7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux:
  riscv: dts: thead: lichee-pi-4a: enable HDMI
  riscv: dts: thead: add DPU and HDMI device tree nodes

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2026-03-27 12:40:55 +01:00
commit c4d677691d
2 changed files with 91 additions and 0 deletions
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25
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
View File

@ -29,6 +29,17 @@ chosen {
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
thermal-zones {
cpu-thermal {
polling-delay = <1000>;
@ -121,6 +132,20 @@ rx-pins {
};
};
&dpu {
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_out_port {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;

66
arch/riscv/boot/dts/thead/th1520.dtsi
View File

@ -585,6 +585,72 @@ clk_vo: clock-controller@ffef528050 {
#clock-cells = <1>;
};
hdmi: hdmi@ffef540000 {
compatible = "thead,th1520-dw-hdmi";
reg = <0xff 0xef540000 0x0 0x40000>;
reg-io-width = <4>;
interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_vo CLK_HDMI_PCLK>,
<&clk_vo CLK_HDMI_SFR>,
<&clk_vo CLK_HDMI_CEC>,
<&clk_vo CLK_HDMI_PIXCLK>;
clock-names = "iahb", "isfr", "cec", "pix";
resets = <&rst TH1520_RESET_ID_HDMI>,
<&rst TH1520_RESET_ID_HDMI_APB>;
reset-names = "main", "apb";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_in: endpoint {
remote-endpoint = <&dpu_out_dp1>;
};
};
hdmi_out_port: port@1 {
reg = <1>;
};
};
};
dpu: display@ffef600000 {
compatible = "thead,th1520-dc8200", "verisilicon,dc";
reg = <0xff 0xef600000 0x0 0x100000>;
interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_vo CLK_DPU_CCLK>,
<&clk_vo CLK_DPU_ACLK>,
<&clk_vo CLK_DPU_HCLK>,
<&clk_vo CLK_DPU_PIXELCLK0>,
<&clk_vo CLK_DPU_PIXELCLK1>;
clock-names = "core", "axi", "ahb", "pix0", "pix1";
resets = <&rst TH1520_RESET_ID_DPU_CORE>,
<&rst TH1520_RESET_ID_DPU_AXI>,
<&rst TH1520_RESET_ID_DPU_AHB>;
reset-names = "core", "axi", "ahb";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
dpu_port1: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dpu_out_dp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmi_in>;
};
};
};
};
dmac0: dma-controller@ffefc00000 {
compatible = "snps,axi-dma-1.01a";
reg = <0xff 0xefc00000 0x0 0x1000>;