New boards: RK3576-EVB2, OneThing Edge Cube

New soc-peripherals: DisplayPort on RK3576
 New overlays: TSx33 device-revisions, HD702E display/touchscreen on
 NanoPC-T4
 
 And as always a number of per-board changes for added or enabled
 peripherals, added supplies, things moved to more fitting positions.
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Merge tag 'v7.1-rockchip-dts64-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

New boards: RK3576-EVB2, OneThing Edge Cube
New soc-peripherals: DisplayPort on RK3576
New overlays: TSx33 device-revisions, HD702E display/touchscreen on
NanoPC-T4

And as always a number of per-board changes for added or enabled
peripherals, added supplies, things moved to more fitting positions.

* tag 'v7.1-rockchip-dts64-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (28 commits)
  arm64: dts: rockchip: enable vicap dvp on wolfvision pf5 io expander
  arm64: dts: rockchip: Add analog audio switches to RK3576 EVB1
  arm64: dts: rockchip: Enable GPU on rk3566-pinenote
  arm64: dts: rockchip: Make Jaguar PCIe-refclk pin use pull-up config
  arm64: dts: rockchip: add pinctrl for clk-generator GPIO on rk3588-tiger
  arm64: dts: rockchip: use gated-fixed-clock for pcie-refclk on rk3588-tiger
  arm64: dts: rockchip: use gated-fixed-clock for pcie-refclk on rk3588-jaguar
  arm64: dts: rockchip: Enable displayport for rk3576 evb2
  arm64: dts: rockchip: Add battery and charger on rk3566-pinenote
  arm64: dts: rockchip: Fix sdmmc pwren pinctrl for rk3576-evb2
  arm64: dts: rockchip: Describe HDMI supplies for nanopi4 boards
  arm64: dts: rockchip: Clean up NanoPi-R2S Plus gmac2io
  arm64: dts: rockchip: add pwm-fan for NanoPC-T6
  arm64: dts: rockchip: Add rk3576 evb2 board
  dt-bindings: arm: rockchip: Add rk3576 evb2 board
  arm64: dts: rockchip: Add overlay for FriendlyElec HD702E
  arm64: dts: rockchip: Move RK3399 eDP pinctrl to boards
  arm64: dts: rockchip: add overlay for qnap-ts133 device revision
  arm64: dts: rockchip: add overlay for qnap-ts233 device revision
  arm64: dts: rockchip: add overlay for qnap-ts433 device revision
  ...

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2026-03-21 11:57:53 +01:00
commit 45ffabad4b
27 changed files with 2093 additions and 63 deletions

View File

@ -813,6 +813,11 @@ properties:
- const: openailab,eaidk-610
- const: rockchip,rk3399
- description: OneThing Edge Cube series
items:
- const: onething,edge-cube
- const: rockchip,rk3566
- description: Xunlong Orange Pi RK3399 board
items:
- const: xunlong,rk3399-orangepi
@ -1187,7 +1192,9 @@ properties:
- description: Rockchip RK3576 Evaluation board
items:
- const: rockchip,rk3576-evb1-v10
- enum:
- rockchip,rk3576-evb1-v10
- rockchip,rk3576-evb2-v10
- const: rockchip,rk3576
- description: Rockchip RK3588 Evaluation board

View File

@ -1199,6 +1199,8 @@ patternProperties:
description: One Laptop Per Child
"^oneplus,.*":
description: OnePlus Technology (Shenzhen) Co., Ltd.
"^onething,.*":
description: Shenzhen OneThing Technologies Co., Ltd.
"^onie,.*":
description: Open Network Install Environment group
"^onion,.*":

View File

@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-kobol-helios64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4-hd702e.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
@ -104,6 +105,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-odroid-m1s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-onething-edge-cube.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v1.1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v2.1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
@ -116,6 +118,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rgb30.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rk2023.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-x55.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qnap-ts133.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qnap-ts133-pcb-13.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
@ -150,7 +153,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts233.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts233-pcb-12-11.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433-pcb-12-10.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-cm3j-rpi-cm4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
@ -164,6 +169,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-pcie1.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb2-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-luckfox-omni3576.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-m5.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-r76s.dtb
@ -245,6 +251,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou-haikou-video-demo.dtb
px30-ringneck-haikou-haikou-video-demo-dtbs := px30-ringneck-haikou.dtb \
px30-ringneck-haikou-video-demo.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4-hd702e.dtb
rk3399-nanopc-t4-hd702e-dtbs := rk3399-nanopc-t4.dtb \
rk3399-nanopc-t4-hd702e.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou-haikou-video-demo.dtb
rk3368-lion-haikou-haikou-video-demo-dtbs := rk3368-lion-haikou.dtb \
rk3368-lion-haikou-video-demo.dtbo
@ -261,6 +271,18 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2-screen.dtb
rk3399-rockpro64-v2-screen-dtbs := rk3399-rockpro64-v2.dtb \
rk3399-rockpro64-screen.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qnap-ts133-pcb-13.dtb
rk3566-qnap-ts133-pcb-13-dtbs := rk3566-qnap-ts133.dtb \
rk3566-qnap-ts133-pcb-13.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts233-pcb-12-11.dtb
rk3568-qnap-ts233-pcb-12-11-dtbs := rk3568-qnap-ts233.dtb \
rk3568-qnap-ts233-pcb-12-11.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433-pcb-12-10.dtb
rk3568-qnap-ts433-pcb-12-10-dtbs := rk3568-qnap-ts433.dtb \
rk3568-qnap-ts433-pcb-12-10.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-vz-2-uhd.dtb
rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb \
rk3568-wolfvision-pf5-display-vz.dtbo \

View File

@ -29,20 +29,3 @@ &emmc {
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
&gmac2io {
phy-handle = <&rtl8211e>;
tx_delay = <0x24>;
rx_delay = <0x18>;
mdio {
rtl8211e: ethernet-phy@1 {
reg = <1>;
pinctrl-0 = <&eth_phy_reset_pin>;
pinctrl-names = "default";
reset-assert-us = <10000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
};
};
};

View File

@ -2145,8 +2145,6 @@ edp: dp@ff970000 {
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
clock-names = "dp", "pclk", "grf";
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
power-domains = <&power RK3399_PD_EDP>;
resets = <&cru SRST_P_EDP_CTRL>;
reset-names = "dp";
@ -2384,6 +2382,7 @@ cif_clkouta: cif-clkouta {
};
edp {
/omit-if-no-ref/
edp_hpd: edp-hpd {
rockchip,pins =
<4 RK_PC7 2 &pcfg_pull_none>;

View File

@ -241,6 +241,8 @@ &dmc {
};
&edp {
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
status = "okay";
/*

View File

@ -0,0 +1,96 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* FriendlyElec HD702E LCD on NanoPC-T4 board
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
&{/} {
vdd_3_3v: regulator-vdd_3_3v {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vdd_3.3v";
vin-supply = <&vcc12v0_sys>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm0 0 25000 0>;
enable-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
brightness-levels = <0 255>;
default-brightness-level = <200>;
num-interpolated-steps = <255>;
pinctrl-0 = <&bl_en>;
pinctrl-names = "default";
};
};
&edp {
force-hpd;
status = "okay";
aux-bus {
panel {
compatible = "friendlyarm,hd702e";
backlight = <&backlight>;
no-hpd;
power-supply = <&vdd_3_3v>;
port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
};
};
&edp_out {
edp_out_panel: endpoint {
remote-endpoint = <&panel_in_edp>;
};
};
&i2c4 {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@5d {
compatible = "goodix,gt9271";
reg = <0x5d>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
irq-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&touch_int &touch_rst>;
pinctrl-names = "default";
AVDD28-supply = <&vdd_3_3v>;
VDDIO-supply = <&vdd_3_3v>;
};
};
&pinctrl {
backlight {
bl_en: bl-en {
rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
touchscreen {
touch_int: touch-int {
rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
touch_rst: touch-rst {
rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

View File

@ -206,6 +206,8 @@ &gpu {
};
&hdmi {
avdd-0v9-supply = <&vcca0v9_s3>;
avdd-1v8-supply = <&vcca1v8_s3>;
ddc-i2c-bus = <&i2c7>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;

View File

@ -401,8 +401,6 @@ &cpu_l3 {
&edp {
force-hpd;
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
status = "okay";
};

View File

@ -141,6 +141,8 @@ sdio_pwrseq: sdio-pwrseq {
};
&edp {
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
status = "okay";
};

View File

@ -0,0 +1,342 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3566.dtsi"
/ {
model = "OneThing Edge Cube (OEC)/OEC Turbo";
compatible = "onething,edge-cube", "rockchip,rk3566";
aliases {
ethernet0 = &gmac1;
mmc0 = &sdhci;
};
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
gmac1_clkin: external-gmac1-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac1_clkin";
#clock-cells = <0>;
};
leds {
compatible = "gpio-leds";
rgb_led_b: led-0 {
color = <LED_COLOR_ID_BLUE>;
default-state = "off";
function = LED_FUNCTION_STATUS;
gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&rgb_led_b_enable_l>;
};
rgb_led_g: led-1 {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
function = LED_FUNCTION_STATUS;
gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&rgb_led_g_enable_l>;
};
rgb_led_r: led-2 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&rgb_led_r_enable_l>;
};
};
vcc_1v8: regulator-vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc12v0_dcin: regulator-vcc12v0-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v0_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc3v3_sys: regulator-vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc12v0_dcin>;
};
vcc5v0_sys: regulator-vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v0_dcin>;
};
vcc5v0_usb_host: regulator-vcc5v0-usb-host {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_host_en>;
regulator-name = "vcc5v0_usb_host";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
vdd_cpu: regulator-vdd-cpu {
compatible = "pwm-regulator";
pwms = <&pwm0 0 5000 PWM_POLARITY_INVERTED>;
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd_cpu";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1200000>;
regulator-settling-time-up-us = <250>;
pwm-supply = <&vcc5v0_sys>;
};
vdd_fixed: regulator-vdd-fixed {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd_fixed";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
vin-supply = <&vcc5v0_sys>;
};
vdd_logic: regulator-vdd-logic {
compatible = "pwm-regulator";
pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1100000>;
regulator-settling-time-up-us = <250>;
pwm-supply = <&vcc5v0_sys>;
};
};
/* No hardware video output port */
&display_subsystem {
status = "disabled";
};
&combphy1 {
status = "okay";
};
&combphy2 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
clock_in_out = "input";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus
&gmac1m1_clkinout>;
status = "okay";
};
&gpu {
status = "okay";
};
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
gmac {
eth_phy_reset_pin: eth-phy-reset-pin {
rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
rgb_led_b_enable_l: rgb-led-b-enable-l {
rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
rgb_led_g_enable_l: rgb-led-g-enable-l {
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
rgb_led_r_enable_l: rgb-led-r-enable-l {
rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
vcc5v0_usb_host_en: vcc5v0-usb-host-en {
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc_3v3>;
pmuio2-supply = <&vcc_3v3>;
vccio1-supply = <&vcc_1v8>;
vccio3-supply = <&vcc_3v3>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&pwm0 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";
};
&sata2 {
status = "okay";
};
&sdhci {
bus-width = <8>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
no-sd;
no-sdio;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy0_otg {
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy1_otg {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};

View File

@ -40,6 +40,25 @@ spk_amp: audio-amplifier {
sound-name-prefix = "Speaker Amp";
};
battery: battery {
compatible = "simple-battery";
charge-full-design-microamp-hours = <4000000>;
charge-term-current-microamp = <300000>;
constant-charge-current-max-microamp = <2000000>;
constant-charge-voltage-max-microvolt = <4200000>;
factory-internal-resistance-micro-ohms = <96000>;
voltage-max-design-microvolt = <4200000>;
voltage-min-design-microvolt = <3500000>;
ocv-capacity-celsius = <20>;
ocv-capacity-table-0 = <4168000 100>, <4109000 95>, <4066000 90>, <4023000 85>,
<3985000 80>, <3954000 75>, <3924000 70>, <3897000 65>,
<3866000 60>, <3826000 55>, <3804000 50>, <3789000 45>,
<3777000 40>, <3770000 35>, <3763000 30>, <3750000 25>,
<3732000 20>, <3710000 15>, <3680000 10>, <3670000 5>,
<3500000 0>;
};
dmic_codec: dmic-codec {
compatible = "dmic-codec";
num-channels = <6>;
@ -215,6 +234,11 @@ &cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gpu {
mali-supply = <&vdd_gpu_npu>;
status = "okay";
};
&i2c0 {
status = "okay";
@ -260,6 +284,13 @@ rk817: pmic@20 {
vcc8-supply = <&vcc_sys>;
vcc9-supply = <&dcdc_boost>;
charger {
monitored-battery = <&battery>;
rockchip,resistor-sense-micro-ohms = <10000>;
rockchip,sleep-enter-current-microamp = <150000>;
rockchip,sleep-filter-current-microamp = <100000>;
};
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";

View File

@ -0,0 +1,64 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Device tree overlay for TS133 board PCB-13 revision.
*
* Copyright (C) 2025 Heiko Stuebner <heiko@sntech.de>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
&{/} {
/*
* The default hardware-state of this gpio causes the drive
* to be already running when entering the kernel.
* regulator-boot-on is needed to prevent one additional
* power-cycle on the drive.
*
* With regulator-boot-on we get the expected 1 cycle
* per boot, without it we end up with 2 cycles as seen
* via smartctl.
*/
hdd1_pwr: regulator-hdd1-power {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hdd1_power_pin>;
regulator-name = "hdd1-power";
regulator-boot-on;
vin-supply = <&dc_12v>;
};
};
&gpio2 {
hdd1-present-hog {
gpios = <RK_PA2 GPIO_ACTIVE_LOW>;
gpio-hog;
input;
line-name = "hdd1-present";
};
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&hdd1_present_pin>;
hdd-power {
hdd1_power_pin: hdd1-power-pin {
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hdd-present {
hdd1_present_pin: hdd1-present-pin {
rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&sata2_port0 {
target-supply = <&hdd1_pwr>;
};

View File

@ -354,6 +354,7 @@ sound {
compatible = "simple-audio-card";
pinctrl-0 = <&hp_det>;
pinctrl-names = "default";
simple-audio-card,aux-devs = <&aw87391_pa_l>, <&aw87391_pa_r>;
simple-audio-card,format = "i2s";
simple-audio-card,hp-det-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
simple-audio-card,mclk-fs = <256>;
@ -363,8 +364,10 @@ sound {
"MICL", "Mic Jack",
"Headphones", "HPOL",
"Headphones", "HPOR",
"Internal Speakers", "HPOL",
"Internal Speakers", "HPOR";
"Internal Speakers", "Left Amp OUT",
"Internal Speakers", "Right Amp OUT",
"Left Amp IN", "HPOL",
"Right Amp IN", "HPOR";
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Headphone", "Headphones",
@ -468,6 +471,18 @@ vcc_wifi: regulator-vcc-wifi {
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_wifi";
};
vdd_amp: regulator-vcc-amp {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&vdd_amp_h>;
pinctrl-names = "default";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vccio_acodec>;
regulator-name = "vdd_amp";
};
};
&cpu0 {
@ -840,8 +855,22 @@ &i2c2 {
pinctrl-names = "default";
status = "okay";
/* awinic,aw87391 at 0x58 */
/* awinic,aw87391 at 0x5b */
aw87391_pa_l: audio-codec@58 {
compatible = "anbernic,rgds-amp", "awinic,aw87391";
reg = <0x58>;
vdd-supply = <&vdd_amp>;
#sound-dai-cells = <0>;
sound-name-prefix = "Left Amp";
};
aw87391_pa_r: audio-codec@5b {
compatible = "anbernic,rgds-amp", "awinic,aw87391";
reg = <0x5b>;
vdd-supply = <&vdd_amp>;
#sound-dai-cells = <0>;
sound-name-prefix = "Right Amp";
};
/* invensense,icm42607p at 0x68 */
};
@ -1014,6 +1043,13 @@ touch1_irq: touch1-irq {
};
};
vdd-amp {
vdd_amp_h: vdd-amp-h {
rockchip,pins =
<4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
vcc-lcd {
vdd_lcd0_h: vdd-lcd0-h {
rockchip,pins =

View File

@ -0,0 +1,93 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Device tree overlay for TS233 board PCBs-12-11 revision.
*
* Copyright (C) 2025 Heiko Stuebner <heiko@sntech.de>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
&{/} {
/*
* The default hardware-state of this gpio causes the drive
* to be already running when entering the kernel.
* regulator-boot-on is needed to prevent one additional
* power-cycle on the drive.
*
* With regulator-boot-on we get the expected 1 cycle
* per boot, without it we end up with 2 cycles as seen
* via smartctl.
*/
hdd1_pwr: regulator-hdd1-power {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hdd1_power_pin>;
regulator-name = "hdd1-power";
regulator-boot-on;
vin-supply = <&dc_12v>;
};
hdd2_pwr: regulator-hdd2-power {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hdd2_power_pin>;
regulator-name = "hdd2-power";
regulator-boot-on;
vin-supply = <&dc_12v>;
};
};
&gpio2 {
hdd1-present-hog {
gpios = <RK_PA2 GPIO_ACTIVE_LOW>;
gpio-hog;
input;
line-name = "hdd1-present";
};
hdd2-present-hog {
gpios = <RK_PA1 GPIO_ACTIVE_LOW>;
gpio-hog;
input;
line-name = "hdd2-present";
};
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&hdd1_present_pin &hdd2_present_pin>;
hdd-power {
hdd1_power_pin: hdd1-power-pin {
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdd2_power_pin: hdd2-power-pin {
rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hdd-present {
hdd1_present_pin: hdd1-present-pin {
rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
hdd2_present_pin: hdd2-present-pin {
rockchip,pins = <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&sata1_port0 {
target-supply = <&hdd2_pwr>;
};
&sata2_port0 {
target-supply = <&hdd1_pwr>;
};

View File

@ -0,0 +1,151 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Device tree overlay for TS433 board PCBs-12-10 revision.
*
* Copyright (C) 2025 Heiko Stuebner <heiko@sntech.de>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
&{/} {
/*
* The default hardware-state of this gpio causes the drive
* to be already running when entering the kernel.
* regulator-boot-on is needed to prevent one additional
* power-cycle on the drive.
*
* With regulator-boot-on we get the expected 1 cycle
* per boot, without it we end up with 2 cycles as seen
* via smartctl.
*/
hdd1_pwr: regulator-hdd1-power {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hdd1_power_pin>;
regulator-name = "hdd1-power";
regulator-boot-on;
vin-supply = <&dc_12v>;
};
hdd2_pwr: regulator-hdd2-power {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hdd2_power_pin>;
regulator-name = "hdd2-power";
regulator-boot-on;
vin-supply = <&dc_12v>;
};
/*
* HDD3+4 are connected to ports of the PCIe SATA controller.
* Currently there is no way to attach those, so keep them
* always on.
*/
hdd3_pwr: regulator-hdd3-power {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hdd3_power_pin>;
regulator-name = "hdd3-power";
regulator-always-on;
regulator-boot-on;
vin-supply = <&dc_12v>;
};
hdd4_pwr: regulator-hdd4-power {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hdd4_power_pin>;
regulator-name = "hdd4-power";
regulator-always-on;
regulator-boot-on;
vin-supply = <&dc_12v>;
};
};
&gpio2 {
hdd1-present-hog {
gpios = <RK_PA2 GPIO_ACTIVE_LOW>;
gpio-hog;
input;
line-name = "hdd1-present";
};
hdd2-present-hog {
gpios = <RK_PA1 GPIO_ACTIVE_LOW>;
gpio-hog;
input;
line-name = "hdd2-present";
};
hdd3-present-hog {
gpios = <RK_PD0 GPIO_ACTIVE_LOW>;
gpio-hog;
input;
line-name = "hdd3-present";
};
hdd4-present-hog {
gpios = <RK_PD1 GPIO_ACTIVE_LOW>;
gpio-hog;
input;
line-name = "hdd4-present";
};
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&hdd1_present_pin &hdd2_present_pin &hdd3_present_pin
&hdd4_present_pin>;
hdd-power {
hdd1_power_pin: hdd1-power-pin {
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdd2_power_pin: hdd2-power-pin {
rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdd3_power_pin: hdd3-power-pin {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdd4_power_pin: hdd4-power-pin {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hdd-present {
hdd1_present_pin: hdd1-present-pin {
rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
hdd2_present_pin: hdd2-present-pin {
rockchip,pins = <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
};
hdd3_present_pin: hdd3-present-pin {
rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
};
hdd4_present_pin: hdd4-present-pin {
rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&sata1_port0 {
target-supply = <&hdd2_pwr>;
};
&sata2_port0 {
target-supply = <&hdd1_pwr>;
};

View File

@ -11,6 +11,7 @@
#include <dt-bindings/clock/rk3568-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/media/video-interfaces.h>
#include <dt-bindings/pinctrl/rockchip.h>
&{/} {
@ -134,3 +135,22 @@ &usb2phy0_host {
phy-supply = <&usb_host_vbus>;
status = "okay";
};
&vicap {
pinctrl-names = "default";
pinctrl-0 = <&cif_clk &cif_dvp_clk &cif_dvp_bus16>;
status = "okay";
};
&vicap_dvp {
vicap_dvp_input: endpoint {
bus-type = <MEDIA_BUS_TYPE_BT656>;
bus-width = <16>;
pclk-sample = <MEDIA_PCLK_SAMPLE_DUAL_EDGE>;
rockchip,dvp-clk-delay = <10>;
};
};
&vicap_mmu {
status = "okay";
};

View File

@ -3,6 +3,7 @@
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/ata/ahci.h>
#include <dt-bindings/clock/rk3568-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
@ -221,11 +222,20 @@ sata1: sata@fc400000 {
<&cru CLK_SATA1_RXOOB>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
phys = <&combphy1 PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
power-domains = <&power RK3568_PD_PIPE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata1_port0: sata-port@0 {
reg = <0>;
hba-port-cap = <HBA_PORT_FBSCP>;
phys = <&combphy1 PHY_TYPE_SATA>;
phy-names = "sata-phy";
snps,rx-ts-max = <32>;
snps,tx-ts-max = <32>;
};
};
sata2: sata@fc800000 {
@ -235,11 +245,20 @@ sata2: sata@fc800000 {
<&cru CLK_SATA2_RXOOB>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
phys = <&combphy2 PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
power-domains = <&power RK3568_PD_PIPE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata2_port0: sata-port@0 {
reg = <0>;
hba-port-cap = <HBA_PORT_FBSCP>;
phys = <&combphy2 PHY_TYPE_SATA>;
phy-names = "sata-phy";
snps,rx-ts-max = <32>;
snps,tx-ts-max = <32>;
};
};
usb_host0_xhci: usb@fcc00000 {

View File

@ -270,6 +270,7 @@ sound {
simple-audio-card,frame-master = <&masterdai>;
simple-audio-card,hp-det-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,pin-switches = "Headphones", "Speaker", "Main Mic", "Headset Mic";
simple-audio-card,routing =
"Headphone Power INL", "LOUT1",
"Headphone Power INR", "ROUT1",

File diff suppressed because it is too large Load Diff

View File

@ -1483,6 +1483,34 @@ hdmi_out: port@1 {
};
};
dp: dp@27e40000 {
compatible = "rockchip,rk3576-dp";
reg = <0x0 0x27e40000 0x0 0x30000>;
interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&cru CLK_AUX16MHZ_0>;
assigned-clock-rates = <16000000>;
clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16MHZ_0>,
<&cru ACLK_DP0>;
clock-names = "apb", "aux", "hdcp";
resets = <&cru SRST_DP0>;
phys = <&usbdp_phy PHY_TYPE_DP>;
power-domains = <&power RK3576_PD_VO1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
dp0_in: port@0 {
reg = <0>;
};
dp0_out: port@1 {
reg = <1>;
};
};
};
sai7: sai@27ed0000 {
compatible = "rockchip,rk3576-sai";
reg = <0x0 0x27ed0000 0x0 0x1000>;

View File

@ -907,7 +907,7 @@ power-domain@RK3588_PD_VCODEC {
#size-cells = <0>;
#power-domain-cells = <0>;
power-domain@RK3588_PD_RKVDEC0 {
pd_rkvdec0: power-domain@RK3588_PD_RKVDEC0 {
reg = <RK3588_PD_RKVDEC0>;
clocks = <&cru HCLK_RKVDEC0>,
<&cru HCLK_VDPU_ROOT>,
@ -917,7 +917,7 @@ power-domain@RK3588_PD_RKVDEC0 {
pm_qos = <&qos_rkvdec0>;
#power-domain-cells = <0>;
};
power-domain@RK3588_PD_RKVDEC1 {
pd_rkvdec1: power-domain@RK3588_PD_RKVDEC1 {
reg = <RK3588_PD_RKVDEC1>;
clocks = <&cru HCLK_RKVDEC1>,
<&cru HCLK_VDPU_ROOT>,
@ -926,7 +926,7 @@ power-domain@RK3588_PD_RKVDEC1 {
pm_qos = <&qos_rkvdec1>;
#power-domain-cells = <0>;
};
power-domain@RK3588_PD_VENC0 {
pd_venc0: power-domain@RK3588_PD_VENC0 {
reg = <RK3588_PD_VENC0>;
clocks = <&cru HCLK_RKVENC0>,
<&cru ACLK_RKVENC0>;
@ -937,7 +937,7 @@ power-domain@RK3588_PD_VENC0 {
#size-cells = <0>;
#power-domain-cells = <0>;
power-domain@RK3588_PD_VENC1 {
pd_venc1: power-domain@RK3588_PD_VENC1 {
reg = <RK3588_PD_VENC1>;
clocks = <&cru HCLK_RKVENC1>,
<&cru HCLK_RKVENC0>,

View File

@ -568,6 +568,22 @@ &pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pd_rkvdec0 {
domain-supply = <&vdd_vdenc_s0>;
};
&pd_rkvdec1 {
domain-supply = <&vdd_vdenc_s0>;
};
&pd_venc0 {
domain-supply = <&vdd_vdenc_s0>;
};
&pd_venc1 {
domain-supply = <&vdd_vdenc_s0>;
};
&pinctrl {
audio {
hp_detect: headphone-detect {

View File

@ -86,25 +86,16 @@ led-1 {
};
};
/*
* 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
* clock generator.
* The clock output is gated via the OE pin on the clock generator.
* This is modeled as a fixed-clock plus a gpio-gate-clock.
*/
pcie_refclk_gen: pcie-refclk-gen-clock {
compatible = "fixed-clock";
/* 100MHz PCIe reference clock from PI6C557-05BLE */
pcie_refclk: pcie-clock-generator {
compatible = "gated-fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie_refclk: pcie-refclk-clock {
compatible = "gpio-gate-clock";
clocks = <&pcie_refclk_gen>;
#clock-cells = <0>;
clock-output-names = "pcie-refclk-clock";
enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */
pinctrl-names = "default";
pinctrl-0 = <&pcie30x4_clkreqn_m0>;
vdd-supply = <&vcca_3v3_s0>;
};
pps {
@ -588,7 +579,7 @@ led1_pin: led1-pin {
pcie30x4 {
pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 {
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
};
pcie30x4_perstn_m0: pcie30x4-perstn-m0 {

View File

@ -11,6 +11,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/usb/pd.h>
#include "rk3588.dtsi"
@ -89,6 +90,14 @@ usr_led: led-1 {
};
};
fan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <0 35 64 100 150 255>;
fan-supply = <&vcc5v0_sys>;
pwms = <&pwm1 0 50000 0>;
#cooling-cells = <2>;
};
sound {
compatible = "simple-audio-card";
pinctrl-names = "default";
@ -590,6 +599,36 @@ &i2s6_8ch {
status = "okay";
};
&package_thermal {
polling-delay = <1000>;
trips {
package_warm: package-warm {
temperature = <55000>;
hysteresis = <2000>;
type = "active";
};
package_hot: package-hot {
temperature = <65000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map0 {
trip = <&package_warm>;
cooling-device = <&fan THERMAL_NO_LIMIT 1>;
};
map1 {
trip = <&package_hot>;
cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
};
};
};
&pcie2x1l0 {
reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_pcie20>;

View File

@ -47,23 +47,16 @@ led-1 {
};
};
/*
* 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
* clock generator.
* The clock output is gated via the OE pin on the clock generator.
* This is modeled as a fixed-clock plus a gpio-gate-clock.
*/
pcie_refclk_gen: pcie-refclk-gen-clock {
compatible = "fixed-clock";
/* 100MHz PCIe reference clock from PI6C557-05BLE */
pcie_refclk: pcie-clock-generator {
compatible = "gated-fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie_refclk: pcie-refclk-clock {
compatible = "gpio-gate-clock";
clocks = <&pcie_refclk_gen>;
#clock-cells = <0>;
clock-output-names = "pcie-refclk-clock";
enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */
pinctrl-names = "default";
pinctrl-0 = <&pcie30x4_clkreqn_m1_l>;
vdd-supply = <&vcca_3v3_s0>;
};
vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
@ -362,6 +355,12 @@ module_led_pin: module-led-pin {
};
};
pcie30x4 {
pcie30x4_clkreqn_m1_l: pcie30x4-clkreqn-m1-l {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb3 {
usb3_id: usb3-id {
rockchip,pins =

View File

@ -381,6 +381,22 @@ &pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pd_rkvdec0 {
domain-supply = <&vdd_vdenc_s0>;
};
&pd_rkvdec1 {
domain-supply = <&vdd_vdenc_s0>;
};
&pd_venc0 {
domain-supply = <&vdd_vdenc_s0>;
};
&pd_venc1 {
domain-supply = <&vdd_vdenc_s0>;
};
&pinctrl {
audio {
hp_detect: headphone-detect {