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dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules

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Add documentation to describe StarFive JHB100 SoC System Controller
Registers.

Add the PLL clocks for the sys0, per0, and per1 domains under syscon,
as well as the PCIe RP reset.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Changhuang Liang 2026-08-28 02:56:01 -07:00 committed by Conor Dooley
parent 17986e31f3
commit c4a545d3e4
3 changed files with 130 additions and 0 deletions
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115
Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml Normal file
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@ -0,0 +1,115 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/starfive/starfive,jhb100-syscon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JHB100 SoC system controller
maintainers:
- Kevin Xie <kevin.xie@starfivetech.com>
- Changhuang Liang <changhuang.liang@starfivetech.com>
description:
The StarFive JHB100 SoC system controller contains MMIO registers used by
other hardware modules (e.g., PLL, eMMC, PCIe). These modules access
specific register offsets, bit masks, and shifts within the system
controller region for configuration and status.
properties:
compatible:
items:
- enum:
- starfive,jhb100-b2h-syscon
- starfive,jhb100-gpu-syscon
- starfive,jhb100-h2b-syscon
- starfive,jhb100-host-syscon
- starfive,jhb100-husb-syscon
- starfive,jhb100-husbcmn-syscon
- starfive,jhb100-husbd-syscon
- starfive,jhb100-npu-syscon
- starfive,jhb100-pcieep-ecsr-syscon
- starfive,jhb100-pcierp-ecsr-syscon
- starfive,jhb100-pcierp-syscon
- starfive,jhb100-per0-syscon
- starfive,jhb100-per1-syscon
- starfive,jhb100-per2-syscon
- starfive,jhb100-per3-syscon
- starfive,jhb100-sfc-filter-syscon
- starfive,jhb100-strap-syscon
- starfive,jhb100-sys0-syscon
- starfive,jhb100-sys1-syscon
- starfive,jhb100-sys2-syscon
- starfive,jhb100-usb-syscon
- starfive,jhb100-vout-syscon
- const: syscon
reg:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- starfive,jhb100-per0-syscon
- starfive,jhb100-per1-syscon
- starfive,jhb100-sys0-syscon
then:
required:
- clocks
- '#clock-cells'
else:
properties:
clocks: false
'#clock-cells': false
- if:
properties:
compatible:
contains:
const: starfive,jhb100-pcierp-syscon
then:
required:
- '#reset-cells'
else:
properties:
'#reset-cells': false
additionalProperties: false
examples:
- |
syscon@13010000 {
compatible = "starfive,jhb100-sys0-syscon", "syscon";
reg = <0x13010000 0x2000>;
clocks = <&osc>;
#clock-cells = <1>;
};
syscon@13014000 {
compatible = "starfive,jhb100-sys1-syscon", "syscon";
reg = <0x13014000 0x4000>;
};
syscon@11719000 {
compatible = "starfive,jhb100-pcierp-syscon", "syscon";
reg = <0x11719000 0x1000>;
#reset-cells = <1>;
};
...

12
include/dt-bindings/clock/starfive,jhb100-crg.h
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@ -8,6 +8,18 @@
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__
#define __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__
/* SYS0PLL clocks */
#define JHB100_SYS0PLL_PLL2_OUT 0
#define JHB100_SYS0PLL_PLL3_OUT 1
#define JHB100_SYS0PLL_PLL4_OUT 2
#define JHB100_SYS0PLL_PLL5_OUT 3
/* PER0PLL clocks */
#define JHB100_PER0PLL_PLL6_OUT 0
/* PER1PLL clocks */
#define JHB100_PER1PLL_PLL7_OUT 0
/* SYS0CRG clocks */
#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_MAIN 17
#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG 18

3
include/dt-bindings/reset/starfive,jhb100-crg.h
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@ -183,4 +183,7 @@
#define JHB100_PER3RST_MAIN_RSTN_PERIPH3_SENSORS 5
#define JHB100_PER3RST_IOMUX_PRESETN 6
/* PCIERP SYSCON resets */
#define JHB100_PCIERP_SYSCONRST_PE2RST_OUT 0
#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */