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dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator
Add bindings for the Peripheral-3 clock and reset generator (PER3CRG) on the JHB100 RISC-V SoC by StarFive Ltd. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Changhuang Liang
Conor Dooley
parent
5b86a2f941
commit
17986e31f3
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jhb100-per3crg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JHB100 Peripheral-3 Clock and Reset Generator
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maintainers:
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- Changhuang Liang <changhuang.liang@starfivetech.com>
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properties:
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compatible:
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const: starfive,jhb100-per3crg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Non Coherent NOC Initiator
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- description: Non Coherent NOC Target
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- description: Configure 125MHz
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- description: GMAC0 RMII Reference clock
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- description: GMAC1 SGMII TX
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- description: GMAC1 SGMII RX
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- description: Main Oscillator (25 MHz)
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clock-names:
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items:
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- const: ncnoc_init
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- const: ncnoc_targ
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- const: cfg_125
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- const: gmac0_rmii_rclki
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- const: gmac1_sgmii_tx
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- const: gmac1_sgmii_rx
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- const: osc
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jhb100-crg.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@11c40000 {
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compatible = "starfive,jhb100-per3crg";
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reg = <0x11c40000 0x1000>;
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clocks = <&sys0crg 65>,
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<&sys1crg 18>,
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<&sys1crg 19>,
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<&per3_gmac0_rmii_rclki>,
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<&per3_gmac1_sgmii_tx>,
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<&per3_gmac1_sgmii_rx>,
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<&osc>;
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clock-names = "ncnoc_init", "ncnoc_targ", "cfg_125",
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"gmac0_rmii_rclki", "gmac1_sgmii_tx",
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"gmac1_sgmii_rx", "osc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@ -504,4 +504,39 @@
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#define JHB100_PER2CLK_MAIN_ICG_EN_GMAC2 69
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#define JHB100_PER2CLK_MAIN_ICG_EN_GMAC3 70
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/* PER3CRG clocks */
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#define JHB100_PER3CLK_300 0
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#define JHB100_PER3CLK_200 1
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#define JHB100_PER3CLK_GMAC1_PTP_REF 2
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#define JHB100_PER3CLK_GMAC1_TX_125_MUX 3
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#define JHB100_PER3CLK_GMAC1_TX 4
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#define JHB100_PER3CLK_GMAC1_RX_125_MUX 5
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#define JHB100_PER3CLK_GMAC1_RX 6
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#define JHB100_PER3CLK_GMAC0_PTP_REF 7
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#define JHB100_PER3CLK_GMAC0_RMII_PLL 8
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#define JHB100_PER3CLK_GMAC0_RMII_MUX 9
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#define JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2 10
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#define JHB100_PER3CLK_ETHER0_RMII_CLK_TX_I 17
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#define JHB100_PER3CLK_ETHER0_RMII_CLK_RX_I 18
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#define JHB100_PER3CLK_ETHER0_RMII_CLK_PTP_REF_I 19
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#define JHB100_PER3CLK_ETHER0_RMII_CLK_RMII_I 20
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#define JHB100_PER3CLK_ETHER0_RMII_CLK_CSR_I 21
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#define JHB100_PER3CLK_ETHER0_RMII_ACLK_I 22
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#define JHB100_PER3CLK_GMAC0_RMII_RCLKO 23
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#define JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_I 24
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#define JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_I 25
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#define JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_125_I 26
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#define JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_125_I 27
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#define JHB100_PER3CLK_ETHER0_SGMII_CLK_PTP_REF_I 28
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#define JHB100_PER3CLK_ETHER0_SGMII_CLK_REF_25_I 29
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#define JHB100_PER3CLK_ETHER0_SGMII_CLK_CSR_I 30
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#define JHB100_PER3CLK_ETHER0_SGMII_ACLK_I 31
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#define JHB100_PER3CLK_ETHER0_SGMII_PHY_PCLK_I 32
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#define JHB100_PER3CLK_MAIN_ICG_EN_SENSORS_PERIPH3 33
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#define JHB100_PER3CLK_MAIN_ICG_EN_PECI0 34
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#define JHB100_PER3CLK_MAIN_ICG_EN_PECI1 35
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#define JHB100_PER3CLK_MAIN_ICG_EN_GMAC0 36
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#define JHB100_PER3CLK_MAIN_ICG_EN_GMAC1 37
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#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */
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@ -174,4 +174,13 @@
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#define JHB100_PER2RST_ADC1_IOMUX_PRESETN 13
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#define JHB100_PER2RST_MAIN_RSTN_PERIPH2_SENSORS 14
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/* PER3CRG resets */
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#define JHB100_PER3RST_SYSREG_RSTN 0
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#define JHB100_PER3RST_MAIN_RSTN_GMAC0 1
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#define JHB100_PER3RST_MAIN_RSTN_GMAC1 2
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#define JHB100_PER3RST_MAIN_RSTN_PECI0 3
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#define JHB100_PER3RST_MAIN_RSTN_PECI1 4
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#define JHB100_PER3RST_MAIN_RSTN_PERIPH3_SENSORS 5
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#define JHB100_PER3RST_IOMUX_PRESETN 6
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#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */
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