mirror of
https://github.com/torvalds/linux.git
synced 2026-11-07 06:17:02 +01:00
dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator
Add bindings for the Peripheral-2 clock and reset generator (PER2CRG) on the JHB100 RISC-V SoC by StarFive Ltd. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Changhuang Liang
Conor Dooley
parent
d20c33354c
commit
5b86a2f941
|
|
@ -0,0 +1,76 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/starfive,jhb100-per2crg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: StarFive JHB100 Peripheral-2 Clock and Reset Generator
|
||||
|
||||
maintainers:
|
||||
- Changhuang Liang <changhuang.liang@starfivetech.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: starfive,jhb100-per2crg
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Non Coherent NOC Initiator
|
||||
- description: Configure 400MHz
|
||||
- description: Configure 125MHz
|
||||
- description: GMAC2 RGMII RX
|
||||
- description: GMAC2 RMII Reference
|
||||
- description: GMAC3 SGMII TX
|
||||
- description: GMAC3 SGMII RX
|
||||
- description: Main Oscillator (25 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ncnoc_init
|
||||
- const: cfg_400
|
||||
- const: cfg_125
|
||||
- const: gmac2_rgmii_rx
|
||||
- const: gmac2_rmii_ref
|
||||
- const: gmac3_sgmii_tx
|
||||
- const: gmac3_sgmii_rx
|
||||
- const: osc
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices.
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
description:
|
||||
See <dt-bindings/reset/starfive,jhb100-crg.h> for valid indices.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@11bc0000 {
|
||||
compatible = "starfive,jhb100-per2crg";
|
||||
reg = <0x11bc0000 0x1000>;
|
||||
clocks = <&sys0crg 52>, <&sys0crg 54>, <&sys0crg 55>,
|
||||
<&per2_gmac2_rgmii_rx>, <&per2_gmac2_rmii_ref>,
|
||||
<&per2_gmac3_sgmii_tx>, <&per2_gmac3_sgmii_rx>,
|
||||
<&osc>;
|
||||
clock-names = "ncnoc_init", "cfg_400", "cfg_125",
|
||||
"gmac2_rgmii_rx", "gmac2_rmii_ref",
|
||||
"gmac3_sgmii_tx", "gmac3_sgmii_rx",
|
||||
"osc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -447,4 +447,61 @@
|
|||
#define JHB100_PER1CLK_MAIN_ICG_EN_RAS 75
|
||||
#define JHB100_PER1CLK_MAIN_ICG_EN_UFS 76
|
||||
|
||||
/* PER2CRG clocks */
|
||||
#define JHB100_PER2CLK_300 0
|
||||
#define JHB100_PER2CLK_100 1
|
||||
#define JHB100_PER2CLK_50 2
|
||||
#define JHB100_PER2CLK_GMAC2_RMII_50 3
|
||||
#define JHB100_PER2CLK_CAN0_CORE_DIV 4
|
||||
#define JHB100_PER2CLK_CAN1_CORE_DIV 5
|
||||
#define JHB100_PER2CLK_CAN0_TIMER 6
|
||||
#define JHB100_PER2CLK_CAN1_TIMER 7
|
||||
|
||||
#define JHB100_PER2CLK_RTC_CORE_DIV 11
|
||||
#define JHB100_PER2CLK_GMAC2_RMII_MUX_DLY 12
|
||||
#define JHB100_PER2CLK_GMAC2_RMII_DIV 13
|
||||
|
||||
#define JHB100_PER2CLK_GMAC2_RGMII_125_MUX 15
|
||||
#define JHB100_PER2CLK_GMAC2_RGMII_DIV 16
|
||||
#define JHB100_PER2CLK_GMAC2_TX_MUX 17
|
||||
#define JHB100_PER2CLK_GMAC2_TX_180_BUF 18
|
||||
#define JHB100_PER2CLK_GMAC2_RX_MUX_DLY 19
|
||||
#define JHB100_PER2CLK_GMAC2_RX_180_BUF 20
|
||||
#define JHB100_PER2CLK_GMAC2_TXCK_MUX_DLY 21
|
||||
#define JHB100_PER2CLK_GMAC3_TX_125_MUX 22
|
||||
#define JHB100_PER2CLK_GMAC3_RX_125_MUX 23
|
||||
#define JHB100_PER2CLK_GMAC3_TX_DIV 24
|
||||
#define JHB100_PER2CLK_GMAC3_RX_DIV 25
|
||||
#define JHB100_PER2CLK_SENSORS_PERIPH2 26
|
||||
|
||||
#define JHB100_PER2CLK_FAN_TACH_PCLK 33
|
||||
|
||||
#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_I 44
|
||||
#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_I 45
|
||||
#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_180_I 46
|
||||
#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_180_I 47
|
||||
#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_PTP_REF_I 48
|
||||
#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RMII_I 49
|
||||
#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_CSR_I 50
|
||||
#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_ACLK_I 51
|
||||
#define JHB100_PER2CLK_RMIIANDRGMII_IOMUX_GMAC2_TXCK 52
|
||||
#define JHB100_PER2CLK_ETHER1_SGMII_TX_I 53
|
||||
#define JHB100_PER2CLK_ETHER1_SGMII_RX_I 54
|
||||
#define JHB100_PER2CLK_ETHER1_SGMII_TX_125_I 55
|
||||
#define JHB100_PER2CLK_ETHER1_SGMII_RX_125_I 56
|
||||
#define JHB100_PER2CLK_ETHER1_SGMII_PTP_REF_I 57
|
||||
#define JHB100_PER2CLK_ETHER1_SGMII_CSR_I 58
|
||||
#define JHB100_PER2CLK_ETHER1_SGMII_ACLK_I 59
|
||||
#define JHB100_PER2CLK_ETHER1_SGMII_PHY_PCLK_I 60
|
||||
#define JHB100_PER2CLK_ETHER1_SGMII_REF_25_I 61
|
||||
#define JHB100_PER2CLK_MAIN_ICG_EN_CAN0 62
|
||||
#define JHB100_PER2CLK_MAIN_ICG_EN_CAN1 63
|
||||
|
||||
#define JHB100_PER2CLK_MAIN_ICG_EN_DMAC_8CH 65
|
||||
#define JHB100_PER2CLK_MAIN_ICG_EN_RTC_SCAN 66
|
||||
#define JHB100_PER2CLK_MAIN_ICG_EN_ADC0 67
|
||||
#define JHB100_PER2CLK_MAIN_ICG_EN_ADC1 68
|
||||
#define JHB100_PER2CLK_MAIN_ICG_EN_GMAC2 69
|
||||
#define JHB100_PER2CLK_MAIN_ICG_EN_GMAC3 70
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */
|
||||
|
|
|
|||
|
|
@ -157,4 +157,21 @@
|
|||
#define JHB100_PER1RST_MAIN_RSTN_DMAC_SPI0 15
|
||||
#define JHB100_PER1RST_MAIN_RSTN_PERIPH1_RAS 16
|
||||
|
||||
/* PER2CRG resets */
|
||||
#define JHB100_PER2RST_IOMUX_PRESETN 0
|
||||
#define JHB100_PER2RST_POK_IOMUX_PRESETN 1
|
||||
#define JHB100_PER2RST_SYSREG_RSTN 2
|
||||
#define JHB100_PER2RST_MAIN_RSTN_CAN0 3
|
||||
#define JHB100_PER2RST_MAIN_RSTN_CAN1 4
|
||||
#define JHB100_PER2RST_FAN_TACH_PRESETN 5
|
||||
#define JHB100_PER2RST_MAIN_RSTN_GMAC2 6
|
||||
#define JHB100_PER2RST_MAIN_RSTN_GMAC3 7
|
||||
#define JHB100_PER2RST_MAIN_RSTN_DMAC_8CH 8
|
||||
#define JHB100_PER2RST_MAIN_RSTN_RTC 9
|
||||
#define JHB100_PER2RST_ADC0_PRESETN 10
|
||||
#define JHB100_PER2RST_ADC0_IOMUX_PRESETN 11
|
||||
#define JHB100_PER2RST_ADC1_PRESETN 12
|
||||
#define JHB100_PER2RST_ADC1_IOMUX_PRESETN 13
|
||||
#define JHB100_PER2RST_MAIN_RSTN_PERIPH2_SENSORS 14
|
||||
|
||||
#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user