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arm64: dts: freescale: Add support for Variscite DART-MX95
Add device tree support for the Variscite DART-MX95 system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX95 MPU processor - Up to 16GB of LPDDR5 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-95/dart-mx95/ Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Stefano Radaelli
Frank Li
parent
a69ba865a7
commit
bec2988b47
425
arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi
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425
arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi
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@ -0,0 +1,425 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Common dtsi for Variscite DART-MX95
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*
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* Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-95/dart-mx95/
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*
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* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
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*
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*/
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/dts-v1/;
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/usb/pd.h>
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#include "imx95.dtsi"
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/ {
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model = "Variscite DART-MX95 Module";
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compatible = "variscite,var-dart-mx95", "fsl,imx95";
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0 0x80000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "+V1.8_SW";
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "+V3.3_SW";
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};
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reg_vref_1v8: regulator-adc-vref {
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compatible = "regulator-fixed";
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regulator-name = "vref_1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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reg_audio: regulator-audio-vdd {
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compatible = "regulator-fixed";
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regulator-name = "wm8904_supply";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reserved-memory {
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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linux_cma: linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x80000000 0 0x7F000000>;
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reusable;
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size = <0 0x3c000000>;
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linux,cma-default;
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};
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};
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sound-wm8904 {
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compatible = "simple-audio-card";
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simple-audio-card,bitclock-master = <&codec_dai>;
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simple-audio-card,format = "i2s";
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simple-audio-card,frame-master = <&codec_dai>;
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simple-audio-card,mclk-fs = <256>;
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simple-audio-card,name = "wm8904-audio";
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simple-audio-card,routing =
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"Headphone Jack", "HPOUTL",
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"Headphone Jack", "HPOUTR",
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"IN2L", "Line In Jack",
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"IN2R", "Line In Jack",
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"IN1L", "Microphone Jack",
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"IN1R", "Microphone Jack";
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simple-audio-card,widgets =
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"Microphone", "Microphone Jack",
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"Headphone", "Headphone Jack",
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"Line", "Line In Jack";
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codec_dai: simple-audio-card,codec {
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sound-dai = <&wm8904>;
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};
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simple-audio-card,cpu {
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sound-dai = <&sai3>;
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};
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};
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wifi_pwrseq: wifi-pwrseq {
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compatible = "mmc-pwrseq-simple";
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post-power-on-delay-ms = <100>;
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power-off-delay-us = <10000>;
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reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
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<&gpio2 27 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
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};
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};
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&adc1 {
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vref-supply = <®_vref_1v8>;
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status = "okay";
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};
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&enetc_port0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enetc0>;
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phy-handle = <ðphy0>;
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/*
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* The required RGMII TX and RX 2ns delays are implemented directly
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* in hardware via passive delay elements on the SOM PCB.
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* No delay configuration is needed in software via PHY driver.
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*/
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phy-mode = "rgmii";
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status = "okay";
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};
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&lpi2c8 {
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clock-frequency = <400000>;
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pinctrl-names = "default","gpio","sleep";
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pinctrl-0 = <&pinctrl_lpi2c8>;
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pinctrl-1 = <&pinctrl_lpi2c8_gpio>;
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pinctrl-2 = <&pinctrl_lpi2c8_gpio>;
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scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio2 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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wm8904: audio-codec@1a {
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compatible = "wlf,wm8904";
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reg = <0x1a>;
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#sound-dai-cells = <0>;
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clocks = <&scmi_clk IMX95_CLK_SAI3>;
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clock-names = "mclk";
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AVDD-supply = <®_audio>;
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CPVDD-supply = <®_audio>;
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DBVDD-supply = <®_audio>;
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DCVDD-supply = <®_audio>;
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MICVDD-supply = <®_audio>;
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wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
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"soft", "music";
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/*
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* Config registers per name, respectively:
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* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
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* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
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* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
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* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
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* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
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*/
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wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
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/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
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/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
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/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
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/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
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/* GPIO1 = DMIC_CLK, don't touch others */
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wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
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};
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};
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/* BT */
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&lpuart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>;
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status = "okay";
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bluetooth {
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compatible = "nxp,88w8987-bt";
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};
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};
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&mu7 {
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status = "okay";
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};
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&netc_emdio {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_emdio>, <&pinctrl_phy0res>;
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status = "okay";
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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reset-gpios = <&gpio5 16 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <100000>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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linux,default-trigger = "netdev";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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linux,default-trigger = "netdev";
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};
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};
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};
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};
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&netc_timer {
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status = "okay";
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};
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&sai3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai3>;
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assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
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<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
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<&scmi_clk IMX95_CLK_AUDIOPLL1>,
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<&scmi_clk IMX95_CLK_AUDIOPLL2>,
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<&scmi_clk IMX95_CLK_SAI3>;
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assigned-clock-parents = <0>, <0>, <0>, <0>,
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<&scmi_clk IMX95_CLK_AUDIOPLL1>;
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assigned-clock-rates = <3932160000>,
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<3612672000>, <393216000>,
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<361267200>, <12288000>;
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#sound-dai-cells = <0>;
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fsl,sai-mclk-direction-output;
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status = "okay";
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};
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/* eMMC */
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&usdhc1 {
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pinctrl-names = "default","state_100mhz","state_200mhz","sleep";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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pinctrl-3 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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non-removable;
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no-sdio;
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no-sd;
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status = "okay";
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};
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/* WiFi */
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&usdhc3 {
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pinctrl-names = "default","state_100mhz","state_200mhz","sleep";
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pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
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pinctrl-3 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
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mmc-pwrseq = <&wifi_pwrseq>;
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bus-width = <4>;
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non-removable;
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wakeup-source;
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keep-power-in-suspend;
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status = "okay";
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};
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&wdog3 {
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fsl,ext-reset-output;
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status = "okay";
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};
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&scmi_iomuxc {
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pinctrl_bt: btgrp {
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fsl,pins = <
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IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e
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>;
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};
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pinctrl_emdio: emdiogrp {
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fsl,pins = <
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IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e
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IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e
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>;
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};
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pinctrl_enetc0: enetc0grp {
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fsl,pins = <
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IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e
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IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e
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IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e
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IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e
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IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e
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IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e
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IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e
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IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e
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IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e
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IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e
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IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e
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IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e
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>;
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};
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pinctrl_lpi2c8: lpi2c8grp {
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fsl,pins = <
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IMX95_PAD_GPIO_IO10__LPI2C8_SDA 0x40000b9e
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IMX95_PAD_GPIO_IO11__LPI2C8_SCL 0x40000b9e
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>;
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};
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pinctrl_lpi2c8_gpio: lpi2c8gpiogrp {
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fsl,pins = <
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IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x31e
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IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e
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>;
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};
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pinctrl_phy0res: phy0resgrp {
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fsl,pins = <
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IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e
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>;
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};
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pinctrl_sai3: sai3grp {
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fsl,pins = <
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IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e
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IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
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IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
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IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e
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IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e
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>;
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};
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pinctrl_uart5: uart5grp {
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fsl,pins = <
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IMX95_PAD_GPIO_IO00__LPUART5_TX 0x31e
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IMX95_PAD_GPIO_IO01__LPUART5_RX 0x31e
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IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e
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IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
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IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
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IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
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IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
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IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
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IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
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IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
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IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
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IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
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IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
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IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
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fsl,pins = <
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IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
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IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
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IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
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IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
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IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
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IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
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IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
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IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
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IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
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IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
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IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
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fsl,pins = <
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IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
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IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
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IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
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IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
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IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
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IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
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IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
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IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
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IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
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IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
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IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
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>;
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};
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pinctrl_usdhc3_gpio: usdhc3gpiogrp {
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fsl,pins = <
|
||||
IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x31e
|
||||
IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x31e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e
|
||||
IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e
|
||||
IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
|
||||
IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
|
||||
IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
|
||||
IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e
|
||||
IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e
|
||||
IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
|
||||
IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
|
||||
IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
|
||||
IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins = <
|
||||
IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe
|
||||
IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe
|
||||
IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
|
||||
IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
|
||||
IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
|
||||
IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
|
||||
>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user