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ASoC: codec drivers: sort the reg_defaults tables

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Peter Ujfalusi <peter.ujfalusi@linux.intel.com> says:

reg_defaults must be sorted by ascending register address, since
regcache_lookup_reg() locates entries in it with bsearch().  When a table is
not sorted, bsearch() cannot find the entries which follow a descending step,
so regcache_reg_needs_sync() falls back to reporting that a sync is needed for
them.  Those registers are then written to the device on every regcache_sync()
even when they were never touched.

See commit fd80df352b ("regcache: Add support for sorting defaults arrays")
for the same problem in a different context.

Affected tables:
  ml26124_reg                1 of 79 entries unreachable
  cx2072x_reg_defaults      75 of 132 entries unreachable
  max9860_reg_defaults       1 of 14 entries unreachable
  stih407_sas_reg_defaults   1 of 2 entries unreachable

Link: https://patch.msgid.link/20260805122811.13713-1-peter.ujfalusi@linux.intel.com
This commit is contained in:
Mark Brown 2026-08-07 15:57:50 +01:00
commit bce4f1fd27
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
4 changed files with 72 additions and 70 deletions
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134
sound/soc/codecs/cx2072x.c
View File

@ -97,51 +97,60 @@ static const struct reg_default cx2072x_reg_defaults[] = {
{ CX2072X_GPIO_WAKE, 0x00000000 },
{ CX2072X_GPIO_UM_ENABLE, 0x00000000 },
{ CX2072X_GPIO_STICKY_MASK, 0x00000000 },
{ CX2072X_DAC1_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_DAC1_AMP_GAIN_RIGHT, 0x0000004a },
{ CX2072X_DAC1_AMP_GAIN_LEFT, 0x0000004a },
{ CX2072X_DAC1_POWER_STATE, 0x00000433 },
{ CX2072X_DAC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
{ CX2072X_DAC1_EAPD_ENABLE, 0x00000000 },
{ CX2072X_DAC2_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_DAC2_AMP_GAIN_RIGHT, 0x0000004a },
{ CX2072X_DAC2_AMP_GAIN_LEFT, 0x0000004a },
{ CX2072X_DAC1_AMP_GAIN_RIGHT, 0x0000004a },
{ CX2072X_DAC1_AMP_GAIN_LEFT, 0x0000004a },
{ CX2072X_DAC1_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_DAC2_POWER_STATE, 0x00000433 },
{ CX2072X_DAC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
{ CX2072X_ADC1_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_0, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_1, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_2, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_3, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_3, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_4, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_4, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_5, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_5, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_6, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_6, 0x0000004a },
{ CX2072X_DAC2_AMP_GAIN_RIGHT, 0x0000004a },
{ CX2072X_DAC2_AMP_GAIN_LEFT, 0x0000004a },
{ CX2072X_DAC2_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 0x00000000 },
{ CX2072X_ADC1_POWER_STATE, 0x00000433 },
{ CX2072X_ADC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
{ CX2072X_ADC2_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_ADC2_AMP_GAIN_RIGHT_0, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_LEFT_0, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_RIGHT_1, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_LEFT_1, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_RIGHT_2, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_LEFT_2, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_3, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_4, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_5, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_6, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_0, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_1, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_2, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_3, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_4, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_5, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_6, 0x0000004a },
{ CX2072X_ADC1_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_ADC2_CONNECTION_SELECT_CONTROL, 0x00000000 },
{ CX2072X_ADC2_POWER_STATE, 0x00000433 },
{ CX2072X_ADC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
{ CX2072X_ADC2_AMP_GAIN_RIGHT_0, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_RIGHT_1, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_RIGHT_2, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_LEFT_0, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_LEFT_1, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_LEFT_2, 0x0000004a },
{ CX2072X_ADC2_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_MIXER_POWER_STATE, 0x00000433 },
{ CX2072X_MIXER_GAIN_RIGHT_0, 0x0000004a },
{ CX2072X_MIXER_GAIN_RIGHT_1, 0x0000004a },
{ CX2072X_MIXER_GAIN_LEFT_0, 0x0000004a },
{ CX2072X_MIXER_GAIN_LEFT_1, 0x0000004a },
{ CX2072X_PORTA_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTA_POWER_STATE, 0x00000433 },
{ CX2072X_PORTA_PIN_CTRL, 0x000000c0 },
{ CX2072X_PORTA_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTA_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTA_EAPD_BTL, 0x00000002 },
{ CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTG_POWER_STATE, 0x00000433 },
{ CX2072X_PORTG_PIN_CTRL, 0x00000040 },
{ CX2072X_PORTG_EAPD_BTL, 0x00000002 },
{ CX2072X_PORTB_POWER_STATE, 0x00000433 },
{ CX2072X_PORTB_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTB_UNSOLICITED_RESPONSE, 0x00000000 },
@ -149,43 +158,16 @@ static const struct reg_default cx2072x_reg_defaults[] = {
{ CX2072X_PORTB_EAPD_BTL, 0x00000002 },
{ CX2072X_PORTB_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTB_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTC_POWER_STATE, 0x00000433 },
{ CX2072X_PORTC_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTC_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTC_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTD_POWER_STATE, 0x00000433 },
{ CX2072X_PORTD_PIN_CTRL, 0x00000020 },
{ CX2072X_PORTD_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTD_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTD_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTD_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTE_POWER_STATE, 0x00000433 },
{ CX2072X_PORTE_PIN_CTRL, 0x00000040 },
{ CX2072X_PORTE_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTE_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTE_EAPD_BTL, 0x00000002 },
{ CX2072X_PORTE_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTE_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTF_POWER_STATE, 0x00000433 },
{ CX2072X_PORTF_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTF_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTF_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTF_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTF_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTG_POWER_STATE, 0x00000433 },
{ CX2072X_PORTG_PIN_CTRL, 0x00000040 },
{ CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTG_EAPD_BTL, 0x00000002 },
{ CX2072X_PORTM_POWER_STATE, 0x00000433 },
{ CX2072X_PORTM_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTM_EAPD_BTL, 0x00000002 },
{ CX2072X_MIXER_POWER_STATE, 0x00000433 },
{ CX2072X_MIXER_GAIN_RIGHT_0, 0x0000004a },
{ CX2072X_MIXER_GAIN_LEFT_0, 0x0000004a },
{ CX2072X_MIXER_GAIN_RIGHT_1, 0x0000004a },
{ CX2072X_MIXER_GAIN_LEFT_1, 0x0000004a },
{ CX2072X_PORTC_POWER_STATE, 0x00000433 },
{ CX2072X_PORTC_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTC_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTC_GAIN_LEFT, 0x00000000 },
{ CX2072X_SPKR_DRC_ENABLE_STEP, 0x040065a4 },
{ CX2072X_SPKR_DRC_CONTROL, 0x007b0024 },
{ CX2072X_SPKR_DRC_TEST, 0x00000000 },
@ -196,12 +178,15 @@ static const struct reg_default cx2072x_reg_defaults[] = {
{ CX2072X_I2SPCM_CONTROL3, 0x00000000 },
{ CX2072X_I2SPCM_CONTROL4, 0x00000000 },
{ CX2072X_I2SPCM_CONTROL5, 0x00000000 },
{ CX2072X_I2SPCM_CONTROL6, 0x00000000 },
{ CX2072X_UM_INTERRUPT_CRTL_E, 0x00000000 },
{ CX2072X_I2SPCM_CONTROL6, 0x00000000 },
{ CX2072X_DIGITAL_TEST16, 0x00000021 },
{ CX2072X_DIGITAL_TEST17, 0x00000018 },
{ CX2072X_DIGITAL_TEST18, 0x00000024 },
{ CX2072X_DIGITAL_TEST19, 0x00000001 },
{ CX2072X_DIGITAL_TEST20, 0x00000002 },
{ CX2072X_CODEC_TEST2, 0x00000000 },
{ CX2072X_CODEC_TEST9, 0x00000004 },
{ CX2072X_CODEC_TEST20, 0x00000600 },
{ CX2072X_CODEC_TEST26, 0x00000208 },
{ CX2072X_ANALOG_TEST4, 0x00000000 },
{ CX2072X_ANALOG_TEST5, 0x00000000 },
{ CX2072X_ANALOG_TEST6, 0x0000059a },
@ -216,11 +201,26 @@ static const struct reg_default cx2072x_reg_defaults[] = {
{ CX2072X_DIGITAL_TEST11, 0x00000000 },
{ CX2072X_DIGITAL_TEST12, 0x00000084 },
{ CX2072X_DIGITAL_TEST15, 0x00000077 },
{ CX2072X_DIGITAL_TEST16, 0x00000021 },
{ CX2072X_DIGITAL_TEST17, 0x00000018 },
{ CX2072X_DIGITAL_TEST18, 0x00000024 },
{ CX2072X_DIGITAL_TEST19, 0x00000001 },
{ CX2072X_DIGITAL_TEST20, 0x00000002 },
{ CX2072X_CODEC_TEST20, 0x00000600 },
{ CX2072X_CODEC_TEST26, 0x00000208 },
{ CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTE_POWER_STATE, 0x00000433 },
{ CX2072X_PORTE_PIN_CTRL, 0x00000040 },
{ CX2072X_PORTE_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTE_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTE_EAPD_BTL, 0x00000002 },
{ CX2072X_PORTE_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTE_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTF_POWER_STATE, 0x00000433 },
{ CX2072X_PORTF_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTF_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTF_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTF_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTF_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTM_POWER_STATE, 0x00000433 },
{ CX2072X_PORTM_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTM_EAPD_BTL, 0x00000002 },
};
/*

2
sound/soc/codecs/max9860.c
View File

@ -48,7 +48,6 @@ static int max9860_dvddio_event(struct notifier_block *nb,
}
static const struct reg_default max9860_reg_defaults[] = {
{ MAX9860_PWRMAN, 0x00 },
{ MAX9860_INTEN, 0x00 },
{ MAX9860_SYSCLK, 0x00 },
{ MAX9860_AUDIOCLKHIGH, 0x00 },
@ -62,6 +61,7 @@ static const struct reg_default max9860_reg_defaults[] = {
{ MAX9860_MICGAIN, 0x00 },
{ MAX9860_MICADC, 0x00 },
{ MAX9860_NOISEGATE, 0x00 },
{ MAX9860_PWRMAN, 0x00 },
};
static bool max9860_readable(struct device *dev, unsigned int reg)

4
sound/soc/codecs/ml26124.c
View File

@ -224,7 +224,6 @@ static const struct reg_default ml26124_reg[] = {
/* Analog Path Control Register */
{0x54, 0x00}, /* Speaker AMP Output Control */
{0x5a, 0x00}, /* Mic IF Control */
{0xe8, 0x01}, /* Mic Select Control */
/* Audio Interface Control Register */
{0x60, 0x00}, /* SAI-Trans Control */
@ -287,6 +286,9 @@ static const struct reg_default ml26124_reg[] = {
{0xd0, 0x01}, /* VIDEO AMP Gain Control */
{0xd2, 0x01}, /* VIDEO AMP Setup 1 */
{0xd4, 0x01}, /* VIDEO AMP Control2 */
/* Analog Path Control Register */
{0xe8, 0x01}, /* Mic Select Control */
};
/* Get sampling rate value of sampling rate setting register (0x0) */

2
sound/soc/codecs/sti-sas.c
View File

@ -44,8 +44,8 @@ enum {
};
static const struct reg_default stih407_sas_reg_defaults[] = {
{ STIH407_AUDIO_DAC_CTRL, 0x000000000 },
{ STIH407_AUDIO_GLUE_CTRL, 0x00000040 },
{ STIH407_AUDIO_DAC_CTRL, 0x000000000 },
};
struct sti_dac_audio {