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ASoC: tegra: sort the reg_defaults tables

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Peter Ujfalusi <peter.ujfalusi@linux.intel.com> says:

reg_defaults must be sorted by ascending register address, since
regcache_lookup_reg() locates entries in it with bsearch().  When a table is
not sorted, bsearch() cannot find the entries which follow a descending step,
so regcache_reg_needs_sync() falls back to reporting that a sync is needed for
them.  Those registers are then written to the device on every regcache_sync()
even when they were never touched.

See commit fd80df352b ("regcache: Add support for sorting defaults arrays")
for the same problem in a different context.

The series is based on broonie/for-linus (05eebef3c7).

Affected tables:
  tegra210_i2s_reg_defaults     2 of 8 entries unreachable
  tegra264_i2s_reg_defaults     4 of 9 entries unreachable
  tegra210_mixer_reg_defaults   1 entry unreachable

Link: https://patch.msgid.link/20260805122748.13090-1-peter.ujfalusi@linux.intel.com
This commit is contained in:
Mark Brown 2026-08-07 15:56:06 +01:00
commit 9b57f08ab5
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GPG Key ID: 24D68B725D5487D0
2 changed files with 5 additions and 5 deletions
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8
sound/soc/tegra/tegra210_i2s.c
View File

@ -23,9 +23,9 @@ static const struct reg_default tegra210_i2s_reg_defaults[] = {
{ TEGRA210_I2S_RX_CIF_CTRL, 0x00007700 },
{ TEGRA210_I2S_TX_INT_MASK, 0x00000003 },
{ TEGRA210_I2S_TX_CIF_CTRL, 0x00007700 },
{ TEGRA210_I2S_ENABLE, 0x1 },
{ TEGRA210_I2S_CG, 0x1 },
{ TEGRA210_I2S_TIMING, 0x0000001f },
{ TEGRA210_I2S_ENABLE, 0x1 },
/*
* Below update does not have any effect on Tegra186 and Tegra194.
* On Tegra210, I2S4 has "i2s4a" and "i2s4b" pins and below update
@ -38,13 +38,13 @@ static const struct reg_default tegra210_i2s_reg_defaults[] = {
static const struct reg_default tegra264_i2s_reg_defaults[] = {
{ TEGRA210_I2S_RX_INT_MASK, 0x00000003 },
{ TEGRA210_I2S_RX_CIF_CTRL, 0x00003f00 },
{ TEGRA264_I2S_RX_FIFO_WR_ACCESS_MODE, 0x1 },
{ TEGRA264_I2S_TX_INT_MASK, 0x00000003 },
{ TEGRA264_I2S_TX_CIF_CTRL, 0x00003f00 },
{ TEGRA264_I2S_TX_FIFO_RD_ACCESS_MODE, 0x1 },
{ TEGRA264_I2S_ENABLE, 0x1 },
{ TEGRA264_I2S_CG, 0x1 },
{ TEGRA264_I2S_TIMING, 0x0000001f },
{ TEGRA264_I2S_ENABLE, 0x1 },
{ TEGRA264_I2S_RX_FIFO_WR_ACCESS_MODE, 0x1 },
{ TEGRA264_I2S_TX_FIFO_RD_ACCESS_MODE, 0x1 },
};
static void tegra210_i2s_set_slot_ctrl(struct tegra210_i2s *i2s,

2
sound/soc/tegra/tegra210_mixer.c
View File

@ -57,10 +57,10 @@ static const struct reg_default tegra210_mixer_reg_defaults[] = {
MIXER_TX_REG_DEFAULTS(3),
MIXER_TX_REG_DEFAULTS(4),
{ TEGRA210_MIXER_ENABLE, 0x1 },
{ TEGRA210_MIXER_CG, 0x00000001},
{ TEGRA210_MIXER_GAIN_CFG_RAM_CTRL, 0x00004000},
{ TEGRA210_MIXER_PEAKM_RAM_CTRL, 0x00004000},
{ TEGRA210_MIXER_ENABLE, 0x1 },
};
/* Default gain parameters */