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media: i2c: imx214: Make use of CCS PLL calculator
Calculate PLL parameters based on clock frequency and link frequency. Acked-by: Ricardo Ribalda <ribalda@chromium.org> Signed-off-by: André Apitzsch <git@apitzsch.eu> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
This commit is contained in:
André Apitzsch
Hans Verkuil
parent
a55a5e616b
commit
b9b3596629
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@ -141,6 +141,7 @@ config VIDEO_IMX214
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depends on GPIOLIB
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select REGMAP_I2C
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select V4L2_CCI_I2C
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select VIDEO_CCS_PLL
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help
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This is a Video4Linux2 sensor driver for the Sony
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IMX214 camera.
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@ -20,6 +20,8 @@
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#include <media/v4l2-fwnode.h>
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#include <media/v4l2-subdev.h>
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#include "ccs-pll.h"
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/* Chip ID */
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#define IMX214_REG_CHIP_ID CCI_REG16(0x0016)
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#define IMX214_CHIP_ID 0x0214
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@ -34,7 +36,6 @@
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#define IMX214_DEFAULT_LINK_FREQ 600000000
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/* Keep wrong link frequency for backward compatibility */
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#define IMX214_DEFAULT_LINK_FREQ_LEGACY 480000000
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#define IMX214_DEFAULT_PIXEL_RATE ((IMX214_DEFAULT_LINK_FREQ * 8LL) / 10)
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#define IMX214_FPS 30
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/* V-TIMING internal */
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@ -84,6 +85,7 @@
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#define IMX214_CSI_DATA_FORMAT_RAW10 0x0A0A
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#define IMX214_CSI_DATA_FORMAT_COMP6 0x0A06
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#define IMX214_CSI_DATA_FORMAT_COMP8 0x0A08
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#define IMX214_BITS_PER_PIXEL_MASK 0xFF
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#define IMX214_REG_CSI_LANE_MODE CCI_REG8(0x0114)
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#define IMX214_CSI_2_LANE_MODE 1
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@ -249,6 +251,10 @@ struct imx214 {
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struct clk *xclk;
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struct regmap *regmap;
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struct ccs_pll pll;
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struct v4l2_fwnode_endpoint bus_cfg;
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struct v4l2_subdev sd;
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struct media_pad pad;
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@ -758,16 +764,22 @@ static int imx214_configure_pll(struct imx214 *imx214)
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{
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int ret = 0;
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cci_write(imx214->regmap, IMX214_REG_VTPXCK_DIV, 5, &ret);
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cci_write(imx214->regmap, IMX214_REG_VTSYCK_DIV, 2, &ret);
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cci_write(imx214->regmap, IMX214_REG_PREPLLCK_VT_DIV, 3, &ret);
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cci_write(imx214->regmap, IMX214_REG_PLL_VT_MPY, 150, &ret);
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cci_write(imx214->regmap, IMX214_REG_OPPXCK_DIV, 10, &ret);
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cci_write(imx214->regmap, IMX214_REG_OPSYCK_DIV, 1, &ret);
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cci_write(imx214->regmap, IMX214_REG_VTPXCK_DIV,
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imx214->pll.vt_bk.pix_clk_div, &ret);
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cci_write(imx214->regmap, IMX214_REG_VTSYCK_DIV,
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imx214->pll.vt_bk.sys_clk_div, &ret);
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cci_write(imx214->regmap, IMX214_REG_PREPLLCK_VT_DIV,
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imx214->pll.vt_fr.pre_pll_clk_div, &ret);
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cci_write(imx214->regmap, IMX214_REG_PLL_VT_MPY,
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imx214->pll.vt_fr.pll_multiplier, &ret);
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cci_write(imx214->regmap, IMX214_REG_OPPXCK_DIV,
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imx214->pll.op_bk.pix_clk_div, &ret);
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cci_write(imx214->regmap, IMX214_REG_OPSYCK_DIV,
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imx214->pll.op_bk.sys_clk_div, &ret);
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cci_write(imx214->regmap, IMX214_REG_PLL_MULT_DRIV,
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IMX214_PLL_SINGLE, &ret);
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cci_write(imx214->regmap, IMX214_REG_EXCK_FREQ,
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IMX214_EXCK_FREQ(IMX214_DEFAULT_CLK_FREQ / 1000000), &ret);
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IMX214_EXCK_FREQ(imx214->pll.ext_clk_freq_hz / 1000000), &ret);
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return ret;
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}
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@ -872,9 +884,6 @@ static const struct v4l2_ctrl_ops imx214_ctrl_ops = {
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static int imx214_ctrls_init(struct imx214 *imx214)
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{
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static const s64 link_freq[] = {
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IMX214_DEFAULT_LINK_FREQ
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};
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static const struct v4l2_area unit_size = {
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.width = 1120,
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.height = 1120,
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@ -895,15 +904,14 @@ static int imx214_ctrls_init(struct imx214 *imx214)
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if (ret)
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return ret;
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imx214->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, NULL,
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V4L2_CID_PIXEL_RATE, 0,
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IMX214_DEFAULT_PIXEL_RATE, 1,
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IMX214_DEFAULT_PIXEL_RATE);
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imx214->pixel_rate =
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v4l2_ctrl_new_std(ctrl_hdlr, NULL, V4L2_CID_PIXEL_RATE, 1,
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INT_MAX, 1, 1);
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imx214->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, NULL,
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V4L2_CID_LINK_FREQ,
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ARRAY_SIZE(link_freq) - 1,
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0, link_freq);
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imx214->bus_cfg.nr_of_link_frequencies - 1,
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0, imx214->bus_cfg.link_frequencies);
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if (imx214->link_freq)
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imx214->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
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@ -1006,6 +1014,7 @@ static int imx214_start_streaming(struct imx214 *imx214)
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const struct v4l2_mbus_framefmt *fmt;
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struct v4l2_subdev_state *state;
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const struct imx214_mode *mode;
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int bit_rate_mbps;
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int ret;
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ret = cci_multi_reg_write(imx214->regmap, mode_table_common,
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@ -1021,8 +1030,10 @@ static int imx214_start_streaming(struct imx214 *imx214)
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return ret;
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}
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bit_rate_mbps = (imx214->pll.pixel_rate_csi / 1000000)
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* imx214->pll.bits_per_pixel;
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ret = cci_write(imx214->regmap, IMX214_REG_REQ_LINK_BIT_RATE,
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IMX214_LINK_BIT_RATE_MBPS(4800), NULL);
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IMX214_LINK_BIT_RATE_MBPS(bit_rate_mbps), NULL);
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if (ret) {
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dev_err(imx214->dev, "failed to configure link bit rate\n");
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return ret;
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@ -1105,6 +1116,109 @@ static int imx214_s_stream(struct v4l2_subdev *subdev, int enable)
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return ret;
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}
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static int imx214_pll_calculate(struct imx214 *imx214, struct ccs_pll *pll,
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unsigned int link_freq)
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{
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struct ccs_pll_limits limits = {
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.min_ext_clk_freq_hz = 6000000,
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.max_ext_clk_freq_hz = 27000000,
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.vt_fr = {
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.min_pre_pll_clk_div = 1,
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.max_pre_pll_clk_div = 15,
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/* Value is educated guess as we don't have a spec */
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.min_pll_ip_clk_freq_hz = 6000000,
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/* Value is educated guess as we don't have a spec */
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.max_pll_ip_clk_freq_hz = 12000000,
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.min_pll_multiplier = 12,
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.max_pll_multiplier = 1200,
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.min_pll_op_clk_freq_hz = 338000000,
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.max_pll_op_clk_freq_hz = 1200000000,
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},
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.vt_bk = {
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.min_sys_clk_div = 2,
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.max_sys_clk_div = 4,
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.min_pix_clk_div = 5,
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.max_pix_clk_div = 10,
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.min_pix_clk_freq_hz = 30000000,
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.max_pix_clk_freq_hz = 120000000,
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},
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.op_bk = {
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.min_sys_clk_div = 1,
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.max_sys_clk_div = 2,
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.min_pix_clk_div = 6,
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.max_pix_clk_div = 10,
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.min_pix_clk_freq_hz = 30000000,
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.max_pix_clk_freq_hz = 120000000,
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},
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.min_line_length_pck_bin = IMX214_PPL_DEFAULT,
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.min_line_length_pck = IMX214_PPL_DEFAULT,
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};
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unsigned int num_lanes = imx214->bus_cfg.bus.mipi_csi2.num_data_lanes;
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/*
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* There are no documented constraints on the sys clock frequency, for
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* either branch. Recover them based on the PLL output clock frequency
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* and sys_clk_div limits on one hand, and the pix clock frequency and
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* the pix_clk_div limits on the other hand.
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*/
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limits.vt_bk.min_sys_clk_freq_hz =
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max(limits.vt_fr.min_pll_op_clk_freq_hz / limits.vt_bk.max_sys_clk_div,
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limits.vt_bk.min_pix_clk_freq_hz * limits.vt_bk.min_pix_clk_div);
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limits.vt_bk.max_sys_clk_freq_hz =
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min(limits.vt_fr.max_pll_op_clk_freq_hz / limits.vt_bk.min_sys_clk_div,
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limits.vt_bk.max_pix_clk_freq_hz * limits.vt_bk.max_pix_clk_div);
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limits.op_bk.min_sys_clk_freq_hz =
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max(limits.vt_fr.min_pll_op_clk_freq_hz / limits.op_bk.max_sys_clk_div,
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limits.op_bk.min_pix_clk_freq_hz * limits.op_bk.min_pix_clk_div);
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limits.op_bk.max_sys_clk_freq_hz =
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min(limits.vt_fr.max_pll_op_clk_freq_hz / limits.op_bk.min_sys_clk_div,
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limits.op_bk.max_pix_clk_freq_hz * limits.op_bk.max_pix_clk_div);
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memset(pll, 0, sizeof(*pll));
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pll->bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY;
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pll->op_lanes = num_lanes;
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pll->vt_lanes = num_lanes;
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pll->csi2.lanes = num_lanes;
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pll->binning_horizontal = 1;
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pll->binning_vertical = 1;
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pll->scale_m = 1;
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pll->scale_n = 1;
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pll->bits_per_pixel =
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IMX214_CSI_DATA_FORMAT_RAW10 & IMX214_BITS_PER_PIXEL_MASK;
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pll->flags = CCS_PLL_FLAG_LANE_SPEED_MODEL;
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pll->link_freq = link_freq;
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pll->ext_clk_freq_hz = clk_get_rate(imx214->xclk);
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return ccs_pll_calculate(imx214->dev, &limits, pll);
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}
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static int imx214_pll_update(struct imx214 *imx214)
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{
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u64 link_freq;
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int ret;
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link_freq = imx214->bus_cfg.link_frequencies[imx214->link_freq->val];
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ret = imx214_pll_calculate(imx214, &imx214->pll, link_freq);
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if (ret) {
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dev_err(imx214->dev, "PLL calculations failed: %d\n", ret);
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return ret;
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}
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ret = v4l2_ctrl_s_ctrl_int64(imx214->pixel_rate,
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imx214->pll.pixel_rate_pixel_array);
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if (ret) {
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dev_err(imx214->dev, "failed to set pixel rate\n");
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return ret;
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}
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return 0;
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}
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static int imx214_get_frame_interval(struct v4l2_subdev *subdev,
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struct v4l2_subdev_state *sd_state,
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struct v4l2_subdev_frame_interval *fival)
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@ -1211,12 +1325,10 @@ static int imx214_identify_module(struct imx214 *imx214)
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return 0;
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}
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static int imx214_parse_fwnode(struct device *dev)
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static int imx214_parse_fwnode(struct device *dev, struct imx214 *imx214)
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{
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struct v4l2_fwnode_endpoint *bus_cfg = &imx214->bus_cfg;
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struct fwnode_handle *endpoint;
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struct v4l2_fwnode_endpoint bus_cfg = {
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.bus_type = V4L2_MBUS_CSI2_DPHY,
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};
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unsigned int i;
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int ret;
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@ -1224,42 +1336,52 @@ static int imx214_parse_fwnode(struct device *dev)
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if (!endpoint)
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return dev_err_probe(dev, -EINVAL, "endpoint node not found\n");
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ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg);
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bus_cfg->bus_type = V4L2_MBUS_CSI2_DPHY;
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ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, bus_cfg);
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fwnode_handle_put(endpoint);
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if (ret) {
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dev_err_probe(dev, ret, "parsing endpoint node failed\n");
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goto done;
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goto error;
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}
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/* Check the number of MIPI CSI2 data lanes */
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if (bus_cfg.bus.mipi_csi2.num_data_lanes != 4) {
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if (bus_cfg->bus.mipi_csi2.num_data_lanes != 4) {
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ret = dev_err_probe(dev, -EINVAL,
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"only 4 data lanes are currently supported\n");
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goto done;
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goto error;
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}
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if (bus_cfg.nr_of_link_frequencies != 1)
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if (bus_cfg->nr_of_link_frequencies != 1)
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dev_warn(dev, "Only one link-frequency supported, please review your DT. Continuing anyway\n");
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for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
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if (bus_cfg.link_frequencies[i] == IMX214_DEFAULT_LINK_FREQ)
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for (i = 0; i < bus_cfg->nr_of_link_frequencies; i++) {
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u64 freq = bus_cfg->link_frequencies[i];
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struct ccs_pll pll;
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if (!imx214_pll_calculate(imx214, &pll, freq))
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break;
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if (bus_cfg.link_frequencies[i] ==
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IMX214_DEFAULT_LINK_FREQ_LEGACY) {
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if (freq == IMX214_DEFAULT_LINK_FREQ_LEGACY) {
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dev_warn(dev,
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"link-frequencies %d not supported, please review your DT. Continuing anyway\n",
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IMX214_DEFAULT_LINK_FREQ);
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freq = IMX214_DEFAULT_LINK_FREQ;
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if (imx214_pll_calculate(imx214, &pll, freq))
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continue;
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bus_cfg->link_frequencies[i] = freq;
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break;
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}
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}
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if (i == bus_cfg.nr_of_link_frequencies)
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if (i == bus_cfg->nr_of_link_frequencies)
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ret = dev_err_probe(dev, -EINVAL,
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"link-frequencies %d not supported, please review your DT\n",
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IMX214_DEFAULT_LINK_FREQ);
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"link-frequencies %lld not supported, please review your DT\n",
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bus_cfg->nr_of_link_frequencies ?
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bus_cfg->link_frequencies[0] : 0);
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done:
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v4l2_fwnode_endpoint_free(&bus_cfg);
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fwnode_handle_put(endpoint);
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return 0;
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error:
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v4l2_fwnode_endpoint_free(&imx214->bus_cfg);
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return ret;
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}
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@ -1299,7 +1421,7 @@ static int imx214_probe(struct i2c_client *client)
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return dev_err_probe(dev, PTR_ERR(imx214->regmap),
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"failed to initialize CCI\n");
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ret = imx214_parse_fwnode(dev);
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ret = imx214_parse_fwnode(dev, imx214);
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if (ret)
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return ret;
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@ -1310,7 +1432,9 @@ static int imx214_probe(struct i2c_client *client)
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* Enable power initially, to avoid warnings
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* from clk_disable on power_off
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*/
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imx214_power_on(imx214->dev);
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ret = imx214_power_on(imx214->dev);
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if (ret < 0)
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goto error_fwnode;
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ret = imx214_identify_module(imx214);
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if (ret)
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@ -1341,6 +1465,12 @@ static int imx214_probe(struct i2c_client *client)
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pm_runtime_set_active(imx214->dev);
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pm_runtime_enable(imx214->dev);
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ret = imx214_pll_update(imx214);
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if (ret < 0) {
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dev_err_probe(dev, ret, "failed to update PLL\n");
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goto error_subdev_cleanup;
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}
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ret = v4l2_async_register_subdev_sensor(&imx214->sd);
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if (ret < 0) {
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dev_err_probe(dev, ret,
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@ -1366,6 +1496,9 @@ static int imx214_probe(struct i2c_client *client)
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error_power_off:
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imx214_power_off(imx214->dev);
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error_fwnode:
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v4l2_fwnode_endpoint_free(&imx214->bus_cfg);
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return ret;
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}
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@ -1378,6 +1511,8 @@ static void imx214_remove(struct i2c_client *client)
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v4l2_subdev_cleanup(sd);
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media_entity_cleanup(&imx214->sd.entity);
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v4l2_ctrl_handler_free(&imx214->ctrls);
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v4l2_fwnode_endpoint_free(&imx214->bus_cfg);
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pm_runtime_disable(&client->dev);
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if (!pm_runtime_status_suspended(&client->dev)) {
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imx214_power_off(imx214->dev);
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