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dt-bindings: display: imx: Add i.MX8qxp Display Controller blit engine
i.MX8qxp Display Controller contains a blit engine for raster graphics. It may read up to 3 source images from memory and computes one destination image from it, which is written back to memory. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-3-victor.liu@nxp.com
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Liu Ying
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-blit-engine.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8qxp Display Controller Blit Engine
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description: |
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A blit operation (block based image transfer) reads up to 3 source images
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from memory and computes one destination image from it, which is written
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back to memory. The following basic operations are supported:
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* Buffer Fill
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Fills a buffer with constant color
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* Buffer Copy
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Copies one source to a destination buffer.
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* Image Blend
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Combines two source images by a blending equation and writes result to
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destination (which can be one of the sources).
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* Image Rop2/3
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Combines up to three source images by a logical equation (raster operation)
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and writes result to destination (which can be one of the sources).
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* Image Flip
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Mirrors the source image in horizontal and/or vertical direction.
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* Format Convert
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Convert between the supported color and buffer formats.
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* Color Transform
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Modify colors by linear or non-linear transformations.
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* Image Scale
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Changes size of the source image.
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* Image Rotate
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Rotates the source image by any angle.
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* Image Filter
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Performs an FIR filter operation on the source image.
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* Image Warp
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Performs a re-sampling of the source image with any pattern. The sample
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point positions are read from a compressed coordinate buffer.
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* Buffer Pack
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Writes an image with color components stored in up to three different
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buffers (planar formats) into a single buffer (packed format).
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* Chroma Resample
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Converts between different YUV formats that differ in chroma sampling rate
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(4:4:4, 4:2:2, 4:2:0).
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maintainers:
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- Liu Ying <victor.liu@nxp.com>
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properties:
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compatible:
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const: fsl,imx8qxp-dc-blit-engine
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: pec
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- const: cfg
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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patternProperties:
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"^blitblend@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-blitblend
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"^clut@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-clut
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"^fetchdecode@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-fetchdecode
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"^fetcheco@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-fetcheco
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"^fetchwarp@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-fetchwarp
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"^filter@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-filter
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"^hscaler@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-hscaler
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"^matrix@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-matrix
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"^rop@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-rop
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"^store@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-store
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"^vscaler@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-vscaler
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required:
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- compatible
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- reg
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- reg-names
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- "#address-cells"
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- "#size-cells"
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- ranges
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additionalProperties: false
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examples:
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- |
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blit-engine@56180820 {
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compatible = "fsl,imx8qxp-dc-blit-engine";
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reg = <0x56180820 0x13c>, <0x56181000 0x3400>;
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reg-names = "pec", "cfg";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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fetchdecode@56180820 {
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compatible = "fsl,imx8qxp-dc-fetchdecode";
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reg = <0x56180820 0x10>, <0x56181000 0x404>;
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reg-names = "pec", "cfg";
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};
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store@56180940 {
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compatible = "fsl,imx8qxp-dc-store";
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reg = <0x56180940 0x1c>, <0x56184000 0x5c>;
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reg-names = "pec", "cfg";
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interrupt-parent = <&dc0_intc>;
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interrupts = <0>, <1>, <2>;
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interrupt-names = "shdload", "framecomplete", "seqcomplete";
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};
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};
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