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Minor improvements in ARM64 DTS for v6.18

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Add default address cells for interrupt controllers to fix dtc W=1
 warnings on Amazon, APM, Socionext and Toshiba boards.
 -----BEGIN PGP SIGNATURE-----
 
 iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmjAcEQQHGtyemtAa2Vy
 bmVsLm9yZwAKCRDBN2bmhouD1zz5D/4wVVWp+gl5WoWPAKmIqi1BxpzlTnU2uSLf
 HxmFCJ8vyA0MyAjlK8A9Kew+BH1DyLw3ObXLNhD2BuWyJosPO30SkY1H5EP9s3Sw
 gsbkYY4HwAOLpuCiF/DxF83bU+rHHdspbQ8XktulCFy0iGOLkh8eqRnuJ4ujgTUV
 JyvCiqZ/yPxwRXzeYq0M3t4cLS3qEzMFckGqD65EAurfH0laQbVBvXgSMS0oug/L
 WsBErYoJejQSEltyaT1hPWM4g7RVxiufSlHHBCariuXAyCEq3/Flk6bJcG3xdDAE
 NJESCg13yautnYW5z0LE0wt3+aI0IVg3NdqQ/xwcKeJnmMX/o7y7o4TkzPVvqL2l
 oGTV5495Pz/HrBEHr1yF152Ll1eh07+Y05ytnsX2ikC+POWC4lHPMi9TTwb9sac5
 Nw0XfGA9Ljl028mJ6cMMiEHWaTm2lMOAJXJXv47BvomUUO5lBsSTEeEFW5lLOyA7
 LJqxVZtCk97g+WerEcDGLLohJP5/vAUjYMtV0XzFowhPaIG6dAm+h33ZouabI/HW
 lZaO1G3a/qi/WQkG4zIshvmqHjMt5ywpn1Wk/0d0xKrZhUYSnRlvlQgKvVp5SW+6
 9cj35o/iw0j/+eW+cVwmlEw99ViLUr63AIDINmvli2GdKHxzDIxlFj80d4ag6UDw
 5NU6E54GCw==
 =g+Rb
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjIEDUACgkQmmx57+YA
 GNmCxBAApFtIErNYjTImyo/lRwgUt7kQP9p7gtSzwwiYm+fcJ5iP95iEF11qQiFy
 LAzlWoZYdc3x4jxFptpoVIzcxDJN5uaQODTaLxJvfncliOCWTZ9bYF7vBued3Oe+
 98uebYu7AJy+tU0eQhOnsFnqei2uJqZPbQCSKB7QybnAk8DrMaCy/Y0MOYmfOuEF
 g2Di7R+o2cilhmVwEKRYYlvfBPYBN5NMiEb72o0iuIk76R1t5Btu/GXBDuEag34I
 ofwHeOxmfoGgf4KenqYb6Gp5DSozHVIrIqCIrEEPwUf0vTZFvUBQ06iPcJUWmyjj
 g1RufBcuy3Xiv9Si7A3sRD3skGrPpud8rczHZxm7wuIInBUgkRf9fgfG702dVwxW
 CFbzIKSUySXPwPGz48cAcI27kEm07M8kTioO7CO3rmmJ5Z6Wv3bUPASfadC4bDjO
 GECh313g+EhC160On+FMHq8YIRHJ/kWIn7+o9KcRIFb+Q8SigbrM46WwXCWCHHBr
 myWQJcig9eLuNMSXsJoEBNJtmRSuxtHChuloxRmhrnMnsr/9b0IS6IkLMuuNTBzP
 VvBndr6momTSvaDKVkaFRzZezzr74YnWnHfv8TG5Fdc7Jr/9OxOuu4+vb2tykYk7
 Pos00YgXqCVuftGuco5Xyav5acn+6RFFmrzx8IaRDEPXfkA0VbU=
 =5RVU
 -----END PGP SIGNATURE-----

Merge tag 'dt64-cleanup-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt

Minor improvements in ARM64 DTS for v6.18

Add default address cells for interrupt controllers to fix dtc W=1
warnings on Amazon, APM, Socionext and Toshiba boards.

* tag 'dt64-cleanup-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
  arm64: dts: toshiba: tmpv7708: Add default GIC address cells
  arm64: dts: amazon: alpine-v3: Add default GIC address cells
  arm64: dts: amazon: alpine-v2: Add default GIC address cells
  arm64: dts: apm: storm: Add default GIC address cells
  arm64: dts: socionext: uniphier-pxs3: Add default PCI interrup controller address cells
  arm64: dts: socionext: uniphier-ld20: Add default PCI interrup controller address cells

Link: https://lore.kernel.org/r/20250909182256.102840-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-09-15 15:10:11 +02:00
commit b425afb348
6 changed files with 6 additions and 0 deletions
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1
arch/arm64/boot/dts/amazon/alpine-v2.dtsi
View File

@ -123,6 +123,7 @@ gic: interrupt-controller@f0200000 {
<0x0 0xf0120000 0x0 0x2000>; /* GICH */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <3>;
};

1
arch/arm64/boot/dts/amazon/alpine-v3.dtsi
View File

@ -320,6 +320,7 @@ soc {
gic: interrupt-controller@f0800000 {
compatible = "arm,gic-v3";
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0xf0800000 0 0x10000>, /* GICD */

1
arch/arm64/boot/dts/apm/apm-storm.dtsi
View File

@ -103,6 +103,7 @@ xgene_L2_3: l2-cache-3 {
gic: interrupt-controller@78010000 {
compatible = "arm,cortex-a15-gic";
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */

1
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
View File

@ -947,6 +947,7 @@ pcie: pcie@66000000 {
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;

1
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
View File

@ -921,6 +921,7 @@ pcie: pcie@66000000 {
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;

1
arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
View File

@ -152,6 +152,7 @@ soc {
gic: interrupt-controller@24001000 {
compatible = "arm,gic-400";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
reg = <0 0x24001000 0 0x1000>,