arm64: dts: renesas: s4sk: Access rswitch ports via phandles

The r8a779f0.dtsi now contains labels for each rswitch port in the form
'rswitch_portN'.  Use those to access rswitch ports and slightly reduce
the depth of this board DT.  No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250118111344.361617-3-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Marek Vasut 2025-01-18 12:13:10 +01:00 committed by Geert Uytterhoeven
parent d7801582dc
commit b231d607b7

View File

@ -179,53 +179,48 @@ &rswitch {
pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>;
pinctrl-names = "default";
status = "okay";
};
ethernet-ports {
&rswitch_port0 {
reg = <0>;
phy-handle = <&ic99>;
phy-mode = "sgmii";
phys = <&eth_serdes 0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phy-handle = <&ic99>;
phy-mode = "sgmii";
phys = <&eth_serdes 0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ic99: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>;
};
};
};
port@1 {
ic99: ethernet-phy@1 {
reg = <1>;
phy-handle = <&ic102>;
phy-mode = "sgmii";
phys = <&eth_serdes 1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ic102: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>;
};
};
};
port@2 {
status = "disabled";
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&rswitch_port1 {
reg = <1>;
phy-handle = <&ic102>;
phy-mode = "sgmii";
phys = <&eth_serdes 1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ic102: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&rswitch_port2 {
status = "disabled";
};
&rwdt {
timeout-sec = <60>;
status = "okay";