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arm64: dts: renesas: spider-ethernet: Access rswitch ports via phandles

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The r8a779f0.dtsi now contains labels for each rswitch port in the form
'rswitch_portN'.  Use those to access rswitch ports and slightly reduce
the depth of this board DT.  No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250118111344.361617-2-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Marek Vasut 2025-01-18 12:13:09 +01:00 committed by Geert Uytterhoeven
parent a4fdcbdcc4
commit d7801582dc
1 changed files with 47 additions and 50 deletions
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97
arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
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@ -42,61 +42,58 @@ &rswitch {
pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
pinctrl-names = "default";
status = "okay";
};
ethernet-ports {
&rswitch_port0 {
reg = <0>;
phy-handle = <&u101>;
phy-mode = "sgmii";
phys = <&eth_serdes 0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phy-handle = <&u101>;
phy-mode = "sgmii";
phys = <&eth_serdes 0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
u101: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>;
};
};
};
port@1 {
u101: ethernet-phy@1 {
reg = <1>;
phy-handle = <&u201>;
phy-mode = "sgmii";
phys = <&eth_serdes 1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
u201: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>;
};
};
};
port@2 {
reg = <2>;
phy-handle = <&u301>;
phy-mode = "sgmii";
phys = <&eth_serdes 2>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
u301: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 9 IRQ_TYPE_LEVEL_LOW>;
};
};
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&rswitch_port1 {
reg = <1>;
phy-handle = <&u201>;
phy-mode = "sgmii";
phys = <&eth_serdes 1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
u201: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&rswitch_port2 {
reg = <2>;
phy-handle = <&u301>;
phy-mode = "sgmii";
phys = <&eth_serdes 2>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
u301: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 9 IRQ_TYPE_LEVEL_LOW>;
};
};
};