ARM: dts: aspeed: msx4: enable BMC networking via MAC0

Add &mac0, &mdio3, and the ethphy3 PHY node to enable BMC networking
on the AST2600-based NVIDIA MSX4 board. The PHY is attached to MDIO3
at address 2 and uses RGMII with PHY-internal delays.

These nodes were intentionally omitted in commit f28674fab3 ("ARM:
dts: aspeed: Add NVIDIA MSX4 HPM") at Andrew Lunn's request, pending
clarification of the RGMII delay handling. Following his guidance on
linux-aspeed, the bootloader has been modified to stop enabling MAC
clock delays on the SoC side, so phy-mode = "rgmii-id" correctly
results in the PHY adding the required ~2ns delay without any
double-delay from the MAC controller.

The corresponding U-Boot change has been submitted to openbmc/u-boot.

Link: https://patch.msgid.link/eac09481-0ba1-4ac2-ad8c-d859822ff0d5@lunn.ch
Link: https://patch.msgid.link/20260504044702.2613879-1-andhsieh@nvidia.com
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Marc Olberding <molberding@nvidia.com>
Signed-off-by: Ender Hsieh <andhsieh@nvidia.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
This commit is contained in:
Ender Hsieh 2026-05-05 14:05:41 +09:00 committed by Andrew Jeffery
parent 79fb6e46a9
commit ae326783b7

View File

@ -208,6 +208,21 @@ &lpc_reset {
status = "okay";
};
&mac0 {
phy-mode = "rgmii-id";
phy-handle = <&ethphy3>;
status = "okay";
};
&mdio3 {
status = "okay";
ethphy3: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
};
&rtc {
status = "okay";
};