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ARM: dts: aspeed: anacapa: Add JTAG CPLD TRST pin to SGPIO map

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Add JTAG_CPLD_TRST_R_N to the sgpiom0 pin name table on Facebook Anacapa
BMC. This exposes the CPLD JTAG TRST signal through SGPIO, allowing
proper JTAG reset control during debug.

[arj: Minor tidying of commit message formatting]

Signed-off-by: Colin Huang <u8813345@gmail.com>
Link: https://patch.msgid.link/20260511-add-jtag-trst-pin-v1-1-b0be2f7b2da5@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
This commit is contained in:
Colin Huang 2026-05-11 17:47:56 +08:00 committed by Andrew Jeffery
parent 91b9aed738
commit 79fb6e46a9
1 changed files with 1 additions and 1 deletions
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arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
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@ -882,7 +882,7 @@ &sgpiom0 {
/* C0-C7 line 32-47 */
"RSVD_RMC_GPIO3", "", "", "",
"", "", "", "",
"LEAK_DETECT_RMC_N", "", "", "",
"LEAK_DETECT_RMC_N", "JTAG_CPLD_TRST_R_N", "", "",
"", "", "", "",
/* D0-D7 line 48-63 */