From 79fb6e46a92003b9aed5391218e1e27b12147b94 Mon Sep 17 00:00:00 2001 From: Colin Huang Date: Mon, 11 May 2026 17:47:56 +0800 Subject: [PATCH] ARM: dts: aspeed: anacapa: Add JTAG CPLD TRST pin to SGPIO map Add JTAG_CPLD_TRST_R_N to the sgpiom0 pin name table on Facebook Anacapa BMC. This exposes the CPLD JTAG TRST signal through SGPIO, allowing proper JTAG reset control during debug. [arj: Minor tidying of commit message formatting] Signed-off-by: Colin Huang Link: https://patch.msgid.link/20260511-add-jtag-trst-pin-v1-1-b0be2f7b2da5@gmail.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 2cb7bd128d24..9a43e0c87257 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -882,7 +882,7 @@ &sgpiom0 { /* C0-C7 line 32-47 */ "RSVD_RMC_GPIO3", "", "", "", "", "", "", "", - "LEAK_DETECT_RMC_N", "", "", "", + "LEAK_DETECT_RMC_N", "JTAG_CPLD_TRST_R_N", "", "", "", "", "", "", /* D0-D7 line 48-63 */