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soc/tegra: Changes for v7.2-rc1
These changes update some maintainer contact information, add a modern way of reading the chip information and cleanup/enhance some existing code. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmobyCUACgkQ3SOs138+ s6GPYg//dX92g9SuxAemSCQNpvJlVJ+bUY39aL4AD+94bvT9h9aXmTthJSmWiWq+ gh75d2meLanswoD8ziRnL4TKixI21TxzCCxHEBJ0rknIVDnXx5lU/6ihPgHvcUfm 43CZzrLad4O9EnifGxPdA1HLD/uyCl/iN2DB/3hjL03zQO/2694hFjJEV8CYDFeO Lwcbft9AvdjKDdRwIEXniBvIQSBvchYdQ1FUAoPAabpVKIPYvKjSdynXMfWrDuoI Lf0anSBP0RiRTPiaV2iSBaQ2i+IAMnyljPba4uJ6NcXaVO7o+Cjlv4eaTpxbrR3v NrK4zDXUSfT/1zdLThhzvQMI+3wW/Ni79P0hc676VFZW6SjdVuQWjkwlx1CFAvxr nIWNM/Y+ESakKl2sjmZVV9L4uoU6gMTe1jtZCYjcU6jB93cw6swCzJvyu8QDPfKE qEYAmSYEfDhTCy2rOn0PwotAfh33vcH+Q/G7KhMsT44vHBETMPI41DQtWpQizWqm Gerll7ugHSuk5D5GU1yRcZTSxbsgnPq2sYEjBFV5Px2daZ55/q5DTD7S2f7PD6Z7 XFijgYr3XdS73k1EpJUl2zkkXcIaErZF3wSAMn4c5wVFQuWipbP6ZJuwtzRzGdXw 5ywOp2coxfe36ks3/oP6GIybPiepsEPk1yYbYR4ssnOuO9EqAys= =d+5I -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmooFMgACgkQmmx57+YA GNlehhAAnDZM42f71/vVzCC0Ll/H365l9yCg5JtwgenvgpTBSgXmGNoYcMR9zadj qNa9lotrHjSf4Fh0+XKRTaiozddbRKOAykdaOXqvBQEqTR8tXYNAHWFnIb6lov6r 1shqs09kb6hm7p4hTo1D//fQI93OAxiOKdQkPVEjJKYoSFYaWAg5Wb3nj3D4gIh1 NLsyjcjvSTcOOEio/JPvHjNpi5/3s/urkmE7xpULagd+C0FnUL5q88pP4IcffMzi U4XnpMBfUVdVsrYZPgBXhN2g1ii33c8/kGaq8CKIyn+U8o4llHapmomXZm16ZXHj sc6idjXEbfzsbaXBHvtVIb+MdOIZ9AJ2Z3Y/PVkoC3h9Cki++44Ym1RGlb7lu4Hj MkdTx1j+hJImQcQval1XPnO89vt9SPcPZ9DHi6bqo2SEyXrXtum7IuAmVUpPFAl6 39yFkzjnnc/3plau2AmGN7+8aD6qwsauWzI160CryAc51xJIFa7Oyc6plRPdRZ3r ICNGoL6vGlntPvhPW4oNJ+yQ4SL2CN4PkN6MRPAJ2g9l8WuL0pojtaB+WKjbc9X7 DnbnJJUobz14yquxmBKah6waijUkv3RpguNgaDvv4yNjglJLHiG7mLCZLBxw1wo8 dr709LRGSG20cQjRl2j+wzI1iUXuJ4AZJ2UfnUyhreHrfQf6t5c= =zXJz -----END PGP SIGNATURE----- Merge tag 'tegra-for-7.2-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers soc/tegra: Changes for v7.2-rc1 These changes update some maintainer contact information, add a modern way of reading the chip information and cleanup/enhance some existing code. * tag 'tegra-for-7.2-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: Use ARM SMCCC to get chip ID, revision, and platform info soc/tegra: fuse: Register nvmem lookups at probe Documentation: ABI: Take over as contact for sysfs-driver-tegra-fuse MAINTAINERS: Move Peter De Schrijver to CREDITS bus: tegra-aconnect: Use dev_err_probe for probe error paths Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
aa75b5370d
10
CREDITS
10
CREDITS
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@ -3668,7 +3668,17 @@ D: Macintosh IDE Driver
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N: Peter De Schrijver
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E: stud11@cc4.kuleuven.ac.be
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E: p2@mind.be
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E: peter.de-schrijver@nokia.com
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E: pdeschrijver@nvidia.com
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E: p2@psychaos.be
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D: Apollo Domain workstations
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D: Ariadne and Hydra Amiga Ethernet drivers
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D: IBM PS/2, Microchannel, and Token Ring support
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D: Mitsumi CD-ROM driver patches March version
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D: TWL4030 power management and audio codec driver
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D: OMAP power management
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D: NVIDIA Tegra clock and BPMP drivers, among many other things
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S: Molenbaan 29
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S: B2240 Zandhoven
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S: Belgium
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@ -1,6 +1,6 @@
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What: /sys/devices/*/<our-device>/fuse
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Date: February 2014
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Contact: Peter De Schrijver <pdeschrijver@nvidia.com>
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Contact: Thierry Reding <thierry.reding@kernel.org>
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Description: read-only access to the efuses on Tegra20, Tegra30, Tegra114
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and Tegra124 SoC's from NVIDIA. The efuses contain write once
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data programmed at the factory. The data is laid out in 32bit
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@ -26229,7 +26229,6 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git
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N: [^a-z]tegra
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TEGRA CLOCK DRIVER
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M: Peter De Schrijver <pdeschrijver@nvidia.com>
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M: Prashant Gaikwad <pgaikwad@nvidia.com>
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S: Supported
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F: drivers/clk/tegra/
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@ -32,16 +32,14 @@ static int tegra_aconnect_probe(struct platform_device *pdev)
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return -ENOMEM;
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aconnect->ape_clk = devm_clk_get(&pdev->dev, "ape");
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if (IS_ERR(aconnect->ape_clk)) {
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dev_err(&pdev->dev, "Can't retrieve ape clock\n");
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return PTR_ERR(aconnect->ape_clk);
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}
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if (IS_ERR(aconnect->ape_clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(aconnect->ape_clk),
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"can't retrieve ape clock\n");
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aconnect->apb2ape_clk = devm_clk_get(&pdev->dev, "apb2ape");
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if (IS_ERR(aconnect->apb2ape_clk)) {
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dev_err(&pdev->dev, "Can't retrieve apb2ape clock\n");
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return PTR_ERR(aconnect->apb2ape_clk);
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}
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if (IS_ERR(aconnect->apb2ape_clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(aconnect->apb2ape_clk),
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"can't retrieve apb2ape clock\n");
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dev_set_drvdata(&pdev->dev, aconnect);
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pm_runtime_enable(&pdev->dev);
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@ -182,10 +182,6 @@ static int tegra_fuse_probe(struct platform_device *pdev)
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}
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fuse->soc->init(fuse);
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err = tegra_fuse_add_lookups(fuse);
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if (err)
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return dev_err_probe(&pdev->dev, err, "failed to add FUSE lookups\n");
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}
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fuse->clk = devm_clk_get_optional(&pdev->dev, "fuse");
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@ -231,6 +227,10 @@ static int tegra_fuse_probe(struct platform_device *pdev)
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return err;
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}
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err = tegra_fuse_add_lookups(fuse);
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if (err)
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return dev_err_probe(&pdev->dev, err, "failed to add FUSE lookups\n");
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fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse");
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if (IS_ERR(fuse->rst))
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return dev_err_probe(&pdev->dev, PTR_ERR(fuse->rst), "failed to get FUSE reset\n");
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@ -473,7 +473,7 @@ static int __init tegra_init_fuse(void)
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const struct of_device_id *match;
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struct device_node *np;
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struct resource regs;
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int err;
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int err = 0;
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tegra_init_apbmisc();
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@ -566,10 +566,6 @@ static int __init tegra_init_fuse(void)
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tegra_fuse_print_sku_info(&tegra_sku_info);
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err = tegra_fuse_add_lookups(fuse);
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if (err)
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pr_err("failed to add FUSE lookups\n");
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return err;
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}
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early_initcall(tegra_init_fuse);
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@ -4,6 +4,7 @@
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*/
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#include <linux/acpi.h>
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#include <linux/arm-smccc.h>
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#include <linux/export.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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@ -27,6 +28,11 @@
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#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
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(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
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#define TEGRA_SMCCC_PLATFORM(x) (((x) >> 8) & 0xff)
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#define TEGRA_SMCCC_CHIP_ID(x) (((x) >> 4) & 0xff)
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#define TEGRA_SMCCC_MAJOR_REV(x) ((x) & 0xf)
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#define TEGRA_SMCCC_MINOR_REV(x) ((x) & 0xf)
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static void __iomem *apbmisc_base;
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static bool long_ram_code;
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static u32 strapping;
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@ -34,28 +40,56 @@ static u32 chipid;
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u32 tegra_read_chipid(void)
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{
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WARN(!chipid, "Tegra APB MISC not yet available\n");
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WARN(!apbmisc_base, "Tegra APB MISC not yet available\n");
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if (!chipid)
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chipid = readl_relaxed(apbmisc_base + 4);
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return chipid;
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}
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u8 tegra_get_chip_id(void)
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{
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#if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY)
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s32 soc_id = arm_smccc_get_soc_id_version();
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if (soc_id >= 0)
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return TEGRA_SMCCC_CHIP_ID(soc_id);
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#endif
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return (tegra_read_chipid() >> 8) & 0xff;
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}
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u8 tegra_get_major_rev(void)
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{
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#if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY)
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s32 soc_id = arm_smccc_get_soc_id_version();
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if (soc_id >= 0)
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return TEGRA_SMCCC_MAJOR_REV(soc_id);
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#endif
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return (tegra_read_chipid() >> 4) & 0xf;
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}
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u8 tegra_get_minor_rev(void)
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{
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#if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY)
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s32 revision = arm_smccc_get_soc_id_revision();
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if (revision >= 0)
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return TEGRA_SMCCC_MINOR_REV(revision);
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#endif
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return (tegra_read_chipid() >> 16) & 0xf;
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}
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u8 tegra_get_platform(void)
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{
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#if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY)
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s32 revision = arm_smccc_get_soc_id_revision();
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if (revision >= 0)
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return TEGRA_SMCCC_PLATFORM(revision);
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#endif
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return (tegra_read_chipid() >> 20) & 0xf;
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}
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@ -170,9 +204,7 @@ static void tegra_init_apbmisc_resources(struct resource *apbmisc,
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void __iomem *strapping_base;
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apbmisc_base = ioremap(apbmisc->start, resource_size(apbmisc));
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if (apbmisc_base)
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chipid = readl_relaxed(apbmisc_base + 4);
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else
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if (!apbmisc_base)
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pr_err("failed to map APBMISC registers\n");
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strapping_base = ioremap(straps->start, resource_size(straps));
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