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ARM: dts: imx6ul: align pin config nodes with bindings

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Bindings expect pin configuration nodes in pinctrl to match certain
naming:

  imx6ul-kontron-bl.dtb: pinctrl@20e0000: 'usbotg1' does not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2024-09-02 13:40:38 +02:00 committed by Shawn Guo
parent e515be1280
commit a9c741d8e9
18 changed files with 47 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi
View File

@ -608,7 +608,7 @@ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
@ -620,7 +620,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9

4
arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts
View File

@ -112,7 +112,7 @@ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_ecspi3_master: ecspi3grp1 {
pinctrl_ecspi3_master: ecspi3-1-grp {
fsl,pins = <
MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
@ -121,7 +121,7 @@ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 /* Chip Select */
>;
};
pinctrl_ecspi3_slave: ecspi3grp2 {
pinctrl_ecspi3_slave: ecspi3-2-grp {
fsl,pins = <
MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0

14
arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts
View File

@ -248,7 +248,7 @@ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
>;
};
pinctrl_ecspi1_master: ecspi1grp1 {
pinctrl_ecspi1_master: ecspi1-1-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x10b0
MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x10b0
@ -309,7 +309,7 @@ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1020
>;
};
pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 {
pinctrl_lcdif_dat0_17: lcdifdat0-17-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
@ -332,14 +332,14 @@ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
>;
};
pinctrl_lcdif_clken: lcdifctrlgrp1 {
pinctrl_lcdif_clken: lcdifctrl-1-grp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x17050
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
>;
};
pinctrl_lcdif_hvsync: lcdifctrlgrp2 {
pinctrl_lcdif_hvsync: lcdifctrl-2-grp {
fsl,pins = <
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
@ -370,7 +370,7 @@ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10b0
>;
};
pinctrl_sai2_sleep: sai2grp-sleep {
pinctrl_sai2_sleep: sai2-sleep-grp {
fsl,pins = <
MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x3000
MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x3000
@ -381,7 +381,7 @@ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x3000
>;
};
pinctrl_uart2_4wires: uart2grp-4wires {
pinctrl_uart2_4wires: uart2-4wires-grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
@ -390,7 +390,7 @@ MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart3_2wires: uart3grp-2wires {
pinctrl_uart3_2wires: uart3-2wires-grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1

4
arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi
View File

@ -232,7 +232,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
pinctrl_usdhc1_sleep: usdhc1grp-sleep {
pinctrl_usdhc1_sleep: usdhc1-sleep-grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x3000
MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x3000
@ -250,7 +250,7 @@ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x08a0
>;
};
pinctrl_wifibt_ctrl_sleep: wifibt-ctrl-grp-sleep {
pinctrl_wifibt_ctrl_sleep: wifibt-ctrl-sleep-grp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x3000
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3000

4
arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
View File

@ -410,7 +410,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
@ -421,7 +421,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9

4
arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi
View File

@ -346,7 +346,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
@ -357,7 +357,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9

2
arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi
View File

@ -351,7 +351,7 @@ MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1 {
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
>;

2
arch/arm/boot/dts/nxp/imx/imx6ul-liteboard.dts
View File

@ -100,7 +100,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
pinctrl_usb_otg1_vbus: usb-otg1-vbus {
pinctrl_usb_otg1_vbus: usb-otg1-vbus-grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x79
>;

4
arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-wlbt-05.dtsi
View File

@ -31,7 +31,7 @@ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x3031 /* DEV WAKEUP */
>;
};
pinctrl_uart2_bt: uart2grp-bt {
pinctrl_uart2_bt: uart2-bt-grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x17059
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x17059
@ -40,7 +40,7 @@ MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x17059
>;
};
pinctrl_usdhc2_wl: usdhc2grp-wl {
pinctrl_usdhc2_wl: usdhc2-wl-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x10051
MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x10061

6
arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin.dtsi
View File

@ -219,7 +219,7 @@ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
>;
};
pinctrl_flexcan1: flexcan1 {
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
@ -275,7 +275,7 @@ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
@ -286,7 +286,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9

2
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi
View File

@ -202,7 +202,7 @@ MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x4001b8b0
>;
};
pinctrl_pmic: pmic {
pinctrl_pmic: pmicgrp {
fsl,pins = <
/* PMIC irq */
MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099

2
arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts
View File

@ -198,7 +198,7 @@ MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x0b0b0 /* WLAN_RESET */
>;
};
pinctrl_disp0_3: disp0grp-3 {
pinctrl_disp0_3: disp0-3-grp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */

12
arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi
View File

@ -584,7 +584,7 @@ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */
>;
};
pinctrl_disp0_1: disp0grp-1 {
pinctrl_disp0_1: disp0-1-grp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
@ -617,7 +617,7 @@ MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
>;
};
pinctrl_disp0_2: disp0grp-2 {
pinctrl_disp0_2: disp0-2-grp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
@ -707,25 +707,25 @@ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */
>;
};
pinctrl_etnphy0_int: etnphy-intgrp-0 {
pinctrl_etnphy0_int: etnphy-int-0-grp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */
>;
};
pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
pinctrl_etnphy0_rst: etnphy-rst-0-grp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */
>;
};
pinctrl_etnphy1_int: etnphy-intgrp-1 {
pinctrl_etnphy1_int: etnphy-int-1-grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */
>;
};
pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
pinctrl_etnphy1_rst: etnphy-rst-1-grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */
>;

8
arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi
View File

@ -169,7 +169,7 @@ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
@ -180,7 +180,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
@ -206,7 +206,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
@ -221,7 +221,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9

8
arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi
View File

@ -323,7 +323,7 @@ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x79
>;
};
pinctrl_reg_vmmc: usdhc1regvmmc {
pinctrl_reg_vmmc: usdhc1regvmmc-grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059
>;
@ -394,7 +394,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
@ -405,7 +405,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
@ -416,7 +416,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
pinctrl_usdhc1_cd: usdhc1cd {
pinctrl_usdhc1_cd: usdhc1cd-grp {
fsl,pins = <
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
>;

6
arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi
View File

@ -102,7 +102,7 @@ MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
>;
};
pinctrl_reg_vqmmc: usdhc1regvqmmc {
pinctrl_reg_vqmmc: usdhc1regvqmmcgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x17059
>;
@ -123,7 +123,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
@ -138,7 +138,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9

2
arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts
View File

@ -94,7 +94,7 @@ &wdog1 {
};
&iomuxc {
pinctrl_gpmi_nand: gpmi-nand {
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1

6
arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi
View File

@ -505,7 +505,7 @@ MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1
>;
};
pinctrl_uart6dte: uart6dte {
pinctrl_uart6dte: uart6dtegrp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1
MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1
@ -537,7 +537,7 @@ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9
@ -552,7 +552,7 @@ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9