mirror of
https://github.com/torvalds/linux.git
synced 2026-05-26 16:12:59 +02:00
- Convert the tsx= cmdline parsing to use early_param()
- Cleanup forward declarations gunk in bugs.c -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmkt3IMACgkQEsHwGGHe VUqPxRAAkul5R9zZgR9XcV/ZRA6iulo4M0o38Z2COeWtlDtDXpAJ5vNarDBB1l+K ea9YzbfN4iECXNXOCtSrEr7SmJ2ld8xBSyzISeWx2V1AXi4A6A8GX574egtDDCaV vN+eTT1ki9YuJLhgi0eZ+uHkdoTLhChrBehuvlcHnEOXN1N9D/P8/QfDYG7IyCxu /jSnuXyQ3AA2uM3IMEAGLcAarI+cU4HgMsF2Za5Dp8SKhSbhpgpEfFkp8+p+bUO/ nKLgUj2dqibFZd+hvhrwtrnsDL8rTJxLr0dVwg7MZeBea4GliUsaT8jBRBMQddIL DGjAR2niGeGM42DWvFUVZczcgdP0NI8ChpZ3zCjdICrZBGMkZe70iqcPaL0BELob toeBjlHIrlUnXIfZhVBYj59+E+q4yjSwvOd23FYqj1XKcgSR+j305dxo9jTAndLV M/f8o8au3tlccE308OQ/XgIkXFBlGLjrNlak32ze4P2nHFMTlYJBCbAFIti3qcpT Er7q866s7kzagphmZ/2vf0I7JuYI2le/8OnneVFz7l+SVXY1SNEpA7qRM5bA220J n2Orfaen3CgotX7c3yT/XP0c9Wqbd29LMXiQbOdGMMONv5O4aaWMsfRPhlCEYiTK VZ/FklfXrVxtSqa96zBny4MlvtKoYwYklk+McuGF5M4iDXGCthw= =kAho -----END PGP SIGNATURE----- Merge tag 'x86_bugs_for_v6.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 CPU mitigation updates from Borislav Petkov: - Convert the tsx= cmdline parsing to use early_param() - Cleanup forward declarations gunk in bugs.c * tag 'x86_bugs_for_v6.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/bugs: Get rid of the forward declarations x86/tsx: Get the tsx= command line parameter with early_param() x86/tsx: Make tsx_ctrl_state static
This commit is contained in:
Linus Torvalds
commit
a9a10e920e
|
|
@ -53,53 +53,6 @@
|
|||
* mitigation option.
|
||||
*/
|
||||
|
||||
static void __init spectre_v1_select_mitigation(void);
|
||||
static void __init spectre_v1_apply_mitigation(void);
|
||||
static void __init spectre_v2_select_mitigation(void);
|
||||
static void __init spectre_v2_update_mitigation(void);
|
||||
static void __init spectre_v2_apply_mitigation(void);
|
||||
static void __init retbleed_select_mitigation(void);
|
||||
static void __init retbleed_update_mitigation(void);
|
||||
static void __init retbleed_apply_mitigation(void);
|
||||
static void __init spectre_v2_user_select_mitigation(void);
|
||||
static void __init spectre_v2_user_update_mitigation(void);
|
||||
static void __init spectre_v2_user_apply_mitigation(void);
|
||||
static void __init ssb_select_mitigation(void);
|
||||
static void __init ssb_apply_mitigation(void);
|
||||
static void __init l1tf_select_mitigation(void);
|
||||
static void __init l1tf_apply_mitigation(void);
|
||||
static void __init mds_select_mitigation(void);
|
||||
static void __init mds_update_mitigation(void);
|
||||
static void __init mds_apply_mitigation(void);
|
||||
static void __init taa_select_mitigation(void);
|
||||
static void __init taa_update_mitigation(void);
|
||||
static void __init taa_apply_mitigation(void);
|
||||
static void __init mmio_select_mitigation(void);
|
||||
static void __init mmio_update_mitigation(void);
|
||||
static void __init mmio_apply_mitigation(void);
|
||||
static void __init rfds_select_mitigation(void);
|
||||
static void __init rfds_update_mitigation(void);
|
||||
static void __init rfds_apply_mitigation(void);
|
||||
static void __init srbds_select_mitigation(void);
|
||||
static void __init srbds_apply_mitigation(void);
|
||||
static void __init l1d_flush_select_mitigation(void);
|
||||
static void __init srso_select_mitigation(void);
|
||||
static void __init srso_update_mitigation(void);
|
||||
static void __init srso_apply_mitigation(void);
|
||||
static void __init gds_select_mitigation(void);
|
||||
static void __init gds_apply_mitigation(void);
|
||||
static void __init bhi_select_mitigation(void);
|
||||
static void __init bhi_update_mitigation(void);
|
||||
static void __init bhi_apply_mitigation(void);
|
||||
static void __init its_select_mitigation(void);
|
||||
static void __init its_update_mitigation(void);
|
||||
static void __init its_apply_mitigation(void);
|
||||
static void __init tsa_select_mitigation(void);
|
||||
static void __init tsa_apply_mitigation(void);
|
||||
static void __init vmscape_select_mitigation(void);
|
||||
static void __init vmscape_update_mitigation(void);
|
||||
static void __init vmscape_apply_mitigation(void);
|
||||
|
||||
/* The base value of the SPEC_CTRL MSR without task-specific bits set */
|
||||
u64 x86_spec_ctrl_base;
|
||||
EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
|
||||
|
|
@ -233,99 +186,6 @@ static void __init cpu_print_attack_vectors(void)
|
|||
}
|
||||
}
|
||||
|
||||
void __init cpu_select_mitigations(void)
|
||||
{
|
||||
/*
|
||||
* Read the SPEC_CTRL MSR to account for reserved bits which may
|
||||
* have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
|
||||
* init code as it is not enumerated and depends on the family.
|
||||
*/
|
||||
if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
|
||||
rdmsrq(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
|
||||
|
||||
/*
|
||||
* Previously running kernel (kexec), may have some controls
|
||||
* turned ON. Clear them and let the mitigations setup below
|
||||
* rediscover them based on configuration.
|
||||
*/
|
||||
x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
|
||||
}
|
||||
|
||||
x86_arch_cap_msr = x86_read_arch_cap_msr();
|
||||
|
||||
cpu_print_attack_vectors();
|
||||
|
||||
/* Select the proper CPU mitigations before patching alternatives: */
|
||||
spectre_v1_select_mitigation();
|
||||
spectre_v2_select_mitigation();
|
||||
retbleed_select_mitigation();
|
||||
spectre_v2_user_select_mitigation();
|
||||
ssb_select_mitigation();
|
||||
l1tf_select_mitigation();
|
||||
mds_select_mitigation();
|
||||
taa_select_mitigation();
|
||||
mmio_select_mitigation();
|
||||
rfds_select_mitigation();
|
||||
srbds_select_mitigation();
|
||||
l1d_flush_select_mitigation();
|
||||
srso_select_mitigation();
|
||||
gds_select_mitigation();
|
||||
its_select_mitigation();
|
||||
bhi_select_mitigation();
|
||||
tsa_select_mitigation();
|
||||
vmscape_select_mitigation();
|
||||
|
||||
/*
|
||||
* After mitigations are selected, some may need to update their
|
||||
* choices.
|
||||
*/
|
||||
spectre_v2_update_mitigation();
|
||||
/*
|
||||
* retbleed_update_mitigation() relies on the state set by
|
||||
* spectre_v2_update_mitigation(); specifically it wants to know about
|
||||
* spectre_v2=ibrs.
|
||||
*/
|
||||
retbleed_update_mitigation();
|
||||
/*
|
||||
* its_update_mitigation() depends on spectre_v2_update_mitigation()
|
||||
* and retbleed_update_mitigation().
|
||||
*/
|
||||
its_update_mitigation();
|
||||
|
||||
/*
|
||||
* spectre_v2_user_update_mitigation() depends on
|
||||
* retbleed_update_mitigation(), specifically the STIBP
|
||||
* selection is forced for UNRET or IBPB.
|
||||
*/
|
||||
spectre_v2_user_update_mitigation();
|
||||
mds_update_mitigation();
|
||||
taa_update_mitigation();
|
||||
mmio_update_mitigation();
|
||||
rfds_update_mitigation();
|
||||
bhi_update_mitigation();
|
||||
/* srso_update_mitigation() depends on retbleed_update_mitigation(). */
|
||||
srso_update_mitigation();
|
||||
vmscape_update_mitigation();
|
||||
|
||||
spectre_v1_apply_mitigation();
|
||||
spectre_v2_apply_mitigation();
|
||||
retbleed_apply_mitigation();
|
||||
spectre_v2_user_apply_mitigation();
|
||||
ssb_apply_mitigation();
|
||||
l1tf_apply_mitigation();
|
||||
mds_apply_mitigation();
|
||||
taa_apply_mitigation();
|
||||
mmio_apply_mitigation();
|
||||
rfds_apply_mitigation();
|
||||
srbds_apply_mitigation();
|
||||
srso_apply_mitigation();
|
||||
gds_apply_mitigation();
|
||||
its_apply_mitigation();
|
||||
bhi_apply_mitigation();
|
||||
tsa_apply_mitigation();
|
||||
vmscape_apply_mitigation();
|
||||
}
|
||||
|
||||
/*
|
||||
* NOTE: This function is *only* called for SVM, since Intel uses
|
||||
* MSR_IA32_SPEC_CTRL for SSBD.
|
||||
|
|
@ -3371,6 +3231,99 @@ void cpu_bugs_smt_update(void)
|
|||
mutex_unlock(&spec_ctrl_mutex);
|
||||
}
|
||||
|
||||
void __init cpu_select_mitigations(void)
|
||||
{
|
||||
/*
|
||||
* Read the SPEC_CTRL MSR to account for reserved bits which may
|
||||
* have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
|
||||
* init code as it is not enumerated and depends on the family.
|
||||
*/
|
||||
if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
|
||||
rdmsrq(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
|
||||
|
||||
/*
|
||||
* Previously running kernel (kexec), may have some controls
|
||||
* turned ON. Clear them and let the mitigations setup below
|
||||
* rediscover them based on configuration.
|
||||
*/
|
||||
x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
|
||||
}
|
||||
|
||||
x86_arch_cap_msr = x86_read_arch_cap_msr();
|
||||
|
||||
cpu_print_attack_vectors();
|
||||
|
||||
/* Select the proper CPU mitigations before patching alternatives: */
|
||||
spectre_v1_select_mitigation();
|
||||
spectre_v2_select_mitigation();
|
||||
retbleed_select_mitigation();
|
||||
spectre_v2_user_select_mitigation();
|
||||
ssb_select_mitigation();
|
||||
l1tf_select_mitigation();
|
||||
mds_select_mitigation();
|
||||
taa_select_mitigation();
|
||||
mmio_select_mitigation();
|
||||
rfds_select_mitigation();
|
||||
srbds_select_mitigation();
|
||||
l1d_flush_select_mitigation();
|
||||
srso_select_mitigation();
|
||||
gds_select_mitigation();
|
||||
its_select_mitigation();
|
||||
bhi_select_mitigation();
|
||||
tsa_select_mitigation();
|
||||
vmscape_select_mitigation();
|
||||
|
||||
/*
|
||||
* After mitigations are selected, some may need to update their
|
||||
* choices.
|
||||
*/
|
||||
spectre_v2_update_mitigation();
|
||||
/*
|
||||
* retbleed_update_mitigation() relies on the state set by
|
||||
* spectre_v2_update_mitigation(); specifically it wants to know about
|
||||
* spectre_v2=ibrs.
|
||||
*/
|
||||
retbleed_update_mitigation();
|
||||
/*
|
||||
* its_update_mitigation() depends on spectre_v2_update_mitigation()
|
||||
* and retbleed_update_mitigation().
|
||||
*/
|
||||
its_update_mitigation();
|
||||
|
||||
/*
|
||||
* spectre_v2_user_update_mitigation() depends on
|
||||
* retbleed_update_mitigation(), specifically the STIBP
|
||||
* selection is forced for UNRET or IBPB.
|
||||
*/
|
||||
spectre_v2_user_update_mitigation();
|
||||
mds_update_mitigation();
|
||||
taa_update_mitigation();
|
||||
mmio_update_mitigation();
|
||||
rfds_update_mitigation();
|
||||
bhi_update_mitigation();
|
||||
/* srso_update_mitigation() depends on retbleed_update_mitigation(). */
|
||||
srso_update_mitigation();
|
||||
vmscape_update_mitigation();
|
||||
|
||||
spectre_v1_apply_mitigation();
|
||||
spectre_v2_apply_mitigation();
|
||||
retbleed_apply_mitigation();
|
||||
spectre_v2_user_apply_mitigation();
|
||||
ssb_apply_mitigation();
|
||||
l1tf_apply_mitigation();
|
||||
mds_apply_mitigation();
|
||||
taa_apply_mitigation();
|
||||
mmio_apply_mitigation();
|
||||
rfds_apply_mitigation();
|
||||
srbds_apply_mitigation();
|
||||
srso_apply_mitigation();
|
||||
gds_apply_mitigation();
|
||||
its_apply_mitigation();
|
||||
bhi_apply_mitigation();
|
||||
tsa_apply_mitigation();
|
||||
vmscape_apply_mitigation();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYSFS
|
||||
|
||||
#define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
|
||||
|
|
|
|||
|
|
@ -42,15 +42,6 @@ extern const struct cpu_dev *const __x86_cpu_dev_start[],
|
|||
*const __x86_cpu_dev_end[];
|
||||
|
||||
#ifdef CONFIG_CPU_SUP_INTEL
|
||||
enum tsx_ctrl_states {
|
||||
TSX_CTRL_ENABLE,
|
||||
TSX_CTRL_DISABLE,
|
||||
TSX_CTRL_RTM_ALWAYS_ABORT,
|
||||
TSX_CTRL_NOT_SUPPORTED,
|
||||
};
|
||||
|
||||
extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state;
|
||||
|
||||
extern void __init tsx_init(void);
|
||||
void tsx_ap_init(void);
|
||||
void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c);
|
||||
|
|
|
|||
|
|
@ -19,7 +19,17 @@
|
|||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "tsx: " fmt
|
||||
|
||||
enum tsx_ctrl_states tsx_ctrl_state __ro_after_init = TSX_CTRL_NOT_SUPPORTED;
|
||||
enum tsx_ctrl_states {
|
||||
TSX_CTRL_AUTO,
|
||||
TSX_CTRL_ENABLE,
|
||||
TSX_CTRL_DISABLE,
|
||||
TSX_CTRL_RTM_ALWAYS_ABORT,
|
||||
TSX_CTRL_NOT_SUPPORTED,
|
||||
};
|
||||
|
||||
static enum tsx_ctrl_states tsx_ctrl_state __ro_after_init =
|
||||
IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_AUTO) ? TSX_CTRL_AUTO :
|
||||
IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_OFF) ? TSX_CTRL_DISABLE : TSX_CTRL_ENABLE;
|
||||
|
||||
static void tsx_disable(void)
|
||||
{
|
||||
|
|
@ -156,11 +166,28 @@ static void tsx_dev_mode_disable(void)
|
|||
}
|
||||
}
|
||||
|
||||
static int __init tsx_parse_cmdline(char *str)
|
||||
{
|
||||
if (!str)
|
||||
return -EINVAL;
|
||||
|
||||
if (!strcmp(str, "on")) {
|
||||
tsx_ctrl_state = TSX_CTRL_ENABLE;
|
||||
} else if (!strcmp(str, "off")) {
|
||||
tsx_ctrl_state = TSX_CTRL_DISABLE;
|
||||
} else if (!strcmp(str, "auto")) {
|
||||
tsx_ctrl_state = TSX_CTRL_AUTO;
|
||||
} else {
|
||||
tsx_ctrl_state = TSX_CTRL_DISABLE;
|
||||
pr_err("invalid option, defaulting to off\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
early_param("tsx", tsx_parse_cmdline);
|
||||
|
||||
void __init tsx_init(void)
|
||||
{
|
||||
char arg[5] = {};
|
||||
int ret;
|
||||
|
||||
tsx_dev_mode_disable();
|
||||
|
||||
/*
|
||||
|
|
@ -194,27 +221,8 @@ void __init tsx_init(void)
|
|||
return;
|
||||
}
|
||||
|
||||
ret = cmdline_find_option(boot_command_line, "tsx", arg, sizeof(arg));
|
||||
if (ret >= 0) {
|
||||
if (!strcmp(arg, "on")) {
|
||||
tsx_ctrl_state = TSX_CTRL_ENABLE;
|
||||
} else if (!strcmp(arg, "off")) {
|
||||
tsx_ctrl_state = TSX_CTRL_DISABLE;
|
||||
} else if (!strcmp(arg, "auto")) {
|
||||
tsx_ctrl_state = x86_get_tsx_auto_mode();
|
||||
} else {
|
||||
tsx_ctrl_state = TSX_CTRL_DISABLE;
|
||||
pr_err("invalid option, defaulting to off\n");
|
||||
}
|
||||
} else {
|
||||
/* tsx= not provided */
|
||||
if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_AUTO))
|
||||
tsx_ctrl_state = x86_get_tsx_auto_mode();
|
||||
else if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_OFF))
|
||||
tsx_ctrl_state = TSX_CTRL_DISABLE;
|
||||
else
|
||||
tsx_ctrl_state = TSX_CTRL_ENABLE;
|
||||
}
|
||||
if (tsx_ctrl_state == TSX_CTRL_AUTO)
|
||||
tsx_ctrl_state = x86_get_tsx_auto_mode();
|
||||
|
||||
if (tsx_ctrl_state == TSX_CTRL_DISABLE) {
|
||||
tsx_disable();
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user